GAL6001
High Performance E2CMOS FPLA
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS® Advanced CMOS Technology
ICLK
INPUT
CLOCK
2
{
14
11
23
ILMC
IOLMC
RESET
INPUTS
2-11
AND
OUTPUT
ENABLE
• LOW POWER CMOS
— 90mA Typical Icc
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
14
D
23
OLMC
E
OR
0
D
7
BLMC
{ OUTPUTS
14 - 23
E
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
OCLK
OUTPUT
CLOCK
Macrocell Names
ILMC
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL®
and FPLA Devices
INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
BLMC
BURIED LOGIC MACROCELL
OLMC
OUTPUT LOGIC MACROCELL
Pin Names
Description
Using a high performance E2CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24pin, 300-mil package.
I0 - I10
INPUT
I/O/Q
BIDIRECTIONAL
ICLK
INPUT CLOCK
VCC
POWER (+5)
OCLK
OUTPUT CLOCK
GND
GROUND
Pin Configuration
DIP
PLCC
I
I/O/Q
NC
2
28
5
I
I
I/O/Q
I
NC
I
Top View
9
23
21
I
11
I/O/Q
I/O/Q
GND
19
18
16
OCLK
14
I
I
12
NC
I
I/O/Q
I
I/O/Q
GAL6001
Vcc
26
25
7
24
I/O/Q
I
Advanced features that simplify programming and reduce test time,
coupled with E2CMOS reprogrammable cells, enable 100% AC, DC,
programmability, and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
1
I
I/O/Q
4
Vcc
I
I
I/ICLK
I/ICLK
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
I/O/Q
I
6
I/O/Q
GAL
6001
I/O/Q
I/O/Q
18
I/O/Q
NC
I
I/O/Q
I
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
I
I/O/Q
I
I/O/Q
GND
12
13
OCLK
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6001_02
1
July 1997
Specifications GAL6001
GAL6001 Ordering Information
Commercial Grade Specifications
Tpd (ns)
Fmax (MHz)
Icc (mA)
Ordering #
Package
30
27
150
GAL6001B-30LP
24-Pin Plastic DIP
150
GAL6001B-30LJ
28-Lead PLCC
Part Number Description
XXXXXXXX _ XX
X
X X
GAL6001B Device Name
Grade
Speed (ns)
L = Low Power
Power
Blank = Commercial
Package P = Plastic DIP
J = PLCC
2
Specifications GAL6001
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
The GAL6001 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is configurable
as a block for asynchronous, latched, or registered inputs. Pin 1
(ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Configurable input blocks
provide system designers with unparalleled design flexibility. With
the GAL6001, external registers and latches are not necessary.
Both the ILMC and the IOLMC are block configurable. However,
the ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations are shown in the macrocell equivalent
diagrams on the following pages.
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND array, are available at the device pins. Cells in this group are known
as Output Logic Macrocells (OLMC).
When the macrocell is configured as a D-type register with a sum
term clock, the register is always enabled and its “E” sum term is
routed directly to the clock input. This permits asynchronous programmable clocking, selected on a register-by-register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are reset
to a logic zero. If connected to an output pin, a logic one will occur because of the inverting output buffer.
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinatorial, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the “D” XOR.
Polarity selection is available for BLMCs, since both the true and
complemented forms of their outputs are available in the AND array.
Polarity of all “E” sum terms is selected through the “E” XOR.
There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer and always present). When the OLMC is used as an output, the second feedback path is through the IOLMC. With this dual
feedback arrangement, the OLMC can be permanently buried (the
associated OLMC pin is an input), or dynamically buried with the
use of the output enable product term.
The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS-, JK-, and T-type registers with the same efficiency as a dedicated RS-, JK-, or T-register.
When the macrocell is configured as a D/E type register, it is clocked
from the common OCLK and the register clock enable input is controlled by the associated “E” sum term. This configuration is useful
for building counters and state-machines with state hold functions.
The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.
3
Specifications GAL6001
ILMC and IOLMC Configurations
ICLK
LATCH
E
Q
MUX
D
INVALID
REG.
0
0
0
1
10
INPUT
or I/O
10
Q
1
0
1
1
D
LATCH
ISYN
ILMC/IOLMC
Generic Logic Block Diagram
ILMC (Input Logic Macrocell)
JEDEC Fuse Numbers
ISYN
8218
IOLMC (I/O Logic Macrocell)
JEDEC Fuse Numbers
LATCH
8219
ISYN
8220
4
LATCH
8221
AND
ARRAY
Specifications GAL6001
OLMC and BLMC Configurations
OE
PRODUCT
TERM
AND
ARRAY
RESET
IOLMC
MUX
OLMC ONLY
XORD(i)
1
R
I/O
D
D
MUX
Vcc
0
Q
0
E
OLMC ONLY
XORE(i)
OSYN(i)
1
E
CKS(i)
MUX
0
1
OCLK
OLMC/BLMC
Generic Logic Block Diagram
OLMC (Output Logic Macrocell)
BLMC (Buried Logic Macrocell)
JEDEC Fuse Numbers
JEDEC Fuse Numbers
OLMC
OCLK
OSYN
XORE
XORD
BLMC
OCLK
OSYN
XORE
0
8178
8179
8180
8181
7
8175
8176
8177
1
8182
8183
8184
8185
6
8172
8173
8174
2
8186
8187
8188
8189
5
8169
8170
8171
3
8190
8191
8192
8193
4
8166
8167
8168
4
8194
8195
8196
8197
3
8163
8164
8165
5
8198
8199
8200
8201
2
8160
8161
8162
6
8202
8203
8204
8205
1
8157
8158
8159
7
8206
8207
8208
8209
0
8154
8155
8156
8
8210
8211
8212
8213
9
8214
8215
8216
8217
5
11(13)
9(11)
10(12)
8(10)
LTC H.
7(9)
6(7)
5(6)
4(5)
3(4)
2(3)
1(2)
ICLK
MU X
R EG.
6
BLMC 7
BLMC 6
BLMC 5
BLMC 4
BLMC 3
BLMC 2
BLMC 1
BLMC 0
OLMC 9
OLMC 8
OLMC 7
OLMC 6
OLMC 5
OLMC 4
OLMC 3
OLMC 2
OLMC 1
OLMC 0
IOLMC 0
IOLMC 1
IOLMC 2
IOLMC 3
LTCH.
IOLMC 4
IOLMC 5
IOLMC 6
IOLMC 7
IOLMC 8
IOLMC 9
Specifications GAL6001
GAL6001 Logic Diagram
REG.
MUX
7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
R
R
R
R
R
R
R
R
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XORE
BLMC 0
XORE
BLMC 1
XORE
BLMC 2
XORE
BLMC 3
XORE
BLMC 4
XORE
BLMC 5
XORE
BLMC 6
XORE
BLMC 7
The number of Differential Product Terms that may
switch is limited to a maximum of 15. Refer to the
Differential Product Term Switching Applications section of this data sheet for a full explanation.
OCLK
RESET
OLMC 9
XORE
XORD
OLMC 0
XORE
XORD
OLMC 1
XORE
XORD
OLMC 2
XORE
XORD
OLMC 3
XORE
XORD
OLMC 4
XORE
XORD
OLMC 5
XORE
XORD
OLMC 6
XORE
XORD
OLMC 7
XORE
XORD
OLMC 8
XORE
XORD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
R
R
R
R
R
R
R
R
R
R
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
13(16)
14(17)
15(18)
16(19)
17(20)
18(21)
19(23)
20(24)
21(25)
22(26)
23(27)
Specifications GAL6001
GAL6001 Logic Diagram (Continued)
Specifications GAL6001
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Ambient Temperature with
Power Applied ........................................ –55 to 125°C
Commercial Devices:
Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL
IIH
VOL
VOH
IOL
IOH
IOS1
MIN.
TYP.2
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
-10
µA
Input or I/O High Leakage Current
3.5VIH ≤ VIN ≤ VCC
—
—
10
µA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
–30
—
–130
mA
—
90
150
mA
Output Short Circuit Current
COMMERCIAL
ICC
Operating Power
Supply Current
VIL = 0.5V
VCC = 5V VOUT = 0.5V
VIH = 3.0V
L -30
ftoggle = 15MHz Outputs Open
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25 °C
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
10
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
8
Specifications GAL6001
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
TEST
COND1.
COM
-30
DESCRIPTION
MIN. MAX.
UNITS
tpd1
tpd2
tpd3
A
Combinatorial Input to Combinatorial Output
—
30
ns
A
Feedback or I/O to Combinatorial Output
—
30
ns
A
Transparent Latch Input to Combinatorial Output
—
35
ns
tco1
tco2
tco3
A
Input Latch ICLK to Combinatorial Output Delay
—
35
ns
A
Input Reg. ICLK to Combinatorial Output Delay
—
35
ns
A
Output D/E Reg. OCLK to Output Delay
—
12
ns
tco4
tsu1
tsu2
tsu3
tsu4
tsu5
tsu6
th1
th2
th3
th4
fmax
twh1
twh2
twl1
twl2
tarw
ten
tdis
tar
tarr1
tarr2
A
Output D Reg. Sum Term CLK to Output Delay
—
35
ns
—
Setup Time, Input before Input Latch ICLK
2.5
—
ns
—
Setup Time, Input before Input Reg. ICLK
2.5
—
ns
—
Setup Time, Input or Feedback before D/E Reg. OCLK
25
—
ns
—
Setup Time, Input or Feedback before D Reg. Sum Term CLK
7.5
—
ns
—
Setup Time, Input Reg. ICLK before D/E Reg. OCLK
30
—
ns
—
Setup Time, Input Reg. ICLK before D Reg. Sum Term CLK
15
—
ns
—
Hold Time, Input after Input Latch ICLK
5
—
ns
—
Hold Time, Input after Input Reg. ICLK
5
—
ns
—
Hold Time, Input or Feedback after D/E Reg. OCLK
0
—
ns
—
Hold Time, Input or Feedback after D Reg. Sum Term CLK
10
—
ns
—
Maximum Clock Frequency, OCLK
27
—
MHz
—
ICLK or OCLK Pulse Duration, High
10
—
ns
—
Sum Term CLK Pulse Duration, High
15
—
ns
—
ICLK or OCLK Pulse Duration, Low
10
—
ns
—
Sum Term CLK Pulse Duration, Low
15
—
ns
—
Reset Pulse Duration
15
—
ns
B
Input or I/O to Output Enabled
—
25
ns
C
Input or I/O to Output Disabled
—
25
ns
A
Input or I/O to Asynchronous Reg. Reset
—
35
ns
—
Asynchronous Reset to OCLK Recovery Time
20
—
ns
—
Asynchronous Reset to Sum Term CLK Recovery Time
10
—
ns
1) Refer to Switching Test Conditions section.
9
Specifications GAL6001
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
tsu2
tpd1,2
COMBINATORIAL
OUTPUT
th2
ICLK (REGISTER)
tco2
Combinatorial Output
COMBINATORIAL
OUTPUT
tsu5
INPUT or
I/O FEEDBACK
VALID INPUT
tsu1
OCLK
th1
tsu6
ICLK (LATCH)
Sum Term CLK
tco1
tpd3
COMBINATORIAL
OUTPUT
Registered Input
Latched Input
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
tsu4
VALID INPUT
tsu3
th4
th3
OCLK
Sum Term CLK
tco3
tco4
1/ fmax
REGISTERED
OUTPUT
REGISTERED
OUTPUT
Registered Output (Sum Term CLK)
Registered Output (OCLK)
INPUT or
I/O FEEDBACK
tdis
ten
INPUT or
I/O FEEDBACK
DRIVING AR
OUTPUT
tarw
REGISTERED
OUTPUT
Input or I/O to Output Enable/Disable
tar
twh1
twl1
Sum Term CLK
ICLK or
OCLK
tarr2
twh2
twl2
OCLK
Sum Term CLK
tarr1
Asynchronous Reset
Clock Width
10
Specifications GAL6001
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
ARRAY
REGISTER
tsu
tco
fmax with External Feedback 1/(tsu+tco)
t cf
t pd
Note: fmax with external feedback is calculated from measured
tsu and tco.
LOGIC
ARRAY
CLK
fmax with Internal Feedback 1/(tsu+tcf)
REGISTER
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
+5V
3ns 10% – 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Output Load Conditions (see figure)
R1
R2
CL
300Ω
390Ω
50pF
Active High
∞
390Ω
50pF
Active Low
300Ω
390Ω
50pF
Active High
∞
390Ω
5pF
Active Low
300Ω
390Ω
5pF
Test Condition
A
B
C
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
11
Specifications GAL6001
Array Description
Bulk Erase
The GAL6001 contains two E2 reprogrammable arrays. The first
is an AND array and the second is an OR array. These arrays are
described in detail below.
Before writing a new pattern into a previously programmed part,
the old pattern must first be erased. This erasure is done automatically by the programming hardware as part of the programming
cycle and takes only 50 milliseconds.
AND ARRAY
The AND array is organized as 78 inputs by 75 product term outputs. The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC
feedbacks, and ICLK comprise the 39 inputs to this array (each
available in true and complement forms). 64 product terms serve
as inputs to the OR array. The RESET product term generates the
RESET signal described in the Output and Buried Logic Macrocells
section. There are 10 output enable product terms which allow
device pins 14-23 to be bi-directional or tri-state.
Register Preload
When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because in system operation, certain events
may occur that cause the logic to assume an illegal state: powerup, brown out, line voltage glitches, etc. To test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (i.e., illegal) into the
registers. Then the machine can be sequenced and the outputs
tested for correct next state generation.
OR ARRAY
The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the OR
array. Of the 36 sum term outputs, 18 are data (“D”) terms and 18
are enable/clock (“E”) terms. These terms feed into the 10 OLMCs
and 8 BLMCs, one “D” term and one “E” term to each.
All of the registers in the GAL6001 can be preloaded, including the
ILMC, IOLMC, OLMC, and BLMC registers. In addition, the contents of the state and output registers can be examined in a special
diagnostics mode. Programming hardware takes care of all preload
timing and voltage requirements.
The programmable OR array offers unparalleled versatility in product term usage. This programmability allows from 1 to 64 product
terms to be connected to a single sum term. A programmable OR
array is more flexible than a fixed, shared, or variable product term
architecture.
Latch-Up Protection
GAL6001 devices are designed with an on-board charge pump to
negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any possibility of SCR induced latching.
Electronic Signature
An electronic signature (ES) is provided in every GAL6001 device.
It contains 72 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
Input Buffers
GAL devices are designed with TTL level compatible input buffers.
These buffers, with their characteristically high impedance, load
driving logic much less than traditional bipolar devices. This allows for a greater fan out from the driving logic.
NOTE: The ES is included in checksum calculations. Changing the
ES will alter the checksum.
Security Cell
GAL6001 devices do not possess active pull-ups within their input
structures. As a result, Lattice Semiconductor recommends that
all unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise
immunity and reduce Icc for the device.
A security cell is provided in every GAL6001 device as a deterrent
to unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the AND and OR arrays.
This cell can be erased only during a bulk erase cycle, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user,
regardless of the state of this control cell.
12
Specifications GAL6001
Power-Up Reset
Vcc
Vcc (min.)
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL6001 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1µs MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
of system power-up, some conditions must be met to provide a
valid power-up reset of the GAL6001. First, the VCC rise must
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse
width requirements.
Differential Product Term Switching (DPTS) Applications
The number of Differential Product Term Switching (DPTS ) for
a given design is calculated by subtracting the total number of
product terms that are switching from a Logical HI to a Logical LO
from those switching from a Logical LO to a Logical HI within a
5ns period. After subtracting take the absolute value.
simultaneously - there is no limit on the number of product terms
that can be used.
A software utility is available from Lattice Semiconductor
Applications Engineering that will perform this calculation on any
GAL6001 JEDEC file. This program, DPTS, and additional
information may be obtained from your local Lattice
Semiconductor representative or by contacting Lattice
Semiconductor's Applications Engineering Dept. (Tel: 503-6810118 or 1-888-ISP-PLDS; FAX: 681-3037).
DPTS = (P-Terms)LH - (P-Terms)HL
DPTS restricts the number of product terms that can be switched
13
Specifications GAL6001
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
1.2
1.1
PT L->H
1
0.9
0.8
RISE
1.1
FALL
1
0.9
1.1
PT L->H
1
0.9
0.8
0.8
4.50
4.75
5.00
5.25
5.50
4.50
4.75
Supply Voltage (V)
Normalized Tpd vs Temp
5.00
5.25
4.50
5.50
1.1
PT L->H
1
0.9
0.8
0
25
50
75
100
1.4
1.2
RISE
1.1
FALL
1
0.9
0.8
-25
0
25
50
75
100
Delta Tpd vs # of Outputs
Switching
PT L->H
1.1
1
0.9
0.8
125
-55
-25
0
25
0
-0.5
-1
RISE
-1.5
FALL
-2
-0.5
-1
RISE
-1.5
FALL
-2
1
2
3
4
5
6
7
8
9
10
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
12
10
RISE
8
FALL
Delta Tco (ns)
12
6
4
2
10
RISE
8
FALL
6
4
2
0
0
-2
-2
0
50
100
150
200
250
300
0
50
100
150
200
250
Output Loading (pF)
Output Loading (pF)
14
50
75
100
Temperature (deg. C)
Delta Tco vs # of Outputs
Switching
0
Delta Tpd (ns)
PT H->L
1.2
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd (ns)
1.3
0.7
-55
125
5.50
Normalized Tsu vs Temp
Delta Tco (ns)
-25
5.25
Normalized Tco vs Temp
0.7
0.7
5.00
Supply Voltage (V)
Normalized Tsu
PT H->L
Normalized Tco
1.2
4.75
Supply Voltage (V)
1.3
1.3
-55
PT H->L
Normalized Tsu
PT H->L
Normalized Tco
Normalized Tpd
1.2
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
300
125
Specifications GAL6001
Typical AC and DC Characteristic Diagrams
Voh vs Ioh
5
2
4
1.5
1
0.5
4.5
4.25
3
2
0
0.00
20.00
40.00
60.00
80.00
3.5
0.00
10.00
20.00
30.00
40.00
50.00
1.00
2.00
3.00
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.00
0.90
1.1
Normalized Icc
Normalized Icc
1.10
1
0.9
0.8
0.7
4.75
5.00
5.25
5.50
Supply Voltage (V)
-25
0
25
75
100
125
Temperature (deg. C)
0
10
30
40
Iik (mA)
20
2
1.5
1
50
60
70
80
0.5
90
100
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
1.00
0.90
-2.00
-1.50
-1.00
Vik (V)
15
-0.50
0
25
50
75
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
2.5
1.10
0.80
-55
3
4.00
1.20
1.2
0.80
Delta Icc (mA)
0.00
60.00
Iol (mA)
1.20
4.50
4
3.75
1
0
Normalized Icc
Voh vs Ioh
Voh (V)
2.5
Voh (V)
Vol (V)
Vol vs Iol
0.00
100