IDT IDT74FCT16270TPFB

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT
R/W BUFFER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
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The FCT162701T/AT is an 18-bit Read/Write buffer with
a four deep FIFO and a read-back latch. It can be used as
a read/write buffer between a CPU and memory or to
interface a high-speed bus and a slow peripheral. The Ato-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is
indicated by the full flag (FF). The B-to-A (read) path has a
latch. A HIGH on LE, allows data to flow transparently from
B-to-A. A LOW on LE allows the data to be latched on the
falling edge of LE.
The FCT162701T/AT has a balanced output drive with
series termination. This provides low ground bounce,
minimal undershoot and controlled output edge rates.
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40°C to +85°C
Balanced Output Drivers:
±24mA (commercial),
±16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V, TA = 25°C
Ideal for new generation x86 write-back cache solutions
Suitable for modular x86 architectures
Four deep write FIFO
Latch in read path
Synchronous FIFO reset
FUNCTIONAL BLOCK DIAGRAM
A1-18
18
OEBA
RESET
CLK
WCE
FIFO
(4 deep)
LATCH
LE
RCE
FF
OEAB
18
2915 drw 01
B1-18
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
5.15
AUGUST 1996
DSC-2915/3
1
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB
1
56
RCE
OEAB
1
56
RCE
WCE
2
55
CLK
WCE
2
55
CLK
A1
3
54
B1
A1
3
54
B1
GND
4
53
GND
GND
4
53
GND
A2
5
52
B2
A2
5
52
B2
A3
6
51
B3
A3
6
51
B3
VCC
7
50
VCC
VCC
7
50
VCC
A4
8
49
B4
A4
8
49
B4
A5
9
48
B5
A5
9
48
B5
A6
10
47
B6
A6
10
47
B6
GND
11
46
GND
GND
11
46
GND
A7
12
45
B7
A7
12
45
B7
A8
13
44
B8
A8
13
44
B8
A9
14
B9
A9
14
43
B9
A10
15
SO56-1 43
SO56-2
SO56-3 42
B10
A10
15
42
B10
A11
16
41
B11
A11
16
41
B11
A12
17
40
B12
A12
17
40
B12
GND
18
39
GND
GND
18
39
GND
A13
19
38
B13
A13
19
38
B13
A14
20
37
B14
A14
20
37
B14
A15
21
36
B15
A15
21
36
B15
VCC
22
35
VCC
VCC
22
35
VCC
A16
23
34
B16
A16
23
34
B16
A17
24
33
B17
A17
24
33
B17
GND
25
32
GND
GND
25
32
GND
A18
26
31
B18
A18
26
31
B18
OEBA
27
30
FF
OEBA
27
30
FF
LE
28
29
RESET
LE
28
29
RESET
SSOP/
TSSOP/TVSOP
TOP VIEW
E56-1
CERPACK
TOP VIEW
2915 drw 02
5.15
2915 drw 03
2
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
I/O
A1-18
I/O
18 bit I/O port.
B1-18
I/O
18 bit I/O port.
CLK
I
WCE
RCE
FF
RESET
OEAB
OEBA
LE
Description
I
Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is
low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the
FIFO are inhibited. CLK also resets the FIFO when RESET is low.
Enable pin for FIFO input clock.
I
Enable pin for FIFO output clock.
O
Write path FIFO full flag. Goes low when FIFO is full.
I
I
Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the
"empty" condition and FIFO output is forced high (all ones). The FIFO full flag (FF) will be high
immediately after reset.
Output Enable pin for B port.
I
Output Enable pin for A port.
I
Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched
on the falling edge of LE.
2915 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
(3)
Terminal Voltage with Respect to
VTERM
–0.5 to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
Unit
V
I OUT
mA
DC Output Current
–60 to +120
Symbol
Parameter(1)
CIN
Input
Capacitance
CI/O
I/O
Capacitance
V
°C
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
Max. Unit
6.0
pF
8.0
NOTE:
1. This parameter is measured at characterization but not tested.
pF
2915 lnk 03
2915 lnk 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.15
3
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
This device is useful as a read/write buffer for modular high
end designs. It provides multi-level buffering in the write path
and single deep buffering in the read path, and is suited to
write back cache implementation. The read path provides a
transparent latch.
The four deep FIFO uses one clock with two clock enable
pins, WCE and RCE to clock data in and out. The FIFO has
an external full flag which goes LOW when the FIFO is full.
Internal read and write pointers keep track of the words stored
in the FIFO. A write attempt to a full FIFO is ignored. An
attempt to read from an empty FIFO will have no effect and the
last read data remains at the output of the FIFO. The FIFO
may be reset by the synchronous RESET input. This resets
the read and write pointers to the original "empty" condition
and also sets all B outputs = 1. Simultaneous read and write
attempts (clock data into FIFO as well as clock data out of
FIFO) are possible except on FIFO empty and full boundaries.
When the FIFO is empty, and a simultaneous read and write
is attempted, the read is ignored while the write is executed.
If the same is attempted when the FIFO is full, the write is
ignored while the read is executed. Normal operation of the
four deep FIFO in the write path is independent of the read
path operation.
Power, ground and data pin positions on the FCT162701T
match those on the FCT16501T/162501T, allowing an easy
upgrade.
APPLICATIONS: 486 INTERFACE
Coprocessor
CacheRAM
DRAM
i486
FCT162701T
B
A
W/R
CLK
CLK,WCE,
LE,OEBA,
RCE, RST
OEAB
PAL
2915 drw 04
Figure 1. FCT162701T Application Example
5.15
4
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current (Input pins)(5)
Symbol
VIH
Min.
2.0
Typ.(2)
—
Max.
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
±1
µA
—
—
±1
VI = GND
—
—
±1
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
II L
Input LOW Current (Input
Input LOW Current (I/O
I OZH
pins)(5)
pins)(5)
High Impedance Output Current
VCC = Max.
pins) (5)
—
Unit
V
µA
I OZL
(3-State Output
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
I OS
Short Circuit Current
VCC = Max., VO = GND (3)
–80
–140
–225
mA
VH
Input Hysteresis
—
100
—
mV
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
—
5
500
µA
—
VCC = Max., VIN = GND or VCC
2915 lnk 04
OUTPUT DRIVE CHARACTERISTICS
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
60
Typ.(2)
115
Max.
200
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–60
–115
–200
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or V IL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.55
V
I OH = –16mA MIL.
I OH = –24mA COM'L.
I OL = 16mA MIL.
I OL = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.15
2915 lnk 05
5
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPLY CHARACTERISTICS
Symbol
∆ICC
ICCD (CLK)
ICCD (O/P)
IC
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
due to clock switching (4)
Dynamic Power Supply Current
due to output switching(4)
Total Power Supply Current (6)
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
CLK Toggling
Outputs Open 50% Duty Cycle
One Bit Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP= 10MHz
50% Duty Cycle
OEAB = GND; OEBA = VCC
LE = WCE = RCE = GND
RESET = VCC
All Inputs Low
VCC = Max.
Outputs Open
fCP= 10MHz
50% Duty Cycle
OEAB = GND; OEBA = VCC
LE = WCE = RCE = GND
RESET = VCC
One Bit Toggling
at fo = 5MHz
50% Duty Cycle
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
—
180
240
µA/
MHz
—
80
120
VIN = VCC
VIN = GND
—
1.8
2.9 (5)
VIN = 3.4V
VIN = GND
—
2.1
3.7 (5)
VIN = VCC
VIN = GND
—
2.2
3.5
VIN = 3.4V
VIN = GND
—
2.7
5.0
VIN = VCC
VIN = GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN) = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (CLK) X fCP + ICCD (O/P) x fO NO
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at D
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fO = Output Frequency
NO = Number of Outputs at fO
5.15
mA
2915 tbl 06
6
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162701T
Parameter
FCT162701AT
Min.(2)
Max.(2)
Min.(2)
Max.(2)
Unit
Read path/latch
1.5
6.5
1.5
5.5
ns
Test
Conditions(1)
PROPAGATION DELAYS
1
B1-18 to A 1-18
2
LE (Low to Hi) to A 1-18
Read path/latch
1.5
5.7
1.5
4.7
ns
3
CLK to FF
Write path
2
7.0
2
6.0
ns
4
CLK to B 1-18
Write path
1
6.0
1
5.2
ns
SETUP & HOLD
TIMES(3)
5
A1-18 to CLK (Low to Hi) Setup
Write path
2.5
—
2.5
—
ns
6
A1-18 to CLK (Low to Hi) Hold
Write path
0
—
0
—
ns
7
B1-18 to LE (Hi to Low) Setup
Read path/latch
3
—
3
—
ns
8
B1-18 to LE (Hi to Low) Hold
Read path/latch
0
—
0
—
ns
Write path
3
—
3
—
ns
Write path
0
—
0
—
ns
Write path
3
—
3
—
ns
Write path
0
—
0
—
ns
Write path
1.5
7.0
1.5
6.0
ns
Write path
1.5
6.0
1.5
5.0
ns
Read path
1.5
7.0
1.5
6.0
ns
Read path
1.5
6.0
1.5
5.0
ns
9
10
11
12
WCE, RCE (Low) to CLK Setup
WCE, RCE (Low) to CLK Hold
RESET (Low) to CLK Setup
RESET (Low) to CLK Hold
ENABLE & DISABLE
13
14
15
16
TIMES(3)
OEBA Low to A 1-18 Enable
OEBA High to A 1-18 Disable
OEAB Low to B 1-18 Enable
OEAB High to B 1-18 Disable
MINIMUM PULSE WIDTHS
17
CLK HIGH or LOW Pulse Width
Write path
3.0
—
3.0
—
ns
18
LE HIGH Pulse Width
Read path/latch
3.0
—
3.0
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Guaranteed but not tested.
2915 tbl 07
5.15
7
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
500Ω
Switch
Open Drain
Disable Low
Closed
Enable Low
V OUT
VIN
Pulse
Generator
Test
7.0V
Open
All Other Tests
D.U.T.
50pF
RT
2915 lnk 07
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2915 drw 04
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2915 drw 06
3V
1.5V
0V
tH
2915 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
0V
CONTROL
INPUT
tPZL
VOH
1.5V
VOL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
tPZH
OUTPUT
NORMALLY
HIGH
2915 drw 07
SWITCH
OPEN
3.5V
3.5V
1.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2915 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.15
8
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
FCT XXXX
X
Device
Temperature
Type
Range
X
Package
X
Process
Blank
B
PV
PA
PF
E
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
162701T
162701AT
18-Bit R/W Buffer
54
74
-55°C to +125°C
-40°C to +85°C
2915 drw 09
5.15
9