IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE FAST CMOS 18-BIT READ/WRITE BUFFER IDT74FCT162701T/AT FEATURES: DESCRIPTION: • • • • The FCT162701T is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to interface a high-speed bus and a slow peripheral. The A-to-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. A high on LE, allows data to flow transparently from B-to-A. A low on LE allows the data to be latched on the falling edge of LE. The FCT162701T has a balanced output drive with series termination. This provides low ground bounce, minimal undershoot and controlled output edge rates. • • • • • • • • • 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps Low input and output leakage ≤ 1µA (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Balanced Output Drivers (±24mA) Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C Ideal for new generation x86 write-back cache solutions Suitable for modular x86 architectures Four deep write FIFO Latch in read path Synchronous FIFO reset Available in SSOP and TSSOP packages FUNCTIONAL BLOCK DIAGRAM A 1-18 18 OEB A RESE T CLK W CE FIFO (4 deep) LATCH LE RCE FF OEA B 18 B 1-18 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2002 1 © 2002 Integrated Device Technology, Inc. DSC-2915/1 IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION OEAB ABSOLUTE MAXIMUM RATINGS(1) 56 1 Symbol RCE W CE 2 55 CLK A1 3 54 B1 GND 4 53 GND A2 5 52 B2 A3 6 51 B3 V CC 7 50 V CC A4 8 49 B4 A5 9 48 B5 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 A9 14 43 B9 Description VTERM(2) Terminal Voltage with Respect to GND Max Unit –0.5 to 7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX. A 10 15 42 B 10 A 11 16 41 B 11 A 12 17 40 B 12 GND 18 39 GND Symbol A 13 19 38 B 13 CIN Input Capacitance VIN = 0V 3.5 6 pF A 14 20 37 B 14 COUT Output Capacitance VOUT = 0V 3.5 8 pF A 15 21 36 B 15 V CC 22 35 V CC A 16 23 34 B 16 A 17 24 33 B 17 GND 25 32 GND A 18 26 31 B 18 OEBA 27 30 FF LE 28 29 RESET CAPACITANCE (TA = +25°C, f = 1.0MHz) Parameter(1) Conditions Typ. Max. Unit NOTE: 1. This parameter is measured at characterization but not tested. SSOP/ TSSOP TOP VIEW PIN DESCRIPTION Pin Names I/O Description A1-18 I/O 18 bit I/O port B1-18 I/O 18 bit I/O port CLK I Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the FIFO are inhibited. CLK also resets the FIFO when RESET is low. WCE I Enable pin for FIFO input clock RCE I Enable pin for FIFO output clock FF O Write path FIFO full flag. Goes low when FIFO is full. RESET I Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the “empty” condition and FIFO output is forced high (all ones). The FIFO full flag (FF) will be high immediately after reset. OEAB I Output Enable pin for B port OEBA I Output Enable pin for A port LE I Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched on the falling edge of LE. 2 IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION input. This resets the read and write pointers to the original "empty" condition and also sets all B outputs = 1. Simultaneous read and write attempts (clock data into FIFO as well as clock data out of FIFO) are possible except on FIFO empty and full boundaries. When the FIFO is empty, and a simultaneous read and write is attempted, the read is ignored while the write is executed. If the same is attempted when the FIFO is full, the write is ignored while the read is executed. Normal operation of the four deep FIFO in the write path is independent of the read path operation. Power, ground and data pin positions on the FCT162701T match those on the FCT16501T/162501T, allowing an easy upgrade. This device is useful as a read/write buffer for modular high end designs. It provides multi-level buffering in the write path and single deep buffering in the read path, and is suited to write back cache implementation. The read path provides a transparent latch. The four deep FIFO uses one clock with two clock enable pins, WCE and RCE to clock data in and out. The FIFO has an external full flag which goes LOW when the FIFO is full. Internal read and write pointers keep track of the words stored in the FIFO. A write attempt to a full FIFO is ignored. An attempt to read from an empty FIFO will have no effect and the last read data remains at the output of the FIFO. The FIFO may be reset by the synchronous RESET APPLICATIONS486 INTERFACE Coprocessor CacheRA M DRAM i486 FCT162701T B A W /R CLK CLK,W CE, LE,O EBA, RCE, RST O EAB PAL Figure 1. FCT162701T Application Example 3 IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10% Symbol VIH Input HIGH Level VIL Input LOW Level IIH Test Conditions(1) Min. Typ.(2) Max. Unit Guaranteed Logic HIGH Level 2 — — V Guaranteed Logic LOW Level — — 0.8 V — — ±1 µA — — ±1 — — ±1 — — ±1 VO = 2.7V — — ±1 VO = 0.5V — — ±1 Parameter (4) Input HIGH Current (Input pins) VCC = Max. VI = VCC (4) Input HIGH Current (I/O pins) IIL (4) Input LOW Current (Input pins) VI = GND (4) Input LOW Current (I/O pins) IOZH High Impedance Output Current VCC = Max. (4) µA IOZL (3-State Output pins) VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V IOS Short Circuit Current VCC = Max., VO = GND(3) –80 –140 –250 mA VH Input Hysteresis — 100 — mV ICCL ICCH ICCZ Quiescent Power Supply Current — 5 500 µA Min. Typ.(2) Max. Unit 1.5V(3) 60 115 200 mA — VCC = Max. VIN = GND or VCC OUTPUT DRIVE CHARACTERISTICS Symbol Test Conditions(1) Parameter IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VO = IODH Output HIGH Current VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) –60 –115 –200 mA VOH Output HIGH Voltage VCC = Min. IOH = –24mA 2.4 3.3 — V IOL = 24mA — 0.3 0.55 V VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. The test limit of this parameter is ±5µA at TA = –55°C. 4 IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Test Conditions(1) Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD (CLK) Dynamic Power Supply Current due to clock switching(4) VCC = Max. Outputs Open ICCD (O/P) Dynamic Power Supply Current due to clock switching(4) IC Total Power Supply Current(6) CLK Toggling 50% Duty Cycling VIN = VCC VIN = GND One Input Toggling 50% Duty Cycle Min. Typ.(2) Max. Unit — 0.5 1.5 µA — 180 240 µA/ MHz — 80 120 VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle VIN = VCC VIN = GND — 1.8 2.9(5) OEAB = GND; OEBA = VCC LE = WCE = RCE = GND RESET = VCC All Inputs Low VIN = 3.4V VIN = GND — 2.1 3.7(5) VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle VIN = VCC VIN = GND — 2.2 3.5 OEAB = GND; OEBA = VCC LE = WCE = RCE = GND RESET = VCC VIN = 3.4V VIN = GND — 2.7 5 One Bit Toggling at fO = 5MHz 50% Duty Cycle NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (CLK) x fCP + ICCD (O/P) x fO NO ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fO = Output Frequency NO = Number of Outputs at fO 5 mA IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT162701T Test Conditions(1) Parameter FCT162701AT Min.(2) Max.(2) Min.(2) Max.(2) Unit ns PROPAGATION DELAYS 1 B1-18 to A 1-18 Read path/latch 1.5 6.5 1.5 5.5 2 LE (LOW to HIGH) to A 1-18 Read path/latch 1.5 5.7 1.5 4.7 ns 3 CLK to FF Write path 2 7 2 6 ns 4 CLK to B 1-18 Write path 1 6 1 5.2 ns SETUP & HOLD TIMES(3) 5 A1-18 to CLK (LOW to HIGH) Setup Write path 2.5 — 2.5 — ns 6 A1-18 to CLK (LOW to HIGH) Hold Write path 0 — 0 — ns 7 B1-18 to LE (HIGH to LOW) Setup Read path/latch 3 — 3 — ns 8 B1-18 to LE (HIGH to LOW) Hold Read path/latch 0 — 0 — ns 9 WCE, RCE (LOW) to CLK Setup Write path 3 — 3 — ns 10 WCE, RCE (LOW) to CLK Hold Write path 0 — 0 — ns 11 RESET (LOW) to CLK Setup Write path 3 — 3 — ns 12 RESET (LOW) to CLK Hold Write path 0 — 0 — ns ENABLE & DISABLE TIMES(3) 13 OEBA LOW to A 1-18 Enable Write path 1.5 7 1.5 6 ns 14 OEBA HIGH to A 1-18 Disable Write path 1.5 6 1.5 5 ns 15 OEAB LOW to B 1-18 Enable Read path 1.5 7 1.5 6 ns 16 OEAB HIGH to B 1-18 Disable Read path 1.5 6 1.5 5 ns MINIMUM PULSE WIDTHS 17 CLK HIGH or LOW Pulse Width Write path 3 — 3 — ns 18 LE HIGH Pulse Width Read path/latch 3 — 3 — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Guaranteed but not tested. 6 IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500 Ω V OUT V IN Pulse Generator D.U.T. 50pF RT 500 Ω Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL Test Circuits for All Outputs DATA INPUT tH t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t REM t SU 3V 1.5V 0V 3V 1.5V 0V LOW -HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW -HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Set-up, Hold, and Release Times ENABLE SAM E PHASE INPUT TRANSITION t PLH t PH L OUTPUT t PLH OPPOSITE PHASE INPUT TRANSITION t PH L 3V 1.5V 0V DISABLE 3V CONTROL INPUT 1.5V t PZL V OH 1.5V V OL OUTPUT NORMALLY LOW 3V 1.5V 0V SW ITCH CLOSED Propagation Delay SW ITCH OPEN 3.5V 3.5V 1.5V 0.3V t PZH OUTPUT NORMALLY HIGH 0V t PLZ V OL t PHZ 0.3V V OH 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 7 IDT74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX Temp. Range FCT XXX XXXX XX Family Device Type Package PV PA Shrink Small Outline Package Thin Shrink Small Outline Package 701T 701AT 18-Bit Read/W rite Buffer 162 Double-Density, 5 Volt, Balanced Drive 74 – 40°C to +85°C DATA SHEET DOCUMENT HISTORY 1/21/2002 Removed Military temp grade CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: [email protected] (408) 654-6459