Lattice Products Reliability Report First Quarter 2016 © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com Lattice Semiconductor Q1 2016 Lattice Products Reliability Report INDEX 1.0 INTRODUCTION .......................................................................................................................................................... 4 2.0 LATTICE RELIABILITY PROGRAM ........................................................................................................................... 4 3.0 FAILURE RATE CALCULATIONS AND PREDICTIONS ........................................................................................... 5 4.0 QUALIFICATION TESTING......................................................................................................................................... 6 5.0 PROCESS OVERVIEW ............................................................................................................................................. 11 6.0 RELIABILITY MONITORING ..................................................................................................................................... 14 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7.0 8.0 LATTICE RELIABILITY SUMMARY ......................................................................................................................... 17 RELIABILITY DATA BY PROCESS TECHNOLOGY ............................................................................................... 18 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 9.0 High Temperature Operating Life Monitor (HTOL) ............................................................................................................... 14 High Temperature Storage Life (HTSL) ................................................................................................................................ 14 High Temperature Data Retention (HTRX) ........................................................................................................................... 14 Surface Mount Preconditioning Testing (SMPC) .................................................................................................................. 14 Temperature Cycling (TC) .................................................................................................................................................... 14 Unbiased HAST (UHAST) .................................................................................................................................................... 15 Temperature Humidity Bias (THB) ........................................................................................................................................ 15 Biased HAST ........................................................................................................................................................................ 15 40LP (40nm SRAM) Process Technology ............................................................................................................................ 18 CS200A (65nm SRAM) Process Technology ....................................................................................................................... 19 CS200F (65nm Flash) Process Technology ......................................................................................................................... 20 CS100 A/L (90nm SRAM) Process Technology ................................................................................................................... 22 CS100F (90nm Flash) Process Technology ......................................................................................................................... 23 CS90A/L (130nm SRAM) Process Technology .................................................................................................................... 25 CS90F (130nm Flash) Process Technology ......................................................................................................................... 26 EE9 Process Technology ..................................................................................................................................................... 28 EE8 Process Technology ..................................................................................................................................................... 30 EE8A Process Technology ................................................................................................................................................... 31 UltraMOS VI Process Technology ........................................................................................................................................ 33 PACKAGE RELIABILITY DATA BY LOGIC TECHNOLOGY .................................................................................. 35 9.1 9.2 9.3 9.4 9.5 9.6 9.7 10.0 40nm node............................................................................................................................................................................ 35 65nm node............................................................................................................................................................................ 39 90nm node............................................................................................................................................................................ 44 130nm node.......................................................................................................................................................................... 47 0.18m node ........................................................................................................................................................................ 53 0.25m node ........................................................................................................................................................................ 55 0.35m and 1.0 m nodes .................................................................................................................................................. 59 ASSEMBLY RELIABILITY MONITOR DATA ....................................................................................................... 61 10.1 10.2 10.3 10.4 Temperature Cycling ............................................................................................................................................................ 61 Autoclave / Pressure Cooker ................................................................................................................................................ 63 Unbiased Highly Accelerated Stress Testing (uHAST) ......................................................................................................... 64 High Temperature Storage (HTS) ......................................................................................................................................... 66 11.0 PROCESS RELIABILITY WAFER LEVEL REVIEW ............................................................................................. 68 12.0 PACKAGE ASSEMBLY MONITORING DATA ..................................................................................................... 69 Lattice Semiconductor Corporation Doc 73-107566 Rev. A 2 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Dear Customer, Enclosed is Lattice Semiconductor’s Monitor Report for the First Quarter of 2016. New product data is in italics. This report provides updated reliability data for each process technology and package family included in the attached tables. The information in this report is drawn from an extensive program of wafer technology and packaging assembly monitoring performed by Lattice, along with our foundry partners and assembly suppliers, to improve all our Quality Systems. If you have suggestions to improve this report, we encourage you to forward them to your Lattice representative. Your feedback is valuable to Lattice. Sincerely, James M. Orr Vice President, Corporate Quality & Product Development Lattice Semiconductor Corporation Lattice Semiconductor Corporation Doc 73-107566 Rev. A 3 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 1.0 INTRODUCTION Oregon-based Lattice Semiconductor Corporation (Lattice) designs, develops and markets the broadest range of high-performance ISP programmable logic devices (PLDs), Field Programmable Gate Arrays (FPGAs) and Field Programmable System Chip (FPSC) devices. Lattice offers total solutions for today’s system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Lattice Semiconductor was founded in 1983 and is based in Hillsboro, Oregon. This report summarizes the reliability testing results for Lattice Semiconductor products as of March 2016. Detailed data for the testing described in this report is available on request. Please direct inquiries to Customer Requirements at [email protected]. 2.0 LATTICE RELIABILITY PROGRAM Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice products is assured through ongoing monitor programs as described in Reliability Monitor Program Procedure (Doc. #70-101667). All product qualification plans are generated in conformance with Lattice Semiconductor’s Qualification Policy (Doc. #70-100164) with failure analysis performed in conformance with Lattice Semiconductor’s Failure Analysis Procedure (Doc. #70-100166). Both documents are referenced in Lattice Semiconductor’s Quality Assurance Manual, which can be obtained upon request from the Lattice Semiconductor sales office. Failure rates in this reliability report are expressed in FITS. Due to the very low failure rate of integrated circuits, it is convenient to refer to failures in a population during a period of 10 9 device hours; one failure in 109 device hours is defined as one FIT. Product families are qualified based upon the requirements outlined in Tables 4.1 and 4.2. Ongoing production is monitored based on the requirements outlined in Table 4.3. In general, Lattice Semiconductor follows the current Joint Electron Device Engineering Council (JEDEC) and Military Standard testing methods. Lattice automotive products are qualified and characterized to the Automotive Electronics Council (AEC) testing requirements and methods. Product family qualification will include products with a wide range of circuit densities, package types, and package lead counts. Major changes to products, processes, or vendors require additional qualification before implementation. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 4 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 3.0 FAILURE RATE CALCULATIONS AND PREDICTIONS The long-term failure rate for a technology is gauged by a Failures In Time (FIT) calculation based upon accelerated stress data. The units for FIT are failures per Billion device hours. ( 2 / 2) 109 FITRate Accelerated Stress Device Hours The stress that enables FIT is High Temperature Operating Life (HTOL), which is a product level test. HTOL is accelerated by temperature and by voltage. The total number of failures in stress determines the chi-squared factor (a dimensionless number representing a 60% confidence level of statistics). The number of product units times the stress period (in Hours) is the “raw” device-Hours number. The Arrhenius equation uses the Activation energy for the fail mode as well as the stress temperature and the reporting temperature (e.g. 55C) to compute the HTOL temperature acceleration factor, AF(T). The accelerated stress device-Hours is AF(T) times the “Raw” device-Hours number. Lattice performs HTOL at Vccmax, which is 5% to 10% larger than the nominal Vcc, depending on the technology node. This does qualify as voltage acceleration, but convention dictates that AF(V) =1 in this case. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 5 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 4.0 QUALIFICATION TESTING Table 4.1: Standard Qualification Testing TEST High Temperature Operating Life HTOL High Temp Data Retention High Temp Storage Life STANDARD Lattice Procedure # 87-101943, MIL-STD-883 Method 1005.8, JESD22-A108 2 SAMPLE SIZE PERFORMED ON (Typ) 125° C at maximum operating 77 per lot Design, Fab Process Vcc 3 lots Package Qualification MachXO2 LatticeXP2 ispLSI-2K-5K-8K ispGDXV Preconditioned with 10,000 read/write cycles LatticeXP ispMACH-4K ispGDX2, ispCLK Products ispPAC-POWR ispGAL22LV Preconditioned with 1000 read/write cycles ORCA Products LatticeECP/EC LatticeECP2/M LatticeECP3 LatticeSC ICE40 Lattice Procedure # 87-101925, JESD22-A117 105° C Ambient, Maximum operating Vcc, 168, 500, 1000, 2000 101943. SRAM based – no preconditioning 150° C bake MachXO2 LatticeXP2 ispLSI-2K-5K-8K ispGDXV Preconditioned with 10,000 read/write cycles LatticeXP ispMACH-4K ispLSI-1K ispGDX2, ispCLK Products ispPAC-POWR ispGAL22LV Lattice Procedure # 87-101925, JESD22-A103 Preconditioned with 1000 read/write cycles SRAM based Products ORCA Products Lattice ECP/EC LatticeECP2/M LatticeECP3 LatticeSC ICE40 Endurance Lattice Procedure, Program/Erase # 70-104633 Cycling JESD22-A117 E Cell Products TEST CONDITIONS ispLSI, GAL, ispMACH Flash based Products MachXO, LatticeXP, Lattice XP2 77 per lot 3 lots Design, Fab Process, Package Qualification Only 2 E Cell Products Flash based Products 150° C bake 25 per lot 3 lots Design, Fab Process, Package Qualification Program/Erase devices to 100,000 cycles 25 per lot 3 lots Design, Fab Process, Package Qualification Program/Erase devices to 10X cycles of data sheet specification Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 6 Lattice Semiconductor TEST Q1 2016 STANDARD ESD HBM Human Body Model Lattice Procedure # 70-100844, MIL-STD-883 Method 3015.7 JS001 ESD CDM Lattice Procedure Charged Device model # 70-100844, JESD22-C101 Latch Up Resistance Lattice Procedure # 70-101570, JESD78 Surface Mount Preconditioning Lattice Procedure # 70-103467, IPC/JEDEC J-STD-020 JESD22-A113 Lattice Products Reliability Report TEST CONDITIONS SAMPLE SIZE PERFORMED ON (Typ) 3 per lot Design, Fab Process, 1-3 lots typical Package Qualification sweep to: 2000 volts (≥130nm) 1000 volts (≤90nm) sweep to: 1000 volts (≥130nm) 500 volts (≤90nm) ±100 ma on I/O's, Vcc +50% on Power Supplies. (Max operating temp.) 5 Temp cycles, 24 hr 125° C Bake FlipChip Packages MSL 4 96hr. 30/60 Soak 3 SMT simulation cycles CPLD/FPGA/FPSC - MSL 3 192hr. 30/60 Soak 3 SMT simulation cycles 3 per lot Design, Fab Process, 1-2 lots typical Package Qualification 3 per lot Design, Fab Process 1-2 lots typical All units going Plastic Packages only into HTSL, Temp Cycling, UnHAST, BHAST, 85/85 SPLD - MSL 1 168hr. 85/85 Soak 3 SMT simulation cycles. Temperature Cycling Lattice Procedure (700* cycles) Repeatedly #87-101932, cycled between -55° C and MIL-STD-883 Method 1010, Cond. +125° C in an air B environment JESD22-A104 Unbiased HAST Lattice Procedure 96 hrs, 130 C, # 78-104561 85% Relative Humidity JESD22-A118 or 264 hrs, 110 C, 85% Relative Humidity Moisture Resistance Lattice Procedure Biased to maximum operating Temperature Humidity # 87-101918/ Vcc, Bias 87-104561, 1000 hours 85° C, 85% 85/85 JESD22-A101 Relative Humidity, or Biased HAST 96 hrs, 130 C, 85% Relative JESD22-A110 Humidity or 264 hrs, 110 C, 85% Relative Humidity Physical Dimensions Lattice Procedure Measure all dimensions listed # 70-100211, on the case outline. MIL-STD-883 Method 2016 or applicable LSC case outline drawings Lead Integrity Lattice Procedure PDIP, CDIP packages # 70-100192, MIL-STD-883 Method 2004 25 per lot 3 lots Design, Fab Process, Package Qualification 25 per lot 3 lots Fab Process, Package Qualification Plastic Pkg. only 25 per lot 3 lots Design, Fab Process Package Qualification Plastic Pkg. only 5 devices Package Qualification 3 devices PDIP, CDIP package Qualification * changed from Q4’13 to conform with JESD47I Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 7 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Table 4.2: Reliability Monitor Testing TEST High Temperature Operating Life HTOL High Temp Data Retention (HTRX) High Temp Storage Life (HTSL) Surface Mount Preconditioning Temperature Cycling Unbiased HAST STD Lattice Procedure # 87-101943, MIL-STD-883 Method 1005.8, JESD22-A108 TEST CONDITIONS 125° C at maximum operating Vcc SAMPLE SIZE Early Life 300 per quarter typical PERFORMED ON Production Released Process Technologies MachXO2 LatticeXP2 ispLSI-2K-5K-8K ispGDXV Preconditioned with 10,000 read/write cycles Inherent Life 77 per quarter typical Sample Sizes are production volume based. LatticeXP ispMACH-4K ispLSI-1K ispGDX2, ispCLK Products ispPAC-POWR ispGAL22LV Preconditioned with 1000 read/write cycles GAL Products ispLSI-1K PAC Products Preconditioned with 100 read/write cycles ORCA Products LatticeECP/EC LatticeECP2/M LatticeECP3 LatticeSC ICE40 Lattice Procedure # 87-101925, JESD22-A117 Lattice Procedure # 87-101925, JESD22-A103 Lattice Procedure # 70-103467, IPC/JEDEC J-STD-020 JESD22-A113 105° C Ambient, Maximum operating Vcc, 48, 1000 hrs. SRAM based – no preconditioning 1000 hours bake at 150°C (unbiased) 77 per quarter Design, Fab Process, Package Qualification 1000 hours bake at 150°C. 45 per quarter Design, Fab Process, Package Qualification 5 Temp cycles, 24 hr 125° C Bake, moisture soak (below) + 3 reflow cycles Plastic Packages only FlipChip Packages MSL 4 96hr. 30/60 Soak All units going into HTSL, Temp Cycling, UnHAST, BHAST, 85/85 CPLD/FPGA/FPSC - MSL 3 192hr. 30/60 Soak SPLD MSL 1 Lattice Procedure #87-101932, MIL-STD-883, Method 1010, Cond. B JESD22-A104 Lattice Procedure # 87-104561 JESD22-A118 168hr. 85/85 Soak 700* cycles between -55° C and +125° C in an air environment 45 per quarter Design, Fab Process, Package Qualification 45 per quarter Fab Process, Package Qualification Plastic Pkg. only 96 hrs, 130 C, 85% Relative Humidity or 264 hrs, 110 C, 85% Relative Humidity * changed from Q4’13 to conform with JESD47I Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 8 Lattice Semiconductor Q1 2016 Temperature Humidity Lattice Procedure Bias (THB) # 87-101918/87-104561, Biased to maximum operating Vcc 85/85 JESD22-A101 1000 hours at 85° C, 85% Relative Humidity or Biased-HAST JES22-A110 96 hrs at 130 C, 85% Relative Humidity or 264 hrs at 110 C, 85% Relative Humidity Lattice Products Reliability Report 45 per quarter typical Selected Fab Process and Packages only Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 9 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Table 4.3: QA Package Monitor Testing TEST Incoming Assembly Inspection External Visual Scanning Acoustic Tomography Physical Dimensions STD Lattice Procedure# 94-102927 and # 94-102447 Lattice Procedure# 80-100000 # 70-103064 Lattice Procedure# 70-103772 IPC/JEDEC J-STD-035 Lattice Procedure# 70-100211 Resistance to Solvents Lattice Procedure# 70-100030, MIL-STD-883 Method 2015 X-Ray Lattice Procedure# 70-10330 Solderability Lattice Procedure# 70-100212, MIL-STD-883 Method 2003 TEST CONDITIONS Accept (0) Mark legible in one of 3 solutions. Monitor if mark is degrading. Steam Pre-conditioning 4-8 hours. Solder dip at 245°C+5°C Internal Visual - Decap Wire Bond Pull Lattice Procedure# 70-104056 Bond Shear Lattice Procedure# 70-104056 Ball Shear Lattice Procedure# 70-104056, # 70-100433 SAMPLE SIZE Various PERFORMED ON All packages All packages 10 units/ Package family All plastic packages except PDIP 3 units/ Package family All packages 3 units/ Package family All packages except laser marked 10 units/ Package family 22 leads/ 3 devices/ Package family/ 3 units/ Package family 3 units/ 30 bonds total 3 units/ 30 bonds total 3 units/ 30 balls total All plastic packages All packages except BGAs All packages All wirebonded packages All wirebonded packages BGA packages only Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 10 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 5.0 PROCESS OVERVIEW Table 5.1: Lattice Process Mapping LATTICE PROCESS INDUSTRY NODE 40LP/40LM 40nm CS200F CS200A CS100F CS100A/L/EC CS90F CS90A/L SMP-COM2 EE9 UM10 SMP-COM1 UltraMOS VIII 65nm 65nm 90nm 90nm 130 nm 130 nm 0.16 um 0.18 um 0.22 um 0.25 um 0.25 um EE8/EE8A 0.25 um CSM-F2 0.35 um UltraMOS VI 0.35 um UltraMOS V UltraMOS IV UltraMOS IVAR 0.65 um 1.0 um 1.0 um PRODUCTS iCE5LPxx (iCE40Ultra), iCE40ULxx (iCE40UltraLite), iCE40HXxx, iCE40LPxx, iCE40LMxx LCMXO2-xx, LCMXO3L/LF-xx LFE3-xx, LAE3-xx LFXP2-xx, LAXP2-xx LFE2Mxx, LFE2-xx LFXPxx, LCMXOxx, LAMXOxx LFECxx, OR4xx, ORLxx, ORSxx, ORT42xx, ORT82xx, , ORT88xx LC4kxx, LA4kxx, LC5kxx, LFXxx, LXxx, ispGAL22V10Ax ispPAC-CLK53kxx, ispPAC-CLK54kxx, ispPAC-CLK55kxx, ispPAC-CLK56kxx, OR3Lxx, M-OR3xx, ORT46xx ispLSI 5000VE, ispLSI2000VE, ispGDXVA M4A3-xx, M4A5-xx, M5LV-xx, M5A3-xx, M5-xx, LC5kxx / ispPAC-POWRxx, LAispPAC-POWRxx (Power Manager II) / LPTMxx (Platform Manager II) OR2xx, OR3Txx GAL16V8D, GAL16LV8D, GAL22V10D, GAL22LV10D, ispGAL22LV10, ispGDX, ispLSI 1k, ispLSI 2k, ispLSI 2000VE, ispLSI 3k, ispLSI 5k GAL16LV8C, GAL20V8C, GAL22LV10C, GAL26V12C GAL16V8Z, GAL18V10, GAL20V8B, GAL26V12B, ispGAL22V10C, ispLSI 1k ispPAC-POWRxx (Power Manager I) 40LP (40nm) The iCE40 devices are fabricated on a 40nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. CS200F (65nm) The MachXO2 and MachXO3L/3LF family combines an optimized look-up table (LUT) architecture with 65nm low- embedded Flash process technology to deliver a 3x increase in logic density, a 10x increase in embedded memory, more than a 100x reduction in static power and up to 30% lower cost compared to the prior generation MachXO PLD family. CS200A (65nm) The LatticeECP3 devices are implemented on a cost-effective, production-proven, SRAM based, Low-, 65nm CMOS process with copper metallization fabricated by Fujitsu Microelectronics Limited. This process is optimized to deliver high performance features suitable for high-volume, high-speed, low-cost applications. CS100F (90nm) The LatticeXP2 devices are implemented on a cost-effective, production-proven, Low-, 90nm CMOS process with SRAM + FLASH and copper metallization fabricated by Fujitsu Microelectronics Limited. This process technology, combined with efficient silicon design, results in very small die sizes while providing the new Lattice FPGAs with the most attractive feature sets in their class. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 11 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report CS100 A/L (90nm) The LatticeSC/M and LatticeEC2/M devices are implemented on a cost-effective, production-proven, Low-, 90 nm CMOS process with copper metallization fabricated by Fujitsu Microelectronics Limited. This process technology, combined with efficient silicon design, results in very small die sizes while providing the new Lattice FPGAs with the most attractive feature sets in their class. CS90F The CS90F (previously EE12) Technology is a low-, 130 nm Flash CMOS process with copper metallization fabricated by Fujitsu Microelectronics Limited. This process uses 8 planarized Cu – barrier metal interconnect layers, an Al top layer metal layer and a double layer poly-silicon flash cell. The CS90F metallization system includes Cu-barrier sandwich metals and low-k dielectric layers to enhance product performance. CS90A/L The CS90A/L (previously UM12) Technology is a cost-effective, production-proven, Low-, 130nm CMOS process with copper metallization fabricated by Fujitsu Microelectronics Limited. This process uses 8 planarized Cu –barrier metal interconnect layers, an aluminum top layer metal layer and single layer poly-silicon transistors. The CS90A/L metallization system includes Cu-barrier sandwich metals and low-k dielectric layers to enhance product performance. UM10 UM10 is a shallow trench isolated, 0.22 µm CMOS process with Electrically Erasable cell (E² Cell) modules. This process use five planarized metal interconnect layers and a single layer polysilicon. UM10 is manufactured at Seiko Epson Corporation. EE9 EE9 is a 1.8V/2.5V/3.3V shallow trench isolated, 0.18µm CMOS process with Electrically Erasable cell (E2 cell) modules. This process uses five or six planarized metal interconnect layers and single layer polysilicon. EE9 uses 5 to 6 layers of metal to provide smaller chip dimensions and improved signal routing. The EE9 metallization system includes the utilization of barrier metals to enhance electromigration performance. UltraMOS VIII (UM8) The 3.3V UltraMOS VIII process utilizes a twin well CMOS technology for low power operation with a grounded substrate for enhanced latch-up protection. UltraMOS VIII uses 4 layers of metal to provide smaller chip dimensions and improved signal routing. The UltraMOS VIII metallization system includes the utilization of barrier metals to enhance electromigration performance. UltraMOS VIII utilizes a single layer of polysilicon for improved manufacturability by reducing the number of processing steps. This reduction in processing steps enhances cell retention and endurance characteristics by reducing the amount of stress applied to the tunnel oxide during processing. EE8 EE8 is a 3.3V/5.5V shallow trench isolated, 0.25µm Leff CMOS process with Electrically Erasable cell (E2 cell). This process uses three planarized metal interconnect layers and single layer polysilicon. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 12 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report EE8A EE8A includes the feature size and digital functionality of process EE8 while integrating analog functions - including precision resistors, MIM capacitor, and additional low-threshold transistors. UltraMOS VI (UM6) UltraMOS VI Process Technology utilizes an N-well CMOS technology for low power operation with a negatively biased substrate for enhanced latch-up protection. UltraMOS VI uses multiple layers of metal to provide smaller chip dimensions and improved signal routing. UltraMOS VI utilizes a single layer of polysilicon for improved manufacturability by reducing the number of processing steps. This reduction in processing steps enhances cell retention and endurance characteristics by reducing the amount of stress the tunnel oxide will see during processing. UltraMOS VI is processed with high quality oxides ranging from a tunnel oxide of 90Å to a gate oxide of 130Å. The UltraMOS VI two-layer metal process has a 0.35µm Leff, and the three-layer metal process has a 0.55µm Leff. UltraMOS V (UM5) UltraMOS V Process Technology utilizes an N-well CMOS technology for low power operation with a negatively biased substrate for enhanced latch-up protection. UltraMOS V uses 2 layers of metal to provide smaller chip dimensions and improved signal routing. UltraMOS V utilizes a single layer of polysilicon for improved manufacturability by reducing the number of processing steps. This reduction in processing steps enhances cell retention and endurance characteristics by reducing the amount of stress the tunnel oxide will see during processing. UltraMOS V is processed with high quality oxides ranging from a tunnel oxide of 90Å to a gate oxide of 160Å. The UltraMOS V effective gate lengths are 0.65 µm and 0.80µm. UltraMOS IV (UM4) UltraMOS IV Process Technology utilizes an N-well CMOS technology for low power operation with a negatively biased substrate for enhanced latch-up protection. UltraMOS IV uses 2 layers of metal to provide smaller chip dimensions and improved signal routing. UltraMOS IV utilizes a single layer of polysilicon for improved manufacturability by reducing the number of processing steps. This reduction in processing steps enhances cell retention and endurance characteristics by reducing the amount of stress the tunnel oxide will see during processing. UltraMOS IV is processed with high quality oxides ranging from a tunnel oxide of 90Å to a gate oxide of 225Å. The UltraMOS IV effective gate lengths are 1.0 µm. UltraMOS IVAR (UM4AR) The 5V UltraMOS Analog process utilizes a twin well CMOS technology for low power operation with a grounded substrate. The UltraMOS Analog process uses 2 layers of metal to provide smaller chip dimensions and improved signal routing. The UltraMOS Analog process utilizes two layers of polysilicon for improved manufacturability. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 13 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 6.0 RELIABILITY MONITORING 6.1 High Temperature Operating Life Monitor (HTOL) The High Temperature Operating Life Monitor Test is used to thermally activate those failure mechanisms that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC JESD22A-108, a pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and test conditions include the appropriate supply voltages, Vcc = Vcc-max (per device data sheet), and temperature acceleration (125°C or 105°C). 6.2 High Temperature Storage Life (HTSL) The High Temperature Storage Life test is used to determine the effect of time and ambient temperature, under storage conditions, for thermally activated failure mechanisms. Consistent with JEDEC JESD22-A103, the devices are subjected to high temperature storage Condition B: +150 (0/+10) °C for equivalent of 1000 hours. Prior to High Temperature Storage Life testing, all Lattice devices are subjected to Surface Mount Preconditioning. 6.3 High Temperature Data Retention (HTRX) The High Temperature Data Retention test measures the Non-Volatile Memory (NVM) cell reliability while the High Temperature Operating Life test is structured to measure functional operating circuitry failure mechanisms. The High Temperature Data Retention test is specifically designed to accelerate charge gain on to or charge loss off of the floating gates in the device's array. Since the charge on these gates determines the actual pattern and function of the device, this test is a measure of the reliability of the device in retaining programmed information. Consistent with JEDEC JESD22-A117, NVM cell reliability is determined by monitoring the cell margin after biased static operation at 150°C. All cells in all arrays are life-tested in both programmed and erased states. Prior to data retention testing, all products are pre-conditioned to the maximum data sheet conditions program/erase cycles. 6.4 Surface Mount Preconditioning Testing (SMPC) The Surface Mount Preconditioning Test is used to model the surface mount assembly conditions during component solder processing. Consistent with JEDEC JESD22-A113 “Preconditioning Procedures of Plastic Surface Mount Devices Prior to Reliability Testing”, the devices are subjected to 5 temperature cycles between -55°C and +125°C in an air environment, a moisture bake out for 24 hours at 125°C, a controlled moisture soak for either 192 hours (JEDEC Moisture Sensitivity Level 3 for wire bonded packages), or 96 hours (JEDEC Moisture Sensitivity Level 4 for flip-chip packages) at 30°C/60% R. H., or 168 hours at 85°C/85% R. H. (JEDEC Moisture Sensitivity Level 1), followed by 3 cycles through the appropriate Pb-free Reflow Simulation temperature profile as defined in IPC/JEDEC J-STD-020. 6.5 Temperature Cycling (TC) The Temperature Cycling test is used to accelerate those failures resulting from mechanical stresses induced by differential thermal expansion of adjacent films, layers and metallurgical interfaces in the die and package. Devices are tested at 25°C after exposure to repeated cycling between -55°C and +125°C in an air environment consistent with JEDEC JESD22-A104 “Temperature Cycling”, Condition B temperature cycling requirements. Prior to Temperature Cycling testing, all Lattice devices are subjected to Surface Mount Preconditioning. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 14 Lattice Semiconductor 6.6 Q1 2016 Lattice Products Reliability Report Unbiased HAST (UHAST) Unbiased Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of moisture into the package and to the die surface. The Unbiased HAST test is designed to detect ionic contaminants present within the package or on the die surface, which can cause chemical corrosion. Consistent with JEDEC JESD22-A118, “Accelerated Moisture Resistance - Unbiased HAST,” the Unbiased HAST conditions are either 96 hour exposure at 130°C, 85% R.H., or 264 hour exposure at 110°C, 85% R.H. Prior to Unbiased-HAST testing, all Lattice devices are subjected to Surface Mount Preconditioning. 6.7 Temperature Humidity Bias (THB) The Temperature Humidity Bias (THB) test is performed for the purpose of evaluating the reliability of non-hermetic packaged devices in humid environments. It employs conditions of temperature, humidity, and bias, which accelerate the penetration of moisture through the external protective material (encapsulant or seal). Test conditions consist of a temperature, relative humidity, and duration used in conjunction with an electrical bias configuration specific to the device. Consistent with JEDEC JESD22-A101, the THB conditions, devices are biased to maximum operating Vcc, 85°C, 85% relative humidity for 1000 hours. Prior to Temperature Humidity Bias testing, all Lattice devices are subjected to Surface Mount Preconditioning. 6.8 Biased HAST Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of moisture into the package and to the die surface. The Biased HAST test is used to accelerate threshold shifts in the MOS device associated with moisture diffusion into the gate oxide region as well as electrochemical corrosion mechanisms within the device package. Consistent with JEDEC JESD A110 “Highly-Accelerated Temperature and Humidity Stress Test (HAST)”, the biased HAST conditions are with Vcc bias and alternate pin biasing in an ambient of 130°C or 110°C, 85% relative humidity. Prior to Biased-HAST testing, all Lattice devices are subjected to Surface Mount Preconditioning. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 15 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Figure 6.1: Reliability Monitoring Process Flow Wafer Process Monitor Sample From Finished Goods Based on Production Volume HTOL Early Life Testing 48hr or 168hr/ 125C 77 units 78 units Package Family Monitor Sample From Finished Goods By Supplier / By Volume SMPC Preconditioning MSL Target Level 25% units 25% units 25% units HTOL Inherent Life 1000hr / 125C HTRX Data Retention EEPROM & FLASH 1000hr / 150C T/C Temp Cycle Condition B UHAST Humidity Stress 130C / 85%RH or 110C/85%RH THB Temp / Humidity /Bias 85C / 85%RH or BHAST –130C/85% RH or 110C/85%RH 25% units HTSL High Temp Shelf Life 1000hr / 150C Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 16 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 7.0 LATTICE RELIABILITY SUMMARY Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice products is assured through ongoing monitor programs. Failure rates in this reliability report are expressed in FITS. Due to the very low failure rate of integrated circuits, it is convenient to refer to failures in a population during a period of 10 9 device hours; one failure in 109 device hours is defined as one FIT. These FIT rates are adjusted to an ambient temperature of 55°C with a 60% upper confidence level. The results of the present Lattice Semiconductor technology families are summarized in the table below. Table 7.1: Lattice FIT Rates per Process Technology Technology 40LP CS200A CS200F CS100A/L CS100F CS90F CS90A/L UM10 EE9 UM8 EE8 EE8A UM6 UM5 UM4 0.35 CMOS 0.30 CMOS COM 1 COM 2 (40nm SRAM) (65nm SRAM) (65nm Flash) (90nm SRAM) (90nm Flash) (130nm Flash) (130nm SRAM) (0.22 µm E2) (0.18 um E2) (0.25 um E2) (0.25 µm E2) (0.25 µm E2) (0.35 µm E2) (0.65 µm E2) (1.0 um E2) 0.25μ 3 Volt 0.16μ 1.8 Volt Fails 0 1 1 5 0 0 0 0 3 1 8 0 5 10 6 7 26 2 3 HTOL Device Hours 1,566,000 3,268,616 3,835,500 4,970,000 3,784,250 10,903,334 3,768,000 3,313,000 24,761,244 15,831,500 19,303,000 2,993,500 53,815,872 19,927,000 23,721,000 6,585,000 6,592,000 5,289,500 3,808,000 FIT 14 8 7 16 3 1 3 4 2 2 6 4 2 7 4 17 48 7 14 Fails 0 0 0 0 1 0 0 0 6 11 6 Data Retention Device Hours † † 2,467,000 † 2,468,000 5,057,000 † 2,289,000 8,091,428 8,885,000 6,328,707 2,084,208 32,553,840 15,885,836 33,249,504 † † † † ESD HBM >2000 V >1000 V >2000 V >1000 V >1500 V >1500 V >1500 V >2000V >2000V >2000V >2000V >1500V >2000V >2000V >2000V >2000V >2000V >2000V >2000V CDM > 1000V > 500V** > 500V > 500V* >500 V >500 V >500 V >1000V >1000V >1000V >1000V >1000V >1000V >1000V >1000V >1000V >1000V >1000V >500V † Not applicable *Except Lattice SC/M high speed SERDES pins passed 300V **Except LatticeECP3 HDIN pins passed 400V FIT rate calculations include failures from devices receiving >168h of stress. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 17 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 8.0 RELIABILITY DATA BY PROCESS TECHNOLOGY 8.1 40LP (40nm SRAM) Process Technology The 40LP Technology is a 40nm low-k, CMOS low power process fabricated by Taiwan Semiconductor Manufacturing Company Limited (TSMC) and United Microelectronics Corporation (UMC). The High Temperature Operating Life test is used to thermally accelerate those wear out and failure mechanisms that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC JESD22-A108 “Temperature, Bias, and Operating Life”, a pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at the stress conditions listed below Product Family: ICE40LP/LM/HX, iCE40Ultra and iCE40UltraLite Packages offered: QFN, ucBGA, csBGA, TQFP, WLCSP and ucfBGA Technology Node: 40 nm Life Test (HTOL) 40LP Temperature: 125°C Ambient Voltage: Vcc = 1.26 V, VCCIO = 2.625 V Method: Document # 87-101943 For FIT rate calculations: Ea = 0.6 eV; Tjref=55°C; Confidence Level = 60% Fab Lot PASS Jun-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Jun-15 24m Total FB12 FB12 UMC UMC UMC FB12 FB12 ICE40LP1K ICE40LP1K ICE40UL1K ICE40UL1K ICE40UL1K ICE40LP1K ICE40LP1K DE1NKN70000 DE1NNP51900 KHGCT KHGJK KHGNR DE1NNX52700 DE1NPK86300 299 300 64 96 64 300 300 1,423 0 0 0 0 0 0 0 0 77 76 64 95 64 77 77 530 40LP 24 month Lifetime # fail 0 0 #device hrs 530,000 1,566,000 FIT rate 42 14 FAIL Product FAIL 1000 Foundry PASS 48 Monitor Date #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77,000 76,000 64,000 95,000 64,000 77,000 77,000 530,000 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 18 Lattice Semiconductor 8.2 Q1 2016 Lattice Products Reliability Report CS200A (65nm SRAM) Process Technology The CS200A Technology is a Low-, 65nm CMOS process fabricated by Fujitsu Microelectronics Limited. The High Temperature Operating Life test is used to thermally accelerate those wear out and failure mechanisms that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC JESD22-A108 “Temperature, Bias, and Operating Life”, a pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at the stress conditions listed below. Product Family: ECP3 Packages offered: ftBGA, and fpBGA Technology Node: 65 nm Life Test (HTOL) CS200A Temperature: 105°C ambient = 125°C junction Voltage: Vcc = 1.26 V, VCCIO = 3.47 V Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7 eV; Tjref=55°C; Confidence Level = 60% # fail 1 1 #device hrs 1,101,872 3,268,616 77 0 FAIL CS200A 24 month Lifetime 300 0 274 0 77 300 0 250 0 300 0 300 0 1 165 1 77 2 298 1 299 0 300 0 300 0 300 0 299 0 300 0 300 0 174 0 300 0 77 3 293 1 300 0 5,352 3 231 1000 PASS CZ24K6406501 CY74C2162101 CZ24K6399001 CZ24K6514401 CY74C2330101 CZ24K6576601 CZ24K6609701 CY74C2527801 CY94C2476401 CZ24K6680801 CY74C2590401 CY94C2654701 CZ24K7083901 CY74C2806301 CZ24K7264001 CY74C3038201 CZ24K7379201 CY74C3046801 CZ24K7723801 FAIL LFE3-70EA LFE3-150EA LFE3-70EA LFE3-95EA LFE3-150EA LFE3-70EA LFE3-70EA LFE3-150EA LFE3-35EA LFE3-70EA LFE3-150EA LFE3-35EA LFE3-95EA LFE3-150EA LFE3-95EA LFE3-150EA LFE3-95EA LFE3-150EA LFE3-95EA PASS FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM 500 FAIL Jun-14 Sep-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Mar-15 Jun-15 Jun-15 Jun-15 Sep-15 Sep-15 Dec-15 Dec-15 Mar-16 Mar-16 24m Total PASS Fab Lot 336 FAIL Product PASS Foundry 168 FAIL Monitor Date PASS 48 0 77 77 76 77 0 0 0 0 77 77 77 77 77 77 77 0 0 0 0 0 0 0 77 76 999 0 4 1 1 0 77 0 77 0 0 0 77 0 154 0 #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 38,500 0 77,000 77,000 76,000 77,000 0 25,872 77,000 77,000 77,000 77,000 77,000 77,000 77,000 38,500 0 77,000 76,000 1,101,872 FIT rate 24 8 FAR#1460 – 1 unit failing config sram – random failure FAR#1520 – readback failure – random failure 3 FAR#1602 – rdbk_0 failure – ongoing investigation 4 FAR#1606 – rdbk_5 failure – ongoing investigation 1 2 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 19 Lattice Semiconductor 8.3 Q1 2016 Lattice Products Reliability Report CS200F (65nm Flash) Process Technology The CS200F Technology is a Low-, 65nm CMOS process with FLASH fabricated by Fujitsu Microelectronics Limited. The High Temperature Operating Life test is used to thermally accelerate those wear out and failure mechanisms that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC JESD22-A108 “Temperature, Bias, and Operating Life”, a pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at the stress conditions listed below. Product Family: MachXO2 and MachXO3L/LF Packages offered: TQFP, QFN, fpBGA, ftBGA, csBGA, caBGA, ucBGA, csfBGA and WLCSP Technology Node: 65 nm Life Test (HTOL) CS200F Temperature: 125°C Ambient Voltage: Vcc = 1.26 V (ZE/HE), 3.47 V (HC) VCCIO = 3.47 V Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7 eV; Tjref=55°C; Confidence Level = 60% FAIL Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Sep-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 Mar-16 24m Total FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 CY54C1694001 CY54C1793101* CY54C1883501* DL24C2012601 DL24C2026401 DL24C2172301 DL24C2167001 DL24C2174601 DL24C2392401 DL24C2385801 DL24C2630601 DL24C2734701 DL24C2879501 DL24C2952301 DL24C2938201 DL24C3026001 DL24C3010301 DL24C3035401 DL24C3242401 DL24C3262801 DL24C3393401 300 300 300 300 300 300 300 300 300 300 300 300 300 300 298 300 300 300 300 300 300 6,298 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS200F 24 month Lifetime # fail 0 1 #device hrs 1,498,500 3,835,500 77 77 77 231 FAIL Fab Lot PASS Product 1000 FAIL Foundry PASS 500 PASS 48 Monitor Date 77 75 77 77 77 77 77 77 77 76 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 77 77 1,383 0 0 0 0 0 0 0 0 #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77,000 75,000 77,000 77,000 77,000 77,000 77,000 77,000 77,000 76,000 77,000 77,000 77,000 77,000 77,000 38,500 38,500 38,500 77,000 77,000 77,000 1,498,500 FIT rate 8 7 * run at nominal +10% Vcc Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 20 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Unbiased High Temperature Data Retention (HTRX) CS200F Temperature: 150°C ambient Preconditioned with 10,000 read/write cycles Method: Document # 87-101925 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 CY54C1694001 CY54C1793101 CY54C1883501 DL24C2012601 DL24C2026401 DL24C2172301 DL24C2167001 DL24C2174601 DL24C2392401 DL24C2385801 DL24C2630601 DL24C2734701 DL24C2879501 DL24C2952301 DL24C2938201 DL24C3026001 DL24C3010301 DL24C3035401 DL24C3242401 DL24C3262801 DL24C3393401 Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Sep-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 Mar-16 24m Total 78 78 78 234 FAIL Fab Lot PASS Product 1000 FAIL Foundry PASS 500 Monitor Date Device Hours 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 78 78 78 1,404 0 0 0 0 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 39,000 39,000 39,000 78,000 78,000 78,000 1,521,000 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 21 Lattice Semiconductor 8.4 Q1 2016 Lattice Products Reliability Report CS100 A/L (90nm SRAM) Process Technology The CS100 A/L Technology is a Low-, 90nm CMOS process fabricated by Fujitsu Microelectronics Limited. The High Temperature Operating Life test is used to thermally accelerate those wear out and failure mechanisms that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC JESD22-A108 “Temperature, Bias, and Operating Life”, a pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at the stress conditions listed below. Product Family: ECP2/M, SC/M Packages offered: TQFP, PQFP, fpBGA, and fcBGA Technology Node: 90 nm Life Test (HTOL) CS100 A/L Temperature: 105°C ambient = 125°C junction Voltage: Vcc = 1.14 V, VCCIO = 3.47V Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% 1 2 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM LFE2-12E LFE2M20E LFE2M20E LFE2M20E LFE2M20E LFE2M20E LFE2M20E LFE2-12SE LFE2M20E LFE2M20E LFE2-12E LFE2M20E CC14K6336301 CC84K6343501 CC84K6514001 CC84K6578701 CC84K6682301 CC84K6884001 CC84K7026801 CC14K7035101 CC84K7217801 CC84K7467901 CC14K7633901 CC84K7634001 288 299 255 300 290 300 300 299 300 298 300 300 3,529 CS100A/L 24 month Lifetime # fail 1 5 #device hrs 574,500 4,970,000 0 0 1 1 0 0 0 0 0 0 0 0 0 1 76 77 0 0 76 0 76 0 76 0 381 0 FAIL Jun-14 Jun-14 Sep-14 Dec-14 Dec-14 Mar-15 Jun-15 Jun-15 Sep-15 Dec-15 Mar-16 Mar-16 24m Total PASS Fab Lot FAIL Product 1000 PASS Foundry 500 FAIL Monitor Date PASS 48 77 0 77 77 0 0 77 0 76 1 384 1 2 #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 1 0 1 38,000 38,500 77,000 38,000 0 77,000 77,000 38,000 77,000 38,000 76,000 0 574,500 FIT rate 45 16 FAR#1450 – 1 unit failing idcode_pcm (known issue on ECP2 - fix in place at Test) FAR#1610 – 1 unit failing opens – ongoing investigation Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 22 Lattice Semiconductor 8.5 Q1 2016 Lattice Products Reliability Report CS100F (90nm Flash) Process Technology The CS100F Technology is a Low-, 90nm CMOS process with SRAM + FLASH and copper metallization fabricated by Fujitsu Microelectronics Limited. The High Temperature Operating Life test is used to thermally accelerate those wear out and failure mechanisms that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC JESD22A108 “Temperature, Bias, and Operating Life”, a pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at the conditions shown below. Product Family: LFXP2-xx Packages offered: TQFP, PQFP, csBGA, fpBGA, and ftBGA Technology Node: 90 nm Life Test (HTOL) CS100F Temperature: 125°C Ambient Voltage: VCC = 1.26 V, VCCIO = 3.47 V Preconditioned with 10,000 read/write cycles Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% LFXP2-17E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-17E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E DK34K6463801 CT44K6466401 CT44K6576901 CT44K6542501 DS34K6747301 CT44K6767401 CT44K6983101 CT44K7062001 CT44K7397701 42215 CT44K7543201 CT44K7558401 CT44K7660001 300 300 300 300 300 300 300 300 300 299 300 300 300 3,899 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS100F 24 month Lifetime # fail 0 0 #device hrs 807,500 3,784,250 77 77 77 FAIL FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM PASS FAIL Sep-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Dec-15 Dec-15 Mar-16 Mar-16 24m Total 1000 FAIL Fab Lot PASS Product 500 FAIL Foundry PASS 168 PASS 48 Monitor Date 77 77 77 77 76 77 77 77 0 0 0 0 0 0 0 0 77 77 769 0 0 0 0 0 0 77 0 #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77,000 77,000 77,000 77,000 76,000 77,000 77,000 77,000 0 38,500 0 77,000 77,000 807,500 FIT rate 15 3 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 23 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Unbiased High Temperature Data Retention (HTRX) CS100F Duration: 1000 hours Temperature: 150°C ambient Preconditioned with 10,000 read/write cycles Method: Document # 87-101925 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Dec-15 Dec-15 Mar-16 Mar-16 24m Total FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM LFXP2-17E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-17E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E DK34K6463801 CT44K6397401 CT44K6466401 CT44K6576901 CT44K6542501 DS34K6747301 CT44K6767401 CT44K6983101 CT44K7062001 CT44K7397701 42215 CT44K7543201 CT44K7558401 CT44K7660001 78 78 156 1000 FAIL Fab Lot PASS Product FAIL Foundry PASS 500 Monitor Date Device Hours 78 78 78 78 78 78 78 78 78 78 0 0 0 0 0 0 0 0 0 0 78 78 936 0 0 0 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 39,000 39,000 78,000 78,000 1,014,000 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 24 Lattice Semiconductor 8.6 Q1 2016 Lattice Products Reliability Report CS90A/L (130nm SRAM) Process Technology The CS90A/L Technology1 is a cost-effective, production-proven, Low-, 130nm CMOS process with copper metallization fabricated by Fujitsu Microelectronics Limited. This process uses 8 planarized Cu –barrier metal interconnect layers, an aluminum top layer metal layer and single layer poly-silicon transistors. The CS90A/L metallization system includes Cu-barrier sandwich metals and low-k dielectric layers to enhance product performance. Product Family: LFEC/EC Packages offered: TQFP, PQFP and fpBGA Technology Node: 130 nm Life Test (HTOL) CS90 A/L Temperature: 125°C Ambient Voltage: Vcc = 1.8 V, VCCIO = 3.6 V Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% 1 LFEC1E LFEC1E LFEC1E LFEC1E BG64E8408601 BG64E8408801 BG64E8331401 BG64E7830101 300 315 300 300 1,215 0 0 0 0 0 CS90A/L 24 month Lifetime # fail 0 0 #device hrs 115,500 3,768,000 0 0 77 0 77 0 FAIL FLM FLM FLM FLM PASS FAIL Jun-14 Jun-14 Sep-14 Sep-14 24m Total FAIL Fab Lot 1000 PASS Product 500 FAIL Foundry PASS Monitor Date 168 PASS 48 77 0 77 0 #Fail for FIT Device Hours 0 0 0 0 0 38,500 77,000 0 0 115,500 FIT rate 102 3 PCN#06B-13 – Technology discontinuance due to fab site consolidation. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 25 Lattice Semiconductor 8.7 Q1 2016 Lattice Products Reliability Report CS90F (130nm Flash) Process Technology The CS90F Technology is a low-, 130 nm Flash CMOS process with copper metallization fabricated by Fujitsu Microelectronics Limited. This process uses 8 planarized Cu –barrier metal interconnect layers, an Al top layer metal layer and a double layer poly-silicon flash cell. The CS90F metallization system includes Cu-barrier sandwich metals and low-k dielectric layers to enhance product performance. Product Family: MachXO, LFXP1 Packages offered: TQFP, fpBGA, ftBGA and csBGA Technology Node: 130 nm Life Test (HTOL) CS90F Temperature: 125°C Ambient Voltage: VCC = 1.8 V, VCCIO = 3.6 V Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% 1 Foundry Product Fab Lot PASS FAIL PASS 1000 Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Dec-14 Jun-15 Jun-15 Sep-15 Mar-16 Mar-16 24m Total FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO256C LCMXO256C CN64E8361701 CN64E8361901 CN64E8428201 CN64E8537301 CN64E8654701 CN84E8655201 CN84E8721201 DP94K7006901 DP94K7057101 DP94K7273201 DP24K7733301 DP24K7753201 300 300 300 300 300 300 300 300 300 300 300 300 3,600 0 0 0 0 0 0 0 0 0 0 0 0 0 77 77 77 77 77 71 77 77 77 77 77 77 918 CS90F 24 month Lifetime # fail 0 0 #device hrs 918,000 10,903,334 FIT rate 13 1 FAIL 48 Monitor Date #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77,000 77,000 77,000 77,000 77,000 71,000 77,000 77,000 77,000 77,000 77,000 77,000 918,000 PCN#06B-13 – Product discontinuance due to fab site consolidation. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 26 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Unbiased High Temperature Data Retention (HTRX) CS90F Duration: 1000 hours Temperature: 150°C ambient Preconditioned with 1,000 read/write cycles Method: Document # 87-101925 Foundry Product Fab Lot PASS FAIL 1000 Monitor Date Device Hours Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Mar-16 Mar-16 24m Total FLM FLM FLM FLM FLM FLM FLM LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 CN64E8361701 CN64E8361901 CN64E8428201 CN64E8537301 CN64E8654701 DP24K7733301 DP24K7753201 78 78 78 78 78 78 78 546 0 0 0 0 0 0 0 0 78,000 78,000 78,000 78,000 78,000 78,000 78,000 546,000 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 27 Lattice Semiconductor 8.8 Q1 2016 Lattice Products Reliability Report EE9 Process Technology EE9 is a 1.8V/2.5V/3.3V shallow-trench-isolated 0.18um Leff CMOS process with Electrically Erasable cell (E2 cell) modules. This process uses five or six planarized metal interconnect layers and single layer polysilicon. EE9 uses 5 to 6 layers of metal to provide smaller chip dimensions and improved signal routing. The EE9 metallization system includes the utilization of barrier metals to enhance electromigration performance. A pattern specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at maximum operating voltage and 125°C. Prior to operating life testing, all In-System Programmable High Density Logic devices receive a number of program and erase cycles. Product Family: ispMACH4000, ispGDX2, ispXPLD, ispXPGA Packages offered: TQFP, PQFP, SBGA, fpBGA and CABGA Technology Node: 0.18 um Life Test (HTOL) EE9 Temperature: 125°C Ambient Voltage: VCC = 1.9 V, VCCIO = 2.5 V Preconditioned with 1000 read/write cycles Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% LC4256V LC4256V LC4256V LC4256V LC4256V LC4256V LC4256V LC4256V LC4256V LC4256V LC4256VS LC4256VS LC4256VS LC4256VS LC4256VS LC4256VS LC4256VS LC4256VD CH3260 AQ7459 AC5HQW7S00 AQ7462 AQ7463 AQ7470 AQ7469 AQ7471 CH3272 AQ7475 AQ7482 AQ7483 AQ7488 AQ7489 AQ7491 AQ7498 AQ7497 AD6HSKR000 300 300 300 300 300 299 300 299 300 299 300 300 300 300 300 300 299 299 5,395 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS90A/L 24 month Lifetime # fail 0 3 #device hrs 1,241,244 24,761,244 77 77 0 0 154 0 77 0 77 0 FAIL SAKR SAKR UMC SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR UTEK PASS FAIL Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Dec-15 Mar-16 Mar-16 Mar-16 24m Total 1000 FAIL Fab Lot PASS Product 500 FAIL Foundry PASS 336 PASS 48 Monitor Date 77 77 77 77 75 77 76 76 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 0 1,151 0 #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77,000 77,000 77,000 77,000 75,000 77,000 76,000 76,000 77,000 77,000 77,000 77,000 77,000 77,000 38,500 25,872 25,872 77,000 1,241,244 FIT rate 10 2 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 28 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Unbiased High Temperature Data Retention (HTRX) EE9 Duration: 1000 hours Temperature: 150°C ambient Preconditioned with 1000 read/write cycles Method: Document # 87-101925 Monitor Date Foundry Product Fab Lot FAIL 1000 PASS 500 Device Hours Sep-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Dec-15 24m Total SAKR SAKR SAKR SAKR SAKR SAKR UMC UMC SAKR SAKR SAKR SAKR SAKR SAKR LC4256V LC4256V LC4256V LC4256V LC4256V LC4256V LC4128V LC4128V LC4256V LC4256V LC4256V LC4256V LC4256V LC4256VS AQ7459 AQ7462 AQ7463 AQ7470 AQ7469 AQ7471 DE8HR4WA00 DE8HR2JT00 AQ7475 AQ7482 AQ7483 AQ7488 AQ7489 AQ7491 78 78 78 78 78 78 78 78 78 78 78 78 78 0 0 0 0 0 0 0 0 0 0 0 0 0 1,014 0 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 78,000 39,000 1,053,000 78 78 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 29 Lattice Semiconductor 8.9 Q1 2016 Lattice Products Reliability Report EE8 Process Technology EE8 is a 3.3V shallow-trench-isolated 0.25um Leff CMOS process with Electrically Erasable cell (E2 cell). This process uses three planarized metal interconnect layers and single layer polysilicon. Product Family: ispM4A3, ispM4A5 Packages offered: PLCC, TQFP, PQFP, BGA, fpBGA and caBGA Technology Node: 0.25 um Life Test (HTOL) EE8 Temperature: 125°C Ambient Voltage: 5.5V/3.6V Preconditioned with 1000 read/write cycles Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% 4492R3Y0P CM2116 CM2117 CM2120 CM2126 4492R655S CM2132 216 193 300 300 300 300 299 1,909 0 0 0 0 0 0 0 0 EE8 24 month Lifetime # fail 0 8 #device hrs 364,000 19,303,000 76 76 77 35 0 0 FAIL M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 PASS UMC SAKR SAKR SAKR SAKR UMC SAKR 1000 FAIL FAIL Sep-14 Dec-14 Mar-15 Jun-15 Sep-15 Sep-15 Mar-16 24m Total 500 PASS Fab Lot FAIL Product PASS 168 Foundry PASS 48 Monitor Date 0 0 112 77 77 77 77 308 0 0 0 0 0 0 #Fail for FIT 0 0 0 0 0 0 0 Device Hours 38,500 17,500 0 77,000 77,000 77,000 77,000 364,000 FIT rate 33 6 Unbiased High Temperature Data Retention (HTRX) EE8 Duration: 1000 hours Temperature: 150°C ambient Preconditioned with 1000 read/write cycles Method: Document # 87-101925 Product Fab Lot Sep-14 Dec-14 Jun-15 Jun-15 Sep-15 Sep-15 Mar-16 24m Total UMC Seiko Seiko Seiko Seiko UMC SAKR M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 M4A5-128/64 4492R3Y0P CM2116 CM2117 CM2120 CM2126 4492R655S CM2132 78 78 78 0 0 0 78 312 0 0 FAIL Foundry PASS Monitor Date FAIL 1000 PASS 500 39 78 78 0 0 0 195 0 Device Hours 39,000 39,000 39,000 39,000 78,000 78,000 39,000 351,000 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 30 Lattice Semiconductor 8.10 Q1 2016 Lattice Products Reliability Report EE8A Process Technology Process EE8A includes the feature size and digital functionality of process EE8 while integrating analog functions - including precision resistors, MIM capacitor, and additional low-threshold transistors. Product Family: ispPAC-POWR1014A Packages offered: TQFP Technology Node: 0.25 um Life Test (HTOL) EE8A Temperature: 125°C Ambient Voltage: VCCA = VCCD = 3.6V, VCCIN = 5.5V Preconditioned with 1000 read/write cycles Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% Product Fab Lot PASS FAIL Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Mar-16 24m Total UMC UMC UMC SAKR UMC SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR SAKR ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1220AT8 ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1220AT8 DA4R3GC2 DA5R35W2 DA5R41YS CX4117 DA4R41YQ DD3101 CX4121 DD3104 CX4127 DD3107 CX4133 DD3112 CX4139 CX4152 315 227 264 300 300 299 300 300 300 300 300 300 300 300 4,105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 0 EE8A 24 month Lifetime # fail 0 0 #device hrs 576,500 2,993,500 77 77 77 77 385 FAIL Foundry FAIL 1000 PASS 500 PASS 48 Monitor Date 77 0 77 77 77 0 0 0 76 0 384 0 0 0 0 0 0 #Fail for FIT Device Hours 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38,500 77,000 0 0 0 38,500 38,500 38,500 77,000 77,000 77,000 0 76,000 38,500 576,500 FIT rate 21 4 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 31 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Unbiased High Temperature Data Retention (HTRX) EE8A Duration: 1000 hours Temperature: 150°C ambient Preconditioned with 1000 read/write cycles Method: Document # 87-101925 ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1014A ispPAC-POWR1220AT8 ispPAC-POWR1220AT8 DA5R35W2 DA4R41YQ DA5R41YS DA4R3GC2 CX4117 CX4121 DD3104 CX4127 DD3107 CX4133 DD3112 CX4139 CX4152 78 78 0 0 1000 78 77 0 0 78 78 78 0 0 0 389 0 FAIL UMC UMC UMC UMC UMC Seiko Seiko Seiko Seiko Seiko Seiko Seiko SAKR 500 PASS Fab Lot FAIL Product FAIL Foundry PASS Jun-14 Sep-14 Sep-14 Sep-14 Sep-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Mar-16 24m Total PASS 336 Monitor Date Device Hours 78 0 78 0 78 78 78 78 78 0 0 0 0 0 546 0 78,000 39,000 38,500 78,000 39,000 39,000 39,000 78,000 78,000 78,000 78,000 78,000 26,208 766,708 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 32 Lattice Semiconductor 8.11 Q1 2016 Lattice Products Reliability Report UltraMOS VI Process Technology UltraMOS VI Process Technology utilizes an N-well CMOS technology for low power operation with a negatively biased substrate for enhanced latch-up protection. UltraMOS VI uses multiple layers of metal to provide smaller chip dimensions and improved signal routing. UltraMOS VI utilizes a single layer of polysilicon for improved manufacturability by reducing the number of processing steps. This reduction in processing steps enhances cell retention and endurance characteristics by reducing the amount of stress the tunnel oxide will see during processing. UltraMOS VI is processed with high quality oxides ranging from a tunnel oxide of 90Å to a gate oxide of 130Å. The UltraMOS VI effective gate lengths are 0.40 µm. Product Family: ispGAL/ispLSI Packages offered: PLCC, SSOP and QFNS Technology Node: 0.35 um Life Test (HTOL) UltraMOS VI Temperature: 125°C Ambient Voltage: 3.6V or 5.5V Preconditioned with 10,000 read/write cycles Method: Document # 87-101943 For FIT rate calculations: Ea = 0.7eV; Confidence Level = 60% UM6 24 month Lifetime 300 300 300 300 300 300 300 300 2,400 0 0 0 0 0 0 0 0 0 SAK # fail 0 5 #device hrs 564,872 53,815,872 CG6611 CG6613 77 77 0 0 0 0 FAIL CG8528 CG7305 CG7307 CG7308 CG6610 CG7309 PASS ispLSI 2064A ispLSI 2032E ispLSI 2032E ispLSI 2032E ispLSI 2032A ispLSI 2032E ispLSI 2032A ispLSI 2032A 1000 FAIL SAK SAK SAK SAK SAK SAK SAK PASS Fab Lot 500 FAIL Product PASS Foundry FAIL Jun-14 Sep-14 Dec-14 Mar-15 Jun-15 Jun-15 Sep-15 Mar-16 24m Total 336 PASS 48 Monitor Date #Fail for FIT 77 77 77 77 77 77 77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 539 0 0 Device Hours 77,000 77,000 77,000 77,000 77,000 77,000 77,000 25,872 564,872 FIT rate 21 2 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 33 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Unbiased High Temperature Data Retention (HTRX) UMVI Duration: 1000 hours Temperature: 150°C ambient Preconditioned with 10,000 read/write cycles Method: Document # 87-101925 Foundry Product Fab Lot PASS FAIL 1000 Monitor Date Device Hours Jun-14 Sep-14 Dec-14 Mar-15 Jun-15 Jun-15 Sep-15 24m Total SAK SAK SAK SAK SAK SAK SAK ispLSI 2064A ispLSI 2032E ispLSI 2032E ispLSI 2032E ispLSI 2032A ispLSI 2032E ispLSI 2032A CG8528 CG7305 CG7307 CG7308 CG6610 CG7309 78 78 78 78 78 78 78 546 0 0 0 0 0 0 0 0 78,000 78,000 78,000 78,000 78,000 78,000 78,000 546,000 CG6611 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 34 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 9.0 PACKAGE RELIABILITY DATA BY LOGIC TECHNOLOGY This section contains Package Reliability Monitor data by technology node. 9.1 40nm node Surface Mount Pre-Conditioning (5 Temperature Cycles, 24 hours bake @ 125°C, 85°C/85% RH soak 168hours (MSL1) or 30°C/60% RH soak 192 hours (MSL3), 260°C Reflow Simulation, 3 passes) performed before all 40LP package tests. Method: Document # 70-103467 MSL1 Package: WLCSP MSL3 Packages: TQFP, QFN, csBGA, caBGA, ucBGA Temperature Cycling 40LP Duration: 700 temperature cycles between -55°C to 125°C Method: Document # 87-101932 Pkg Type CBGA QFN WLCS Monitor Date Mar-15 Mar-15 Jun-15 Pbfree? YES YES YES Assy Foundry ASM1 ASM1 ASM1 FB12 FB12 FB12 Dec-14 Mar-16 YES YES ASM1 ASM1 UMC FB12 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Mar-15 Mar-15 YES YES YES YES YES YES YES ASET ASET ASET ASET ASET ASET ASET FB12 FB12 FB12 FB12 UMC UMC UMC Process Tech 40LP 40LP 40LP Total 40LP 40LP Total 40LP 40LP 40LP 40LP 40LP 40LP 40LP Total Pkg Code Assy Lot Product 81ucBGA 81ucBGA 81ucBGA B4411R50 B4481R27 B5041R20 ICE40LP1K ICE40LP1K ICE40LP1K 32QFN 84QFN A4301RB6 B5311R07 ICE40LP384 ICE40LP1K 16WLCSP 16WLCSP 16WLCSP 16WLCSP 16WLCSP 36WLCSP 36WLCSP B347TT02 B334TH20 B427TT13 B427TT14 A430TT05 A445TT02 A448TT05 ICE40LP640 ICE40LP1K ICE40LP640 ICE40LP640 ICE5LP640 ICE5LP640 ICE5LP640 Pass@ 700cyc* 27 45 45 117 45 44 89 37 43 45 45 45 45 45 305 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * Changed from Q4’13 to conform with JESD47I Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 35 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Quick Turn Monitor (QTM) - Temperature Cycling 40LP Pre-Conditioning: 260°C Reflow Simulation Duration: 100 temperature cycles between -55°C to 125°C Pkg Type CBGA WLCSP Monitor Date Apr-14 Apr-14 Apr-14 Apr-14 Apr-14 Apr-14 Apr-14 Apr-14 Apr-14 May-14 May-14 May-14 May-14 May-14 Jun-14 Jun-14 Pbfree? YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Assy Foundry ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM ASEM TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC Nov-14 Nov-14 Dec-14 Jan-15 Jan-15 Feb-15 Feb-15 Feb-15 Feb-15 YES YES YES YES YES YES YES YES YES ASET ASET ASET ASET ASET ASET ASET ASET ASET UMC UMC UMC TSMC TSMC UMC UMC UMC UMC Process Tech 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP Total 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP 40LP Total Pkg Code Assy Lot Product 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 36ucBGA 412SQ43E 412SQ72E 412SQ78E 414SQ81E 414SQ73E 415SQ15E 415SQ06E 415SQ54E 416SQ41E 416SQ36E 416SQ17E 417SQ39E 417SQ19E 419SQ05E 419SQ14E 419SQ27E ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K ICE40LP1K 36WLCSP 36WLCSP 36WLCSP 16WLCSP 16WLCSP 36WLCSP 36WLCSP 36WLCSP 36WLCSP A434TT14 A434TT09 A445TT08 B450TT02 B450TT03 A504TT04 A505TT03 A505TT04 A504TT05 ICE5LP640 ICE5LP640 ICE5LP640 ICE40LP640 ICE40LP640 ICE5LP640 ICE5LP640 ICE5LP640 ICE5LP640 Pass@ 100cyc 180 180 180 178 177 180 180 180 180 180 180 180 180 180 180 180 2,875 186 187 200 180 180 174 180 180 180 1,647 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 36 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Highly Accelerated Stress Test 40LP Unbiased: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85% RH (condition B) Method: Document # 87-104561 Biased or THB: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85%RH (condition B) or 1000 hrs 85°C/85%RH; Voltage: Vcc= 1.2V, Vccio=3.3v Method: Document # 87-101918/87-104561 Pkg Type Voltage Monitor Date Pbfree? Assy Foundry CBGA Unbiased Mar-15 Mar-15 YES YES ASM1 ASM1 FB12 FB12 Biased Mar-15 YES ASM1 Unbiased Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Mar-15 Mar-15 YES YES YES YES YES YES YES ASET ASET ASET ASET ASET ASET ASET Biased Dec-14 YES ASET Unbiased Dec-14 Mar-16 YES YES ASE ASM1 WLCS QFN Process Tech 40LP 40LP Total FB12 40LP Total FB12 40LP FB12 40LP FB12 40LP FB12 40LP UMC 40LP UMC 40LP UMC 40LP Total UMC 40LP Total UMC 40LP FB12 40LP Total Pkg Code Assy Lot Product 81ucBGA 81ucBGA B4411R50 B4481R27 ICE40LP1K ICE40LP1K 81ucBGA B4481R27 ICE40LP1K 16WLCSP 16WLCSP 16WLCSP 16WLCSP 36WLCSP 36WLCSP 36WLCSP B347TT02 B334TH20 B427TT13 B427TT14 A430TT05 A445TT02 A448TT05 ICE40LP640 ICE40LP1K ICE40LP640 ICE40LP640 ICE5LP640 ICE5LP640 ICE5LP640 36WLCSP A430TT05 ICE5LP640 32QFN 84QFN A4301RB6 B5311R07 ICE40LP384 ICE40LP1K Pass Pass 96h@ 264h@ # Fail 130C 110C 43 0 45 0 0 88 0 37 0 0 37 0 43 0 45 0 45 0 45 0 45 0 45 0 42 0 88 222 0 44 0 0 44 0 45 0 45 0 90 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 37 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report High Temperature Storage Life (HTSL) 40LP Duration: 1000 hours Temperature: 150°C ambient Method: Document # 87-101925 Pkg Type CBGA QFN WLCS Monitor Date Dec-14 Mar-15 Mar-15 Jun-15 Pbfree? YES YES YES YES Assy Foundry 33AP ASM1 ASM1 ASM1 UMC FB12 FB12 FB12 Dec-14 Mar-16 YES YES ASE ASM1 UMC FB12 Jun-14 Sep-14 Sep-14 Dec-14 Mar-15 Mar-15 YES YES YES YES YES YES ASET ASET ASET ASET ASET ASET FB12 FB12 FB12 UMC UMC UMC Process Tech 40LM 40LP 40LP 40LP Total 40LP 40LP Total 40LP 40LP 40LP 40LP 40LP 40LP Total Pkg Code Assy Lot Product 49ucBGA 81ucBGA 81ucBGA 81ucBGA B4213V10A B4411R50 B4481R27 B5041R20 ICE40LM4K ICE40LP1K ICE40LP1K ICE40LP1K 32QFN 84QFN A4301RB6 B5311R07 ICE40LP384 ICE40LP1K 16WLCSP 16WLCSP 16WLCSP 36WLCSP 36WLCSP 36WLCSP B334TH20 B427TT13 B427TT14 A430TT05 A445TT02 A448TT05 ICE40LP1K ICE40LP640 ICE40LP640 ICE5LP640 ICE5LP640 ICE5LP640 Pass@ 500h 45 45 45 45 Pass@ 1000h 27 45 45 117 45 0 45 45 45 44 43 132 45 43 133 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 38 Lattice Semiconductor 9.2 Q1 2016 Lattice Products Reliability Report 65nm node Surface Mount Pre-Conditioning (5 Temperature Cycles, 24 hours bake @ 125°C, 85°C/85% RH soak 168hours (MSL1) or 30°C/60% RH soak 192 hours (MSL3), 250°C/260°C Reflow Simulation, 3 passes) performed before all CS200F/CS200A package tests. Method: Document # 70-103467 MSL1 Packages: WLCSP MSL3 Packages: TQFP, QFN, fpBGA, ftBGA, csBGA, caBGA, ucBGA, and csfBGA Temperature Cycling CS200F/CS200A Duration: 700 temperature cycles between -55°C to 125°C Method: Document # 87-101932 Pkg Type BGA QFN QFP 1 2 Assy Foundry Jun-14 Jun-14 Sep-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Mar-15 Jun-15 Sep-15 Sep-15 Dec-15 Dec-15 Mar-16 Mar-16 Mar-16 Mar-16 Mar-16 Pbfree ? YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ASM1 AST2 ASM1 ASM1 ASM1 ASM1 AST2 ASM1 AST2 ASM1 AST2 AST2 ASM1 ASM1 AST2 ASM1 33AP ASE ASE ASE FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM Jun-14 Sep-14 Dec-14 Mar-15 Jun-15 Jun-15 YES YES YES YES YES YES ASET ASET ASET ASET ASET ASET FLM FLM FLM FLM FLM FLM Dec-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Dec-15 Mar-16 YES YES YES YES YES YES YES YES YES ASM1 ASM1 AST2 AST2 AST2 ASM1 33AP ASM1 AST2 FLM FLM FLM FLM FLM FLM FLM FLM FLM Monitor Date Process Tech Pkg Code CS200A 256FTBGA CS200A 484FPBGA CS200A 256FTBGA CS200A 672FPBGA CS200F 256CABGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 256CABGA CS200F 132CSBGA CS200F 132CSBGA CS200A 256FTBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 256CABGA CS200F 256CABGA CS200F 256CABGA Total CS200F 32QFN CS200F 32QFN CS200F 32QFN CS200F 32QFN CS200F 32QFN CS200F 32QFN Total CS200F 144LQFP CS200F 144LQFP CS200F 144LQFP CS200F 144LQFP CS200F 144LQFP CS200F 100TQFP CS200F 100TQFP CS200F 144LQFP CS200F 100TQFP Total Assy Lot Product B4081R68 B4062R15 B4161R17 B4321R60 A4371RB8 A4361R94 A4272T09 A4471R73 A4502T01 A4471R23 A5032T11 A5172T25 B5181R06 A5291R84 A5322T01 A5471RC1 A5443V03 LRB0325-15 LRB0326-15 LRB0327-15 LFE3-17EA LFE3-35EA LFE3-17EA LFE3-70EA LCMXO2-7000 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-7000 LCMXO2-1200 LCMXO2-1200 LFE3-17EA LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO3L-6900 LCMXO3L-6900 LCMXO3L-6900 A404TT02 A418TT02 A429TT02 A441TT08 A504TT09 A506TT02 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 A4271R04 A4291R98 A4282T12 A4282T10 A4372T19 A4411RA0 A4413V02 A5311R44 A5422T37 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-640 Pass@ 700cyc* # Fail 44 45 45 45 45 45 34 45 45 45 38 45 45 45 45 45 45 80 64 65 955 45 45 45 45 45 45 270 45 45 45 45 45 45 45 45 45 405 0 0 0 0 0 0 1 11 0 0 0 2 7 0 0 0 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAR #1451 – 11 units failing open contact test due to delamination; FA done, corrective action in place. FAR#1529 – 7 units failing opens contact test; FA done, corrective action in place. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 39 Lattice Semiconductor Pkg Type WLCS Monitor Date Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Mar-16 Mar-16 Pbfree ? YES YES YES YES YES YES YES YES YES Q1 2016 Assy Foundry UTAC UTAC UTAC UTAC UTAC UTAC UTAC UTAC UTAC FLM FLM FLM FLM FLM FLM FLM FLM FLM Process Tech Pkg Code CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP Total Lattice Products Reliability Report Assy Lot Product A432CC03 A433CC01 A436CC01 A442CC03 A451CC02 A505CC04 A505CC03 A543CC04 A505CC03 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200ZE LCMXO2-1200ZE Pass@ 700cyc* # Fail 44 45 44 45 45 45 45 45 45 403 0 0 0 0 0 0 0 0 0 0 * Changed from Q4’13 to conform with JESD47I Quick Turn Monitor (QTM) - Temperature Cycling CS200F Pre-Conditioning: 260°C Reflow Simulation Duration: 100 temperature cycles between -55°C to 125°C Pkg Type Monitor Date Jan-15 Jan-15 Jun-15 Jun-15 Sep-15 Sep-15 Pbfree? YES YES YES YES YES YES Assy Foundry UTAC UTAC UTAC UTAC UTAC UTAC FLM FLM FLM FLM FLM FLM Process Tech CS200F CS200F CS200F CS200F CS200F CS200F Total Pkg Code Assy Lot Product 25WLCSP 25WLCSP 25WLCSP 25WLCSP 25WLCSP 25WLCSP A451CC01 A451CC03 A513CC03 A513CC04 A516CC02 A516CC04 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 Pass @ 100cycle 177 176 180 180 180 176 1,069 # Fail 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 40 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Highly Accelerated Stress Test CS200F/CS200A Unbiased: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85% RH (condition B) Method: Document # 87-104561 Biased or THB Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85%RH (condition B) or 1000 hrs 85°C/85%RH Voltage: Vcc= 1.2V, Vccio=3.3v Method: Document # 87-101918/87-104561 Pkg Type Monitor PbDate free? Assy Foundry Unbiased Jun-14 Jun-14 Sep-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Mar-15 Jun-15 Sep-15 Sep-15 Mar-16 Mar-16 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES AST2 ASM1 ASM1 ASM1 ASM1 ASM1 AST2 ASM1 AST2 ASM1 AST2 AST2 ASM1 ASM1 33AP FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM Biased Jun-14 Jun-14 Sep-15 YES YES YES ASM1 ASM1 ASM1 FLM FLM FLM Unbiased Jun-14 Sep-14 Dec-14 Mar-15 Jun-15 Jun-15 YES YES YES YES YES YES ASET ASET ASET ASET ASET ASET FLM FLM FLM FLM FLM FLM Unbiased Dec-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Dec-15 Mar-16 YES YES YES YES YES YES YES YES YES ASM1 ASM1 AST2 AST2 AST2 ASM1 33AP ASM1 AST2 FLM FLM FLM FLM FLM FLM FLM FLM FLM Voltage BGA QFN QFP 1 2 Process Pkg Code Tech CS200A CS200A CS200A CS200A CS200F CS200F CS200F CS200F CS200F CS200F CS200F CS200A CS200A CS200F CS200F Total CS200A CS200A CS200A Total CS200F CS200F CS200F CS200F CS200F CS200F Total CS200F CS200F CS200F CS200F CS200F CS200F CS200F CS200F CS200F Total Assy Lot Product 484FPBGA B4062R15 256FTBGA B4081R68 256FTBGA B4161R17 672FPBGA B4321R60 256CABGA A4371RB8 132CSBGA A4361R94 132CSBGA A4272T09 132CSBGA A4471R73 132CSBGA A4502T01 256CABGA A4471R23 132CSBGA A5032T11 132CSBGA A5172T25 256FTBGA B5181R06 132CSBGA A5471RC1 132CSBGA A5443V03 LFE3-35EA LFE3-17EA LFE3-17EA LFE3-70EA LCMXO2-7000 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-7000 LCMXO2-1200 LCMXO2-1200 LFE3-17EA LCMXO2-1200 LCMXO2-1200 256FTBGA B4081R68 256FTBGA B4081R68 256FTBGA B5181R06 LFE3-17EA LFE3-17EA LFE3-17EA 32QFN 32QFN 32QFN 32QFN 32QFN 32QFN A404TT02 A418TT02 A429TT02 A441TT08 A504TT09 A506TT02 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 144TQFP 144TQFP 144TQFP 144TQFP 144TQFP 100TQFP 100TQFP 144TQFP 100TQFP A4271R04 A4291R98 A4282T12 A4282T10 A4372T19 A4411RA0 A4413V02 A5311R44 A5422T37 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-640 Hours/#Pass # 96h@ 264h@ Fail 130C 130C 45 0 1 43 2 45 0 45 0 45 0 44 0 45 0 45 0 45 0 2 44 1 45 0 45 0 45 0 45 0 45 0 88 583 3 45 0 45 0 45 0 45 90 0 45 0 45 0 45 0 45 0 45 0 45 0 270 0 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 44 0 45 0 404 0 0 FAR#1453 – 2 units failing open contact test due to lifted balls; FA done, corrective action in place. FAR#1505 – 1 unit failing open contact test due to lifted ball, FA done, corrective action in place Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 41 Lattice Semiconductor Pkg Type WLCSP Voltage Unbiased Q1 2016 Monitor PbDate free? Assy Foundry Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 UTAC UTAC UTAC UTAC UTAC UTAC UTAC YES YES YES YES YES YES YES FLM FLM FLM FLM FLM FLM FLM Lattice Products Reliability Report Process Pkg Code Tech CS200F CS200F CS200F CS200F CS200F CS200F CS200F Total 25WLCSP 25WLCSP 25WLCSP 25WLCSP 25WLCSP 25WLCSP 25WLCSP Assy Lot Product A432CC03 A433CC01 A436CC01 A442CC03 A451CC02 A505CC04 A505CC03 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 Hours/#Pass 264h@ 130C 44 45 45 45 44 45 45 313 # Fail 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 42 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report High Temperature Storage Life (HTSL) CS200F/CS200A Duration: 1000 hours Temperature: 150°C ambient Method: Document # 87-101925 Pkg Type BGA QFN TQFP WLCS 1 Monitor Date Jun-14 Jun-14 Sep-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Mar-15 Jun-15 Sep-15 Sep-15 Dec-15 Dec-15 Mar-16 Mar-16 Pbfree? YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Assy Foundry ASM1 AST2 ASM1 ASM1 ASM1 ASM1 AST2 ASM1 AST2 ASM1 AST2 AST2 ASM1 ASM1 AST2 ASM1 33AP FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM Jun-14 Sep-14 Dec-14 Mar-15 Jun-15 Jun-15 YES YES YES YES YES YES ASET ASET ASET ASET ASET ASET FLM FLM FLM FLM FLM FLM Dec-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Dec-15 Mar-16 YES YES YES YES YES YES YES YES YES ASM1 ASM1 AST2 AST2 AST2 ASM1 33AP ASM1 AST2 FLM FLM FLM FLM FLM FLM FLM FLM FLM Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Jun-15 Mar-16 Mar-16 YES YES YES YES YES YES YES YES YES UTAC UTAC UTAC UTAC UTAC UTAC UTAC UTAC UTAC FLM FLM FLM FLM FLM FLM FLM FLM FLM Process Pkg Code Tech CS200A 256FTBGA CS200A 484FPBGA CS200A 256FTBGA CS200A 672FPBGA CS200F 256CABGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 256CABGA CS200F 132CSBGA CS200F 132CSBGA CS200A 256FTBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA CS200F 132CSBGA Total CS200F SG32A CS200F SG32A CS200F 32QFN CS200F 32QFN CS200F 32QFN CS200F 32QFN Total CS200F 144LQFP CS200F 144LQFP CS200F 144LQFP CS200F 144LQFP CS200F 144LQFP CS200F 100TQFP CS200F 100TQFP CS200F 144TQFP CS200F 100TQFP Total CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP CS200F 25WLCSP Total Assy Lot Product B4081R68 B4062R15 B4161R17 B4321R60 A4371RB8 A4361R94 A4272T09 A4471R73 A4502T01 A4471R23 A5032T11 A5172T25 B5181R06 A5291R84 A5322T01 A5471RC1 A5443V03 LFE3-17EA LFE3-35EA LFE3-17EA LFE3-70EA LCMXO2-7000 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-7000 LCMXO2-1200 LCMXO2-1200 LFE3-17EA LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 A404TT02 A418TT02 A429TT02 A441TT08 A504TT09 A506TT02 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 LCMXO2-256 A4271R04 A4291R98 A4282T12 A4282T10 A4372T19 A4411RA0 A4413V02 A5311R44 A5422T37 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-640 Pass 500h 45 45 90 45 45 670 45 45 45 45 45 45 45 225 45 45 45 45 45 45 45 45 45 A432CC03 A433CC01 A436CC01 A442CC03 A451CC02 A505CC04 A505CC03 A543CC04 A543CC05 Pass 1000h 45 44 44 43 45 44 45 45 45 45 45 45 45 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 LCMXO2-1200 0 45 360 45 45 42 44 44 45 45 45 45 400 # Fail 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAR#1447 – 1 unit marginally failing serdes test. Test screening improvement in place Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 43 Lattice Semiconductor 9.3 Q1 2016 Lattice Products Reliability Report 90nm node Surface Mount Pre-Conditioning (5 Temperature Cycles, 24 hours bake @ 125°C, 30°C/60% RH, soak 192 hours (MSL3) or 96 hours (MSL4), 245°C/250°C/260°C Reflow Simulation, 3 passes) performed before all CS100F/CS100A/L package tests. Method: Document # 70-103467 MSL3 Packages: PQFP, TQFP, fpBGA, ftBGA, csBGA – CS100F/CS100A/L MSL4 Packages: fcBGA (Flip Chip BGA Packages) - CS100A/L Temperature Cycling CS100F/CS100A/L Duration: 700 temperature cycles between -55°C to 125°C Method: Document # 87-101932 Pkg Type BGA QFP Monitor Date Jun-14 Jun-14 Dec-14 Mar-15 Sep-15 Sep-15 Dec-15 Pbfree? YES YES YES YES YES YES YES Assy Foundry ASM1 AST2 AST2 AST2 ASM1 33AP ASM1 FLM FLM FLM FLM FLM FLM FLM Sep-14 Sep-14 Sep-14 Dec-14 Jun-15 Jun-15 Sep-15 Dec-15 Mar-16 YES YES YES YES YES YES YES YES YES ASM1 ASM1 ASE ASE 33AP 33AP ASM1 ASM1 ASE FLM FLM FLM FLM FLM FLM FLM FLM FLM Process Tech CS100F CS100A CS100F CS100F CS100F CS100F CS100F Total CS100A CS100A CS100F CS100F CS100F CS100F CS100F CS100F CS100F Total Pkg Code 132CSBGA 484FPBGA 256FTBGA 256FTBGA 132CSBGA 256FTBGA 132CSBGA 144LQFP 144LQFP 208PQFP 208PQFP 144LQFP 144LQFP 144LQFP 144LQFP 208PQFP Assy Lot Product A4071R71 LFXP2-5E A4052R01 FE2M20E A4282T15 LFXP2-17E A4502T03 LFXP2-17E CT44K7062001B6 LFXP2-5E A5203V04 LFXP2-17E CT44K73977015 LFXP2-5E A4151R21 A4171R64 A422RR74 A427RR87 A5073V09 A5063V41 A5191R18 CT44K74626011 A542RR64 LFE2-6E LFE2-6E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E Pass@ 700cyc* 45 45 45 45 45 45 45 315 45 45 45 45 45 45 45 45 45 405 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * changed from Q4’13 to conform with JESD47I Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 44 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Highly Accelerated Stress Test CS100F/CS100A/L Unbiased: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85% RH (condition B) Method: Document # 87-104561 Biased or THB Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85%RH (condition B) or 1000 hrs 85°C/85%RH Voltage: Vcc= 1.2V, Vccio=3.3v Method: Document # 87-101918/87-104561 Pkg Monitor PbVoltage Type Date free? Jun-14 Jun-14 Dec-14 Mar-15 Sep-15 Sep-15 YES YES YES YES YES YES ASM1 ASM1 ASET ASET ASM1 ATP Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Jun-14 Jun-14 Dec-14 Unbiased Mar-15 Sep-15 Sep-15 YES YES YES YES YES YES ASM1 AST2 AST2 AST2 ASM1 33AP FLM FLM FLM FLM FLM FLM Sep-14 Sep-14 Sep-14 Dec-14 Unbiased Jun-15 Jun-15 Sep-15 Mar-16 YES YES YES YES YES YES YES YES ASM1 ASM1 ASE ASE 33AP 33AP ASM1 ASE FLM FLM FLM FLM FLM FLM FLM FLM Biased BGA QFP Assy Foundry Process Tech CS100F CS100F CS100F CS100F CS100F CS100F Total CS100F CS100A CS100F CS100F CS100F CS100F Total CS100A CS100A CS100F CS100F CS100F CS100F CS100F CS100F Total Pkg Code Assy Lot Product 132CSBGA A4071R71 LFXP2-5E 132CSBGA A4071R71 LFXP2-5E 256FTBGA A4282T15 LFXP2-17E 256FTBGA A4502T03 LFXP2-17E 132CSBGA CT44K7062001B6 LFXP2-5E 256FTBGA A5203V04 LFXP2-17E 132CSBGA A4071R71 LFXP2-5E 484FPBGA A4052R01 LFE2M20E 256FTBGA A4282T15 LFXP2-17E 256FTBGA A4502T03 LFXP2-17E 132CSBGA CT44K7062001B6 LFXP2-5E 256FTBGA A5203V04 LFXP2-17E 144LQFP 144LQFP 208PQFP 208PQFP 144LQFP 144LQFP 144LQFP 208PQFP A4151R21 A4171R64 A422RR74 A427RR87 A5073V09 A5063V41 A5191R18 A542RR64 LFE2-6E LFE2-6E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E LFXP2-5E Hours/#Pass 96h@ 264h@ 130C 110C 45 45 45 45 45 45 45 225 45 45 45 45 45 45 90 180 45 45 45 44 45 45 45 45 359 0 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A 45 Return to INDEX Lattice Semiconductor Q1 2016 Lattice Products Reliability Report High Temperature Storage Life (HTSL) CS100F/CS100A/L Duration: 1000 hours Temperature: 150°C ambient Method: Document # 87-101925 Pkg Type BGA QFP Monitor Date Jun-14 Jun-14 Dec-14 Mar-15 Sep-15 Sep-15 Dec-15 Pbfree? YES YES YES YES YES YES YES Assy Foundry ASM1 AST2 AST2 AST2 ASM1 33AP ASM1 FLM FLM FLM FLM FLM FLM FLM Sep-14 Sep-14 Sep-14 Dec-14 Jun-15 Jun-15 Sep-15 Dec-15 Mar-16 YES YES YES YES YES YES YES YES YES ASM1 ASM1 ASE ASE 33AP 33AP ASM1 ASM1 ASE FLM FLM FLM FLM FLM FLM FLM FLM FLM Process Pkg Code Tech CS100F 132CSBGA CS100A 484FPBGA CS100F 256FTBGA CS100F 256FTBGA CS100F 132CSBGA CS100F 256FTBGA CS100F 132CSBGA Total CS100A 144LQFP CS100A 144LQFP CS100F 208PQFP CS100F 208PQFP CS100F 144LQFP CS100F 144LQFP CS100F 144LQFP CS100F 144LQFP CS100F 208PQFP Total Assy Lot Pass@ Pass@ 500h 1000h LFXP2-5E 45 LFE2M20E 45 LFXP2-17E 45 LFXP2-17E 45 LFXP2-5E 45 LFXP2-17E 45 LFXP2-5E 45 45 270 LFE2-6E 45 LFE2-6E 45 LFXP2-5E 45 LFXP2-5E 45 LFXP2-5E 45 LFXP2-5E 45 LFXP2-5E 45 LFXP2-5E 45 LFXP2-5E 45 90 315 Product A4071R71 A4052R01 A4282T15 A4502T03 CT44K7062001B6 A5203V04 CT44K73977015 A4151R21 A4171R64 A422RR74 A427RR87 A5073V09 A5063V41 A5191R18 CT44K74626011 A542RR64 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 46 Lattice Semiconductor 9.4 Q1 2016 Lattice Products Reliability Report 130nm node Surface Mount Pre-Conditioning (5 Temperature Cycles, 24 hours bake @ 125°C, 30°C/60% RH, soak 192 hours, 245°C/250°C/260°C Reflow Simulation, 3 passes) performed before all CS90F/CS90A/L package tests. Method: Document # 70-103467 MSL3 Packages: TQFP, fpBGA, ftBGA, caBGA Temperature Cycling CS90F/CS90A/L Duration: 700 temperature cycles between -55°C to 125°C Method: Document # 87-101932 Pkg Type BGA 1 2 Monitor Date Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Mar-15 Jun-15 Jun-15 Jun-15 Jun-15 Jun-15 Jun-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 Mar-16 Mar-16 Mar-16 Pbfree? YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Assy Foundry ASM1 ASM1 ASM1 ASM1 AST2 AST2 AST2 ASM1 ASET AST2 ASM1 AST2 ASM1 AST2 ASM1 ASM1 AST2 AST2 ASM1 AST2 ASM1 ASM1 33AP 33AP ASM1 ASM1 ATP JDV4 JDV4 ASM1 33AP 33AP JDV4 JDV4 33AP AST2 ASM1 AST2 33AP JDV4 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM Process Tech CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F Total Pkg Code Assy Lot Product 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 100CSBGA 100CSBGA 100CSBGA 100CSBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA A4041RB4 A4041RB5 A4161R63 A4161R03 A4192T06 A4182T32 A4172E01 A4301R97 A4272E03 A4302T35 A4281R98 A4412T11 A4411RA9 A4402T06 A5031R96 A5041R17 A5032T01 A5042T14 A5021R70 A5012T20 A5171R10 A5191R39 A5163V09 A5203V24 A5171R17 A5181R02 A5173V04 A5164B18 A5174B01 A5291RD8 A5273V01 A5303V16 A5284B10 A5284B18 A5303V16 A5422T35 A5421RC6 A5432T03 A5423V17 A5434B10 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO1200 LCMXO256 LCMXO256 LCMXO640 LCMXO1200 LCMXO640 LCMXO1200 LCMXO1200 LCMXO640 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO640 LCMXO1200 LCMXO640 LCMXO1200 LCMXO640 LCMXO640C LCMXO640C LCMXO1200C LCMXO1200C LCMXO640C LCMXO1200C LCMXO256C LCMXO640C LCMXO1200C LCMXO1200C LCMXO1200C Pass@ 700cyc* 45 45 45 45 45 45 25 44 45 45 40 45 44 45 45 45 45 45 45 45 45 45 45 45 44 45 45 45 45 45 45 45 45 44 45 45 45 45 45 45 1,726 # Fail 0 0 0 0 0 0 0 1 1 0 0 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 FAR#1452 - Units failing open contact test due to delamination; FA done, corrective action in place. FAR#1532 – Failure due to lifted ball; corrective action in place. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 47 Lattice Semiconductor Pkg Type QFP Monitor Date Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Mar-15 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 Mar-16 Mar-16 Pbfree? YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Q1 2016 Assy Foundry ASM1 ASM1 ASM1 ASM1 AST2 AST2 ASM1 AST2 ASET ASM1 AST2 ASM1 ASM1 ASM1 AST2 33AP JDV4 JDV4 JDV4 ASM1 ASM1 ASM1 33AP FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM Process Tech CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F Total Lattice Products Reliability Report Pkg Code Assy Lot Product 256FTBGA 256FTBGA 256FTBGA 144LQFP 100LQFP 100LQFP 100LQFP 144LQFP 144LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 144LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP A4021RE1 A4031RE3 A4041RC2 A4231R29 A4192T16 A4192T17 A4411RA8 A4412T05 A4402T20 A5031R93 A5042T15 A5171R45 A5191R40 A5291RD1 A5282T16 A5303V09 A5274B01 A5284B02 A5294B08 B5461R14 B5501R02 A5441R86 A5433V08 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO256 LCMXO256 LCMXO256 LCMXO1200 LCMXO640 LCMXO256 LCMXO1200 LCMXO256C LCMXO256C LCMXO256 LCMXO1200 LCMXO1200 LCMXO256 LCMXO256 LCMXO256 LMXO256C LMXO256C LMXO256C LMXO256C Pass@ 700cyc* 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 44 45 45 45 45 45 1,034 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * Changed from Q4’13 to conform with JESD47I Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 48 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Highly Accelerated Stress Test CS90F/CS90A/L Unbiased: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85% RH (condition B) Method: Document # 87-104561 Biased or THB Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85%RH (condition B) or 1000 hrs 85°C/85%RH Voltage: Vcc= 1.2V, Vccio=3.3v Method: Document # 87-101918/87-104561 Pkg Voltage Type Monitor Date Pbfree? Assy Foundry Biased Jun-14 Jun-14 Jun-14 Jun-14 Dec-14 Dec-14 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 YES YES YES YES YES YES YES YES YES YES YES YES YES YES ASM1 ASM1 ASM1 ASM1 ASM1 AST2 ASM1 ASM1 ASM1 ASM1 ASM1 33AP JDV4 JDV4 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM Unbiased Jun-14 Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Mar-15 Jun-15 Jun-15 Jun-15 Jun-15 Jun-15 Jun-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Dec-15 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ASM1 ASM1 ASM1 ASM1 ASM1 ASM1 AST2 AST2 AST2 ASM1 ASM1 ASM1 ASM1 ASM1 ASM1 AST2 ASM1 AST2 ASM1 ASM1 AST2 AST2 ASM1 ASM1 33AP 33AP ASM1 ASM1 33AP JDV4 JDV4 ASM1 BGA 1 Process Tech CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F Total FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F PkgCode Assy Lot Product 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA A4041RB4 LCMXO640 A4041RB5 LCMXO640 A4041RB4 LCMXO640 A4041RB5 LCMXO640 A4301R97 LCMXO640 A4272E03 LCMXO640 A4411RA9 LCMXO640 A5031R96 LCMXO640 A5041R17 LCMXO1200 A5171R17 LCMXO640 A5181R02 LCMXO1200 A5173V04 LCMXO640 A5164B18 LCMXO1200 A5174B01 LCMXO640 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 256FTBGA 256FTBGA 100CSBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 100CSBGA 100CSBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA A4041RB4 A4041RB5 A4041RB4 A4041RB5 A4161R63 A4161R03 A4192T06 A4182T32 A4172E01 A4281R98 A4301R97 A4272E03 A4302T35 A4412T11 A4411RA9 A4402T06 A5021R70 A5012T20 A5031R96 A5041R17 A5032T01 A5042T14 A5171R10 A5191R39 A5163V09 A5203V24 A5171R17 A5181R02 A5173V04 A5164B18 A5174B01 A5291RD8 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO256 LCMXO640 LCMXO640 LCMXO1200 LCMXO256 LCMXO640 LCMXO1200 LCMXO256 LCMXO256 LCMXO640 LCMXO1200 LCMXO1200 LCMXO640 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO640 LCMXO1200 LCMXO640 LCMXO1200 LCMXO640 LCMXO640 Hours/#Pass # 96h@ 264 Fail 130C @110C 45 0 45 0 45 0 45 0 45 0 45 0 39 0 45 0 45 0 44 0 45 0 45 0 45 0 45 0 90 533 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 25 0 45 0 1 44 1 45 0 45 0 45 0 38 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 FAR#1452 - Units failing open contact due to delamination; FA done, corrective action in place. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 49 Lattice Semiconductor Pkg Voltage Type BGA Q1 2016 Monitor Date Pbfree? Assy Foundry Unbiased Dec-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 Mar-16 Mar-16 Mar-16 YES YES YES YES YES YES YES YES YES 33AP 33AP JDV4 JDV4 ASM1 AST2 33AP JDV4 AST2 FLM FLM FLM FLM FLM FLM FLM FLM FLM Biased Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Dec-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ASM1 ASM1 ASM1 ASM1 AST2 AST2 ASM1 AST2 ASM1 AST2 ASM1 ASM1 ASM1 AST2 JDV4 JDV4 ASM1 ASM1 Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Mar-15 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 Sep-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES ASM1 ASM1 ASM1 ASM1 AST2 AST2 ASM1 AST2 AST2 ASM1 AST2 ASM1 ASM1 ASM1 AST2 33AP JDV4 JDV4 33AP ASM1 ASM1 QFP Unbiased Lattice Products Reliability Report Process PkgCode Tech CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F Total FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F Total FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F FLM CS90F Total Assy Lot Product 256FTBGA A5273V01 LCMXO640 256FTBGA A5303V16 LCMXO1200 256FTBGA A5284B10 LCMXO1200 256FTBGA A5284B18 LCMXO640 256FTBGA A5421RC6 LCMXO640 256FTBGA A5432T03 LCMXO1200 256FTBGA A5423V17 LCMXO1200 256FTBGA A5434B10 LCMXO1200 100CSBGA A5422T35 LCMXO256 144LQFP 144LQFP 144LQFP 144LQFP 100LQFP 100LQFP 144LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP A4021RE1 A4031RE3 A4041RC2 A4231R29 A4192T16 A4192T17 A4402T20 A4411RA8 A5031R93 A5042T15 A5171R45 A5191R40 A5291RD1 A5282T16 A5274B01 A5284B02 B5461R14 A5441R86 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO256 LCMXO256 LCMXO640 LCMXO256 LCMXO256 LCMXO1200 LCMXO256C LCMXO256C LCMXO256 LCMXO1200 LCMXO256 LCMXO256 LCMXO256 LCMXO256 144LQFP 144LQFP 144LQFP 144LQFP 100LQFP 100LQFP 100LQFP 144LQFP 144LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 144LQFP 100LQFP 144LQFP 144LQFP 100LQFP 100LQFP A4021RE1 A4031RE3 A4041RC2 A4231R29 A4192T16 A4192T17 A4411RA8 A4412T05 A4402T20 A5031R93 A5042T15 A5171R45 A5191R40 A5291RD1 A5282T16 A5303V09 A5274B01 A5284B02 A5303V09 B5461R14 A5441R86 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO256 LCMXO256 LCMXO256 LCMXO1200 LCMXO640 LCMXO256 LCMXO1200 LCMXO256C LCMXO256C LCMXO256 LCMXO1200 LCMXO1200 LCMXO256 LCMXO256 LCMXO1200 LCMXO256 LCMXO256 Hours/#Pass 264 96h@ @110 130C C 45 45 45 44 45 45 45 45 45 90 1,726 45 45 45 45 45 45 45 44 45 45 45 45 45 45 45 45 45 45 809 0 45 45 45 45 45 45 45 45 44 45 45 45 45 45 45 45 45 45 45 45 45 899 0 # Fail 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 50 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report High Temperature Storage Life (HTSL) CS90F/CS90A/L Duration: 1000 hours Temperature: 150°C ambient Method: Document # 87-101925 Pkg Type BGA QFP 1 2 Monitor Date Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Sep-14 Sep-14 Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Mar-15 Mar-15 Jun-15 Jun-15 Jun-15 Jun-15 Jun-15 Jun-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Sep-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 Mar-16 Mar-16 Mar-16 Pbfree? YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Assy Foundry ASM1 ASM1 ASM1 ASM1 AST2 AST2 AST2 ASM1 ASM1 AST2 AST2 AST2 ASM1 AST2 ASM1 AST2 ASM1 ASM1 AST2 AST2 ASM1 ASM1 33AP 33AP ASM1 ASM1 33AP JDV4 JDV4 ASM1 33AP 33AP JDV4 JDV4 ASM1 AST2 33AP JDV4 AST2 FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM FLM Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Mar-15 Mar-15 Mar-15 Jun-15 Jun-15 Sep-15 YES YES YES YES YES YES YES YES YES YES YES YES ASEM ASEM ASEM ASEM ASET ASET ASEM ASET ASET ASEM ASET ASEM Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Process Tech CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F Total CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F Pkg Code Assy Lot Product 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 256FTBGA 256FTBGA 100CSBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA 100CSBGA 100CSBGA 100CSBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 256FTBGA 100CSBGA A4041RB4 A4041RB5 A4161R63 A4161R03 A4192T06 A4182T32 A4172E01 A4281R98 A4301R97 A4272E03 A4302T35 A4412T11 A4411RA9 A4402T06 A5021R70 A5012T20 A5031R96 A5041R17 A5032T01 A5042T14 A5171R10 A5191R39 A5163V09 A5203V24 A5171R17 A5181R02 A5173V04 A5164B18 A5174B01 A5291RD8 A5273V01 A5303V16 A5284B10 A5284B18 A5421RC6 A5432T03 A5423V17 A5434B10 A5422T35 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO256 LCMXO640 LCMXO640 LCMXO1200 LCMXO256 LCMXO640 LCMXO1200 LCMXO256 LCMXO256 LCMXO640 LCMXO1200 LCMXO1200 LCMXO640 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO640 LCMXO1200 LCMXO640 LCMXO1200 LCMXO640 LCMXO640 LCMXO640 LCMXO1200 LCMXO1200 LCMXO640 LCMXO640 LCMXO1200 LCMXO1200 LCMXO1200 LCMXO256 144LQFP 144LQFP 144LQFP 144LQFP 100LQFP 100LQFP 100LQFP 144LQFP 144LQFP 100LQFP 100LQFP 100LQFP A4021RE1 A4031RE3 A4041RC2 A4231R29 A4192T16 A4192T17 A4411RA8 A4412T05 A4402T20 A5031R93 A5042T15 A5171R45 LCMXO640 LCMXO640 LCMXO640 LCMXO640 LCMXO256 LCMXO256 LCMXO256 LCMXO1200 LCMXO640 LCMXO256 LCMXO1200 LCMXO256 Pass@ 500h Pass@ 1000h 45 45 45 45 41 45 25 45 38 45 44 45 44 45 45 45 45 44 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 180 45 45 45 45 45 1,541 45 45 45 45 45 45 45 45 44 45 45 45 # Fail 0 0 0 0 1 4 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 FAR #1448 – 4 units failing open contact test due to lifted balls; FA done, corrective action in place. FAR # 1455 – 1 unit failed open contact test due to lifted balls; FA done, corrective action in place. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 51 Lattice Semiconductor Pkg Type QFP Monitor Date Sep-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Dec-15 Mar-16 Mar-16 Pbfree? YES YES YES YES YES YES YES YES YES YES Q1 2016 Assy Foundry ASEM ASM1 AST2 33AP JDV4 JDV4 JDV4 JDV4 ASM1 ASM1 Fujitsu FLM FLM FLM FLM FLM FLM FLM FLM FLM Process Tech CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F CS90F Total Lattice Products Reliability Report Pkg Code Assy Lot Product 100LQFP 100LQFP 100LQFP 144LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP 100LQFP A5191R40 A5291RD1 A5282T16 A5303V09 A5274B01 A5284B02 A5294B08 A5274B01 B5461R14 A5441R86 LCMXO256 LCMXO256 LCMXO1200 LCMXO1200 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 LCMXO256 Pass@ 500h Pass@ 1000h 45 45 45 45 45 45 45 45 270 45 45 674 # Fail 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 52 Lattice Semiconductor 9.5 Q1 2016 Lattice Products Reliability Report 0.18m node Surface Mount Pre-Conditioning (5 Temperature Cycles, 24 hours bake @ 125°C, 30°C/60% RH, soak 192 hours, 250°C/260°C Reflow Simulation, 3 passes) performed before all EE9 package tests. Method: Document # 70-103467 MSL3 Packages: TQFP, PQFP, fpBGA, ftBGA, csBGA, caBGA Temperature Cycling EE9 Duration: 700 temperature cycles between -55°C to 125°C Method: Document # 87-101932 Pkg Type BGA QFP Monitor Date Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Pbfree? YES YES YES YES YES Assy Foundry ASM1 ASM1 ASM1 ASM1 ASM1 SAKR SAKR SAKR SAKR SAKR Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Dec-14 Mar-15 Jun-15 Sep-15 Sep-15 Mar-16 YES YES YES YES YES YES YES YES YES YES YES YES AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT UTEK UTEK UTEK UTEK UTEK UTEK SAKR SAKR SAKR SAKR SAKR UTEK Process Tech EE9 EE9 EE9 EE9 EE9 Total EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 Total PkgCode Assy Lot Product 144CBGA 144CBGA 144CBGA 144CBGA 144CBGA A4041RG3 A4051RD3 A4171RC7 A4171R27 A4201RC6 LC4128Z LC4128Z LC4128Z LC4128Z LC4128Z 128TQFP 128TQFP 128TQFP 128TQFP 128TQFP 128TQFP 44TQFP 44TQFP 44TQFP 44TQFP 44TQFP 44TQFP A405KK14 A405KK13 A405KK11 A416KK09 A415KK19 A416KK08 B431KK03 B442KK25 B504KK16 B519KK07 B520KK17 A542KK06 LC4128V LC4128V LC4128V LC4128V LC4128V LC4128V LC4032VD LC4032VD LC4032VD LC4032VD LC4032VD LC4064VS Pass@ 700cyc* 45 45 45 45 45 225 45 45 44 45 43 44 45 45 45 45 45 45 536 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * Changed from Q4’13 to conform with JESD47 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 53 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Highly Accelerated Stress Test EE9 Unbiased: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85% RH (condition B) Method: Document # 87-104561 Biased or THB Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85%RH (condition B) or 1000 hrs 85°C/85%RH Voltage: Vcc= 1.2V, Vccio=3.3v Method: Document # 87-101918/87-104561 Pkg Type BGA QFP Voltage Monito Pbr Date free? Assy Foundry SAKR SAKR SAKR SAKR SAKR Jun-14 Jun-14 Unbiased Sep-14 Sep-14 Sep-14 YES YES YES YES YES ASM1 ASM1 ASM1 ASM1 ASM1 Jun-14 Jun-14 Jun-14 Sep-14 Dec-14 Mar-15 Jun-15 Sep-15 Sep-15 YES YES YES YES YES YES YES YES YES AIT AIT AIT AIT AIT AIT AIT AIT AIT Unbiased Process Tech EE9 EE9 EE9 EE9 EE9 Total UTEK EE9 UTEK EE9 UTEK EE9 UTEK EE9 SAKR EE9 SAKR EE9 SAKR EE9 SAKR EE9 SAKR EE9 Total Pkg Code Assy Lot Product 144CBGA 144CBGA 144CBGA 144CBGA 144CBGA A4041RG3 A4051RD3 A4171RC7 A4171R27 A4201RC6 LC4128ZE LC4128ZE LC4128ZE LC4128ZE LC4128ZE 128TQFP 128TQFP 128TQFP 128TQFP 44TQFP 44TQFP 44TQFP 44TQFP 44TQFP A405KK14 A405KK13 A405KK11 A416KK08 B431KK03 B442KK25 B504KK16 B519KK07 B520KK17 LC4128V LC4128V LC4128V LC4128V LC4032VD LC4032VD LC4032VD LC4032VD LC4032VD Hours/#Pass # 96h@ 264h@ Fail 130C 110C 43 0 45 0 45 0 45 0 45 0 178 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 45 0 405 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 54 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report High Temperature Storage Life (HTSL) EE9 Duration: 1000 hours Temperature: 150°C ambient Method: Document # 87-101925 Pkg Type BGA QFP Monitor Date Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Pbfree? YES YES YES YES YES ASM1 ASM1 ASM1 ASM1 ASM1 SAKR SAKR SAKR SAKR SAKR Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Sep-14 Dec-14 Mar-15 Jun-15 Sep-15 Sep-15 Mar-16 YES YES YES YES YES YES YES YES YES YES YES YES AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT UTEK UTEK UTEK UTEK UTEK UTEK SAKR SAKR SAKR SAKR SAKR UTEK Assy Foundry Process Tech EE9 EE9 EE9 EE9 EE9 Total EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 EE9 Total PkgCode Assy Lot Product 144CBGA 144CBGA 144CBGA 144CBGA 144CBGA A4041RG3 A4051RD3 A4171RC7 A4171R27 A4201RC6 LC4128Z LC4128Z LC4128ZE LC4128ZE LC4128ZE 128TQFP 128TQFP 128TQFP 128TQFP 128TQFP 128TQFP 44TQFP 44TQFP 44TQFP 44TQFP 44TQFP 44TQFP A405KK14 A405KK13 A405KK11 A416KK09 A415KK19 A416KK08 B431KK03 B442KK25 B504KK16 B519KK07 B520KK17 A542KK06 LC4128V LC4128V LC4128V LC4128V LC4128V LC4128V LC4032V LC4032VD LC4032VD LC4032VD LC4032VD LC4064VS Pass @ 336h Pass @ 500h 45 45 45 135 44 44 0 Pass @ 1000h 45 45 90 44 45 45 45 45 45 45 45 45 45 45 494 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 55 Lattice Semiconductor 9.6 Q1 2016 Lattice Products Reliability Report 0.25m node Surface Mount Pre-Conditioning (5 Temperature Cycles, 24 hours bake @ 125°C, 85°C/85% RH soak 168 hours (MSL1) or 30°C/60% RH soak 192 hours (MSL3), 245°C/250°C/260°C Reflow Simulation, 3 passes) performed before all EE8/EE8A/UM8 package tests. Method: Document # 70-103467 MSL1 Packages: QFNS MSL3 Packages: TQFP, PQFP, ftBGA, fpBGA, caBGA and PLCC Temperature Cycling EE8/EE8A/UM8 Duration: 700 cycles Conditions: Temperature cycling between -55°C to 125°C Method: Document # 87-101932 Pkg Type QFN QFP PLCC Monitor Date Jun-14 Sep-14 Sep-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Dec-15 Mar-16 Pbfree? YES YES YES YES YES YES YES YES YES YES Dec-14 Dec-14 Dec-14 Dec-14 Mar-15 Jun-15 Sep-15 Assy Foundry AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT UTEK UTEK UTEK UTEK SAKR UTEK SAKR UTEK SAKR SAKR YES YES YES UNISEM UNISEM UNISEM USC USC USC YES YES YES YES UNISEM UNISEM UNISEM UNISEM USC USC USC USC Process Pkg Tech Code EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS EE8A 32QFNS Total EE8 44TQFP EE8 44TQFP EE8 44TQFP Total EE8 44PLCC EE8 44PLCC EE8 44PLCC EE8 44PLCC Total Assy Lot Product A406KK09 A419KK12 A418KK05 A428KK03 A429KK12 B442KK53 A440KK03 B504KK02 B529KK21 B543KK27 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 A431KK01 A432KK06 B434KK02 M4A5-64/32 M4A5-64/32 M4A3-32/32 B434KK01 B444KK09 B502KK03 B518KK03 M4A5-32/32 M4A5-32/32 M4A5-32/32 M4A5-32/32 Pass@ 700cyc* 90 45 45 45 45 45 45 45 45 45 495 45 45 44 134 45 45 45 45 180 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * Changed from Q4’13 to conform with JESD47I Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 56 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Highly Accelerated Stress Test EE8/EE8A/UM8 Unbiased: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85% RH (condition B) Method: Document # 87-104561 Biased or THB Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85%RH (condition B) or 1000 hrs 85°C/85%RH Voltage: Vcc= 1.2V, Vccio=3.3v Method: Document # 87-101918/87-104561 Pkg Type PLCC QFN QFP Voltage Monitor PbProcess Assy Foundry Date free? Tech Dec-14 Mar-15 Unbiased Jun-15 Sep-15 YES AIT YES YES YES AIT AIT AIT USC USC USC USC Jun-14 Sep-14 Sep-14 Dec-14 Unbiased Dec-14 Mar-15 Mar-15 Jun-15 YES YES YES YES YES YES YES YES AIT AIT AIT AIT AIT AIT AIT AIT UTEK UTEK UTEK UTEK UTEK SAKR UTEK SAKR Dec-14 Unbiased Dec-14 Dec-14 YES YES YES AIT AIT AIT USC USC USC EE8 EE8 EE8 EE8 Total EE8A EE8A EE8A EE8A EE8A EE8A EE8A EE8A Total EE8 EE8 EE8 Total PkgCode Assy Lot Product 44PLCC B434KK01 M4A5-32/32 44PLCC 44PLCC 44PLCC B444KK09 B502KK03 B518KK03 M4A5-32/32 M4A5-32/32 M4A5-32/32 32QFNS 32QFNS 32QFNS 32QFNS 32QFNS 32QFNS 32QFNS 32QFNS A406KK09 A419KK12 A418KK05 A428KK03 A429KK12 B442KK53 A440KK03 B504KK02 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 44TQFP 44TQFP 44TQFP A431KK01 A432KK06 B434KK02 M4A5-64/32 M4A5-64/32 M4A3-32/32 Hours/#Pass 96h@ 264h@ 130C 110C 45 45 45 44 179 90 45 45 45 45 45 45 45 405 45 45 45 135 0 0 0 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 57 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report High Temperature Storage Life (HTSL) EE8/EE8A/UM8 Duration: 1000 hours Temperature: 150°C ambient Method: Document # 87-101925 Pkg Type QFN PLCC QFP Monitor Date Sep-14 Sep-14 Sep-14 Dec-14 Dec-14 Mar-15 Mar-15 Jun-15 Dec-15 Mar-16 Pbfree? YES YES YES YES YES YES YES YES YES YES Assy Foundry AIT AIT AIT AIT AIT AIT AIT AIT AIT AIT UTEK UTEK UTEK UTEK UTEK SAKR UTEK SAKR SAKR SAKR Dec-14 Mar-15 Jun-15 Sep-15 YES YES YES YES AIT AIT AIT AIT USC USC USC USC Dec-14 Dec-14 Dec-14 YES YES YES AIT AIT AIT USC USC USC Process Pkg Tech Code EE8A 32QFN EE8A 32QFN EE8A 32QFN EE8A 32QFN EE8A 32QFN EE8A 32QFN EE8A 32QFN EE8A 32QFN EE8A 32QFN EE8A 32QFN Total EE8 44PLCC EE8 44PLCC EE8 44PLCC EE8 44PLCC Total EE8 44TQFP EE8 44TQFP EE8 44TQFP Total Assy Lot Product A406KK09 A419KK12 A418KK05 A428KK03 A429KK12 B442KK53 A440KK03 B504KK02 B529KK21 B543KK27 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 ispPAC-POWR607 B434KK01 B444KK09 B502KK03 B518KK03 M4A5-32/32 M4A5-32/32 M4A5-32/32 M4A5-32/32 A431KK01 A432KK06 B434KK02 M4A5-64/32 M4A5-64/32 M4A3-32/32 Pass @336 Pass @500 Pass @1000 45 45 45 45 45 45 45 45 45 45 45 135 0 0 0 0 315 45 45 45 43 178 45 45 44 134 # Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 58 Lattice Semiconductor 9.7 Q1 2016 Lattice Products Reliability Report 0.35m and 1.0 m nodes Surface Mount Pre-Conditioning (5 Temperature Cycles, 24 hours bake @ 125°C, 85°C/85% RH soak 168 hours (MSL1) or 30°C/60% RH soak 192 hours (MSL3), 245°C/250°C/260°C Reflow Simulation, 3 passes) performed before all UM6/UM4 package tests. Method: Document # 70-103467 MSL1 Packages: PLCC, PDIP, QFNS(<=28 leads) MSL3 Packages: TQFP, PLCC (>28 leads) Temperature Cycling UM6(0.35m)/UM4(1.0 m) Duration: 700 cycles Conditions: Temperature cycling between -55°C to 125°C Method: Document # 87-101932 Pkg Type PLCC Monitor Date Jun-14 Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Mar-15 Jun-15 Pbfree? YES YES YES YES YES YES YES YES YES Assy Foundry AIT AIT ASE ASE ASE ASE ASE ASE ASE SEIK SEIK SAK SAK SAK SAK SAK SAK SAK Process Tech UMVI UMVI UMVI UMVI UMVI UMVI UMVI UMVI UMVI Total PkgCode Assy Lot Product 28PLCC 28PLCC 44PLCC 44PLCC 44PLCC 44PLCC 44PLCC 44PLCC 44PLCC F406KK01 F406KK02 B402RRA8 A403RRD8 B417RR84 B422RRB5 B435RR32 B444RR47 A507RR74 GAL22V10D GAL22V10D ispLSI 2032E ispLSI 2032A ispLSI 2032A ispLSI 2032A ispLSI 2032E ispLSI 2032E ispLSI 2032A Pass@ 700cyc* 89 90 45 45 45 45 45 45 45 494 # Fail 1 1 0 0 0 0 0 0 0 0 1 *Changed from Q4’13 to conform with JESD47I 1 FAR# 1428 – 1 unit failed open contact test Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 59 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report Highly Accelerated Stress Test UM6(0.35m)/UM4(1.0 m) Unbiased: Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85% RH (condition B) Method: Document # 87-104561 Biased or THB Duration: 96 hours at 130°C/85%RH or 264 hours at 110°C/85%RH (condition B) or 1000 hrs 85°C/85%RH Voltage: Vcc= 1.2V, Vccio=3.3v Method: Document # 87-101918/87-104561 Pkg Type PLCC Voltage Monitor Date Pbfree? Assy Foundry Unbiased Jun-14 Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Mar-15 Jun-15 YES YES YES YES YES YES YES YES YES ASE ASE AIT AIT ASE ASE ASE ASE ASE SAK SAK SAK SAK SAK SAK SAK SAK SAK Process Tech UMVI UMVI UMVI UMVI UMVI UMVI UM6P5 UMVI UMVI Total Pkg Code Assy Lot Product 44PLCC 44PLCC 28PLCC 28PLCC 44PLCC 44PLCC 44PLCC 44PLCC 44PLCC B402RRA8 A403RRD8 F406KK01 F406KK02 B417RR84 B422RRB5 B435RR32 B444RR47 A507RR74 ispLSI 2032E ispLSI 2032A GAL22V10D GAL22V10D ispLSI 2032A ispLSI 2032A ispLSI 2032E ispLSI 2032E ispLSI 2032A Hours/ #Pass 96h@ 130C 45 45 45 90 45 45 45 45 45 450 # Fail 0 0 0 0 0 0 0 0 0 0 High Temperature Storage Life (HTSL) UM6(0.35m)/UM4(1.0 m) Duration: 1000 hours Temperature: 150°C ambient Method: Document # 87-101925 Pkg Type PLCC Monitor Date Jun-14 Jun-14 Jun-14 Jun-14 Sep-14 Sep-14 Dec-14 Mar-15 Jun-15 Pb-free? Assy Foundry YES YES YES YES YES YES YES YES YES AIT AIT ASE ASE ASE ASE ASE ASE ASE SAK SAK SAK SAK SAK SAK SAK SAK SAK Process Tech UMVI UMVI UMVI UMVI UMVI UMVI UMVI UMVI UMVI Total PkgCode Assy Lot Product 28PLCC 28PLCC 44PLCC 44PLCC 44PLCC 44PLCC 44PLCC 44PLCC 44PLCC F406KK01 F406KK02 B402RRA8 A403RRD8 B417RR84 B422RRB5 B435RR32 B444RR47 A507RR74 GAL22V10D GAL22V10D ispLSI 2032E ispLSI 2032A ispLSI 2032A ispLSI 2032A ispLSI 2032E ispLSI 2032E ispLSI 2032A Pass@ 1000h 90 90 45 45 45 45 45 45 45 495 # Fail 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 60 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 10.0 ASSEMBLY RELIABILITY MONITOR DATA Lattice Semiconductor Corp. works closely with assembly partners to collect reliability data on specific Lattice products to enhance Reliability Monitoring Program. This additional information is presented in this section of the report. Prior to Temperature Cycling, Unbiased HAST, Autoclave and High Temperature Storage testing, all Lattice devices are subjected to Surface Mount Preconditioning per JEDEC J-STD-020. 10.1 Temperature Cycling Surface Mount Pre-Conditioning (MSL3) Method: JEDEC J-STD-020. Duration: 1000 temperature cycles between: -65°C to 150°C (Au); -55°C to 125°C (Cu) Method: JEDEC JESD22-A104 Monitor Date Assembler May-14 ASEM Jul -14 ASEM Oct-14 ASEM Feb-15 ASEM Apr-15 ASEM Bondwire Au Au Au Au Cu Cu Cu Cu Au Au Au Au Au Cu Cu Cu Cu Au Au Au Cu Cu Cu Cu Cu Au Au Cu Cu Cu Au Au Au Au Cu Cu Cu Cu PKG LBGA QFP PBGA TQFP PBGA TQFP LQFP LBGA PBGA LQFP PLCC QFP TQFP LQFP LBGA PBGA TQFP PBGA LBGA TQFP TQFP LBGA LQFP PBGA LBGA LBGA LQFP LBGA LQFP PBGA LBGA QFN TQFP LQFP LBGA LQFP TQFP PBGA LEAD 56 208 256 44 484 48 100 36 256 48 44 208 48 100 36 256 48 256 132 48 48 184 100 256 36 256 100 256 144 484 256 208 48 48 36 144 100 672 Product C4064ZCD FXP2 C5256MV C4032VD FE3-17EA C4064ZE MX02-256HC ICE40LP1K C5256MV 5D064 IPL2032A FXP6C A4064VS MXO2-256H ICE40LP640 FE2-6SE C4064ZE FX125EB C4128ZCS C4032VD C4032ZE MX02-4000HE MX02-640HC FE2-6E ICE40LP1K C4256VD 3D128 MXO3L-69C MXO640C FE2-20E C4256VD FXP2-8E A4064VS PWR1014A ICE40LP1K MXO2-1200HC ICE40HX1K FE3-70EA Lot Number DH2171B4 CT34K64472011 AH3HQTWN004 DG4HR2NL006 CY84C164870115 CV417612 CW14C15713016 DE1NKY422004 AH3HR0H3004 4192R3W45A5 CG6608Z1 CR74E8427001A1 DG7407CA23 CW14C17870014 DE1NMK226009 CC24K651100113 CV41825 BZ6HRJTP004 DF41818 DG54339 CJ314825 DL84C23619013 CW64C199250115 CC24K66803017 DE1NMP7490011 CH3275C23 CM1119A03 DM44C23469012 CN84E836240116 CB94K676770116 CH3278C18 CT34K69072014 DG745514 DA4R41YQB1 DE1NMY732006 DL24C217230111 DB8NCK7610013 CZ24K69667013 Qty 30 30 30 30 40 40 40 40 30 30 30 30 30 40 40 40 40 30 30 30 40 40 40 40 40 30 30 40 40 40 30 30 30 30 30 40 40 40 Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 61 Lattice Semiconductor Monitor Date Assembler Sep-15 ASEM Oct-15 ASEM Nov-15 ASEM Mar-16 ASEM Q1 2016 Bondwire Au Au Cu Cu Cu Cu Cu Cu Cu Cu Cu Au Au Au Au Au Au Cu PKG PLCC PBGA LBGA LQFP LBGA PBGA LBGA QFN LQFP PBGA LBGA LQFP TQFP LBGA LQFP PLCC TQFP TQFP Lattice Products Reliability Report LEAD 44 900 36 100 256 1156 132 84 100 1156 256 208 48 256 100 44 48 48 24 month Total Product IPL1016E SCM15E ICE40LP1K MXO256C MXO640C FE3-150EA MXO2-1200HC ICE40LP1K MXO256C FE3-95EA MXO640C C5512MV A4064VS C4256VD PWR1220AT8 IPL1016E C4032VD C5010A Lot Number 7440201C1 CD54K73204013 DE1NNA790001 CN64E845460110 CN84E84549019 CY74C26668015 DL24C262190112 DE1NNF0430010 4K65907058 CZ24K70575013 4K65818012 MH2553 DG74762 CH3286A4 CX4153C1 744020412 DG54688 CV420610 Qty 30 30 30 40 40 40 40 30 30 40 40 30 30 30 30 30 30 40 1940 Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 62 Lattice Semiconductor 10.2 Q1 2016 Lattice Products Reliability Report Autoclave / Pressure Cooker Surface Mount Pre-Conditioning (MSL3) Method: JEDEC J-STD-020 Duration: 168 hours at 121°C / 100%RH, 15PSI Method: JEDEC JESD22-A102 Monitor Date Assembler May-14 ASEM Jul - 14 ASEM Oct-14 ASEM Feb-15 ASEM Apr-15 ASEM July-15 ASEM Oct-15 ASEM Nov-15 ASEM Mar-16 ASEM Bondwire Au Au Au Au Au Au Au Au Au Au Au Au Au Au Au Au Au Au Au Au Cu Cu Cu Au Au Au Au Au Au PKG LBGA QFP PBGA TQFP PBGA LQFP PLCC QFP TQFP PBGA LBGA TQFP LBGA LQFP LBGA QFN TQFP LQFP PLCC PBGA LBGA QFN LQFP LQFP TQFP LBGA LQFP PLCC TQFP LEAD 56 208 256 44 256 48 44 208 48 256 132 48 256 100 256 208 48 48 44 900 36 84 100 208 48 256 100 44 48 24 month Total Product C4064ZCD FXP2 C5256MV C4032VD C5256MV 5D064 IPL2032A FXP6C A4064VS FX125EB C4128ZCS C4032VD C4256VD 3D128 C4256VD FXP2-8E A4064VS PWR1014A IPL1016E SCM15E ICE40LP1K ICE40LP1K MXO256C C5512MV A4064VS C4256VD PWR1220AT8 IPL1016E C4032VD Lot Number DH2171B4 CT34K64472011 AH3HQTWN004 DG4HR2NL006 AH3HR0H3004 4192R3W45A5 CG6608Z1 CR74E8427001A1 DG7407CA23 BZ6HRJTP004 DF41818 DG54339 CH3275C23 CM1119A03 CH3278C18 CT34K69072014 DG745514 DA4R41YQB1 7440201C1 CD54K73204013 DE1NNA790001 DE1NNF0430010 4K65907058 MH2553 DG74762 CH3286A4 CX4153C1 744020412 DG54688 Qty 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 870 Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 63 Lattice Semiconductor 10.3 Q1 2016 Lattice Products Reliability Report Unbiased Highly Accelerated Stress Testing (uHAST) Surface Mount Pre-Conditioning (MSL3) Method: JEDEC J-STD-020 Duration: 96, 168 hours at 130°C / 85% R.H. / 2 atmospheres Method: JEDEC JESD22-A118 Monitor Date Assembler May-14 ASEM Jul - 14 ASEM Oct-14 ASEM Feb-15 ASEM Apr-15 ASEM Sep-15 ASEM Oct-15 ASEM Nov-15 ASEM Bondwire Au Cu Au Cu Au Au Cu Cu Au Au Cu Au Cu Au Cu Au Cu Au Au Au Cu Cu Cu Cu Cu Au Cu Au Cu Cu Au Cu Cu Au Au Au Cu Cu Au Au Cu Cu Cu Cu Cu Cu Cu Cu Cu Au Au PKG LBGA PBGA QFP TQFP PBGA TQFP LQFP LBGA PBGA LQFP LQFP PLCC LBGA QFP PBGA TQFP TQFP PBGA LBGA TQFP TQFP LBGA LQFP PBGA LBGA LBGA LBGA LQFP LQFP PBGA LBGA LBGA LQFP QFN TQFP LQFP TQFP PBGA PLCC PBGA LBGA LQFP LBGA PBGA LBGA QFN PBGA LQFP LBGA LQFP TQFP LEAD 56 484 208 48 256 44 100 36 256 48 100 44 36 208 256 48 48 256 132 48 48 184 100 256 36 256 256 100 144 484 256 36 144 208 48 48 100 672 44 900 36 100 256 1156 132 84 1156 100 256 208 48 Product C4064ZCD FE3-17EA FXP2 C4064ZE C5256MV C4032VD MX02-256HC ICE40LP1K C5256MV 5D064 MXO2-256H IPL2032A ICE40LP640 FXP6C FE2-6SE A4064VS C4064ZE FX125EB C4128ZCS C4032VD C4032ZE MX02-4000HE MX02-640HC FE2-6E ICE40LP1K C4256VD MXO3L-69C 3D128 MXO640C FE2-20E C4256VD ICE40LP1K MXO2-1200HC FXP2-8E A4064VS PWR1014A ICE40HX1K FE3-70EA IPL1016E SCM15E ICE40LP1K MXO256C MXO640C FE3-150EA MXO2-1200HC ICE40LP1K FE3-95EA MXO256C MXO640C C5512MV A4064VS Lot Number DH2171B4 CY84C164870115 CT34K64472011 CV417612 AH3HQTWN004 DG4HR2NL006 CW14C15713016 DE1NKY422004 AH3HR0H3004 4192R3W45A5 CW14C17870014 CG6608Z1 DE1NMK226009 CR74E8427001A1 CC24K651100113 DG7407CA23 CV41825 BZ6HRJTP004 DF41818 DG54339 CJ314825 DL84C23619013 CW64C199250115 CC24K66803017 DE1NMP7490011 CH3275C23 DM44C23469012 CM1119A03 CN84E836240116 CB94K676770116 CH3278C18 DE1NMY732006 DL24C217230111 CT34K69072014 DG745514 DA4R41YQB1 DB8NCK7610013 CZ24K69667013 7440201C1 CD54K73204013 DE1NNA790001 CN64E845460110 CN84E84549019 CY74C26668015 DL24C262190112 DE1NNF0430010 CZ24K70575013 4K65907058 4K65818012 MH2553 DG74762 Qty 30 40 30 40 30 30 40 40 30 30 40 30 40 30 40 30 40 30 30 30 40 40 40 40 40 30 40 30 40 40 30 30 40 30 30 30 40 40 30 30 30 40 40 40 40 30 40 30 40 30 30 Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 64 Lattice Semiconductor Monitor Date Assembler Mar-16 ASEM Q1 2016 Bondwire Au Au Au Au Cu PKG LBGA LQFP PLCC TQFP TQFP Lattice Products Reliability Report LEAD 256 100 44 48 48 24 month Total Product C4256VD PWR1220AT8 IPL1016E C4032VD C5010A Lot Number CH3286A4 CX4153C1 744020412 DG54688 CV420610 Qty 30 30 30 30 40 1940 Fail 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 65 Lattice Semiconductor 10.4 Q1 2016 Lattice Products Reliability Report High Temperature Storage (HTS) Surface Mount Pre-Conditioning (MSL3) Method: JEDEC J-STD-020 Duration: 1000 hours at 150°C ambient Method: JEDEC JESD22-A103 Monitor Date Assembler May-14 ASEM Jul-14 ASEM Oct-14 ASEM Feb-15 ASEM Apr-15 ASEM Sep-15 ASEM Oct-15 ASEM Nov-15 ASEM Bondwire Au Cu Au Cu Au Au Cu Cu Au Au Cu Au Cu Au Cu Au Cu Au Au Au Cu Cu Cu Cu Cu Au Cu Au Cu Cu Au Cu Cu Au Au Au Cu Cu Au Au Cu Cu Cu Cu Cu Cu Cu Cu Cu Au Au PKG LBGA PBGA QFP TQFP PBGA TQFP LQFP LBGA PBGA LQFP LQFP PLCC LBGA QFP PBGA TQFP TQFP PBGA LBGA TQFP TQFP LBGA LQFP PBGA LBGA LBGA LBGA LQFP LQFP PBGA LBGA LBGA LQFP QFN TQFP LQFP TQFP PBGA PLCC PBGA LBGA LQFP LBGA PBGA LBGA QFN PBGA LQFP LBGA LQFP TQFP Lead 56 484 208 48 256 44 100 36 256 48 100 44 36 208 256 48 48 256 132 48 48 184 100 256 36 256 256 100 144 484 256 36 144 208 48 48 100 672 44 900 36 100 256 1156 132 84 1156 100 256 208 48 Product C4064ZCD FE3-17EA FXP2 C4064ZE C5256MV C4032VD MX02-256HC ICE40LP1K C5256MV 5D064 MXO2-256H IPL2032A ICE40LP640 FXP6C FE2-6SE A4064VS C4064ZE FX125EB C4128ZCS C4032VD C4032ZE MX02-4000HE MX02-640HC FE2-6E ICE40LP1K C4256VD MXO3L-69C 3D128 MXO640C FE2-20E C4256VD ICE40LP1K MXO2-1200HC FXP2-8E A4064VS PWR1014A ICE40HX1K FE3-70EA IPL1016E SCM15E ICE40LP1K MXO256C MXO640C FE3-150EA MXO2-1200HC ICE40LP1K FE3-95EA MXO256C MXO640C C5512MV A4064VS Lot Number DH2171B4 CY84C164870115 CT34K64472011 CV417612 AH3HQTWN004 DG4HR2NL006 CW14C15713016 DE1NKY422004 AH3HR0H3004 4192R3W45A5 CW14C17870014 CG6608Z1 DE1NMK226009 CR74E8427001A1 CC24K651100113 DG7407CA23 CV41825 BZ6HRJTP004 DF41818 DG54339 CJ314825 DL84C23619013 CW64C199250115 CC24K66803017 DE1NMP7490011 CH3275C23 DM44C23469012 CM1119A03 CN84E836240116 CB94K676770116 CH3278C18 DE1NMY732006 DL24C217230111 CT34K69072014 DG745514 DA4R41YQB1 DB8NCK7610013 CZ24K69667013 7440201C1 CD54K73204013 DE1NNA790001 CN64E845460110 CN84E84549019 CY74C26668015 DL24C262190112 DE1NNF0430010 CZ24K70575013 4K65907058 4K65818012 MH2553 DG74762 Qty 30 40 30 40 30 30 40 40 30 30 40 30 40 30 40 30 40 30 30 30 40 40 40 40 40 30 40 30 40 40 30 30 40 30 30 30 40 40 30 30 30 40 40 40 40 30 40 30 40 30 30 Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 66 Lattice Semiconductor Monitor Date Assembler Mar-16 ASEM Q1 2016 Bondwire Au Au Au Au Cu PKG LBGA LQFP PLCC TQFP TQFP Lattice Products Reliability Report Lead 256 100 44 48 48 24 month Total Product C4256VD PWR1220AT8 IPL1016E C4032VD C5010A Lot Number CH3286A4 CX4153C1 744020412 DG54688 CV420610 Qty 30 30 30 30 40 1940 Fail 0 0 0 0 0 0 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 67 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 11.0 PROCESS RELIABILITY WAFER LEVEL REVIEW Several key fabrication process related parameters have been identified by the foundry that would affect the Reliability of the End-Product. These parameters are tested during the Development Phase of the Technology. Passing data (a 10yr lifetime at the reliability junction temperature) must be obtained for three lots minimum for each parameter before release to production. Normal operating conditions are defined in the Electrical Design Rules (EDR). These parameters are: Table 11.0 – WLR Results by Process Technology Technology UM4DS UM4AR UM5MC UMVI UM6P3/5 UM8 UM10 EE8 EE8A EE9 CS90F CS90A/L CS100A/L CS100A-EC CS100F CS200A CS200F 40LP Node 1.0 μm 1.0 μm 0.7 μm 0.6 μm 0.5 μm 0.35 μm 0.25 μm 0.35 μm 0.35 μm 0.18 μm 130 nm 130 nm 90 nm 90 nm 90 nm 65 nm 65 nm 40 nm Type EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM Flash SRAM SRAM SRAM Flash SRAM Flash SRAM HCI P P P P P P P P P P P P P P P P P P NBTI na na na na na na na na na na P P P P P P P P TDDB P P P P P P P P P P P P P P P P P P EML P P P P P P P P P P P P P P P P P P SM na na na na na na na na na na P P P P P P P P Hot Carrier Immunity (HCI): Effect is a reduction in transistor drive current. Stress data is plotted and projected back to normal operating conditions. Negative Bias Temperature Instability (NBTI): Effect is a reduction in transistor drive current and a shift in threshold voltage. Stress data is plotted and projected back to normal operating conditions. Time Dependent Dielectric Breakdown (TDDB): Correlates to transistor and capacitor oxide shorts (breakdown) or excessive leakage. Statistical sample data is plotted Weibull and the 0.1% cumulative fail lifetime is obtained and accelerated to normal operating conditions. Electromigration Lifetime (EML): Correlates to opens in metal conductors on chip and to shorts between closely spaced conductors. Statistical sample data is plotted Weibull and the 0.1% cumulative fail lifetime is obtained and accelerated to normal operating conditions. Stress Migration (SM): Correlates to opens in Copper Vias at high stress points. Most affected by Dual Damascene metal patterning technology with LowK dielectrics. A long-term stress is applied at elevated temperature. If there are no fails, the stress time is accelerated to normal operating conditions. Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 68 Lattice Semiconductor Q1 2016 Lattice Products Reliability Report 12.0 PACKAGE ASSEMBLY MONITORING DATA Lattice Semiconductor Corp. conducts a Package Assembly Monitoring program to evaluate package quality and to verify correct manufacturing steps were completed. This monitor is completed either monthly or quarterly depending on the manufacturing volume of the packages covered. Details of the test plan can be found in Table 4.3 – QA Package Monitor Testing. PASS FlipChip TQFP/LQFP/PQ FP/QFN (12/15) WLCSP PLCC (2/16) Subcon PBGA/FPBGA/ FTBGA/CABGA /PBGA PDIP Table 12.1: Package Monitoring Results1 UNISEM INDONESIA AIT AMKOR PHILIPPINES AAP3 (2/16) PASS PASS PASS ASE MALAYSIA ASE PASS PASS UTAC SINGAPORE ASE TAIWAN PASS ASET PASS PASS Not Building Pass Failed Last Tested Tests performed for monitoring data: 1) External Visual 2) Scanning Acoustical Microscope 3) Physical Dimensions 4) X-Ray 5) Solderability (except BGA devices) 6) Resistance to Solvents 7) Decap- Internal Visual 8) Wire Bond Pull 9) Bond Shear 10) Ball Shear (BGA devices only) 1 as of Apr 2016 Lattice Semiconductor Corporation Doc 73-107566 Rev. A Return to INDEX 69 Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, Oregon 97124 U.S.A. Telephone: (503) 268-8000, FAX: (503) 268-8556 www.latticesemi.com © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.