IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES IDT74FCT3932-100 IDT74FCT32932-100 3.3V LOW SKEW PLL-BASED ADVANCE INFORMATION CMOS CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • 0.5 MICRON CMOS Technology Guaranteed low skew 16 programmable frequency configurations 17 3-state outputs: ±24 mA FCT3932 ±8 mA FCT32932 Output configuration: BANK1: 4 outputs BANK2: 8 outputs BANK3: 5 outputs Dedicated feedback output (Q_FB) Maximum output frequency: 100MHz VCC = 3.3V ±0.3V Inputs can be driven from 3.3V or 5V components Available in 48 SSOP, TSSOP packages Suited to SDRAM applications DESCRIPTION: The FCT3932 uses phase-lock loop technology to lock the frequency and phase of the feedback to the input reference clock. It provides a large number of low skew outputs that are configurable in 16 different modes using the CNTRL 1-4 inputs. A dedicated output, Q_FB, is provided to supply the PLL feedback and it should be connected to the FEEDBACK input. Q_FB is located adjacent to FEEDBACK to minimize the delay in the feedback path. In order to offset any delay in the output path from the FCT3932 output to a receiving device, FUNCTIONAL BLOCK DIAGRAM feedback path delay should be made to match this output path delay. The PLL consists of the phase/frequency detector, charge pump, loop filter and VCO. The FCT3932 requires no external loop filter components. The FCT3932 provides 17 outputs grouped in 3 banks with individual 3-state control and an additional dedicated feedback output with no disable. Connecting Q_FB to FEEDBACK ensures uninterrupted PLL operation when all outputs are disabled. Individual bank 3-state allows users to disable unused outputs in order to limit power dissipation or minimize switching noise. It also allows users to shut down outputs in low power modes while maintaining phase lock. The FCT3932 provides a LOCK pin that goes high when the device is phase-locked. The user can bypass the PLL for testability purposes by deasserting PLL_EN. In this "test" mode, the input frequency is not limited to the specified range. The FCT3932 provides an asynchronous reset input, , which resets all outputs. This initializes all internal registers so that outputs start up in a known state. RST APPLICATIONS: SDRAM DIMM Clock, Caches, high speed microprocessors, motherboard clock distribution to DIMMs. LOCK FEEDBACK Phase/Freq. Detector REF_IN PLL_EN 0 Voltage Controlled Oscillator Charge Pump & Loop Filter 1 Mux OE1 C O N T R O L OE2 OE3 Q41-4 (BANK 1) Q81-8 (BANK 2) Q51-5 (BANK 3) CNTRL1-4 Q_FB RST 3267 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. NOVEMBER 1996 9.9 9.9 DSC-3267/2 1 1 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATIONS Symbol Unit Q51 Description Max. VTERM(2) Terminal Voltage with Respect to –0.5 to +4.6 GND (3) Terminal Voltage with Respect to –0.5 to +7.0 VTERM GND VTERM(4) Terminal Voltage with Respect to –0.5 to VCC GND + 0.5 TSTG Storage Temperature –65 to +150 43 VCC IOUT mA 7 42 Q44 CNTRL4 8 41 Q43 Q_FB 9 40 GND FEEDBACK 10 39 Q42 GND 11 38 Q41 REF_IN 12 VCC AVCC 13 SO48-1 37 SO48-2 36 NC 14 35 Q88 AGND 15 34 Q87 GND 16 33 GND OE1 17 32 Q86 OE2 18 31 Q85 OE3 19 30 VCC RST 20 29 Q84 GND 21 28 Q83 PLL_EN 22 27 GND LOCK 23 26 Q82 VCC 24 25 Q81 VCC 1 48 Q54 Q55 2 47 Q53 CNTRL1 3 46 GND GND 4 45 Q52 CNTRL2 5 44 CNTRL3 6 VCC DC Output Current V V V °C –60 to +60 3267 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals. VCC CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V Typ. 3.2 Max. 5.0 Unit pF VOUT = 0V 3.7 8.0 pF NOTE: 1. This parameter is measured at characterization but not tested. 3267 lnk 02 SSOP TSSOP TOP VIEW 3267 drw 02 *NC = No connect 9.9 2 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Pin Name I/O Description REF_IN I Reference clock input. FEEDBACK I Feedback input to phase detector. Q41-4 O BANK1 clock outputs. Q81-8 O BANK2 clock outputs. Q51-5 O BANK3 clock outputs. OE1-3 I Output enable controls for BANKS 1, 2 and 3 (Active LOW). CNTRL1-4 I Control lines to select output configuration (see table). Q_FB O Dedicated PLL feedback output. RST I Asynchronous reset (Active LOW). PLL_EN I Disables phase-lock for low frequency testing (Refer to functional block diagram). LOCK O PLL "LOCK" indicator (HIGH when PLL is locked). 3267 tbl 03 OUTPUT FREQUENCY CONFIGURATION AND INPUT FREQUENCY RANGE TABLE MODE CNTRL 4 3 2 1 Q_FEEDBACK Q_BANK1 (4 outputs) Q_BANK2 (8 outputs) Q_BANK3 (5 outputs) FIN Range 0 0 0 0 0 F (divide-by-1) 1 0 0 0 1 F (divide-by-1) F F F F 50-100MHz F F/2 2 0 0 1 0 F (divide-by-1) 50-100MHz F F F 50-100MHz 3 0 0 1 1 4 0 1 0 0 F (divide-by-1) F F/2 F/2 50-100MHz F (divide-by-1) F F/3 F 50-100MHz 5 6 0 1 0 1 F (divide-by-3) 3F 3F F 16.7-33.3MHz 0 1 1 0 F (divide-by-3) 3F F 3F 16.7-33.3MHz 7 0 1 1 1 F (divide-by-3) 3F 3F 3F 16.7-33.3MHz 8 1 0 0 0 F (divide-by-2) 2F 2F 2F 25-50MHz 9 1 0 0 1 F (divide-by-2) 2F F 2F 25-50MHz 10 1 0 1 0 F (divide-by-2) 2F F F 25-50MHz 11 1 0 1 1 F (divide-by-2) 2F F F/2 25-50MHz 12 1 1 0 0 F (divide-by-2) 2F F/2 F 25-50MHz 13 1 1 0 1 F (divide-by-4) 4F 2F 4F 12.5-25MHz 14 1 1 1 0 F (divide-by-4) 4F 2F 2F 12.5-25MHz 15 1 1 1 1 F (divide-by-4) 4F 2F F 12.5-25MHz 3267 tbl 04 9.9 3 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to 70°C, VCC = 3.3V ± 0.3V Symbol VIH Parameter Input HIGH Level (Input pins) Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 Typ.(2) — Max. 5.5 2.0 — VCC+0.5 Guaranteed Logic LOW Level –0.5 — 0.8 V VI = 5.5V — — ±1 µA VI = GND — — ±1 VO = VCC — — ±1 VO = GND — — ±1 — –0.7 –1.2 VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (3) –36 –75 1.5V (3) 50 75 — — Input HIGH Level (I/O pins) VIL Input LOW Level Unit V (Input and I/O pins) II H Input HIGH Current (Input pins) II L Input LOW Current (Input pins) IOZH High Impedance Output Current IOZL (3-State Output pins) VIK Clamp Diode Voltage IODH Output HIGH Current VCC = Max. VCC = Max. VCC = Min., IIN = –18mA IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max., VIN = GND or VCC µA V mA mA 6 mA 3267 tbl 05 TYPE 1 DRIVER - FCT3932 Symbol VOH Parameter Output HIGH Voltage VCC = Min. Test Conditions(1) IOH = –0.1mA Min. Typ.(2) VCC–0.2 — Max. — Unit V VIN = VIH or VIL VOL Output LOW Voltage VCC = 3.0V VIN = VIH or VIL VCC = Min. IOH = –8mA 2.2 (4) IOL = 0.1mA VIN = VIH or VIL IOL = 16mA IOL = 24mA 2.4 — — — 0.2 — 0.2 0.4 — 0.3 0.5 V 3267 tbl 06 TYPE 2 DRIVER - FCT32932 Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min. IOH = –0.1mA Min. Typ.(2) VCC–0.2 — Max. — Unit V VIN = VIH or VIL VOL Output LOW Voltage VCC = 3.0V VIN = VIH or VIL VCC = Min. IOH = –8mA IOL = 0.05mA VIN = VIH or VIL IOL = 4mA IOL = 8mA 2.4 (4) 3.0 — — — 0.2 — 0.2 0.4 — 0.3 0.5 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. VOH = VCC –0.6V at rated current. 9.9 V 3267 tbl 07 4 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES INPUT TIMING REQUIREMENTS Symbol tRISE/FALL Parameter Rise/Fall Times REF_IN input (0.8V to 2.0V) Frequency Input Frequency REF_IN input Min. — Modes 0, 1, 2, 3, 4 Modes 5, 6, 7 Duty Cycle Unit ns MHz 50 100 16.7 33.3 25 50 12.5 25 25 75 Modes 8, 9, 10, 11, 12 Modes 13, 14, 15 Max. 3.0 Input Duty Cycle, REF_IN input % 3267 tbl 09 OUTPUT FREQUENCY SPECIFICATIONS Mode 0, 1, 2, 3,4 Parameter F, F Outputs Operating frequency Min. Max. Unit 50 100 MHz F/2 Outputs 25 50 F/3 Outputs 16.7 33.3 3F Outputs 50 100 5, 6, 7 Operating frequency F Outputs 16.7 33.3 8, 9, 10, 11, 12 Operating 2F Outputs 50 100 frequency 13, 14, 15 F Outputs 25 50 F/2 Outputs 12.5 25 Operating 4F Outputs 50 100 frequency 2F Outputs 25 50 F Outputs 12.5 25 3267 tbl 10 POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD IC Test Conditions(1) Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (5,6) VCC = Max. VIN = VCC –0.6V(3) VCC = Max. VIN = VCC All Outputs Open VIN = GND 50% Duty Cycle MODE 10 VCC = Max. PLL_EN = 1, LOCK = 1, MODE 10 REF_IN frequency = 50MHz. All outputs open F = 50Mhz Min. Typ.(2) Max. Unit — 2.0 30 µA — 72 — 62 µA/ MHz/ bit mA 3267 tbl 08 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (f) + ILOAD ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) f = SYNC input frequency ILOAD = Dynamic Current due to load. 9.9 5 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE(7) Symbol Condition(1) No Load Min.(2) –0.5 Max. +0.5 Unit ns FCT3932 CL = 20pF for FCT3932 0.5 1.5 ns FCT32932 CL = 10pF for FCT32932 0.5 2.0 Parameter tPD(3) REF_IN-Q_FB Propagation Delay (REF_IN input to Q outputs) tRISE/FALL Rise/Fall Time (between 0.8 and 2.0V) All Outputs tPW(3) Output Duty Cycle 45 55 % tSKEWr(3,4) Output to Output Skew (All outputs at same frequency rising edge) — 500 ps tSKEWf(3,4) Output to Output Skew (All outputs at same frequency falling edge) — 500 ps tSKEWall(3,4) Output to Output Skew (All outputs, rising edge any frequency) — 1.0 ns tLOCK (5) Time required to acquire Phase-Lock from time REF_IN input signal is received 1 10 ms tPZH tPZL Output Enable Time OEx (LOW-to-HIGH) to Q 3.0 8.0 ns tPHZ tPLZ Output Disable Time OEx (HIGH-to-LOW) to Q 3.0 8.0 ns GENERAL AC SPECIFICATION NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested. 3. These specifications are guaranteed but not production tested. 4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage. 5. With VCC fully powered-on and Q_FB properly connected to the FEEDBACK pin. 6. The tPD spec gives the limits of the phase offset between the REF_IN input and the Q_FB output. 7. The AC specifications are only guaranteed with the decoupling scheme shown in figure 2. 3267 tbl 13 tPD = ±0.5ns REF_IN input Feedback Output Offset 3267 drw 03 9.9 6 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES Board VCC Plane 10µF (1) (43) (7) (37) 0.1µF 0.1µF (13) FCT3932 (36) (30) 0.1µF 0.1µF (24) 0.1µF 3267 drw 04 Figure 2. Recommended Decoupling for the FCT3932/FCT32932 NOTES: 1. Figure 2 shows a decoupling scheme which will be effective in most FCT3932 applications. The following guidelines should be followed for stable, jitterfree operation: a. All decoupling capacitors should be connected as close to the package as possible. (Preferably at the device pins). b. The 10µF and 0.1µF bypass capacitors provide protection from power supply and ground plane transients. STANDARD LOAD (USED WHEN SPECIFIED) 500Ω 50pF 9.9 7 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUIT ENABLE/DISABLE TEST CIRCUIT 6.0V VCC VCC Open VOUT VIN Pulse Generator D.U.T. VOUT VIN Pulse Generator RT D.U.T. CL CL 500Ω RT PROPAGATION DELAY, OUTPUT SKEW REF_IN INPUT GND 500Ω 3267 drw 06 3267 drw 05 3V 1.5V 0V tPD VOH 1.5V VOL Q_FB tSKEWf tSKEWr VOH 1.5V VOL Qxx tSKEWr tSKEWf VOH 1.5V VOL Qyy tSKEWall tSKEWf VOH 1.5V VOL Qzz 3267 drw 07 tSKEWr ENABLE AND DISABLE TIMES ENABLE SWITCH POSITION DISABLE Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests 3V CONTROL INPUT 1.5V t PZL OUTPUT NORMALLY SWITCH LOW CLOSED t PZH OUTPUT SWITCH NORMALLY OPEN HIGH 0V t PLZ 3.5V 3.5V 1.5V 0.3V V OL V OH 1.5V 0V 6V GND Open 3267 lnk 14 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. t PHZ 0.3V Switch 0V 3267 drw 08 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns 9.9 8 IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX FCT IDT XX Temp. Range Device Type X Speed X Package PV PA Small Shrink Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) 100 50 - 100Mhz 3932 3.3V Low skew PLL-based 32932 CMOS clock driver 74 9.9 0°C to +70°C 3267 drw 09 9