! " Standard Cell ASIC Structured ASIC # # # #$ % # # # 1. Fast Time to Market: 2. Very Low NRE: 3. Low Risk: 4. ASIC Performance: & ' !()&!%%& %% *& # +! Prototypes in 6-7 weeks from hand-off As little as $25K Pre-built IP, clock trees, analog Over 300MHz in 0.13 # * ,' % - ' ' ' !%%& %%& % #$./0 ! ! 4 - 2+5 67 /! 1+.23/0 - # # ! # 9: " ' # 86 # 86 # , # 8 & # 8 # # 0 # # 6# *!/ # # & ## # #& # ! ' 0 ## # , + # *!/ # # ) 8 # ' ; ' # # 8 ## (7< ' #' *!/ ' # , # # ' # ## # ! ##= # IP Phy Pins IP Phy CX6000 Structured ASIC Interposer To Target ASIC Footprint IP Phy Backend Internal Phy Interface Remainder Of Pkg Signal Pins ASIC Footprint Soft IP Controller FPGA FPGA •••••• ••••• • ••••••• • •• •• •• •• •• •• •• •• •• •• Programmable FPGA Pins OnePass™ System System Board < ! ##= # # # # ! 8 6 ## ,' # ?555 *!/ # # !() # & 8 ## # ! ##= > ## # @5+.1 A % *# 4# # # ' # # ' , # # 8 7< ' ## B *!/ # < " # # # ! ##= > # # # # # 8 4# # # ' # ! ##= ASIC RTL Customer Domain Pinout Translator Linter and Checker No Pass OnePass Library Wrapper Synthesis FPGA Library Gate Level Checker Report Final RTL ASIC Constraints FPGA flow System Test Check RTL w/OnePass RTL Checker Tool Execute ASIC Flow w/out Optimization Yes Constraint Generator * 8 Handoff to ChipX Generate Report: - Max frequency - Gate count - Slice fitting - Power - STA critical paths ChipX Domain Customer can Upload RTL to ChipX and report will be emailed Automatically Within 24 hrs. ! ##= No design conversion necessary One flow for both FPGA and ASIC development All ASIC requirements generated during flow Automatic pre-processing of design by ChipX to provide vital information to customer. Operation can be repeated as often as needed Most timing issues addressed up front Guarantee that design will fit in ASIC Short backend processing time – Two to Four weeks from final RTL to Tape Out. #