IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE 1:4 CLOCK BUFFER IDT5V551 FEATURES: DESCRIPTION: • • • • • • • • • • The 5V551 clock driver is built using advanced CMOS technology. This low skew clock driver offers 1:4 fanout. The fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. The 5V551 offers low capacitance inputs. Typical applications are clock and signal distribution. Advanced, low power CMOS process 5V tolerant inputs Low skew outputs (<250ps) Input/Output frequency up to 160MHz Non-inverting output clock Ideal for networking clocks Operating voltage of 3V Output enable mode tri-states outputs Lead-free packaging available Available in SOIC package PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM Q1 Q2 ICLK Q3 ICLK 1 8 OE Q1 2 7 VDD Q2 3 6 GND Q3 4 5 Q4 Q4 SOIC TOP VIEW OUTPUT ENABLE The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE MAY 2006 1 c 2006 Integrated Device Technology, Inc. DSC - 6567/10 IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD VTERM Unit Name –0.5 to +4.6 V ICLK Input Clock Input, internal pull-up resistor –0.5 to +7 V Qn Output Clock Outputs Description Supply Voltage Max. All Inputs Type Description GND PWR Connect to Ground Ambient Operating Temp –40 to +85 °C VDD PWR Connect to 3.3V TSTG Storage Temperature –65 to +150 °C OE Input Output Enable. Tri-states outputs when LOW. TJ Junction Temperature 150 °C TSOLDER Soldering Temperature 260 °C All Outputs TA –0.5 to VDD + 0.5 Internal pull-up resistor. NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. EXTERNAL COMPONENTS A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01μF should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33Ω series terminating resistor may be used on each clock output if the trace is longer than one inch. RECOMMENDED OPERATING RANGE Symbol Description Min. Typ. Max. Unit TA Ambient Operating Temperature –40 — +85 °C VDD Power Supply Voltage (measured in respect to GND) 3 — 3.6 V DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified TA = -40°C to +85°C, VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Operating Voltage 3.15 — 3.45 V VIH Input HIGH Voltage, ICLK(1) VDD/2 + 0.7 — — V VIL Input LOW Voltage, ICLK(1) — — VDD/2 – 0.7 V VIH Input HIGH Voltage, OE 2 — — V VIL Input LOW Voltage, OE — — 0.8 V VOH Output HIGH Voltage IOH = –25mA 2.4 — — V VOL Output LOW Voltage IOL = 25mA — — 0.4 V VOH Output HIGH Voltage (CMOS) IOH = –12mA VDD – 0.4 — — V IDD Operating Supply Current No Load, 135MHz ZO Nominal Output Impedance RPU Internal Pull-Up Resistor CIN Input Capacitance ICLK IOS — 18 — mA — 20 — Ω ICLK, OE = 0V — 350 — kΩ OE Pin — 5 — pF — 3 — — ±90 — Short Circuit Current NOTE: 1. Nominal switching threshold is VDD/2. 2 mA IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified TA = -40°C to +85°C, VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit FIN Input Frequency 0 — 160 MHz FOUT Output Frequency(1) 15pF load — — 160 MHz tOR Output Clock Rise Time 0.8V to 2V — — 1.5 ns tOF Output Clock Fall Time 2V to 0.8V — — 1.5 ns tPD Propagation Delay(2) 135MHz 2 4 8 ns Output to Output Skew(3) Rising edges at VDD/2 — — 250 ps tSK(O) NOTES: 1. With external series resistor of 33Ω positioned close to each output pin. 2. With rail-to-rail input clock. 3. Between any two outputs with equal loading. 4. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators. TEST CIRCUIT VDD VIN VOUT Pulse Generator D.U.T. RL RT TEST CONDITIONS Symbol VDD = 3.3V ± 5% Unit CL 15 pF RT ZOUT of pulse generator Ω RL 33 Ω tR/tF 1 (0V to 3V or 3V to 0V) ns DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to the ZOUT of the pulse generator. tR/tF = Rise/Fall time of the input stimulus from the pulse generator. 3 CL IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXX Device Type X Package X Temp. Range CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 I Industrial (-40°C to +85°C) DC DCG Small Outline IC SOIC - Green 5V551 1:4 Clock Buffer for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 4 for Tech Support: [email protected]