Single-Phase High-Performance Wide-Span Energy Metering IC 90E21/22/23/24 Version 6 January 10, 2012 6024 Silver Creek Valley Road, San Jose, CA 95138 Printed in U.S.A. © 2012 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Table of Contents FEATURES .............................................................................................................................................................................. 6 APPLICATION ......................................................................................................................................................................... 6 DESCRIPTION......................................................................................................................................................................... 6 BLOCK DIAGRAM .................................................................................................................................................................. 7 1 PIN ASSIGNMENT ............................................................................................................................................................. 9 2 PIN DESCRIPTION .......................................................................................................................................................... 10 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 12 3.1 3.2 3.3 3.4 3.5 3.6 3.7 DYNAMIC METERING RANGE .................................................................................................................................................................... 12 STARTUP AND NO-LOAD POWER ............................................................................................................................................................. 12 ENERGY REGISTERS .................................................................................................................................................................................. 12 N LINE METERING AND ANTI-TAMPERING .............................................................................................................................................. 13 3.4.1 Metering Mode and L/N Line Current Sampling Gain Configuration ......................................................................................... 13 3.4.2 Anti-Tampering Mode .................................................................................................................................................................... 13 MEASUREMENT AND ZERO-CROSSING ................................................................................................................................................... 14 3.5.1 Measurement .................................................................................................................................................................................. 14 3.5.2 Zero-Crossing ................................................................................................................................................................................. 14 CALIBRATION .............................................................................................................................................................................................. 15 RESET ........................................................................................................................................................................................................... 15 4 INTERFACE ..................................................................................................................................................................... 16 4.1 4.2 4.3 SERIAL PERIPHERAL INTERFACE (SPI) ................................................................................................................................................... 16 4.1.1 Four-Wire Mode .............................................................................................................................................................................. 16 4.1.2 Three-Wire Mode ............................................................................................................................................................................ 17 4.1.3 Timeout and Protection ................................................................................................................................................................. 18 WARNOUT PIN FOR FATAL ERROR WARNING ....................................................................................................................................... 18 LOW COST IMPLEMENTATION IN ISOLATION WITH MCU ...................................................................................................................... 18 5 REGISTER ........................................................................................................................................................................ 19 5.1 5.2 5.3 5.4 5.5 REGISTER LIST ............................................................................................................................................................................................ 19 STATUS AND SPECIAL REGISTER ............................................................................................................................................................ 21 METERING/ MEASUREMENT CALIBRATION AND CONFIGURATION .................................................................................................... 25 5.3.1 Metering Calibration and Configuration Register ....................................................................................................................... 25 5.3.2 Measurement Calibration Register ............................................................................................................................................... 32 ENERGY REGISTER .................................................................................................................................................................................... 37 MEASUREMENT REGISTER ....................................................................................................................................................................... 41 6.1 6.2 6.3 6.4 6.5 6.6 6.7 ELECTRICAL SPECIFICATION ................................................................................................................................................................... 48 SPI INTERFACE TIMING .............................................................................................................................................................................. 50 POWER ON RESET TIMING ........................................................................................................................................................................ 51 ZERO-CROSSING TIMING ........................................................................................................................................................................... 51 VOLTAGE SAG TIMING ............................................................................................................................................................................... 52 PULSE OUTPUT ........................................................................................................................................................................................... 52 ABSOLUTE MAXIMUM RATING .................................................................................................................................................................. 53 6 ELECTRICAL SPECIFICATION ....................................................................................................................................... 48 PACKAGE DIMENSIONS...................................................................................................................................................... 54 ORDERING INFORMATION.................................................................................................................................................. 57 Table of Contents 3 January 10, 2012 List of Tables Table-1 Table-2 Table-3 Table-4 Table-5 Table-6 Table-7 Table-8 Table-9 Table-10 Table-11 Table-12 Table-13 Table-14 Table-15 Function List ................................................................................................................................................................................................... 6 Pin Description ............................................................................................................................................................................................. 10 Active Energy Metering Error ....................................................................................................................................................................... 12 Reactive Energy Metering Error ................................................................................................................................................................... 12 Threshold Configuration for Startup and No-Load Power ............................................................................................................................ 12 Energy Registers ......................................................................................................................................................................................... 12 Metering Mode ............................................................................................................................................................................................. 13 The Measurement Format ........................................................................................................................................................................... 14 Read / Write Result in Four-Wire Mode ....................................................................................................................................................... 18 Read / Write Result in Three-Wire Mode ..................................................................................................................................................... 18 Register List ................................................................................................................................................................................................. 19 SPI Timing Specification .............................................................................................................................................................................. 50 Power On Reset Specification ..................................................................................................................................................................... 51 Zero-Crossing Specification ......................................................................................................................................................................... 52 Voltage Sag Specification ............................................................................................................................................................................ 52 List of Tables 4 January 10, 2012 List of Figures Figure-1 Figure-2 Figure-3 Figure-4 Figure-5 Figure-6 Figure-7 Figure-8 Figure-9 Figure-10 Figure-11 Figure-12 Figure-13 Figure-14 Figure-15 90E21 Block Diagram .................................................................................................................................................................................... 7 90E22 Block Diagram .................................................................................................................................................................................... 7 90E23 Block Diagram .................................................................................................................................................................................... 8 90E24 Block Diagram .................................................................................................................................................................................... 8 Pin Assignment (Top View) ............................................................................................................................................................................ 9 Read Sequence in Four-Wire Mode ............................................................................................................................................................ 16 Write Sequence in Four-Wire Mode ............................................................................................................................................................. 16 Read Sequence in Three-Wire Mode .......................................................................................................................................................... 17 Write Sequence in Three-Wire Mode ........................................................................................................................................................... 17 4-Wire SPI Timing Diagram ......................................................................................................................................................................... 50 3-Wire SPI Timing Diagram ......................................................................................................................................................................... 50 Power On Reset Timing Diagram ................................................................................................................................................................ 51 Zero-Crossing Timing Diagram ................................................................................................................................................................... 51 Voltage Sag Timing Diagram ...................................................................................................................................................................... 52 Output Pulse Width ..................................................................................................................................................................................... 52 List of Figures 5 January 10, 2012 Single-Phase High-Performance 90E21/22/23/24 Wide-Span Energy Metering IC FEATURES Other Features Metering Features • 3.3V single power supply. Operating voltage range: 2.8~3.6V. Metering accuracy guaranteed within 3.0V~3.6V. 5V compatible for digital input. • Built-in hysteresis for power-on reset. • Four-wire SPI interface or simplified three-wire SPI interface with fixed 24 cycles for all registers operation • Parameter diagnosis function and programmable interrupt output of the IRQ interrupt signal and the WarnOut signal. • Programmable voltage sag detection and zero-crossing output. • Channel input range - Voltage channel (when gain is '1'): 120µVrms~600mVrms. - L line current channel (when gain is '24'): 5µVrms~25mVrms. - N line current channel (when gain is '1'): 120µVrms~600mVrms. • Programmable L line current gain: 1, 4, 8, 16, 24; Programmable N line gain: 1, 2, 4. • Support L line and N line offset compensation. • CF1 and CF2 output active and reactive energy pulses respectively which can be used for calibration or energy accumulation. • Crystal oscillator frequency: 8.192 MHz. On-chip 10pF capacitors and no need of external capacitors. • Green SSOP28 package. • Operating temperature: -40 ℃ ~ +85 ℃ . • Metering features fully in compliance with the requirements of IEC62052-11, IEC62053-21 and IEC62053-23; applicable in class 1 or class 2 single-phase watt-hour meter or class 2 singlephase var-hour meter. • Accuracy of 0.1% for active energy and 0.2% for reactive energy over a dynamic range of 5000:1. • Temperature coefficient is 15 ppm/ ℃ (typical) for on-chip reference voltage • Single-point calibration over a dynamic range of 5000:1 for active energy; no calibration needed for reactive energy. • Energy Meter Constant doubling at low current to save verification time. • Electrical parameters measurement: less than ±0.5% fiducial error for Vrms, Irms, mean active/ reactive/ apparent power, frequency, power factor and phase angle. • Forward/ reverse active/ reactive energy with independent energy registers. Active/ reactive energy can be output by pulse or read through energy registers to adapt to different applications. • Programmable startup and no-load power threshold. • Dedicated ADC and different gains for L line and N line current sampling circuits. Current sampled over shunt resistor or current transformer (CT); voltage sampled over resistor divider network or potential transformer (PT). • Programmable L line and N line metering modes: anti-tampering mode (larger power), L line mode (fixed L line), L+N mode (applicable for single-phase three-wire system) and flexible mode (configure through register). • Programmable L line and N line power difference threshold in anti-tampering mode. APPLICATION • The 90E21/22/23/24 series are used for active and reactive energy metering for single-phase two-wire, single-phase threewire or anti-tampering energy meters. With the measurement function, the 90E21/22/23/24 series can also be used in power instruments which need to measure voltage, current, etc. DESCRIPTION 90E21/22/23/24 are all of green SSOP28 package with the same pin alignment. In this datasheet, all reactive energy metering parts are only applicable for the 90E22/24, and all N line metering and measurement parts are only applicable for the 90E23/24. The 90E21/22/23/24 series are high-performance wide-span energy metering chips. IDT's proprietary ADC and DSP technology ensure the chips' long-term stability over variations in grid and ambient environmental conditions. Table-1 Function List Part Number 90E21 90E22 90E23 90E24 Active Energy Reactive Energy Metering Metering √ √ √ √ N Line Metering √ √ √ √ Electrical Parameters Measurement √ √ √ √ IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 6 2012 Integrated Device Technology, Inc. January 10, 2012 DSC-7277/6 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC BLOCK DIAGRAM I1P I1N VP VN Vref PGA X1/X4/X8/ X16/X24 PGA X1 DSP Module ∑△ADC HPF0 L Line Forward/Reverse Active Power L Line Apparent Power L Line Irms HPF1 HPF0 Vrms ∑△ADC Reference Voltage Crystal Oscillator RESET HPF1 3-wire or 4-wire SPI Active Energy Pulse Output Power Factor/ Angle/Frequency WarnOut/IRQ/ZX Power On Reset OSCI OSCO CS SCLK SDO SDI CF1 WarnOut IRQ ZX Figure-1 90E21 Block Diagram I1P I1N VP VN Vref PGA X1/X4/X8/ X16/X24 PGA X1 DSP Module ∑△ADC HPF0 L Line Forward/Reverse Active/ Reactive Power L Line Apparent Power L Line Irms HPF1 HPF0 Vrms ∑△ADC Reference Voltage Crystal Oscillator RESET HPF1 3-wire or 4-wire SPI Power On Reset OSCI OSCO CS SCLK SDO SDI Active Reactive Energy Pulse Energy Pulse Output Output CF1 CF2 WarnOut/IRQ/ZX WarnOut IRQ Power Factor/ Angle/Frequency ZX Figure-2 90E22 Block Diagram Block Diagram 7 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MMD1 I1P I1N VP VN I2P I2N Vref PGA X1/X4/X8/ X16/X24 DSP Module ∑△ADC PGA X1 ∑△ADC PGA X1/X2/X4 ∑△ADC HPF1 HPF0 L Line Forward/Reverse Active Power L Line Apparent Power L Line Irms HPF1 HPF0 Vrms HPF1 HPF0 N Line Forward/Reverse Active Power N Line Apparent Power N Line Irms Reference Voltage Crystal Oscillator RESET MMD0 3-wire or 4-wire SPI Active Energy Pulse Output Power Factor/ Angle/Frequency WarnOut/IRQ/ZX Power On Reset OSCI OSCO CF1 CS SCLK SDO SDI WarnOut IRQ ZX Figure-3 90E23 Block Diagram MMD1 I1P I1N VP VN I2P I2N Vref PGA X1/X4/X8/ X16/X24 PGA X1 PGA X1/X2/X4 DSP Module ∑△ADC HPF1 HPF0 L Line Forward/Reverse Active/ Reactive Power L Line Apparent Power L Line Irms HPF1 HPF0 Vrms HPF1 HPF0 N Line Forward/Reverse Active/ Reactive Power N Line Apparent Power N Line Irms ∑△ADC ∑△ADC Reference Voltage Crystal Oscillator RESET MMD0 3-wire or 4-wire SPI Power On Reset OSCI OSCO CS SCLK SDO SDI Active Reactive Energy Pulse Energy Pulse Output Output CF1 CF2 WarnOut/IRQ/ZX WarnOut IRQ Power Factor/ Angle/Frequency ZX Figure-4 90E24 Block Diagram Block Diagram 8 January 10, 2012 90E21/22/23/24 1 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PIN ASSIGNMENT MMD1 1note 1 28note 1 MMD0 DGND 2 27 SDI DVDD 3 26 SDO Reset 4 25 SCLK AVDD 5 24 CS AGND 6 23 OSCO I2P note 2 7 22 OSCI I2N 8note 2 21 ZX NC 9 20 IRQ I1P 10 19note 3 CF2 I1N 11 18 CF1 NC 12 17 WarnOut Vref 13 16 VP AGND 14 15 VN Figure-5 Pin Assignment (Top View) Note 1: Pin 1 and 28 are dedicated for the 90E23/24. Pin 1 should connect to DGND and pin 28 should connect to DVDD for 90E21/22. Note 2: Pin 7 and 8 are dedicated for the 90E23/24. They should be left open for the 90E21/22. Note 3: Pin 19 is dedicated for the 90E22/24. It should be left open for the 90E21/23. Pin Assignment 9 January 10, 2012 90E21/22/23/24 2 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PIN DESCRIPTION Table-2 Pin Description note 1 Name Pin No. Reset 4 I LVTTL DVDD 3 I Power DGND 2 I Power AVDD 5 I Power Vref 13 O Analog AGND 6, 14 I Power I1P I1N 10 11 I Analog I2P I2N 7 8 I Analog VP VN 16 15 I Analog NC 9, 12 I/O Type Reset: Reset Pin (active low) This pin should connect to ground through a 0.1µF filter capacitor. In application it can also directly connect to one output pin from microcontroller (MCU). DVDD: Digital Power Supply This pin provides power supply to the digital part. It should be decoupled with a 10µF electrolytic capacitor and a 0.1µF capacitor. DGND: Digital Ground AVDD: Analog Power Supply This pin provides power supply to the analog part. This pin should connect to DVDD through a 10Ω resistor and be decoupled with a 0.1µF capacitor. Vref: Output Pin for Reference Voltage This pin should be decoupled with a 1µF capacitor and a 1nF capacitor. AGND: Analog Ground I1P: Positive Input for L Line Current I1N: Negative Input for L Line Current These pins are differential inputs for L line current. Input range is 5µVrms~25mVrms when gain is '24'. I2P: Positive Input for N Line Current I2N: Negative Input for N Line Current These pins are differential inputs for N line current. Input range is 120µVrms~600mVrms when gain is '1'. Note: I2P and I2N are dedicated for the 90E23/24. They should be left open for the 90E21/ 22. VP: Positive Input for Voltage VN: Negative Input for Voltage These pins are differential inputs for voltage. Input range is 120µVrms~600mVrms. NC: This pin should be left open. CS 24 I LVTTL SCLK 25 I LVTTL SDO 26 OZ LVTTL SDI 27 I LVTTL MMD1 MMD0 1 28 I LVTTL Pin Description Description CS: Chip Select (Active Low) In 4-wire SPI mode, this pin must be driven from high to low for each read/write operation, and maintain low for the entire operation. In 3-wire SPI mode, this pin must be low all the time. Refer to section 4.1. SCLK: Serial Clock This pin is used as the clock for the SPI interface. Data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the chip on the falling edge of SCLK. SDO: Serial Data Output This pin is used as the data output for the SPI interface. Data on this pin is shifted out of the chip on the falling edge of SCLK. SDI: Serial Data Input This pin is used as the data input for the SPI interface. Address and data on this pin is shifted into the chip on the rising edge of SCLK. MMD1/0: Metering Mode Configuration 00: anti-tampering mode (larger power); 01: L line mode (fixed L line); 10: L+N mode (applicable for single-phase three-wire system); 11: flexible mode (line specified by the LNSel bit (MMode, 2BH)) Note: The MMD1/0 pins are dedicated for the 90E23/24. For the 90E21/22, the metering mode is fixed as L line mode, and MMD1 should connect to DGND and MMD0 should connect to DVDD. 10 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-2 Pin Description (Continued) note 1 Name Pin No. OSCI 22 I LVTTL OSCO 23 O LVTTL CF1 CF2 18 19 O LVTTL ZX 21 O LVTTL IRQ 20 O LVTTL WarnOut 17 O LVTTL I/O Type Description OSCI: External Crystal Input An 8.192 MHz crystal is connected between OSCI and OSCO. There is an on-chip 10pF capacitor, therefore no need of external capacitors. OSCO: External Crystal Output An 8.192 MHz crystal is connected between OSCI and OSCO. There is an on-chip 10pF capacitor, therefore no need of external capacitors. CF1: Active Energy Pulse Output CF2: Reactive Energy Pulse Output These pins output active/reactive energy pulses. Note: CF2 is dedicated for the 90E22/24. It should be left open for the 90E21/23. ZX: Voltage Zero-Crossing Output This pin is asserted when voltage crosses zero. Zero-crossing mode can be configured to positive zero-crossing, negative zero-crossing or all zero-crossing by the Zxcon[1:0] bits (MMode, 2BH). IRQ: Interrupt Output This pin is asserted when one or more events in the SysStatus register (01H) occur. It is deasserted when there is no bit set in the SysStatus register (01H). WarnOut: Fatal Error Warning This pin is asserted when there is metering parameter calibration error or voltage sag. Refer to section 4.2. Note 1: All digital inputs are 5V tolerant except for the OSCI pin. Pin Description 11 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3 FUNCTIONAL DESCRIPTION 3.1 DYNAMIC METERING RANGE Table-5 Threshold Configuration for Startup and No-Load Power Accuracy is 0.1% for active energy metering and 0.2% for reactive energy metering over a dynamic range of 5000:1 (typical). Refer to Table-3 and Table-4. Table-3 Active Energy Metering Error Current 20mA ≤ I ＜ 50mA 50mA ≤ I ≤ 100A Power Factor 1.0 ±0.2 ±0.1 3.3 Table-4 Reactive Energy Metering Error 20mA ≤ I ＜ 50mA 50mA ≤ I ≤ 100A 1.0 50mA ≤ I ＜ 100mA PStartTh, 27H PNolTh, 28H QStartTh, 29H QNolTh, 2AH ENERGY REGISTERS The 90E21/22/23/24 provides energy pulse output CFx (CF1/CF2) which is proportionate to active/reactive energy. Energy is usually accumulated by adding the CFx pulses in system applications. Alternatively, the 90E21/22/23/24 provides energy registers. There are forward (inductive), reverse (capacitive) and absolute energy registers for both active and reactive energy. Refer to Table-6. Error(%) ±0.4 ±0.2 ±0.4 0.5 100mA ≤ I ≤ 100A ±0.2 Note: Shunt resistor is 250 µΩ or CT ratio is 1000:1 and load resistor is 6Ω. 3.2 Threshold for Active Startup Power Threshold for Active No-load Power Threshold for Reactive Startup Power Threshold for Reactive No-load Power The chip has no-load status bits, the Pnoload/Qnoload bit (EnStatus, 46H). The chip will not output any active pulse (CF1) in active no-load state. The chip will not output any reactive pulse (CF2) in reactive noload state. ±0.2 0.5 (Inductive) 100mA ≤ I ≤ 100A 0.8 (Capacitive) ±0.1 Note: Shunt resistor is 250 µΩ or CT ratio is 1000:1 and load resistor is 6Ω. Current Register The chip will start within 1.2 times of the theoretical startup time of the configured startup power, if startup power is less than the corresponding power of 20mA when power factor or sinφ is 1.0. Error(%) 50mA ≤ I ＜ 100mA sinφ (Inductive or Capacitive) Threshold Table-6 Energy Registers STARTUP AND NO-LOAD POWER Startup and no-load power thresholds are programmable, both for active and reactive power. The related registers are listed in Table-5. Energy Register Forward Active Energy Reverse Active Energy Absolute Active Energy Forward (Inductive) Reactive Energy Reverse (Capacitive) Reactive Energy Absolute Reactive Energy APenergy, 40H ANenergy, 41H ATenergy, 42H RPenergy, 43H RNenergy, 44H RTenergy, 45H Each energy register is cleared after read. The resolution of energy registers is 0.1CF, i.e. one LSB represents 0.1 energy pulse. Functional Description 12 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.4 N LINE METERING AND ANTI-TAMPERING 3.4.1 METERING MODE AND L/N LINE CURRENT SAMPLING GAIN CONFIGURATION 1.5625%, altogether 16 choices. The configuration is made by the Pthresh[3:0] bits (MMode, 2BH) and the default value is 3.125%. The threshold is applicable for active energy. The metering line of the reactive energy follows that of the active energy. The 90E23 and 90E24 have two current sampling circuits with N line metering and anti-tampering functions. The MMD1 and MMD0 pins are used to configure the metering mode. Refer to Table-7. Compare Method In anti-tampering mode, the compare method is as follows: If current metering line is L line and Table-7 Metering Mode MMD1 MMD0 0 0 0 1 1 0 1 1 Metering Mode N Line Active Power - L Line Active Power * 100% > Threshold L Line Active Power CFx (CF1 or CF2) Output Anti-tampering (larger power) Mode CFx represents the larger energy line. Refer to section 3.4.2. CFx represents L line energy all L Line Mode (fixed L line) the time. L+N Mode (applicable for CFx represents the arithmetic single-phase three-wire sum of L line and N line energy system) Flexible Mode (line speciCFx represents energy of the fied by the LNSel bit specified line. (MMode, 2BH)) N line is switched as the metering line, otherwise L line keeps as the metering line. If current metering line is N line and L Line Active Power - N Line Active Power * 100% > Threshold N Line Active Power L line is switched as the metering line, otherwise N line keeps as the metering line. This method can achieve hysteresis around the threshold automatically. L line is employed after reset by default. The 90E23 and 90E24 have two current sampling circuits with different gain configurations. L line gain can be 1, 4, 8, 16 and 24, and N line gain can be 1, 2 and 4. The configuration is made by the MMode register (2BH). Generally L line can be sampled over shunt resistor or CT. N line can be sampled over CT for isolation consideration. Note that Rogowski coil is not supported. 3.4.2 Special Treatment at Low Power When power is low, general factors such as the quantization error or calibration difference between L line and N line might cause the power difference to be exceeded. To ensure L line and N line to start up normally, special treatment as follows is adopted: ANTI-TAMPERING MODE The line with higher power is selected as the metering line when both L line and N line power are lower than 8 times of the startup power but higher than the startup power. Threshold In anti-tampering mode, the power difference threshold between L line and N line can be: 1%, 2%,... 12%, 12.5%, 6.25%, 3.125% and Functional Description 13 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.5 MEASUREMENT AND ZERO-CROSSING 3.5.1 MEASUREMENT The above measurements are all calculated with fiducial error except for frequency. The frequency accuracy is 0.01Hz, and the other measurement accuracy is 0.5%. Fiducial error is calculated as follow: The 90E21/22/23/24 has the following measurements: • voltage rms • current rms (L line/N line) • mean active power (L line/N line) • mean reactive power (L line/N line) • voltage frequency • power factor (L line/N line) • phase angle between voltage and current (L line/N line) • mean apparent power (L line/N line) Fiducial_E rror = U mea - U real * 100% U FV Where Umea is the measured voltage, Ureal is the actual voltage and UFV is the fiducial value. Table-8 The Measurement Format 90E21/22/23/24 Defined Format Range Un Imax as 4Ib maximum power as Un*4Ib XXX.XX 0~655.35V XX.XXX 0~65.535A XX.XXX -32.768~+32.767 kW/kvar Complement, MSB as the sign bit Un*4Ib XX.XXX 0~+32.767 kVA Complement, MSB always '0' fn XX.XX 45.00~65.00 Hz 1.000 X.XXX -1.000~+1.000 Measurement Fiducial Value (FV) Voltage rms Current rms note 1, note 2 Active/ Reactive Power Apparent Power Frequency note 1 note 1 note 3 Power Factor Comment Signed, MSB as the sign bit note 4 180° XXX.X -180°~+180° Signed, MSB as the sign bit Phase Angle Note 1: All registers are of 16 bits. For cases when the current and active/reactive/apparent power goes beyond the above range, it is suggested to be handled by microcontroller (MCU) in application. For example, register value can be calibrated to 1/2 of the actual value during calibration, then multiply 2 in application. Note that if the actual current is twice of that of the 90E21/22/23/24, the actual active/reactive/apparent power is also twice of that of the chip. Note 2: The accuracy is not guaranteed when the current is lower than 15mA. Note that the tolerance is 25 mA at IFV of 5A and fiducial accuracy of 0.5%. Note 3: Power factor is obtained by active power dividing apparent power Note 4: Phase angle is obtained when voltage/current crosses zero at the frequency of 256kHz. Precision is not guaranteed at small current. 3.5.2 ZERO-CROSSING The ZX pin is asserted when the sampling voltage crosses zero. Zero-crossing mode can be configured to positive zero-crossing, negative zero-crossing and all zero-crossing by the Zxcon[1:0] bits (MMode, 2BH). Refer to section 6.4. The zero-crossing signal can facilitate operations such as relay operation and power line carrier transmission in typical smart meter applications. Functional Description 14 January 10, 2012 90E21/22/23/24 3.6 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC CALIBRATION 3.7 Metering Calibration RESET Only single-point calibration is needed over the entire dynamic range. The 90E21/22/23/24 has an on-chip power supply monitor circuit with built-in hysteresis. The 90E21/22/23/24 only works within the voltage range. Metering calibration is realized by first calibrating gain at unity power factor and then calibrating phase angle compensation at 0.5 inductive power factor. The 90E21/22/23/24 has three means of reset: power-on reset, hardware reset and software reset. All registers resume to their default value after reset. Power-on Reset: Power-on reset is initiated during power-up. Refer to section 6.3. However, due to very small signal in L line current sampling circuits, any external interference, e.g., a tens of nano volts influence voltage on shunt resistor conducted by transformer in the energy meter’s power supply may cause perceptible metering error, especially in low current state. For this nearly constant external interference, the 90E21/22/23/24 also provides power offset compensation. Hardware Reset: Hardware Reset is initiated when the reset pin is pulled low. The width of the reset signal should be over 200µs. Software Reset: Software Reset is initiated when ‘789AH’ is written to the software reset register (SoftReset, 00H). L line and N line need to be calibrated sequentially. Reactive does not need to be calibrated. Measurement Calibration Measurement calibration is realized by calibrating the gains for voltage rms and current rms. Considering the possible nonlinearity around zero caused by external components, the chip also provides offset compensation for voltage rms, current rms, mean active power and mean reactive power. Frequency, phase angle and power factor do not need calibration. For more calibration details, please refer to Application Note AN-641. Functional Description 15 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 4 INTERFACE 4.1.1 4.1 SERIAL PERIPHERAL INTERFACE (SPI) In four-wire mode, the CS pin must be driven low for the entire read or write operation. The first bit on SDI defines the access type and the lower 7-bit is decoded as address. SPI is a full-duplex, synchronous channel. There are two SPI modes: four-wire mode and three-wire mode. In four-wire mode, four pins are used: CS, SCLK, SDI and SDO. In three-wire mode, three pins are used: SCLK, SDI and SDO. Data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the chip on the falling edge of SCLK. The LastSPIData register (06H) stores the 16-bit data that is just read or written. FOUR-WIRE MODE Read Sequence As shown in Figure-6, a read operation is initiated by a high on SDI followed by a 7-bit register address. A 16-bit data in this register is then shifted out of the chip on SDO. A complete read operation contains 24 cycles. CS 1 2 3 4 5 6 7 8 A1 A0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Register Address SDI A6 A5 A4 A3 A2 16-bit data High Impedance SDO Don't care D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure-6 Read Sequence in Four-Wire Mode Write Sequence As shown in Figure-7, a write operation is initiated by a low on SDI followed by a 7-bit register address. A 16-bit data is then shifted into the chip on SDI. A complete write operation contains 24 cycles. CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Register Address SDI SDO A6 A5 A4 A3 A2 A1 16-bit data A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 High Impedance Figure-7 Write Sequence in Four-Wire Mode Interface 16 January 10, 2012 90E21/22/23/24 4.1.2 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC THREE-WIRE MODE In three-wire mode, CS is always at low level. When there is no operation, SCLK keeps at high level. The start of a read or write operation is triggered if SCLK is consistently low for at least 400µs. The subsequent read or write operation is similar to that in four-wire mode. Refer to Figure-8 and Figure-9. CS Drive Low 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 Low ≥ 400µs Low ≥ 400µs Register address SDI Don’t care A6 A5 A4 A3 A2 A1 Don't care A0 16-bit data Hign Impedance SDO A6 D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 23 24 A5 A4 3 4 High Impedance Figure-8 Read Sequence in Three-Wire Mode CS Drive low 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDO 17 18 19 20 21 22 Don't care 1 2 Low ≥ 400µs Register Address SDI 16 Low ≥ 400µs A6 A5 A4 A3 A2 A1 16-bit data A0 D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Don't care A6 A5 A4 High Impedance Figure-9 Write Sequence in Three-Wire Mode Interface 17 January 10, 2012 90E21/22/23/24 4.1.3 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 4.2 TIMEOUT AND PROTECTION WARNOUT PIN FOR FATAL ERROR WARNING Timeout occurs if SCLK does not toggle for 6ms in both four-wire and three-wire modes. When timeout, the read or write operation is aborted. Fatal error warning is raised through the WarnOut pin in two cases: checksum calibration error and voltage sag. If there are more than 24 SCLK cycles when CS is driven low in fourwire mode or between two starts in three-wire mode, writing operation is prohibited while normal reading operation can be completed by taking the first 24 SCLK cycles as the valid ones. However, the reading result might not be the intended one. Calibration Error The 90E21/22/23/24 performs diagnosis on a regular basis for important parameters such as calibration parameters and metering configuration. When checksum is not correct, the CalErr[1:0] bits (SysStatus, 01H) are set, and both the WarnOut pin and the IRQ pin are asserted. When checksum is not correct, the metering part does not work to prevent a large number of pulses during power-on or any abnormal situation upon incorrect parameters. A read access to an invalid address returns all zero. A write access to an invalid address is discarded. Table-9 and Table-10 list the read or write result in different conditions. Voltage Sag Voltage sag is detected when voltage is continuously below the voltage sag threshold for one cycle which starts from any zero-crossing point. Voltage threshold is configured by the SagTh register (03H). Refer to section 6.5. Table-9 Read / Write Result in Four-Wire Mode Condition Operation Timeout Result SCLK Cycles note 2 >=24 Read Write note 1 Read/Write Status LastSPIData Register Update Normal Read Yes note 2 <24 Partial Read No No =24 Normal Write Yes No !=24 No Write No Yes - No Write No - When voltage sag occurs, the SagWarn bit (SysStatus, 01H) is set and the WarnOut pin is asserted if the FuncEn register (02H) enables voltage sag warning through the WarnOut pin. This function helps reduce power-down detection circuit in system design. In addition, the method of judging voltage sag by detecting AC side voltage eliminates the influence of large capacitor in traditional rectifier circuit, and can detect voltage sag earlier. Note 1: The number of SCLK cycles when CS is driven low or the number of SCLK cycles before timeout if any. Note 2: '-' stands for Don't Care. 4.3 Table-10 Read / Write Result in Three-Wire Mode The following functions can be achieved at low cost when the 90E21/ 22/23/24 is isolated from the MCU: Condition Operation Timeout SCLK Cycles No >=24 Timeout after 24 cycles Timeout before 24 cycles Read Write Result note 2 >24 note 3 note 1 Read/Write Status LastSPIData Register Update Normal Read Yes Normal Read Yes - Partial Read No =24 Normal Read Yes No =24 Normal Write Yes No !=24 No Write No Yes - No Write No Timeout at 24 cycles LOW COST IMPLEMENTATION IN ISOLATION WITH MCU SPI: MCU can perform read and write operations through low speed optocoupler (e.g. NEC2501) when the 90E21/22/23/24 is isolated from the MCU. The SPI interface can be of 3-wire or 4-wire. Energy Pulses CFx: Energy can be accumulated by reading values in corresponding energy registers. CFx can also connect to the optocoupler and the energy pulse light can be turned on by CFx. Fatal Error WarnOut: Fatal error can be acquired by reading the CalE rr[1:0] bits (SysStatus, 01H). IRQ: IRQ interrupt can be acquired by reading the SysStatus register (01H). Reset: The 90E21/22/23/24 is reset when ‘789AH’ is written to the software reset register (SoftReset, 00H). Note 1: The number of SCLK cycles between 2 starts or the number of SCLK cycles before timeout if any. Note 2: There is no such case of less than 24 SCLK cycles when there is no timeout in three-wire mode, because the first few SCLK cycles in the next operation is counted into this operation. In this case, data is corrupted. Note 3: '-' stands for Don't Care. Interface 18 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 5 REGISTER 5.1 REGISTER LIST Table-11 Register List Register Address Register Name Read/Write Type Functional Description Comment note 1 Page Status and Special Register 00H 01H 02H SoftReset SysStatus FuncEn W R/C Software Reset System Status R/W Function Enable P 21 note 2, note 3 P 22 note 2 P 23 different for various chips different for various chips 03H SagTh R/W Voltage Sag Threshold P 23 04H SmallPMod R/W Small-Power Mode P 24 06H LastSPIData R Last Read/Write SPI Value P 24 Metering Calibration and Configuration Register 20H CalStart R/W Calibration Start Command P 25 21H PLconstH R/W High Word of PL_Constant P 25 22H PLconstL R/W Low Word of PL_Constant P 26 23H Lgain R/W L Line Calibration Gain P 26 24H Lphi R/W L Line Calibration Angle 25H Ngain R/W N Line Calibration Gain 26H Nphi R/W N Line Calibration Angle 27H PStartTh R/W Active Startup Power Threshold 28H PNolTh R/W Active No-Load Power Threshold 29H 2AH QStartTh QNolTh R/W R/W Reactive Startup Power Threshold Reactive No-Load Power Threshold P 26 note 3 P 27 note 3 P 27 Not applicable to the 90E21/22 Not applicable to the 90E21/22 P 27 P 28 note 2 P 28 note 2 P 28 note 2, note 3 P 29 Not applicable to the 90E21/23 Not applicable to the 90E21/23 2BH MMode R/W Metering Mode Configuration 2CH CS1 R/W Checksum 1 different for various chips 30H AdjStart R/W Measurement Calibration Start Command P 32 31H Ugain R/W Voltage rms Gain P 32 32H IgainL R/W L Line Current rms Gain P 31 Measurement Calibration Register 33H IgainN R/W N Line Current rms Gain 34H Uoffset R/W Voltage Offset 35H IoffsetL R/W L Line Current Offset 36H IoffsetN R/W N Line Current Offset 37H PoffsetL R/W L Line Active Power Offset 38H 39H QoffsetL PoffsetN R/W R/W L Line Reactive Power Offset N Line Active Power Offset 3AH QoffsetN R/W N Line Reactive Power Offset 3BH CS2 R/W Checksum 2 40H APenergy R/C Forward Active Energy P 33 Not applicable to the 90E21/22 note 3 P 33 P 33 P 34 note 3 Not applicable to the 90E21/22 P 34 P 34 note 2 P 35 note 3 P 35 Not applicable to the 90E21/23 Not applicable to the 90E21/22 Not applicable to the 90E21/22/23 note 2, note 3 P 35 P 36 Energy Register Register 19 P 37 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-11 Register List (Continued) Register Address Register Name Read/Write Type Functional Description 41H ANenergy R/C Reverse Active Energy 42H ATenergy R/C Absolute Active Energy 43H 44H 45H RPenergy RNenergy RTenergy R/C R/C R/C 46H EnStatus R 48H Irms R 49H Urms 4AH Pmean Forward (Inductive) Reactive Energy Reverse (Capacitive) Reactive Energy Absolute Reactive Energy Metering Status Comment note 1 Page P 37 P 38 Not applicable to the 90E21/23 note 2 P 38 Not applicable to the 90E21/23 note 2 P 39 note 2 P 39 note 2, note 3 P 40 Not applicable to the 90E21/23 different for various chips Measurement Register L Line Current rms P 41 R Voltage rms P 41 R L Line Mean Active Power P 42 note 2 Qmean R L Line Mean Reactive Power Freq R Voltage Frequency P 43 4DH PowerF R L Line Power Factor P 43 P 43 P 44 4EH Pangle R Phase Angle between Voltage and L Line Current 4FH Smean R L Line Mean Apparent Power 68H Irms2 R N Line Current rms 6AH 6BH Pmean2 Qmean2 R R N Line Mean Active Power N Line Mean Reactive Power Not applicable to the 90E21/23 P 42 4BH 4CH note 3 P 44 note 3 P 45 Not applicable to the 90E21/22 Not applicable to the 90E21/22 Not applicable to the 90E21/22/23 note 2, note 3 P 46 note 3 P 46 note 3 P 47 6DH PowerF2 R N Line Power Factor Not applicable to the 90E21/22 6EH Pangle2 R Phase Angle between Voltage and N Line Current Not applicable to the 90E21/22 6FH Smean2 R N Line Mean Apparent Power P 45 note 3 Not applicable to the 90E21/22 Note: 1. This register list shows all registers for the 90E24. 2. This register is related to reactive energy metering. Part of this register is invalid for the 90E21/23 which does not have reactive metering. Reading these registers always return 0000H and writing these registers always take no effect. 3. This register is related to N line metering. Part of this register is invalid for the 90E21/22 which does not have N line metering. Reading these registers always return 0000H and writing these registers always have no effect. Register 20 January 10, 2012 90E21/22/23/24 5.2 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC STATUS AND SPECIAL REGISTER SoftReset Software Reset Address: 00H Type: Write Default Value: 0000H 15 14 13 12 11 10 9 8 SoftReset15 SoftReset14 SoftReset13 SoftReset12 SoftReset11 SoftReset10 SoftReset9 SoftReset8 7 6 5 4 3 2 1 0 SoftReset7 SoftReset6 SoftReset5 SoftReset4 SoftReset3 SoftReset2 SoftReset1 SoftReset0 Bit 15 - 0 Register Name Description SoftReset[15:0] Software reset register. The 90E21/22/23/24 resets if only 789AH is written to this register. 21 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SysStatus System Status Address: 01H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 CalErr1 CalErr0 AdjErr1 AdjErr0 - - - - 7 6 5 4 3 2 1 0 LNchange RevQchg RevPchg - - - SagWarn - Bit Name 15 - 14 CalErr[1:0] These bits indicate CS1 checksum status. 00: CS1 checksum correct (default) 11: CS1 checksum error. At the same time, the WarnOut pin is asserted. 13 - 12 AdjErr[1:0] These bits indicate CS2 checksum status. 00: CS2 checksum correct (default) 11: CS2 checksum error. 11 - 8 - 7 LNchange This bit indicates whether there is any change of the metering line (L line and N line). 0: metering line no change (default) 1: metering line changed RevQchq This bit indicates whether there is any change with the direction of reactive energy. 0: direction of reactive energy no change (default) 1: direction of reactive energy changed This status is enabled by the RevQEn bit(FuncEn, 02H). 5 RevPchg This bit indicates whether there is any change with the direction of active energy. 0: direction of active energy no change (default) 1: direction of active energy changed This status is enabled by the RevPEn bit (FuncEn, 02H). 4-2 - 6 1 SagWarn 0 - Description Reserved. Reserved. This bit indicates the voltage sag status. 0: no voltage sag (default) 1: voltage sag Voltage sag is enabled by the SagEn bit (FuncEn, 02H). Voltage sag status can also be reported by the WarnOut pin. It is enabled by the SagWo bit(FuncEn, 02H). Reserved. Note: Any of the above events will prompt the IRQ pin to be asserted, which can be supplied to external MCU as an interrupt. Register 22 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC FuncEn Function Enable Address: 02H Type: Read/Write Default Value: 000CH 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - SagEn SagWo RevQEn RevPEn - - Bit 15 - 6 Name - Description 5 SagEn This bit determines whether to enable the voltage sag interrupt. 0: disable (default) 1: enable 4 SagWo This bit determines whether to enable voltage sag to be reported by the WarnOut pin. 0: disable (default) 1: enable 3 RevQEn This bit determines whether to enable the direction change interrupt of reactive energy. 0: disable 1: enable (default) 2 RevPEn This bit determines whether to enable the direction change interrupt of active energy. 0: disable 1: enable (default) 1-0 - Reserved. Reserved. SagTh Voltage Sag Threshold Address: 03H Type: Read/Write Default Value: 1D6AH 15 14 13 12 11 10 9 8 SagTh15 SagTh14 SagTh13 SagTh12 SagTh11 SagTh10 SagTh9 SagTh8 7 6 5 4 3 2 1 0 SagTh7 SagTh6 SagTh5 SagTh4 SagTh3 SagTh2 SagTh1 SagTh0 Bit 15 - 0 Register Name SagTh[15:0] Description Voltage sag threshold configuration. Data format is XXX.XX. Unit is V. The power-on value of SagTh is 1D6AH, which is calculated by 22000*sqrt(2)*0.78/(4*Ugain/32768) For details, please refer to IDT application note AN-641. 23 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SmallPMod Small-Power Mode Address: 04H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 SmallPMod15 SmallPMod14 SmallPMod13 SmallPMod12 SmallPMod11 SmallPMod10 SmallPMod9 SmallPMod8 7 6 5 4 3 2 1 0 SmallPMod7 SmallPMod6 SmallPMod5 SmallPMod4 SmallPMod3 SmallPMod2 SmallPMod1 SmallPMod0 Bit Name Description Small-power mode command. A987H: small-power mode. The relationship between the register value of L line and N line active/reactive power in small-power mode and normal mode is: SmallPMod[15:0] power in normal mode = power in small-power mode *10*Igain*Ugain /2^42 Others: Normal mode. Small-power mode is mainly used in the power offset calibration. 15 - 0 LastSPIData Last Read/Write SPI Value Address: 06H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 LastSPIData15 LastSPIData14 LastSPIData13 LastSPIData12 LastSPIData11 LastSPIData10 LastSPIData9 LastSPIData8 7 6 5 4 3 2 1 0 LastSPIData7 LastSPIData6 LastSPIData5 LastSPIData4 LastSPIData3 LastSPIData2 LastSPIData1 LastSPIData0 Bit 15 - 0 Register Name LastSPIData[15:0] Description This register stores the data that is just read or written through the SPI interface. Refer to Table-9 and Table-10. 24 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 5.3 METERING/ MEASUREMENT CALIBRATION AND CONFIGURATION 5.3.1 METERING CALIBRATION AND CONFIGURATION REGISTER CalStart Calibration Start Command Address: 20H Type: Read/Write Default Value: 6886H 15 14 13 12 11 10 9 8 CalStart15 CalStart14 CalStart13 CalStart12 CalStart11 CalStart10 CalStart9 CalStart8 7 6 5 4 3 2 1 0 CalStart7 CalStart6 CalStart5 CalStart4 CalStart3 CalStart2 CalStart1 CalStart0 Bit 15 - 0 Name Description CalStart[15:0] Metering calibration start command: 6886H: Power-on value. Metering function is disabled. 5678H: Metering calibration startup command. After 5678H is written to this register, registers 21H-2BH resume to their poweron values. The 90E21/22/23/24 starts to meter and output energy pulses regardless of the correctness of diagnosis. The CalErr[1:0] bits (SysStatus, 01H) are not set and the WarnOut/IRQ pins do not report any warning/interrupt. 8765H: Check the correctness of the 21H-2BH registers. If correct, normal metering. If not correct, metering function is disabled, the CalErr[1:0] bits (SysStatus, 01H) are set and the WarnOut/IRQ pins report warning/interrupt. Others: Metering function is disabled. The CalErr[1:0] bits (SysStatus, 01H) are set and the WarnOut/IRQ pins report warning/ interrupt. PLconstH High Word of PL_Constant Address: 21H Type: Read/Write Default Value: 0015H 15 14 13 12 11 10 9 8 PLconstH15 PLconstH14 PLconstH13 PLconstH12 PLconstH11 PLconstH10 PLconstH9 PLconstH8 7 6 5 4 3 2 1 0 PLconstH7 PLconstH6 PLconstH5 PLconstH4 PLconstH3 PLconstH2 PLconstH1 PLconstH0 Bit 15 - 0 Register Name Description The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively. PL_Constant is a constant which is proportional to the sampling ratios of voltage and current, and inversely proportional to the Meter Constant. PL_Constant is a threshold for energy calculated inside the chip, i.e., energy larger than PL_Constant will be accumulated in the corresponding energy registers and then output on CFx. PLconstH[15:0] It is suggested to set PL_constant as a multiple of 4 so as to double or redouble Meter Constant in low current state to save verification time. Note: PLconstH takes effect after PLconstL are configured. For details, please refer to IDT application note AN-641. 25 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PLconstL Low Word of PL_Constant Address: 22H Type: Read/Write Default Value: D174H 15 14 13 12 11 10 9 8 PLconstL15 PLconstL14 PLconstL13 PLconstL12 PLconstL11 PLconstL10 PLconstL9 PLconstL8 7 6 5 4 3 2 1 0 PLconstL7 PLconstL6 PLconstL5 PLconstL4 PLconstL3 PLconstL2 PLconstL1 PLconstL0 Bit Name Description 15 - 0 PLconstL[15:0] The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively. It is suggested to set PL_constant as a multiple of 4. For details, please refer to IDT application note AN-641. Lgain L Line Calibration Gain Address: 23H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Lgain15 Lgain14 Lgain13 Lgain12 Lgain11 Lgain10 Lgain9 Lgain8 7 6 5 4 3 2 1 0 Lgain7 Lgain6 Lgain5 Lgain4 Lgain3 Lgain2 Lgain1 Lgain0 Bit 15 - 0 Name Lgain[15:0] Description L line calibration gain. For details, please refer to IDT application note AN-641. Lphi L Line Calibration Angle Address: 24H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Lphi15 - - - - - Lphi9 Lphi8 7 6 5 4 3 2 1 0 Lphi7 Lphi6 Lphi5 Lphi4 Lphi3 Lphi2 Lphi1 Lphi0 Bit 15 - 0 Register Name Lphi[15:0] Description L line calibration phase angle. For details, please refer to IDT application note AN-641. 26 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Ngain N Line Calibration Gain Address: 25H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Ngain15 Ngain14 Ngain13 Ngain12 Ngain11 Ngain10 Ngain9 Ngain8 7 6 5 4 3 2 1 0 Ngain7 Ngain6 Ngain5 Ngain4 Ngain3 Ngain2 Ngain1 Ngain0 Bit 15 - 0 Name Ngain[15:0] Description N line calibration gain. For details, please refer to IDT application note AN-641. Nphi N Line Calibration Angle Address: 26H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Nphi15 - - - - - Nphi9 Nphi8 7 6 5 4 3 2 1 0 Nphi7 Nphi6 Nphi5 Nphi4 Nphi3 Nphi2 Nphi1 Nphi0 Bit 15 - 0 Name Nphi[15:0] Description N line calibration phase angle. For details, please refer to IDT application note AN-641. PStartTh Active Startup Power Threshold Address: 27H Type: Read/Write Default Value: 08BDH 15 14 13 12 11 10 9 8 PStartTh15 PStartTh14 PStartTh13 PStartTh12 PStartTh11 PStartTh10 PStartTh9 PStartTh8 7 6 5 4 3 2 1 0 PStartTh7 PStartTh6 PStartTh5 PStartTh4 PStartTh3 PStartTh2 PStartTh1 PStartTh0 Bit 15 - 0 Register Name Description PStartTh[15:0] Active startup power threshold. For details, please refer to IDT application note AN-641. 27 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PNolTh Active No-Load Power Threshold Address: 28H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 PNolTh15 PNolTh14 PNolTh13 PNolTh12 PNolTh11 PNolTh10 PNolTh9 PNolTh8 7 6 5 4 3 2 1 0 PNolTh7 PNolTh6 PNolTh5 PNolTh4 PNolTh3 PNolTh2 PNolTh1 PNolTh0 Bit 15 - 0 Name PNolTh[15:0] Description Active no-load power threshold. For details, please refer to IDT application note AN-641. QStartTh Reactive Startup Power Threshold Address: 29H Type: Read/Write Default Value: 0AECH 15 14 13 12 11 10 9 8 QStartTh15 QStartTh14 QStartTh13 QStartTh12 QStartTh11 QStartTh10 QStartTh9 QStartTh8 7 6 5 4 3 2 1 0 QStartTh7 QStartTh6 QStartTh5 QStartTh4 QStartTh3 QStartTh2 QStartTh1 QStartTh0 Bit 15 - 0 Name Description QStartTh[15:0] Reactive startup power threshold. For details, please refer to IDT application note AN-641. QNolTh Reactive No-Load Power Threshold Address: 2AH Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 QNolTh15 QNolTh14 QNolTh13 QNolTh12 QNolTh11 QNolTh10 QNolTh9 QNolTh8 7 6 5 4 3 2 1 0 QNolTh7 QNolTh6 QNolTh5 QNolTh4 QNolTh3 QNolTh2 QNolTh1 QNolTh0 Bit 15 - 0 Register Name QNolTh[15:0] Description Reactive no-load power threshold. For details, please refer to IDT application note AN-641. 28 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MMode Metering Mode Configuration Address: 2BH Type: Read/Write Default Value: 9422H 15 14 13 12 11 10 9 8 Lgain2 Lgain1 Lgain0 Ngain1 Ngain0 LNSel DisHPF1 DisHPF0 7 6 5 4 3 2 1 0 Amod Rmod ZXCon1 ZXCon0 Pthresh3 Pthresh2 Pthresh1 Pthresh0 Bit Name Description L line current gain, default value is ‘100’. 15 - 13 Lgain2 1 0 0 0 0 Lgain[2:0] 12 - 11 Ngain[1:0] 10 LNSel Lgain1 X 0 0 1 1 Lgain0 X 0 1 0 1 Current Channel Gain 1 4 8 16 24 N line current gain 00: 2 01: 4 10: 1 (default) 11: 1 This bit specifies metering as L line or N line when metering mode is set to flexible mode by MMD1 and MMD0 pins. 0: N line 1: L line (default) These bits configure the High Filter Pass (HPF) after ADC. There are two first-order HPF in serial: HPF1 and HPF0. The configuration are applicable to all channels: DisHPF1 0 0 1 1 DisHPF 0 0 1 0 1 HPF Configuration enable HPF1 and HPF0 (default) enable HPF1, disable HPF0; disable HPF1, enable HPF0; disable HPF1 and HPF0 9-8 DisHPF[1:0] 7 Amod CF1 output for active power: 0: forward or reverse energy pulse output (default) 1: absolute energy pulse output 6 Rmod CF2 output for reactive power: 0: forward (inductive) or reverse (capacitive) energy pulse output (default) 1: absolute energy pulse output Register 29 January 10, 2012 90E21/22/23/24 5-4 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Zxcon[1:0] These bits configure zero-crossing mode. The ZX pin outputs 5ms-width high level when voltage crosses zero. 00: positive zero-crossing 01: negative zero-crossing 10: all zero-crossing: both positive and negative zero-crossing (default) 11: no zero-crossing output These bits configure the L line and N line power difference threshold in anti-tampering mode. 3-0 Register Pthresh[3:0] Pthresh3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Pthresh2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 30 Pthresh1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pthresh0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Threshold 12.5% 6.25% 3.125% (default) 1.5625% 1% 2% 3% 4% 5% 6% 7% 8% 9% 10% 11% 12% January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC CS1 Checksum 1 Address: 2CH Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 CS1_15 CS1_14 CS1_13 CS1_12 CS1_11 CS1_10 CS1_9 CS1_8 7 6 5 4 3 2 1 0 CS1_7 CS1_6 CS1_5 CS1_4 CS1_3 CS1_2 CS1_1 CS1_0 Bit Name Description The CS1 register should be written after the 21H-2BH registers are written. Suppose the high byte and the low byte of the 21H2BH registers are shown in below table. 15 - 0 CS1[15:0] Register Address 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH The calculatiion of the CS1 register is as follows: High Byte H21 H22 H23 H24 H25 H26 H27 H28 H29 H2A H2B Low Byte L21 L22 L23 L24 L25 L26 L27 L28 L29 L2A L2B The low byte of 2CH register is: L2C=MOD(H21+H22+...+H2B+L21+L22+...+L2B, 2^8) The high byte of 2CH register is: H2C=H21 XOR H22 XOR ... XOR H2B XOR L21 XOR L22 XOR ... XOR L2B For 90E21/22/23, a part of registers are not used. These registers can be dealed as 0000H in CS calculation. The 90E21/22/23/24 calculates CS1 regularly. If the value of the CS1 register and the calculation by the 90E21/22/23/24 is different when CalStart=8765H, the CalErr[1:0] bits (SysStatus, 01H) are set and the WarnOut and IRQ pins are asserted. Note: The readout value of the CS1 register is the calculation by the 90E21/22/23/24, which is different from what is written. Register 31 January 10, 2012 90E21/22/23/24 5.3.2 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MEASUREMENT CALIBRATION REGISTER AdjStart Measurement Calibration Start Command Address: 30H Type: Read/Write Default Value: 6886H 15 14 13 12 11 10 9 8 AdjStart15 AdjStart14 AdjStart13 AdjStart12 AdjStart11 AdjStart10 AdjStart9 AdjStart8 7 6 5 4 3 2 1 0 AdjStart7 AdjStart6 AdjStart5 AdjStart4 AdjStart3 AdjStart2 AdjStart1 AdjStart0 Bit 15 - 0 Name Description AdjStart[15:0] Measurement Calibration Start Command 6886H: Power-on value. No measurement. 5678H: Measurement calibration startup command. After 5678H is written to this register, registers 31H-3AH resume to their power-on values. The 90E21/22/23/24 starts to measure regardless of the correctness of diagnosis. The AdjErr[1:0] bits (SysStatus, 01H) are not set and the IRQ pin does not report any interrupt. 8765H: Check the correctness of the 31H-3AH registers. If correct, normal measurement. If not correct, measurement function is disabled, the AdjErr[1:0] bits (SysStatus, 01H) are set and the IRQ pin reports interrupt. Others: No measurement. The AdjErr[1:0] bits (SysStatus, 01H) are set and the IRQ pin reports interrupt. Ugain Voltage rms Gain Address: 31H Type: Read/Write Default Value: 6720H 15 14 13 12 11 10 9 8 Ugain15 Ugain14 Ugain13 Ugain12 Ugain11 Ugain10 Ugain9 Ugain8 7 6 5 4 3 2 1 0 Ugain7 Ugain6 Ugain5 Ugain4 Ugain3 Ugain2 Ugain1 Ugain0 Bit Name 15 - 0 Ugain[15:0] Register Description Voltage rms Gain. For details, please refer to IDT application note AN-641. Note: the Ugain15 bit should only be '0' 32 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC IgainL L Line Current rms Gain Address: 32H Type: Read/Write Default Value: 7A13H 15 14 13 12 11 10 9 8 IgainL15 IgainL14 IgainL13 IgainL12 IgainL11 IgainL10 IgainL9 IgainL8 7 6 5 4 3 2 1 0 IgainL7 IgainL6 IgainL5 IgainL4 IgainL3 IgainL2 IgainL1 IgainL0 Bit 15 - 0 Name IgainL[15:0] Description L Line Current rms Gain, For details, please refer to IDT application note AN-641. IgainN N Line Current rms Gain Address: 33H Type: Read/Write Default Value: 7530H 15 14 13 12 11 10 9 8 IgainN15 IgainN14 IgainN13 IgainN12 IgainN11 IgainN10 IgainN9 IgainN8 7 6 5 4 3 2 1 0 IgainN7 IgainN6 IgainN5 IgainN4 IgainN3 IgainN2 IgainN1 IgainN0 Bit 15 - 0 Name IgainN[15:0] Description N Line Current rms Gain. For details, please refer to IDT application note AN-641. Uoffset Voltage Offset Address: 34H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Uoffset15 Uoffset14 Uoffset13 Uoffset12 Uoffset11 Uoffset10 Uoffset9 Uoffset8 7 6 5 4 3 2 1 0 Uoffset7 Uoffset6 Uoffset5 Uoffset4 Uoffset3 Uoffset2 Uoffset1 Uoffset0 Bit 15 - 0 Register Name Uoffset[15:0] Description Voltage offset. For calculation method, please refer to IDT application note AN-641. 33 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC IoffsetL L Line Current Offset Address: 35H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 IoffsetL15 IoffsetL14 IoffsetL13 IoffsetL12 IoffsetL11 IoffsetL10 IoffsetL9 IoffsetL8 7 6 5 4 3 2 1 0 IoffsetL7 IoffsetL6 IoffsetL5 IoffsetL4 IoffsetL3 IoffsetL2 IoffsetL1 IoffsetL0 Bit 15 - 0 Name IoffsetL[15:0] Description L line current offset. For calculation method, please refer to IDT application note AN-641. IoffsetN N Line Current Offset Address: 36H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 IoffsetN15 IoffsetN14 IoffsetN13 IoffsetN12 IoffsetN11 IoffsetN10 IoffsetN9 IoffsetN8 7 6 5 4 3 2 1 0 IoffsetN7 IoffsetN6 IoffsetN5 IoffsetN4 IoffsetN3 IoffsetN2 IoffsetN1 IoffsetN0 Bit 15 - 0 Name IoffsetN[15:0] Description N line current offset. For calculation method, please refer to IDT application note AN-641. PoffsetL L Line Active Power Offset Address: 37H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 PoffsetL15 PoffsetL14 PoffsetL13 PoffsetL12 PoffsetL11 PoffsetL10 PoffsetL9 PoffsetL8 7 6 5 4 3 2 1 0 PoffsetL7 PoffsetL6 PoffsetL5 PoffsetL4 PoffsetL3 PoffsetL2 PoffsetL1 PoffsetL0 Bit Name 15 - 0 PoffsetL[15:0] Register Description L line active power offset. Complement, MSB is the sign bit. For calculation method, please refer to IDT application note AN-641. 34 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC QoffsetL L Line Reactive Power Offset Address: 38H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 QoffsetL15 QoffsetL14 QoffsetL13 QoffsetL12 QoffsetL11 QoffsetL10 QoffsetL9 QoffsetL8 7 6 5 4 3 2 1 0 QoffsetL7 QoffsetL6 QoffsetL5 QoffsetL4 QoffsetL3 QoffsetL2 QoffsetL1 QoffsetL0 Bit Name Description 15 - 0 QoffsetL[15:0] L line reactive power offset. Complement, MSB is the sign bit. For calculation method, please refer to IDT application note AN-641. PoffsetN N Line Active Power Offset Address: 39H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 PoffsetN15 PoffsetN14 PoffsetN13 PoffsetN12 PoffsetN11 PoffsetN10 PoffsetN9 PoffsetN8 7 6 5 4 3 2 1 0 PoffsetN7 PoffsetN6 PoffsetN5 PoffsetN4 PoffsetN3 PoffsetN2 PoffsetN1 PoffsetN0 Bit Name Description 15 - 0 PoffsetN[15:0] N line active power offset. Complement, MSB is the sign bit. For calculation method, please refer to IDT application note AN-641. QoffsetN N Line Reactive Power Offset Address: 3AH Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 QoffsetN15 QoffsetN14 QoffsetN13 QoffsetN12 QoffsetN11 QoffsetN10 QoffsetN9 QoffsetN8 7 6 5 4 3 2 1 0 QoffsetN7 QoffsetN6 QoffsetN5 QoffsetN4 QoffsetN3 QoffsetN2 QoffsetN1 QoffsetN0 Bit 15 - 0 Register Name Description N line reactive power offset. QoffsetN[15:0] Complement, MSB is the sign bit. For calculation method, please refer to IDT application note AN-641. 35 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC CS2 Checksum 2 Address: 3BH Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 CS2_15 CS2_14 CS2_13 CS2_12 CS2_11 CS2_10 CS2_9 CS2_8 7 6 5 4 3 2 1 0 CS2_7 CS2_6 CS2_5 CS2_4 CS2_3 CS2_2 CS2_1 CS2_0 Bit Name Description The CS2 register should be written after the 31H-3AH registers are written. Suppose the high byte and the low byte of the 31H3AH registers are shown in below table. 15 - 0 CS2[15:0] Register Address 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH High Byte H31 H32 H33 H34 H35 H36 H37 H38 H39 H3A Low Byte L31 L32 L33 L34 L35 L36 L37 L38 L39 L3A The calculatiion of the CS2 register is as follows: The low byte of 3BH register is: L3B=MOD(H31+H32+...+H3A+L31+L32+...+L3A, 2^8) The high byte of 3BH register is: H3B=H31 XOR H32 XOR ... XOR H3A XOR L31 XOR L32 XOR ... XOR L3A For 90E21/22/23, a part of registers are not used. These registers can be dealed as 0000H in CS calculation. The 90E21/22/23/24 calculates CS2 regularly. If the value of the CS2 register and the calculation by the 90E21/22/23/24 is different when AdjStart=8765H, the AdjErr[1:0] bits (SysStatus, 01H) are set. Note: The readout value of the CS2 register is the calculation by the 90E21/22/23/24, which is different from what is written. Register 36 January 10, 2012 90E21/22/23/24 5.4 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ENERGY REGISTER Theory of Energy Registers Forward Active Pulse Reserve Active Pulse Absolute Active Pulse The internal energy resolution is 0.01 pulse. Within 0.01 pulse, forward and reverse energy are counteracted. When energy exceeds 0.01 pulse, the respective forward/reserve energy is increased. The forward and reverse energy are not counteracted in absolute energy registers. Take the example of active energy, suppose: T0: Forward energy is 12.34 pulses and reverse energy is 1.23 pulses; From T0 to T1: 0.005 forward pulse appeared From T1 to T2: 0.004 reverse pulse appeared From T2 to T3: 0.003 reverse pulse appeared T0 12.34 1.23 13.57 T1 12.345 1.23 13.575 T2 12.341 1.23 13.579 T3 12.34 1.232 13.582 When forward/reverse energy or absolute energy reaches 0.1 pulse, the respective register is updated. When forward/reverse energy or absolute energy reaches 1 pulse, CFx pins output pulse and the REVP/REVQ bits (EnStatus, 46H) are updated. Absolute energy might be more than the sum of forward and reverse energies. If “consistency” is required between absolute energy and forward/reverse energy in system application, absolute energy can be obtained by calculating the readout of the forward and reverse energy registers. APenergy Forward Active Energy Address: 40H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 APenergy15 APenergy14 APenergy13 APenergy12 APenergy11 APenergy10 APenergy9 APenergy8 7 6 5 4 3 2 1 0 APenergy7 APenergy6 APenergy5 APenergy4 APenergy3 APenergy2 APenergy1 APenergy0 Bit Name Description Forward active energy; cleared after read. APenergy[15:0] Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. 15 - 0 ANenergy Reverse Active Energy Address: 41H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 ANenergy15 ANenergy14 ANenergy13 ANenergy12 ANenergy11 ANenergy10 ANenergy9 ANenergy8 7 6 5 4 3 2 1 0 ANenergy7 ANenergy6 ANenergy5 ANenergy4 ANenergy3 ANenergy2 ANenergy1 ANenergy0 Bit 15 - 0 Register Name Description Reverse active energy, cleared after read. ANenergy[15:0] Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. 37 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ATenergy Absolute Active Energy Address: 42H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 ATenergy15 ATenergy14 ATenergy13 ATenergy12 ATenergy11 ATenergy10 ATenergy9 ATenergy8 7 6 5 4 3 2 1 0 ATenergy7 ATenergy6 ATenergy5 ATenergy4 ATenergy3 ATenergy2 ATenergy1 ATenergy0 Bit Name Description Absolute active energy, cleared after read. ATenergy[15:0] Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. 15 - 0 RPenergy Forward (Inductive) Reactive Energy Address: 43H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 RPenergy15 RPenergy14 RPenergy13 RPenergy12 RPenergy11 RPenergy10 RPenergy9 RPenergy8 7 6 5 4 3 2 1 0 RPenergy7 RPenergy6 RPenergy5 RPenergy4 RPenergy3 RPenergy2 RPenergy1 RPenergy0 Bit 15 - 0 Register Name Description Forward (inductive) reactive energy, cleared after read. RPenergy[15:0] Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. 38 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC RNenergy Reverse (Capacitive) Reactive Energy Address: 44H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 RNenergy15 RNenergy14 RNenergy13 RNenergy12 RNenergy11 RNenergy10 RNenergy9 RNenergy8 7 6 5 4 3 2 1 0 RNenergy7 RNenergy6 RNenergy5 RNenergy4 RNenergy3 RNenergy2 RNenergy1 RNenergy0 Bit Name Description Reverse (capacitive) reactive energy, cleared after read. RNenergy[15:0] Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. 15 - 0 RTenergy Absolute Reactive Energy Address: 45H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 RTenergy15 RTenergy14 RTenergy13 RTenergy12 RTenergy11 RTenergy10 RTenergy9 RTenergy8 7 6 5 4 3 2 1 0 RTenergy7 RTenergy6 RTenergy5 RTenergy4 RTenergy3 RTenergy2 RTenergy1 RTenergy0 Bit 15 - 0 Register Name Description Absolute reactive energy, cleared after read. RTenergy[15:0] Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. 39 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC EnStatus Metering Status Address: 46H Type: Read Default Value After Power On: C800H 15 14 13 12 11 10 9 8 Qnoload Pnoload RevQ RevP Lline - - - 7 6 5 4 3 2 1 0 - - - - - - LNMode1 LNMode0 Bit Name Description 15 Qnoload This bit indicates whether the chip is in reactive no-load status. 0: not reactive no-load state 1: reactive no-load state 14 Pnoload This bit indicates whether the 90E21/22/23/24 is in active no-load status. 0: not active no-load state 1: active no-load state RevQ This bit indicates the direction of the last CF2 (reactive output). 0: reactive forward 1: reactive reverse Note: This bit is always '0' when the CF2 output is configured to be absolute energy. 12 RevP This bit indicates the direction of the last CF1 (active output). 0: active forward 1: active reverse Note: This bit is always '0' when the CF1 output is configured to be absolute energy. 11 Lline This bit indicates the current metering line in anti-tampering mode. 0: N line 1: L line 10 - 2 - 13 Reserved. These bits indicate the configuration of MMD1 and MMD0 pins. Their relationship is as follows: 1-0 Register LNMode[1:0] MMD1 0 0 1 1 MMD0 0 1 0 1 LNmod1 0 0 1 1 LNmod0 0 1 0 1 40 L/N Metering Mode anti-tampering mode (larger power) L line mode (fixed L line) L+N mode (applicable for single-phase three-wire system) Flexible mode (Line specified by the LNSel bit (MMode, 2BH)) January 10, 2012 90E21/22/23/24 5.5 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MEASUREMENT REGISTER Irms L Line Current rms Address: 48H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Irms15 Irms14 Irms13 Irms12 Irms11 Irms10 Irms9 Irms8 7 6 5 4 3 2 1 0 Irms7 Irms6 Irms5 Irms4 Irms3 Irms2 Irms1 Irms0 Bit 15 - 0 Name Description Irms[15:0] L line current rms. Data format is XX.XXX, which corresponds to 0 ~ 65.535A. For cases when the current exceeds 65.535A, it is suggested to be handled by MCU in application. For example, the register value can be calibrated to 1/2 of the actual value during calibration, then multiplied by 2 in application. Urms Voltage rms Address: 49H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Urms15 Urms14 Urms13 Urms12 Urms11 Urms10 Urms9 Urms8 7 6 5 4 3 2 1 0 Urms7 Urms6 Urms5 Urms4 Urms3 Urms2 Urms1 Urms0 Bit Name 15 - 0 Urms[15:0] Register Description Voltage rms. Data format is XXX.XX, which corresponds to 0 ~ 655.35V. 41 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Pmean L Line Mean Active Power Address: 4AH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pmean15 Pmean14 Pmean13 Pmean12 Pmean11 Pmean10 Pmean9 Pmean8 7 6 5 4 3 2 1 0 Pmean7 Pmean6 Pmean5 Pmean4 Pmean3 Pmean2 Pmean1 Pmean0 Bit 15 - 0 Name Description Pmean[15:0] L line mean active power. Complement, MSB is the sign bit. Data format is XX.XXX, which corresponds to -32.768~+32.768kW. If current is specially handle by MCU, the power of the 90E21/22/23/24 and the actual power have the same multiple relationship as the current. Qmean L Line Mean Reactive Power Address: 4BH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Qmean15 Qmean14 Qmean13 Qmean12 Qmean11 Qmean10 Qmean9 Qmean8 7 6 5 4 3 2 1 0 Qmean7 Qmean6 Qmean5 Qmean4 Qmean3 Qmean2 Qmean1 Qmean0 Bit 15 - 0 Register Name Description Qmean[15:0] L line mean reactive power. Complement, MSB is the sign bit. Data format is XX.XXX, which corresponds to -32.768~+32.768kvar. If current is specially handled by MCU, the power of the 90E22/24 and the actual power have the same multiple relationship as the current. 42 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Freq Voltage Frequency Address: 4CH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Freq15 Freq14 Freq13 Freq12 Freq11 Freq10 Freq9 Freq8 7 6 5 4 3 2 1 0 Freq7 Freq6 Freq5 Freq4 Freq3 Freq2 Freq1 Freq0 Bit Name Description 15 - 0 Freq[15:0] Voltage frequency. Data format is XX.XX. Frequency measurement range is 45.00~65.00Hz. For example, 1388H corresponds to 50.00Hz. PowerF L Line Power Factor Address: 4DH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 PowerF15 PowerF14 PowerF13 PowerF12 PowerF11 PowerF10 PowerF9 PowerF8 7 6 5 4 3 2 1 0 PowerF7 PowerF6 PowerF5 PowerF4 PowerF3 PowerF2 PowerF1 PowerF0 Bit Name Description 15 - 0 PowerF[15:0] L line power factor. Signed, MSB is the sign bit. Data format is X.XXX. Power factor range: -1.000~+1.000. For example, 03E8H corresponds to the power factor of 1.000, and 83E8H corresponds to the power factor of -1.000. Pangle Phase Angle between Voltage and L Line Current Address: 4EH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pangle15 Pangle14 Pangle13 Pangle12 Pangle11 Pangle10 Pangle9 Pangle8 7 6 5 4 3 2 1 0 Pangle7 Pangle6 Pangle5 Pangle4 Pangle3 Pangle2 Pangle1 Pangle0 Bit 15 - 0 Register Name Pangle[15:0] Description L line voltage current angle. Signed, MSB is the sign bit. Data format is XXX.X. Angle range: -180.0~+180.0 degree. 43 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Smean L Line Mean Apparent Power Address: 4FH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Smean15 Smean14 Smean13 Smean12 Smean11 Smean10 Smean9 Smean8 7 6 5 4 3 2 1 0 Smean7 Smean6 Smean5 Smean4 Smean3 Smean2 Smean1 Smean0 Bit 15 - 0 Name Description Smean[15:0] L line mean apparent power. Complement, MSB is always '0'. Data format is XX.XXX, which corresponds to 0~+32.767kVA. If current is specially handled by MCU, the power of the 90E21/22/23/24 and the actual power have the same multiple relationship as the current. Irms2 N Line Current rms Address: 68H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Irms2_15 Irms2_14 Irms2_13 Irms2_12 Irms2_11 Irms2_10 Irms2_9 Irms2_8 7 6 5 4 3 2 1 0 Irms2_7 Irms2_6 Irms2_5 Irms2_4 Irms2_3 Irms2_2 Irms2_1 Irms2_0 Bit 15 - 0 Register Name Description Irms2[15:0] N line current rms. Data format is XX.XXX, which corresponds to 65.535A. For cases when the current exceeds 65.535A, it is suggested to be handled by MCU in application. For example, the register value can be calibrated to 1/2 of the actual value during calibration, then multiplied by 2 in application. 44 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Pmean2 N Line Mean Active Power Address: 6AH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pmean2_15 Pmean2_14 Pmean2_13 Pmean2_12 Pmean2_11 Pmean2_10 Pmean2_9 Pmean2_8 7 6 5 4 3 2 1 0 Pmean2_7 Pmean2_6 Pmean2_5 Pmean2_4 Pmean2_3 Pmean2_2 Pmean2_1 Pmean2_0 Bit 15 - 0 Name Description Pmean2[15:0] N line mean active power. Complement, MSB is the sign bit. Data format is XX.XXX, which corresponds to -32.768~+32.767kW. If current is specially handled by MCU, the power of the 90E21/22/23/24 and the actual power have the same multiple relationship as the current. Qmean2 N Line Mean Reactive Power Address: 6BH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Qmean2_15 Qmean2_14 Qmean2_13 Qmean2_12 Qmean2_11 Qmean2_10 Qmean2_9 Qmean2_8 7 6 5 4 3 2 1 0 Qmean2_7 Qmean2_6 Qmean2_5 Qmean2_4 Qmean2_3 Qmean2_2 Qmean2_1 Qmean2_0 Bit 15 - 0 Register Name Description Qmean2[15:0] N line mean reactive power. Complement, MSB is the sign bit. Data format is XX.XXX, which corresponds to -32.768~+32.767kvar. If current is specially handled by MCU, the power of 90E22/24 and the actual power have the same multiple relationship as the current. 45 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PowerF2 N Line Power Factor Address: 6DH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 PowerF2_15 PowerF2_14 PowerF2_13 PowerF2_12 PowerF2_11 PowerF2_10 PowerF2_9 PowerF2_8 7 6 5 4 3 2 1 0 PowerF2_7 PowerF2_6 PowerF2_5 PowerF2_4 PowerF2_3 PowerF2_2 PowerF2_1 PowerF2_0 Bit Name Description N line power factor. PowerF2[15:0] Signed, MSB is the sign bit. Data format is X.XXX. Power factor range: -1.000~+1.000. For example, 03E8H corresponds to the power factor of 1.000, and 83E8H corresponds to the power factor of -1.000. 15 - 0 Pangle2 Phase Angle between Voltage and N Line Current Address: 6EH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pangle2_15 Pangle2_14 Pangle2_13 Pangle2_12 Pangle2_11 Pangle2_10 Pangle2_9 Pangle2_8 7 6 5 4 3 2 1 0 Pangle2_7 Pangle2_6 Pangle2_5 Pangle2_4 Pangle2_3 Pangle2_2 Pangle2_1 Pangle2_0 Bit 15 - 0 Register Name Pangle2[15:0] Description N line voltage current angle Signed, MSB is the sign bit. Data format is XXX.X. Angle range: -180.0~+180.0 degree. 46 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Smean2 N Line Mean Apparent Power Address: 6FH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Smean2_15 Smean2_14 Smean2_13 Smean2_12 Smean2_11 Smean2_10 Smean2_9 Smean2_8 7 6 5 4 3 2 1 0 Smean2_7 Smean2_6 Smean2_5 Smean2_4 Smean2_3 Smean2_2 Smean2_1 Smean2_0 Bit 15 - 0 Register Name Description Smean2[15:0] N line mean apparent power Complement, MSB is always '0'. Data format is XX.XXX, which corresponds to 0~+32.767kVA. If current is specially handled by MCU, the power of 90E21/22/23/24 and the actual power have the same multiple relationship as the current. 47 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6 ELECTRICAL SPECIFICATION 6.1 ELECTRICAL SPECIFICATION Parameters and Description Min. Typical Max. Accuracy DC Power Supply Rejection Ratio (PSRR) ±0.1 AC Power Supply Rejection Ratio (PSRR) Active Energy Error (Dynamic Range 5000:1) ±0.1 ±0.1 Channel Characteristics 8 Sampling Frequency Unit % % % 19.1 nV/ Hz N Line Current Channel Equivalent Input Noise 458.4 nV/ Hz 458.4 nV/ Hz L Line Current Channel Differential Input N Line Current Channel Differential Input Voltage Channel Differential Input L Line Current Channel Input Impedance N Line Current Channel Input Impedance Voltage Channel Input Impedance L Line Current Channel DC Offset N Line Current Channel DC Offset Voltage Channel DC Offset On-Chip Reference (90E21/22/23/24) Reference Voltage Temperature Coefficient 80 4 4 4 5µ 7.5µ 15µ 30µ 120µ 30µ 60µ 120µ 120µ 1.398 Crystal or External Clock SPI Interface Bit Rate 200 CFx Pulse Width ±0.5 Analog Input 25m 37.5m 75m 150m 600m 150m 300m 600m 600m 1 50 50 10 10 10 Reference 1.417 1.440 ±15 ±40 Clock 8.192 SPI Interface 160k Pulse Width 80 VDD=3.3V±0.3V, 100Hz, I=5A, V=220V, L line shunt resistor 150µΩ, N line CT 1000:1, sampling resistor 4.8Ω VDD=3.3V superimposes 400mVrms, 100Hz Sinusoidal signal, I=5A, V=220V, L line shunt resistor 150µΩ, N line CT 1000:1, sampling resistor 4.8Ω L line current gain is ‘24’; N line current gain is ‘1’ kHz L Line Current Channel Equivalent Input Noise Voltage Channel Equivalent Input Noise Total Harmonic Distortion for Each Channel Reactive Energy Metering Bandwidth Active Energy Metering Bandwidth Irms and Vrms Measurement Bandwidth Measurement Error Test Conditions and Comments dB kHz kHz kHz % Vrms Vrms Vrms KΩ KΩ KΩ mV mV mV V ppm/°C MHz Single side band noise (measured at 50Hz, and PGA gain is ‘24’) Single side band noise (measured at 50Hz, and PGA gain is ‘1’) Single side band noise (measured at 50Hz, and PGA gain is ‘1’) 25°C, PGA gain is ‘1’, 500mVrms input PGA gain is ‘24’ PGA gain is ‘16’ PGA gain is ‘8’ PGA gain is ‘4’ PGA gain is ‘1’ PGA gain is ‘4’ PGA gain is ‘2’ PGA gain is ‘1’ PGA gain is ‘1’ PGA gain is ‘24’ PGA gain is ‘1’ PGA gain is ‘1’ Reference voltage test mode The Accuracy of crystal or external clock is ±100 ppm bps ms If T ≥ 160 ms, width=80ms; if T<160 ms, width = 0.5T. Refer to Section 6.6 V V JESD22-A115 JESD22-C101 ESD Machine Model (MM) Charged Device Model (CDM) Electrical Specification 400 1000 48 January 10, 2012 90E21/22/23/24 Human Body Model (HBM) Latch Up Latch Up AVDD, Analog Power Supply DVDD, Digital Power Supply SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 4000 V mA V IAVDD, Analog Current (90E21/22) 3.00 mA IAVDD, Analog Current (90E23/24) IDVDD, Digital Current 3.75 2.75 DC Characteristics VDD+2.6 VDD+0.3 0.8 ±1 0.4 0.4 mA mA V V V µA V V V V V V VDD=3.3V±10%, VDD=3.3V±10% VDD=3.3V±10% VDD=3.6V, VI=VDD or GND VDD=3.3V, IOL=10mA VDD=3.3V, IOL=5mA VDD=3.3V, IOH=-10mA VDD=3.3V, IOH=-5mA VDD=3.3V, IOL=1mA VDD=3.3V, IOH=-1mA Electrical Specification 2.0 2.0 2.4 2.4 0.4 2.4 49 V V JESD22-A114 JESD78A JESD78A Metering precision guaranteed within 3.0V~3.6V. Metering precision guaranteed within 3.0V~3.6V. L line current channel and voltage channel are open L line/ N line current channel and voltage channel are open VDD=3.3V Digital Input High Level (all digital pins except OSCI) Digital Input High Level (OSCI) Digital Input Low Level Digital Input Leakage Current Digital Output Low Level (CF1, CF2) Digital Output Low Level (IRQ, WarnOut, ZX, SDO) Digital Output High Level (CF1, CF2) Digital Output High Level (IRQ, WarnOut, ZX, SDO) Digital Output Low Level (OSCO) Digital Output High Level (OSCO) 2.8 2.8 ±100 4.95 Operating Conditions 3.3 3.6 3.3 3.6 January 10, 2012 90E21/22/23/24 6.2 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SPI INTERFACE TIMING The SPI interface timing is as shown in Figure-10, Figure-11 and Table-12. tCSH CS t t CSS t CLH t CLL t CSD CLD SCLK tDIS SDI t DIH Valid Input tDW t SDO t PD DF High Impedance High Impedance Valid Output Figure-10 4-Wire SPI Timing Diagram t t CLH CLL SCLK t SDI DIS t DIH Valid Input tDW t SDO PD High Impedance High Impedance Valid Output Figure-11 3-Wire SPI Timing Diagram Table-12 SPI Timing Specification Symbol note 1 tCSH tCSS note 1 note 1 tCSD note 1 tCLD tCLH tCLL tDIS tDIH Electrical Specification Description Min. Typical Max. Unit note 2 ns CS Setup Time 3T+10 ns CS Hold Time 30T+10 ns Clock Disable Time Clock High Level Time Clock Low Level Time Data Setup Time Data Hold Time 1T 30T+10 16T+10 3T+10 22T+10 ns ns ns ns ns Minimum CS High Level Time 30T 50 +10 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-12 SPI Timing Specification (Continued) tDW tPD Minimum Data Width Output Delay 30T+10 14T note 1 tDF Output Disable Time Note: 1. Not applicable for three-wire SPI. 2. T means SCLK cycle. T=122ns. (Typical value for four-wire SPI) 6.3 15T+20 ns ns 16T+20 ns POWER ON RESET TIMING VH VL DVDD T2 T1 RESET Figure-12 Power On Reset Timing Diagram Table-13 Power On Reset Specification Symbol VH VL VH-VL T1 T2 6.4 Description Power On Trigger Voltage Power Off Trigger Voltage Hysteretic Voltage Difference Delay Time After Power On Delay Time After Power Off Min. 2.47 2.185 0.285 5 10 Typical 2.6 2.3 0.3 Max. 2.73 2.415 0.315 Unit V V V ms µs ZERO-CROSSING TIMING V TZX ZX (Positive zero-crossing) TD ZX (Negative zero-crossing) ZX (All zero-crossing) Figure-13 Zero-Crossing Timing Diagram Electrical Specification 51 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-14 Zero-Crossing Specification Symbol TZX TD 6.5 Description Min. Typical 5 High Level Width Delay Time Max. 0.5 Unit ms ms Max. 0.5 Unit ms VOLTAGE SAG TIMING V Voltage Sag Threshold Voltage Sag Threshold TD WarnOut IRQ Figure-14 Voltage Sag Timing Diagram Table-15 Voltage Sag Specification Symbol TD 6.6 Description Min. Typical Delay Time PULSE OUTPUT Tp=80ms Tp=0.5T Tp=5ms CFx T≥160ms 10ms≤T<160ms if T<10ms, force T=10ms Figure-15 Output Pulse Width Electrical Specification 52 January 10, 2012 90E21/22/23/24 6.7 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ABSOLUTE MAXIMUM RATING Parameter Relative Voltage Between AVDD and AGND Relative Voltage Between DVDD and DGND Analog Input Voltage (I1P, I1N, I2P, I2N, VP, VN) Digital Input Voltage Operating Temperature Range Maximum Junction Temperature Package Type note 1 Thermal Resistance θJA Green SSOP28 Note 1: Refer to http://www.idt.com/package/pyg28. Electrical Specification Maximum Limit -0.3V~3.7V -0.3V~3.7V -1V~VDD -0.3V~VDD+2.6V -40~85 °C 150 °C 63.2 53 Unit Condition °C/W No Airflow January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PACKAGE DIMENSIONS 54 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 55 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 56 January 10, 2012 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ORDERING INFORMATION XXXXX Device Type XXX Package X Temperature Range I Industry (-40 ℃ to +85 ℃) PYG Green SSOP28 90E21 90E22 90E23 Single-Phase High-Performance Wide-Span Energy Metering IC 90E24 DATASHEET DOCUMENT HISTORY 09/02/2010 pg. 16 11/02/2010 pg. 37, 40 12/13/2010 pg. 6, 10, 48, 52 12/27/2010 pg. 48 03/22/2011 pg. 53 01/10/2012 pg. 48, 52, 54, 55, 56 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com for Sales: 86-21-64958900 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 57 for Tech Support: 86-21-64958900 email:[email protected]