AD ADE7880ACPZ

Data Sheet
Polyphase Multifunction Energy Metering IC
with Harmonic Monitoring
ADE7880
FEATURES
GENERAL DESCRIPTION
Highly accurate; supports IEC 62053-21, IEC 62053-22,
IEC 62053-23, EN 50470-1, EN 50470-3, ANSI C12.20, and
IEEE1459 standards
Supports IEC 61000-4-7 Class I and Class II accuracy
specification
Compatible with 3-phase, 3- or 4-wire (delta or wye), and
other 3-phase services
Supplies rms, active, reactive and apparent powers, power
factor, THD, and harmonic distortion of all harmonics
within 2.8 kHz pass band on all phases
Supplies rms and harmonic distortions of all harmonics
within 2.8 kHz pass band on neutral current
Less than 1% error in harmonic current and voltage rms,
harmonic active and reactive powers over a dynamic
range of 2000 to 1 at TA = 25°C
Supplies total (fundamental and harmonic) active and
apparent energy and fundamental active/reactive energy
on each phase and on the overall system
Less than 0.1% error in active and fundamental reactive
energy over a dynamic range of 1000 to 1 at TA = 25°C
Less than 0.2% error in active and fundamental reactive
energy over a dynamic range of 5000 to 1 at TA = 25°C
Less than 0.1% error in voltage and current rms over a
dynamic range of 1000 to 1 at TA = 25°C
Battery supply input for missing neutral operation
Wide-supply voltage operation: 2.4 V to 3.7 V
Reference: 1.2 V (drift 10 ppm/°C typical) with external
overdrive capability
40-lead lead frame chip scale package (LFCSP), Pb-free, pinfor-pin compatible with ADE7854, ADE7858, ADE7868 and
ADE7878
The ADE7880 1 is high accuracy, 3-phase electrical energy
measurement IC with serial interfaces and three flexible pulse
outputs. The ADE7880 device incorporates second-order sigma-
APPLICATIONS
Energy metering systems
Power quality monitoring
Solar inverters
Process monitoring
Protective devices
delta (Σ-Δ) analog-to-digital converters (ADCs), a digital
integrator, reference circuitry, and all of the signal processing
required to perform the total (fundamental and harmonic) active,
and apparent energy measurements, rms calculations, as well as
fundamental-only active and reactive energy measurements. In
addition, the ADE7880 computes the rms of harmonics on the
phase and neutral currents and on the phase voltages, together
with the active, reactive and apparent powers, and the power
factor and harmonic distortion on each harmonic for all phases.
Total harmonic distortion (THD) is computed for all currents
and voltages. A fixed function digital signal processor (DSP)
executes this signal processing. The DSP program is stored in
the internal ROM memory.
The ADE7880 is suitable for measuring active, reactive, and
apparent energy in various 3-phase configurations, such as wye
or delta services with, both, three and four wires. The ADE7880
provides system calibration features for each phase, that is, rms
offset correction, phase calibration, and gain calibration. The
CF1, CF2, and CF3 logic outputs provide a wide choice of
power information: total active powers, apparent powers, or the
sum of the current rms values, and fundamental active and
reactive powers.
The ADE7880 contains waveform sample registers that allow
access to all ADC outputs. The devices also incorporate power
quality measurements, such as short duration low or high
voltage detections, short duration high current variations, line
voltage period measurement, and angles between phase voltages
and currents. Two serial interfaces, SPI and I2C, can be used to
communicate with the ADE7880. A dedicated high speed
interface, the high speed data capture (HSDC) port, can be used
in conjunction with I2C to provide access to the ADC outputs
and real-time power information. The ADE7880 also has two
interrupt request pins, IRQ0 and IRQ1, to indicate that an enabled
interrupt event has occurred. Three specially designed low power
modes ensure the continuity of energy accumulation when the
ADE7880 is in a tampering situation. The ADE7880 is available
in the 40-lead LFCSP, Pb-free package, pin-for-pin compatible
with ADE7854, ADE7858, ADE7868, and ADE7878 devices.
1
Patents Pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADE7880
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Changing Phase Voltage Data path.......................................... 30 Applications....................................................................................... 1 Power Quality Measurements................................................... 31 General Description ......................................................................... 1 Phase Compensation ................................................................. 36 Revision History ............................................................................... 2 Reference Circuit........................................................................ 38 Functional Block Diagram .............................................................. 3 Digital Signal Processor............................................................. 38 Specifications..................................................................................... 4 Root Mean Square Measurement............................................. 39 Timing Characteristics ................................................................ 7 Active Power Calculation .......................................................... 43 Absolute Maximum Ratings.......................................................... 10 Fundamental Reactive Power Calculation.............................. 49 Thermal Resistance .................................................................... 10 Apparent Power Calculation..................................................... 53 ESD Caution................................................................................ 10 Power Factor Calculation .......................................................... 55 Pin Configuration and Function Descriptions........................... 11 Harmonics Calculations............................................................ 56 Typical Performance Characteristics ........................................... 13 Waveform Sampling Mode ....................................................... 64 Test Circuit ...................................................................................... 18 Energy-to-Frequency Conversion............................................ 64 Terminology .................................................................................... 19 No Load Condition .................................................................... 69 Power Management........................................................................ 20 Checksum Register..................................................................... 71 PSM0—Normal Power Mode (All Parts)................................ 20 Interrupts..................................................................................... 72 PSM1—Reduced Power Mode.................................................. 20 Serial Interfaces .......................................................................... 73 PSM2—Low Power Mode ......................................................... 20 ADE7880 Quick Setup As Energy Meter ................................ 80 PSM3—Sleep Mode (All Parts) ................................................ 21 ADE7880 Evaluation Board...................................................... 80 Power-Up Procedure.................................................................. 23 Die Version.................................................................................. 80 Hardware Reset........................................................................... 24 Silicon Anomaly ............................................................................. 81 Software Reset Functionality .................................................... 24 ADE7880 Functionality Issues ................................................. 81 Theory of Operation ...................................................................... 25 Functionality Issues.................................................................... 81 Analog Inputs.............................................................................. 25 Section 1. ADE7880 Functionality Issues ............................... 82 Analog-to-Digital Conversion.................................................. 25 Registers List ................................................................................... 83 Current Channel ADC............................................................... 26 Outline Dimensions ..................................................................... 103 di/dt Current Sensor and Digital Integrator............................... 28 Ordering Guide ........................................................................ 103 Voltage Channel ADC ............................................................... 29 REVISION HISTORY
3/12—Rev. 0 to Rev. A
Removed References to + N (Plus Noise) and changed VTHDN
to VTHD and ITHDN to ITHD.................................. Throughout
Changes to Reactive Energy Management Parameter in Table 1 .... 4
Changes to Figure 6........................................................................ 11
Changes to Table 7.......................................................................... 12
Changes to Phase Compensation Section ................................... 36
Changes to Equation 13 ................................................................. 39
Changes to Equation 33 ................................................................. 49
Changes to Fundamental Reactive Energy Calculation Section ... 51
Changes to Figure 80...................................................................... 55
Changes to Figure 85...................................................................... 62
Changes to Energy Registers and CF Outputs for Various
Accumulation Modes Section....................................................... 67
Changes to Figure 95...................................................................... 69
Changes to No Load Condition Section...................................... 69
Changes to Equation 53................................................................. 71
Changes to Figure 100 ................................................................... 74
Changes to Figure 101 and to Figure 102.................................... 75
Changes to SPI-Compatible Interface Section ........................... 76
Changes to HSDC Interface Section............................................ 78
Changes to Figure 109 and to Figure 110.................................... 80
Changes to Silicon Anomaly Section........................................... 81
Changes to Table 48 ....................................................................... 99
Changes to Table 52 ..................................................................... 101
10/11—Revision 0: Initial Version
Rev. A | Page 2 of 104
Data Sheet
ADE7880
FUNCTIONAL BLOCK DIAGRAM
RESET
REFIN/OUT
VDD
AGND
AVDD
DVDD
DGND
4
17
26
25
24
5
6
AIRMSOS
LDO
LDO
27
CLKOUT 28
ADE7880
APGAIN
X2
CLKIN 27
AIRMS
LPF
1.2V
REF
AIGAIN
HPFEN OF
CONFIG3
DIGITAL
INTEGRATOR
X2
HPF
IAN 8
APHCAL
AVGAIN
AVRMSOS
HPFEN OF
CONFIG3
CF2DEN
HPF
COMPUTATIONAL
BLOCK FOR
FUNDAMENTAL
ACTIVE AND
REACTIVE POWER
IBP 9
ADC
PGA1
IBN 12
VBP 22
PGA3
ADC
TOTAL/FUNDAMENTAL ACTIVE ENERGIES
FUNDAMENTAL REACTIVE ENERGY
APPARENT ENERGY
VOLTAGE CURRENT RMS
HARMONIC INFORMATION CALCULATION
FOR PHASE B
(SEE PHASE A FOR DETAILED DATA PATH)
ADC
PGA1
VCP 19
PGA3
VN 18
ADC
APGAIN
AFWATTOS
APGAIN
AFVAROS
PHASE A,
PHASE B,
AND
PHASE C
DATA
TOTAL/FUNDAMENTAL ACTIVE ENERGIES
FUNDAMENTAL REACTIVE ENERGY
APPARENT ENERGY
VOLTAGE/CURRENT RMS
HARMONIC INFORMATION CALCULATION
FOR PHASE C
(SEE PHASE A FOR DETAILED DATA PATH)
:
DFC
32 IRQ1
36 SCLK/SCL
38 MOSI/SDA
HSDC
DIGITAL
INTEGRATOR
PGA2
ADC
HPF
37 MISO/HSD
39 SS/HSA
NIRMSOS
INP 15
INN 16
35 CF3/HSCLK
29 IRQ0
COMPUTATIONAL BLOCK FOR HARMONIC
INFORMATION ON NEUTRAL CURRENT
HPFEN OF
CONFIG3
:
SPI/I2C
I2C
NIGAIN
34 CF2/HREADY
CF3DEN
DFC
COMPUTATIONAL
BLOCK FOR
HARMONIC
INFORMATION ON
PHASE A CURRENT
AND VOLTAGE
ICP 13
ICN 14
33 CF1
AWATTOS
LPF
ADC
:
DFC
APGAIN
VAP 23
PGA3
PM1
CF1DEN
27
ADC
PGA1
PM0
3
AVRMS
LPF
IAP 7
2
X2
LPF
Figure 1. ADE7880 Functional Block Diagram
Rev. A | Page 3 of 104
NIRMS
DIGITAL SIGNAL
PROCESSOR
10193-001
POR
ADE7880
Data Sheet
SPECIFICATIONS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C.
Table 1.
Parameter 1 , 2
ACTIVE ENERGY MEASUREMENT
Active Energy Measurement Error
(per Phase)
Total Active Energy
Fundamental Active Energy
Min
Typ
Unit
Test Conditions/Comments
0.1
%
0.2
%
0.1
%
0.2
%
0.1
%
0.2
%
0.1
%
0.2
%
Over a dynamic range of 1000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1, gain
compensation only
Over a dynamic range of 5000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1
Over a dynamic range of 500 to 1,
PGA = 8, 16; integrator on, pf = 1, gain
compensation only
Over a dynamic range of 2000 to 1,
PGA = 8, 16; integrator on, pf = 1
Over a dynamic range of 1000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1, gain
compensation only
Over a dynamic range of 5000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1
Over a dynamic range of 500 to 1,
PGA = 8, 16; integrator on, pf = 1, gain
compensation only
Over a dynamic range of 2000 to 1,
PGA = 8, 16; integrator on, pf = 1
Line frequency = 45 Hz to 65 Hz, HPF on
Phase lead 37°
Phase lag 60°
VDD = 3.3 V + 120 mV rms/120 Hz,
IPx = VPx = ±100 mV rms
Phase Error Between Channels
Power Factor (PF) = 0.8 Capacitive
PF = 0.5 Inductive
AC Power Supply Rejection
Output Frequency Variation
DC Power Supply Rejection
Output Frequency Variation
Total Active Energy Measurement
Bandwidth (−3 dB)
REACTIVE ENERGY MEASUREMENT
Reactive Energy Measurement Error
(per Phase)
Fundamental Reactive Energy
±0.05
±0.05
Degrees
Degrees
0.01
%
0.01
3.3
%
kHz
0.1
%
0.2
%
0.1
%
0.2
%
VDD = 3.3 V ± 330 mV dc
Phase Error Between Channels
PF = 0.8 Capacitive
PF = 0.5 Inductive
AC Power Supply Rejection
Output Frequency Variation
DC Power Supply Rejection
Max
±0.05
±0.05
0.01
Degrees
Degrees
Over a dynamic range of 1000 to 1,
PGA = 1, 2, 4; integrator off, pf = 0, gain
compensation only
Over a dynamic range of 5000 to 1,
PGA = 1, 2, 4; integrator off, pf = 0
Over a dynamic range of 500 to 1,
PGA = 8, 16; integrator on, pf = 0, gain
compensation only
Over a dynamic range of 2000 to 1,
PGA = 8, 16; integrator on, pf = 0
Line frequency = 45 Hz to 65 Hz, HPF on
Phase lead 37°
Phase lag 60°
VDD = 3.3 V + 120 mV rms/120 Hz,
IPx = VPx = ± 100 mV rms
%
VDD = 3.3 V ± 330 mV dc
Rev. A | Page 4 of 104
Data Sheet
Parameter 1 , 2
Output Frequency Variation
Fundamental Reactive Energy
Measurement Bandwidth (−3 dB)
RMS MEASUREMENTS
I RMS and V RMS Measurement
Bandwidth (−3 dB)
I RMS and V RMS Measurement Error
(PSM0 Mode)
MEAN ABSOLUTE VALUE (MAV)
MEASUREMENT
I MAV Measurement Bandwidth
(PSM1 Mode)
I MAV Measurement Error (PSM1 Mode)
HARMONIC MEASUREMENTS
Bandwidth (−3 dB)
No attenuation Pass Band
Fundamental Line Frequency fL
ADE7880
Min
Typ
0.01
3.3
Max
3.3
kHz
0.1
%
260
Hz
0.5
%
3.3
2.8
kHz
kHz
Hz
45
66
Maximum Number of Harmonics 3
⎡ 2800 ⎤
⎢
⎥
⎣ fL ⎦
Absolute Maximum Number of
Harmonics
Harmonic RMS Measurement Error
63
Harmonic Active/Reactive Power
Measurement Error
1
%
1
%
ANALOG INPUTS
Maximum Signal Levels
Input Impedance (DC)
IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP,
and VCP Pins
VN Pin
ADC Offset Error
Unit
%
kHz
±500
490
mV peak
Test Conditions/Comments
Over a dynamic range of 1000 to 1,
PGA = 1
Over a dynamic range of 100 to 1,
PGA = 1, 2, 4, 8
Nominal voltages must have amplitudes
greater than 100 mV peak at voltage ADCs
Instantaneous reading accuracy over a
dynamic range of 1000 to 1 for harmonics
of frequencies within the pass band; after
the initial 750 ms settling time; PGA = 1
Accuracy over a dynamic range of 2000:1
for harmonics of frequencies within the
pass band; average of 10 readings at 128
ms update rate, after the initial 750 ms
setting time; PGA = 1
Instantaneous reading accuracy over a
dynamic range of 1000 to 1 for harmonics
of frequencies within the pass band; after
the initial 750 ms settling time; PGA = 1.
Accuracy over a dynamic range of 2000:1
for harmonics of frequencies within the
pass band; average of 5 readings at 128 ms
update rate, after the initial 750 ms setting
time; PGA = 1.
Differential inputs between the following
pins: IAP and IAN, IBP and IBN, ICP and ICN;
single-ended inputs between the following
pins: VAP and VN, VBP and VN, VCP, and VN
kΩ
170
kΩ
mV
−35
PGA = 1, uncalibrated error, see the
Terminology section. Scales inversely
Gain Error
−2
%
Rev. A | Page 5 of 104
proportional to the other PGA gains.
External 1.2 V reference
ADE7880
Parameter 1 , 2
WAVEFORM SAMPLING
Data Sheet
Min
Typ
Max
Unit
Current and Voltage Channels
Signal-to-Noise Ratio, SNR
Signal-to-Noise-and-Distortion Ratio,
SINAD
Bandwidth (−3 dB)
TIME INTERVAL BETWEEN PHASES
Measurement Error
CF1, CF2, CF3 PULSE OUTPUTS
Maximum Output Frequency
Duty Cycle
Active Low Pulse Width
Jitter
REFERENCE INPUT
REFIN/OUT Input Voltage Range
72
72
dB
dB
3.3
kHz
0.3
Degrees
Line frequency = 45 Hz to 65 Hz, HPF on
68.818
50
kHz
%
(1 + 1/CFDEN) ×
50
80
0.04
%
WTHR = VARTHR = VATHR = 3
If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is even and > 1
If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is odd and > 1
If CF1, CF2, or CF3 frequency < 6.25 Hz
For CF1, CF2, or CF3 frequency = 1 Hz and
nominal phase currents are larger than
10% of full scale
1.1
Input Capacitance
ON-CHIP REFERENCE
PSM0 and PSM1 Modes
Reference Error
Output Impedance
Temperature Coefficient
CLKIN
Input Clock Frequency
Crystal Equivalent Series Resistance
CLKIN Load Capacitor 4
CLKOUT Load Capacitor4
LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS,
RESET, PM0, AND PM1
Input High Voltage, VINH
Input Current, IIN
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS—IRQ0, IRQ1, AND
MISO/HSD
Output High Voltage, VOH
ISOURCE
Output Low Voltage, VOL
ISINK
CF1, CF2, CF3/HSCLK
Output High Voltage, VOH
ISOURCE
Output Low Voltage, VOL
ISINK
Test Conditions/Comments
Sampling CLKIN/2048, 16.384 MHz/2048 =
8 kSPS
See the Waveform Sampling Mode
section
PGA = 1
PGA = 1
ms
%
1.3
V
10
pF
Minimum = 1.2 V − 8%; maximum =
1.2 V + 8%
Nominal 1.21 V at the REFIN/OUT pin at
TA = 25°C
±2
10
50
mV
kΩ
ppm/°C
16.384
16.55
200
40
40
MHz
Ω
pF
pF
82
0.8
−7.3
10
V
nA
V
μA
pF
1
All specifications CLKIN of 16.384 MHz
16.22
30
20
20
2.4
VDD = 3.3 V ± 10%
Input = VDD = 3.3 V
VDD = 3.3 V ± 10%
Input = 0, VDD = 3.3 V
VDD = 3.3 V ± 10%
3.0
800
0.4
2
V
μA
V
mA
500
0.4
2
V
μA
V
mA
2.4
Rev. A | Page 6 of 104
VDD = 3.3 V ± 10%
VDD = 3.3 V ± 10%
VDD = 3.3 V ± 10%
VDD = 3.3 V ± 10%
Data Sheet
Parameter 1 , 2
POWER SUPPLY
PSM0 Mode
VDD Pin
IDD
PSM1 and PSM2 Modes
VDD Pin
IDD
PSM1 Mode
PSM2 Mode
PSM3 Mode
VDD Pin
IDD in PSM3 Mode
1
2
3
4
ADE7880
Min
Typ
Max
Unit
Test Conditions/Comments
For specified performance
3.63
V
Minimum = 3.3 V − 10%; maximum =
3.3 V + 10%
28
mA
3.7
V
5.3
0.2
5.8
0.27
mA
mA
1.8
3.7
6
V
μA
2.97
25
2.4
For specified performance
2.4
See the Typical Performance Characteristics section.
See the Terminology section for a definition of the parameters.
⎡ 2800 ⎤
⎢
⎥ means the whole number of the division.
⎣ fL ⎦
The CLKIN/CLKOUT load capacitors refer to the capacitors that are mounted between the CLKIN and CLKOUT pins of the ADE7880 and AGND. The capacitors should
be chosen based on the crystal manufacturer’s data sheet specification, and they must not have more than the maximum value specified in the table.
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams (see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions).
Table 2. I2C-Compatible Interface Timing Parameter
Parameter
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of SCL Clock
High Period of SCL Clock
Set-Up Time for Repeated Start Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Suppressed Spikes
1
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
tBUF
tSP
N/A means not applicable.
Rev. A | Page 7 of 104
Standard Mode
Min
Max
0
100
4.0
4.7
4.0
4.7
0
3.45
250
1000
300
4.0
4.7
N/A 1
Fast Mode
Min
Max
0
400
0.6
1.3
0.6
0.6
0
0.9
100
20
300
20
300
0.6
1.3
50
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
ns
ADE7880
Data Sheet
SDA
tSU;DAT
tF
tF
tLOW
tHD;STA
tSP
tBUF
tF
tF
SCLK
tHD;DAT
tSU;STO
tSU;STA
tHIGH
START
CONDITION
REPEATED START
CONDITION
10193-002
tHD;STA
STOP
START
CONDITION CONDITION
Figure 2. I2C-Compatible Interface Timing
Table 3. SPI Interface Timing Parameters
Parameter
SS to SCLK Edge
SCLK Period
SCLK Low Pulse Width
SCLK High Pulse Width
Data Output Valid After SCLK Edge
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
Data Output Fall Time
Data Output Rise Time
SCLK Rise Time
SCLK Fall Time
MISO Disable After SS Rising Edge
SS High After SCLK Edge
Min
50
0.4
175
175
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDIS
tSFS
Max
4000 1
100
100
5
20
20
20
20
200
0
Guaranteed by design.
SS
tSS
tSFS
SCLK
tSL
tSH
tDAV
tSF
tSR
tDIS
MSB
MISO
INTERMEDIATE BITS
tDF
LSB
tDR
INTERMEDIATE BITS
MSB IN
MOSI
LSB IN
tDSU
10193-003
1
Symbol
tSS
tDHD
Figure 3. SPI Interface Timing
Rev. A | Page 8 of 104
Unit
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
ADE7880
Table 4. HSDC Interface Timing Parameter
Parameter
HSA to HSCLK Edge
HSCLK Period
HSCLK Low Pulse Width
HSCLK High Pulse Width
Data Output Valid After HSCLK Edge
Data Output Fall Time
Data Output Rise Time
HSCLK Rise Time
HSCLK Fall Time
HSD Disable After HSA Rising Edge
HSA High After HSCLK Edge
Symbol
tSS
Min
0
125
50
50
tSL
tSH
tDAV
tDF
tDR
tSR
tSF
tDIS
tSFS
Max
40
20
20
10
10
5
0
HSA
tSS
tSFS
HSCLK
tSL
tSF
tSR
tDIS
MSB
INTERMEDIATE BITS
LSB
tDF
tDR
Figure 4. HSDC Interface Timing
2mA
TO OUTPUT
PIN
IOL
1.6V
CL
50pF
800µA
IOH
Figure 5. Load Circuit for Timing Specifications
Rev. A | Page 9 of 104
10193-004
HSD
tSH
10193-005
tDAV
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADE7880
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter1
VDD to AGND
VDD to DGND
Analog Input Voltage to AGND, IAP, IAN,
IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN
Analog Input Voltage to INP and INN
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature
Industrial Range
Storage Temperature Range
Junction Temperature
Lead Temperature (Soldering, 10 sec)
1
Rating
−0.3 V to +3.7 V
−0.3 V to +3.7 V
−2 V to +2 V
−2 V to +2 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
300°C
THERMAL RESISTANCE
θJA is specified equal to 29.3°C/W; θJC is specified equal to
1.8°C/W.
Table 6. Thermal Resistance
Package Type
40-Lead LFCSP
Regarding the temperature profile used in soldering RoHS Compliant Parts,
Analog Devices, Inc. advises that reflow profiles should conform to J-STD 20
from JEDEC. Refer to JEDEC website for the latest revision.
ESD CAUTION
Rev. A | Page 10 of 104
θJA
29.3
θJC
1.8
Unit
°C/W
Data Sheet
ADE7880
40
39
38
37
36
35
34
33
32
31
NC
SS/HSA
MOSI/SDA
MISO/HSD
SCLK/SCL
CF3/HSCLK
CF2/HREADY
CF1
IRQ1
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
ADE7880
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
NC
IRQ0
CLKOUT
CLKIN
VDD
AGND
AVDD
VAP
VBP
NC
NOTES
1. NC = NO CONNECT.
2. CREATE A SIMILAR PAD ON THE PCB UNDER THE
EXPOSED PAD. SOLDER THE EXPOSED PAD TO
THE PAD ON THE PCB TO CONFER MECHANICAL
STRENGTH TO THE PACKAGE. DO NOT CONNECT
THE PADS TO AGND OR DGND.
10193-006
NC
IBN
ICP
ICN
INP
INN
REFIN/OUT
VN
VCP
NC
11
12
13
14
15
16
17
18
19
20
NC
PM0
PM1
RESET
DVDD
DGND
IAP
IAN
IBP
NC
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 10, 11, 20,
21, 30, 31, 40
2
Mnemonic
NC
Description
No Connect. Do not connect to these pins. These pins are not connected internally.
PM0
3
PM1
4
RESET
5
DVDD
6
7, 8
DGND
IAP, IAN
9, 12
IBP, IBN
13, 14
ICP, ICN
15, 16
INP, INN
17
REFIN/OUT
Power Mode Pin 0. This pin, combined with PM1, defines the power mode of the ADE7880, as
described in Table 8.
Power Mode Pin 1. This pin defines the power mode of the ADE7880 when combined with PM0, as
described in Table 8.
Reset Input, Active Low. In PSM0 mode, this pin should stay low for at least 10 μs to trigger a
hardware reset.
This pin provides access to the on-chip 2.5 V digital LDO. Do not connect any external active
circuitry to this pin. Decouple this pin with a 4.7 μF capacitor in parallel with a ceramic 220 nF
capacitor.
Ground Reference. This pin provides the ground reference for the digital circuitry.
Analog Inputs for Current Channel A. This channel is used with the current transducers and is
referenced in this data sheet as Current Channel A. These inputs are fully differential voltage inputs
with a maximum differential level of ±0.5 V. This channel also has an internal PGA equal to the ones
on Channel B and Channel C.
Analog Inputs for Current Channel B. This channel is used with the current transducers and is
referenced in this data sheet as Current Channel B. These inputs are fully differential voltage inputs
with a maximum differential level of ±0.5 V. This channel also has an internal PGA equal to the ones
on Channel C and Channel A.
Analog Inputs for Current Channel C. This channel is used with the current transducers and is
referenced in this data sheet as Current Channel C. These inputs are fully differential voltage inputs
with a maximum differential level of ±0.5 V. This channel also has an internal PGA equal to the ones
on Channel A and Channel B.
Analog Inputs for Neutral Current Channel N. This channel is used with the current transducers and
is referenced in this data sheet as Current Channel N. These inputs are fully differential voltage
inputs with a maximum differential level of ±0.5 V. This channel also has an internal PGA, different
from the ones found on the A, B, and C channels.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal
value of 1.2 V. An external reference source with 1.2 V ± 8% can also be connected at this pin. In
either case, decouple this pin to AGND with a 4.7 μF capacitor in parallel with a ceramic 100 nF
capacitor. After reset, the on-chip reference is enabled.
Rev. A | Page 11 of 104
ADE7880
Data Sheet
Pin No.
18, 19, 22, 23
Mnemonic
VN, VCP, VBP, VAP
24
AVDD
25
AGND
26
VDD
27
CLKIN
28
CLKOUT
29, 32
IRQ0, IRQ1
33, 34, 35
CF1, CF2/HREADY,
CF3/HSCLK
36
SCLK/SCL
37
38
39
EP
MISO/HSD
MOSI/SDA
SS/HSA
Exposed Pad
Description
Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is
referenced as the voltage channel in this data sheet. These inputs are single-ended voltage inputs
with a maximum signal level of ±0.5 V with respect to VN for specified operation. This channel also
has an internal PGA.
This pin provides access to the on-chip 2.5 V analog low dropout regulator (LDO). Do not connect
external active circuitry to this pin. Decouple this pin with a 4.7 μF capacitor in parallel with a
ceramic 220 nF capacitor.
Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the
analog ground plane or to the quietest ground reference in the system. Use this quiet ground
reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers.
Supply Voltage. This pin provides the supply voltage. In PSM0 (normal power mode), maintain the
supply voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low
power mode), and PSM3 (sleep mode), when the ADE7880 is supplied from a battery, maintain the
supply voltage between 2.4 V and 3.7 V. Decouple this pin to DGND with a 10 μF capacitor in parallel with
a ceramic 100 nF capacitor.
Master Clock. An external clock can be provided at this logic input. Alternatively, a parallel resonant
AT-cut crystal can be connected across CLKIN and CLKOUT to provide a clock source for the
ADE7880. The clock frequency for specified operation is 16.384 MHz. Use ceramic load capacitors of
a few tens of picofarad with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet
for load capacitance requirements.
A crystal can be connected across this pin and CLKIN (as previously described with Pin 27 in this
table) to provide a clock source for the ADE7880.
Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a
detailed presentation of the events that can trigger interrupts.
Calibration Frequency (CF) Logic Outputs. These outputs provide power information based on the
CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the CFMODE register. These outputs are used for
operational and calibration purposes. The full-scale output frequency can be scaled by writing to the
CF1DEN, CF2DEN, and CF3DEN registers, respectively (see the Energy-to-Frequency Conversion
section). CF2 is multiplexed with the HREADY signal generated by the harmonic calculations block.
CF3 is multiplexed with the serial clock output of the HSDC port.
Serial Clock Input for SPI Port/Serial Clock Input for I2C Port. All serial data transfers are synchronized
to this clock (see the Serial Interfaces section). This pin has a Schmidt trigger input for use with a
clock source that has a slow edge transition time, for example, opto-isolator outputs.
Data Out for SPI Port/Data Out for HSDC Port.
Data In for SPI Port/Data Out for I2C Port.
Slave Select for SPI Port/HSDC Port Active.
Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the
PCB to confer mechanical strength to the package. Do not connect the pads to AGND or DGND.
Rev. A | Page 12 of 104
Data Sheet
ADE7880
0.5
0.5
0.3
0.3
0.1
0.1
ERROR (%)
–0.1
–0.3
1
10
100
Figure 7. Total Active Energy Error as Percentage of Reading (Gain = +1,
Power Factor = 1) over Temperature with Internal Reference and
Integrator Off
100
0.3
0.1
–0.1
–0.3
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
–0.5
0.01
10193-101
–0.5
0.01
Figure 8. Total Active Energy Error as Percentage of Reading over Gain with
Internal Reference and Integrator Off
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
10193-104
–0.3
Figure 11. Total Active Energy Error as Percentage of Reading (Gain = +16)
over Temperature with Internal Reference and Integrator On
0.5
PF = +1.0
PF = +0.5
PF = –0.5
0.3
0.3
0.1
0.1
ERROR (%)
ERROR (%)
10
0.5
–0.1
–0.1
–0.1
–0.3
–0.3
47
49
51
53
55
57
59
LINE FREQUENCY (Hz)
61
63
65
–0.5
0.01
10193-102
–0.5
45
1
Figure 10. Total Active Energy Error as Percentage of Reading (Gain = +1)
over Power Supply with Internal Reference and Integrator Off
GAIN = +1
GAIN = +2
GAIN = +4
GAIN = +8
GAIN = +16
0.1
0.5
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
ERROR (%)
ERROR (%)
0.3
–0.5
0.01
10193-103
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
0.5
–0.1
–0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
10193-100
–0.5
0.01
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
Figure 9. Total Active Energy Error as Percentage of Reading (Gain = +1) over
Frequency with Internal Reference and Integrator Off
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
0.1
1
10
PERCENTAGE OF FULL-SCALE CURRENT (%)
100
10193-105
ERROR (%)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 12. Fundamental Active Energy Error as Percentage of Reading
(Gain = +1, Power Factor = 1) over Temperature with Internal Reference and
Integrator Off
Rev. A | Page 13 of 104
ADE7880
0.1
–0.1
1
10
100
0.5
0.3
–0.1
–0.3
1
10
100
Figure 14. Fundamental Active Energy Error as Percentage of Reading
(Gain = +1) over Power Supply with Internal Reference and Integrator Off
GAIN = +1
GAIN = +2
GAIN = +4
GAIN = +8
GAIN = +16
0.1
–0.1
–0.5
0.01
1
10
100
Figure 17. Fundamental Reactive Energy Error as Percentage of Reading over
Gain with Internal Reference and Integrator Off
0.5
0.5
0.3
0.3
0.1
0.1
–0.1
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
ERROR (%)
ERROR (%)
100
10193-110
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
PF = +1.0
PF = +0.5
PF = –0.5
–0.1
–0.3
–0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
0.1
1
10
PERCENTAGE OF FULL-SCALE CURRENT (%)
100
–0.5
45
10193-108
–0.5
0.01
10
–0.3
10193-107
–0.5
0.01
1
Figure 16. Fundamental Reactive Energy Error as Percentage of Reading
(Gain = +1, Power Factor = 0) over Temperature with Internal Reference and
Integrator Off
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
0.1
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
ERROR (%)
ERROR (%)
–0.5
0.01
10193-106
0.1
Figure 13. Fundamental Active Energy Error as Percentage of Reading over
Gain with Internal Reference and Integrator Off
0.3
–0.1
–0.3
PERCENTAGE OF FULL-SCALE CURRENT (%)
0.5
0.1
10193-109
–0.3
–0.5
0.01
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
0.3
ERROR (%)
ERROR (%)
0.3
0.5
GAIN = +1
GAIN = +2
GAIN = +4
GAIN = +8
GAIN = +16
Figure 15. Fundamental Active Energy Error as Percentage of Reading
(Gain = +1) over Temperature with Internal Reference and Integrator On
47
49
51
53
55
57
59
LINE FREQUENCY (Hz)
61
63
65
10193-111
0.5
Data Sheet
Figure 18. Fundamental Reactive Energy Error as Percentage of Reading
(Gain = +1) over Frequency with Internal Reference and Integrator Off
Rev. A | Page 14 of 104
Data Sheet
0.3
0.1
0.1
ERROR (%)
–0.1
–0.1
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
–0.5
0.01
10193-112
–0.5
0.01
–0.3
GAIN ERROR
(% ERROR RELATIVE TO FUNDAMENTAL)
ERROR (%)
10
100
5
0.3
0.1
–0.1
–0.3
0.1
1
10
100
Figure 20. Fundamental Reactive Energy Error as Percentage of Reading
(Gain = +16) over Temperature with Internal Reference and Integrator On
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
10193-113
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
PERCENTAGE OF FULL-SCALE CURRENT (%)
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
HARMONIC ORDER (55Hz FUNDAMENTAL)
Figure 23. Harmonic I RMS Error as a Percentage of Reading over Harmonic
Order, 63 Harmonics, 55 Hz Fundamental, 30 Averages per Reading, 750 ms
Settling time, 125 μs Update Rate
6
MEASUREMENT ERROR (% of Reading)
0.5
0.3
0.1
–0.1
–0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 21. I RMS Error as Percentage of Reading (Gain = +1) over
Temperature with Internal Reference and Integrator Off
4
2
0
–2
–4
–6
0.01
10193-114
ERROR (%)
1
Figure 22. V RMS Error as a Percentage of Reading (Gain = +1) over
Temperature with Internal Reference
0.5
–0.5
0.01
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 19. Fundamental Reactive Energy Error as Percentage of Reading
(Gain = +1) over Power Supply with Internal Reference and Integrator Off
–0.5
0.01
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
10193-115
–0.3
10193-116
ERROR (%)
0.3
0.5
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
0.1
1
10
PERCENTAGE OF FULL-SCALE CURRENT (%)
100
10193-117
0.5
ADE7880
Figure 24. Harmonic I RMS Error as a Percentage of Reading (Gain = +1),
51 Harmonics, 55 Hz Fundamental, Single Reading, 750 ms Settling Time
Rev. A | Page 15 of 104
ADE7880
Data Sheet
4
2
0
–2
–4
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 25. Harmonic I RMS Error as Percentage of Reading (Gain = +1),
51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading, 750 ms
Settling Time, 125 μs Update Rate
–4
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 28. Harmonic Reactive Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading, 750 ms
Settling Time, 125 μs Update Rate
–2
–4
0.1
1
10
100
Figure 26. Harmonic Active Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading,
750 ms Settling Time, 125 μs Update Rate
4
2
0
–2
–4
–6
0.01
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
10193-122
MEASUREMENT ERROR (% of Reading)
0
10193-119
MEASUREMENT ERROR (% of Reading)
2
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 29. Harmonic Reactive Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,
750 ms Settling Time, 125 μs Update Rate
6
MEASUREMENT ERROR (% of Reading)
6
4
2
0
–2
–4
0.1
1
10
PERCENTAGE OF FULL-SCALE CURRENT (%)
100
Figure 27. Harmonic Active Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,
750 ms Settling Time, 125 μs Update Rate
4
2
0
–2
–4
–6
0.01
10193-120
MEASUREMENT ERROR (% of Reading)
–2
6
4
–6
0.01
0
–6
0.01
6
–6
0.01
2
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 30. Harmonic Apparent Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading,
750 ms Settling Time, 125 μs Update Rate
Rev. A | Page 16 of 104
10193-123
–6
0.01
4
10193-121
MEASUREMENT ERROR (% of Reading)
6
10193-118
MEASUREMENT ERROR (% of Reading)
6
Data Sheet
ADE7880
4
2
0
–2
–4
–6
0.01
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
10193-124
MEASUREMENT ERROR (% of Reading)
6
Figure 31. Harmonic Apparent Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,
750 ms Settling Time, 125 μs Update Rate
Rev. A | Page 17 of 104
ADE7880
Data Sheet
TEST CIRCUIT
3.3V
10kΩ
1µF
1kΩ
5
10nF
MISO/HSD 37
SAME AS
IAP, IAN
10nF
13 ICP
CF3/HSCLK 35
ADE7880
14 ICN
1.5kΩ
6
25
4.7µF
+
0.1µF
16.384MHz
CLKIN 27
20pF
10193-007
23 VAP
20pF
CLKOUT 28
AGND
22 VBP
SAME AS
CF2
IRQ0 29
REFIN/OUT 17
DGND
SAME AS
VCP
SAME AS
VCP
CF1 33
IRQ1 32
19 VCP
10nF
10kΩ
CF2/HREADY 34
18 VN
1kΩ
3.3V
SCLK/SCL 36
9 IBP
12 IBN
0.22µF
MOSI/SDA 38
RESET
8 IAN
SAME AS
IAP, IAN
+
SS/HSA 39
7 IAP
10nF
1kΩ
26
3 PM1
4
1kΩ
24
DVDD
2 PM0
4.7µF
VDD
3.3V
0.22µF
AVDD
4.7µF
+
Figure 32. Test Circuit
Rev. A | Page 18 of 104
Data Sheet
ADE7880
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7880 is defined by
Measurement Error =
Energy Registered by ADE 7880 − True Energy
× 100% (1)
True Energy
Phase Error Between Channels
The high-pass filter (HPF) and digital integrator introduce a
slight phase mismatch between the current and the voltage
channel. The all digital design ensures that the phase matching
between the current channels and voltage channels in all three
phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2°
over a range of 40 Hz to 1 kHz. This internal phase mismatch
can be combined with the external phase error (from current
sensor or component tolerance) and calibrated with the phase
calibration registers.
Power Supply Rejection (PSR)
This quantifies the ADE7880 measurement error as a percentage of reading when the power supplies are varied. For the ac
PSR measurement, a reading at nominal supplies (3.3 V) is
taken. A second reading is obtained with the same input signal
levels when an ac signal (120 mV rms at 100 Hz) is introduced
onto the supplies. Any error introduced by this ac signal is
expressed as a percentage of reading—see the Measurement
Error definition.
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same
input signal levels when the power supplies are varied ±10%.
Any error introduced is expressed as a percentage of the
reading.
ADC Offset Error
This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection
(see the Typical Performance Characteristics section). However,
the HPF removes the offset from the current and voltage channels
and the power calculation remains unaffected by this offset.
Gain Error
The gain error in the ADCs of the ADE7880 is defined as the
difference between the measured ADC output code (minus the
offset) and the ideal output code (see the Current Channel ADC
section and the Voltage Channel ADC section). The difference
is expressed as a percentage of the ideal code.
CF Jitter
The period of pulses at one of the CF1, CF2, or CF3 pins is
continuously measured. The maximum, minimum, and average
values of four consecutive pulses are computed as follows:
Maximum = max(Period0, Period1, Period2, Period3)
Minimum = min(Period0, Period1, Period2, Period3)
Average =
Period0 + Period1 + Period 2 + Period3
4
The CF jitter is then computed as
CFJITTER =
Maximum− Minimum
× 100%
Average
(2)
Harmonic Power Measurement Error
To measure the error in the harmonic active and reactive power
calculations made by the ADE7880, the voltage channel is supplied
with a signal comprising a fundamental and one harmonic
component with amplitudes equal to 250 mV. The current
channel is supplied with a signal comprising a fundamental
with amplitude of 50 mV and one harmonic component of the
same index as the one in the voltage channel. The amplitude of
the harmonic is varied from 250 mV, down to 250 μV, 2000 times
lower than full scale.
The error is defined by
Rev. A | Page 19 of 104
Measurement Error =
Power Registered by ADE 7880 − True Power
× 100% (3)
True Power
ADE7880
Data Sheet
POWER MANAGEMENT
The ADE7880 has four modes of operation, determined by the
state of the PM0 and PM1 pins (see Table 8). These pins provide
complete control of the ADE7880 operation and can easily be
connected to an external microprocessor I/O. The PM0 and
PM1 pins have internal pull-up resistors. See Table 10 and Table 11
for a list of actions that are recommended before and after setting
a new power mode.
Table 8. Power Supply Modes
Power Supply Modes
PSM0, Normal Power Mode
PSM1, Reduced Power Mode
PSM2, Low Power Mode
PSM3, Sleep Mode
PM1
0
0
1
1
PM0
1
0
0
1
PSM0—NORMAL POWER MODE (ALL PARTS)
In PSM0 mode, the ADE7880 is fully functional. The PM0 pin
is set to high, and the PM1 pin is set to low for the ADE7880 to
enter this mode. If the ADE7880 is in PSM1, PSM2, or PSM3
mode and is switched into PSM0 mode, then all control registers
take the default values with the exception of the threshold register,
LPOILVL, which is used in PSM2 mode, and the CONFIG2
register, both of which maintain their values.
The ADE7880 signals the end of the transition period by triggering
the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in the
STATUS1 register to 1. This bit is 0 during the transition period
and becomes 1 when the transition is finished. The status bit is
cleared and the IRQ1 pin is set back to high by writing to the
STATUS1 register with the corresponding bit set to 1. Bit 15
(RSTDONE) in the interrupt mask register does not have any
functionality attached even if the IRQ1 pin goes low when Bit 15
(RSTDONE) in the STATUS1 register is set to 1. This makes the
RSTDONE interrupt unmaskable.
PSM1—REDUCED POWER MODE
In the reduced power mode, PSM1, the ADE7880 measures the
mean absolute values (mav) of the 3-phase currents and stores
the results in the AIMAV, BIMAV, and CIMAV 20-bit registers.
This mode is useful in missing neutral cases in which the voltage
supply of the ADE7880 is provided by an external battery. The
serial ports, I2C or SPI, are enabled in this mode; the active port
can be used to read the AIMAV, BIMAV, and CIMAV registers. It
is not recommended to read any of the other registers because their
values are not guaranteed in this mode. Similarly, a write operation
is not taken into account by the ADE7880 in this mode.
during PSM1 (see the Current Mean Absolute Value Calculation
section for more details on the xIMAV registers).
The 20-bit mean absolute value measurements done in PSM1,
although available also in PSM0, are different from the rms
measurements of phase currents and voltages executed only in
PSM0 and stored in the HxIRMS and HxVRMS 24-bit registers.
See the Current Mean Absolute Value Calculation section for
details.
If the ADE7880 is set in PSM1 mode after it was in the PSM0
mode, the ADE7880 immediately begins the mean absolute
value calculations without any delay. The xIMAV registers are
accessible at any time; however, if the ADE7880 is set in PSM1
mode after it was in PSM2 or PSM3 modes, the ADE7880
signals the start of the mean absolute value computations by
triggering the IRQ1 pin low. The xIMAV registers can be
accessed only after this moment.
PSM2—LOW POWER MODE
In the low power mode, PSM2, the ADE7880 compares all
phase currents against a threshold for a period of 0.02 ×
(LPLINE[4:0] + 1) seconds, independent of the line frequency.
LPLINE[4:0] are Bits[7:3] of the LPOILVL register (see Table 9).
Table 9. LPOILVL Register
Bit
[2:0]
Mnemonic
LPOIL[2:0]
Default
111
[7:3]
LPLINE[4:0]
00000
Description
Threshold is put at a value
corresponding to full scale
multiplied by LPOIL/8
The measurement period is
(LPLINE[4:0] + 1)/50 sec
The threshold is derived from Bits[2:0] (LPOIL[2:0]) of the
LPOILVL register as LPOIL[2:0]/8 of full scale. Every time
one phase current becomes greater than the threshold, a
counter is incremented. If every phase counter remains below
LPLINE[4:0] + 1 at the end of the measurement period, then
the IRQ0 pin is triggered low. If a single phase counter becomes
greater or equal to LPLINE[4:0] + 1 at the end of the measurement
period, the IRQ1 pin is triggered low. Figure 33 illustrates how
the ADE7880 behaves in PSM2 mode when LPLINE[4:0] = 2
and LPOIL[2:0] = 3. The test period is three 50 Hz cycles (60 ms),
and the Phase A current rises above the LPOIL[2:0] threshold three
times. At the end of the test period, the IRQ1 pin is triggered low.
In summary, in this mode, it is not recommended to access any
register other than AIMAV, BIMAV, and CIMAV. The circuit
that computes the rms estimates is also active during PSM0;
therefore, its calibration can be completed in either PSM0 mode
or in PSM1 mode. Note that the ADE7880 does not provide any
register to store or process the corrections resulting from the
calibration process. The external microprocessor stores the gain
values in connection with these measurements and uses them
Rev. A | Page 20 of 104
Data Sheet
ADE7880
into Sleep Mode PSM3. If the IRQ1 pin is triggered low at the
end of the measurement period, this signifies that at least one
current input is above the defined threshold and current is
flowing through the system, although no voltage is present at
the ADE7880 pins. This situation is often called missing neutral
and is considered a tampering situation, at which point the
external microprocessor sets the ADE7880 into PSM1 mode,
measures the mean absolute values of phase currents, and
integrates the energy based on their values and the nominal
voltage.
LPLINE[4:0] = 2
LPOIL[2:0]
THRESHOLD
IA CURRENT
PHASE
COUNTER = 2
PHASE
COUNTER = 3
10193-008
PHASE
COUNTER = 1
IRQ1
Figure 33. PSM2 Mode Triggering IRQ Pin for LPLINE[4:0] = 2 (50 Hz Systems)
The I2C or SPI port is not functional during this mode. The PSM2
mode reduces the power consumption required to monitor the
currents when there is no voltage input and the voltage supply
of the ADE7880 is provided by an external battery. If the IRQ0
pin is triggered low at the end of a measurement period, this
signifies all phase currents stayed below threshold and,
therefore, there is no current flowing through the system.
At this point, the external microprocessor sets the ADE7880
It is recommended to use the ADE7880 in PSM2 mode when
Bits[2:0] (PGA1[2:0]) of the Gain register are equal to 1 or 2.
These bits represent the gain in the current channel datapath. It
is not recommended to use the ADE7880 in PSM2 mode when
the PGA1[2:0] bits are equal to 4, 8, or 16.
PSM3—SLEEP MODE (ALL PARTS)
In sleep mode, the ADE7880 has most of its internal circuits
turned off and the current consumption is at its lowest level.
The I2C, HSDC, and SPI ports are not functional during this
mode, and the RESET, SCLK/SCL, MOSI/SDA, and SS/HSA pins
should be set high.
Table 10. Power Modes and Related Characteristics
All Registers1
LPOILVL, CONFIG2
I2C/SPI
Functionality
Set to default
Set to default
I2C enabled
Set to default
Unchanged
PSM1
Not available
PSM0 values retained
Active serial port is
unchanged if lockin procedure has
been previously
executed
Enabled
All circuits are active and DSP is in idle
mode.
All circuits are active and DSP is in idle
mode.
PSM2
Not available
PSM0 values retained
Disabled
PSM3
Not available
PSM0 values retained
Disabled
Power Mode
PSM0
State After Hardware Reset
State After Software Reset
1
Setting for all registers except the LPOILVL and CONFIG2 registers.
Rev. A | Page 21 of 104
Current mean absolute values are
computed and the results are stored
in the AIMAV, BIMAV, and CIMAV
registers. The I2C or SPI serial port is
enabled with limited functionality.
Compares phase currents against the
threshold set in LPOILVL. Triggers
IRQ0or IRQ1 pins accordingly. The
serial ports are not available.
Internal circuits shut down and the
serial ports are not available.
ADE7880
Data Sheet
Table 11. Recommended Actions When Changing Power Modes
Initial Power
Mode
PSM0
Before Setting Next
Power Mode
Stop DSP by setting the
Run register = 0x0000
PSM1
Disable HSDC by clearing
Bit 6 (HSDCEN) to 0 in the
CONFIG register
Mask interrupts by setting
MASK0 = 0x0 and
MASK1 = 0x0
Erase interrupt status flags
in the STATUS0 and STATUS1
registers
No action necessary
PSM2
No action necessary
PSM3
No action necessary
Next Power Mode
PSM1
PSM2
Current mean absolute
Wait until the IRQ0
values (mav) computed
or IRQ1 pin is
immediately
triggered
accordingly
xIMAV registers can be
accessed immediately
PSM0
Wait until the IRQ1 pin
is triggered low
Poll the STATUS1
register until Bit 15
(RSTDONE) is set to 1
Wait until the IRQ1 pin
is triggered low
Poll the STATUS1
register until Bit 15
(RSTDONE) is set to 1
Wait until the IRQ1 pin
is triggered low
Poll the STATUS1
register until Bit 15
(RSTDONE) is set to 1
Wait until the IRQ0
or IRQ1 pin is
triggered
accordingly
Wait until the IRQ1 pin
triggered low
Current mean absolute
values compute at this
moment
xIMAV registers may be
accessed from this
moment
Wait until the IRQ1 pin is
triggered low
Current mav circuit
begins computations at
this time
xIMAV registers can be
accessed from this
moment
Rev. A | Page 22 of 104
PSM3
No action
necessary
No action
necessary
No action
necessary
Wait until the IRQ0
or IRQ1 pin is
triggered
accordingly
Data Sheet
ADE7880
POWER-UP PROCEDURE
3.3V – 10%
2.0V ± 10%
ADE7880
PSM0 READY
0V
ADE7880
POWERED UP
POR TIMER
TURNED ON
40ms
MICROPROCESSOR
MAKES THE
ADE7880
MICROPROCESSOR RSTDONE CHOICE BETWEEN
INTERRUPT I2C AND SPI
ENTER PSM3
SETS ADE7880
TRIGGERED
IN PSM0
10193-009
26ms
Figure 34. Power-Up Procedure
The ADE7880 contains an on-chip power supply monitor that
supervises the power supply (VDD). At power-up, until VDD
reaches 2 V ± 10%, the chip is in an inactive state. As VDD
crosses this threshold, the power supply monitor keeps the chip
in this inactive state for an additional 26 ms, allowing VDD to
achieve 3.3 V − 10%, the minimum recommended supply
voltage. Because the PM0 and PM1 pins have internal pull-up
resistors and the external microprocessor keeps them high, the
ADE7880 always powers up in sleep mode (PSM3). Then, an
external circuit (that is, a microprocessor) sets the PM1 pin to a
low level, allowing the ADE7880 to enter normal mode (PSM0).
The passage from PSM3 mode, in which most of the internal
circuitry is turned off, to PSM0 mode, in which all functionality
is enabled, is accomplished in less than 40 ms (see Figure 34 for
details).
If PSM0 mode is the only desired power mode, the PM1 pin
may be set low permanently, using a direct connection to
ground. The PM0 pin may be left open because the internal pull
up resistor ensures its state is high. At power up, the ADE7880
briefly passes through PSM3 mode and then enters PSM0.
When the ADE7880 enters PSM0 mode, the I2C port is the
active serial port. If the SPI port is used, then the SS/HSA pin
must be toggled three times, high to low. This action selects the
SPI port for further use. If I2C is the active serial port, Bit 1
(I2C_LOCK) of the CONFIG2 register must be set to 1 to lock
it in. From this moment, the ADE7880 ignores spurious toggling
of the SS/HSA pin, and an eventual switch to use the SPI port is
no longer possible. Likewise, if SPI is the active serial port, any
write to the CONFIG2 register locks the port, at which time a
switch to use the I2C port is no longer possible. Only a powerdown or by setting the RESET pin low can the ADE7880 be
reset to use the I2C port. Once locked, the serial port choice is
maintained when the ADE7880 changes PSMx power modes.
The ADE7880 signals the end of the transition period by triggering
the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in
the STATUS1 register to 1. This bit is 0 during the transition
period and becomes 1 when the transition ends. The status bit is
cleared and the IRQ1 pin is returned high by writing the STATUS1
register with the corresponding bit set to 1. Because the RSTDONE
is an unmaskable interrupt, Bit 15 (RSTDONE) in the STATUS1
register must be cancelled for the IRQ1 pin to return high. It is
recommended to wait until the IRQ1 pin goes low before accessing
the STATUS1 register to test the state of the RSTDONE bit. At
this point, as a good programming practice, it is also recommended
to cancel all other status flags in the STATUS1 and STATUS0
registers by writing the corresponding bits with 1.
Initially, the DSP is in idle mode, which means it does not
execute any instruction. This is the moment to initialize all
ADE7880 registers. The last register in the queue must be
written three times to ensure the register has been initialized.
Then write 0x0001 into the Run register to start the DSP (see
the Digital Signal Processor section for details on the Run
register).
If the supply voltage, VDD, drops lower than 2 V ± 10%,
the ADE7880 enters an inactive state, which means that no
measurements or computations are executed.
Immediately after entering PSM0, the ADE7880 sets all registers
to their default values, including the CONFIG2 and LPOILVL
registers.
Rev. A | Page 23 of 104
ADE7880
Data Sheet
HARDWARE RESET
SOFTWARE RESET FUNCTIONALITY
The ADE7880 has a RESET pin. If the ADE7880 is in PSM0
mode and the RESET pin is set low, then the ADE7880 enters
the hardware reset state. The ADE7880 must be in PSM0 mode
for a hardware reset to be considered. Setting the RESET pin
low while the ADE7880 is in PSM1, PSM2, and PSM3 modes
does not have any effect.
Bit 7 (SWRST) in the CONFIG register manages the software
reset functionality in PSM0 mode. The default value of this bit is 0.
If this bit is set to 1, then the ADE7880 enters the software reset
state. In this state, almost all internal registers are set to their
default values. In addition, the choice of which serial port, I2C or
SPI, is in use remains unchanged if the lock-in procedure has
been executed previously (see the Serial Interfaces section for
details). The registers that maintain their values despite the
SWRST bit being set to 1 are the CONFIG2 and LPOILVL
registers. When the software reset ends, Bit 7 (SWRST) in the
CONFIG register is cleared to 0, the IRQ1 interrupt pin is set
low, and Bit 15 (RSTDONE) in the STATUS1 register is set to 1.
This bit is 0 during the transition period and becomes 1 when
the transition ends. The status bit is cleared and the IRQ1 pin is
set back high by writing to the STATUS1 register with the
corresponding bit set to 1.
If the ADE7880 is in PSM0 mode and the RESET pin is toggled
from high to low and then back to high after at least 10 μs, all the
registers are set to their default values, including the CONFIG2 and
LPOILVL registers. The ADE7880 signals the end of the transition
period by triggering the IRQ1 interrupt pin low and setting Bit 15
(RSTDONE) in the STATUS1 register to 1. This bit is 0 during
the transition period and becomes 1 when the transition ends.
The status bit is cleared and the IRQ1 pin is returned high by
writing to the STATUS1 register with the corresponding bit set
to 1.
After a hardware reset, the DSP is in idle mode, which means it
does not execute any instruction.
Because the I2C port is the default serial port of the ADE7880, it
becomes active after a reset state. If SPI is the port used by the
external microprocessor, the procedure to enable it must be
repeated immediately after the RESET pin is toggled back to
high (see the Serial Interfaces section for details).
After a software reset ends, the DSP is in idle mode, which
means it does not execute any instruction. As a good programming
practice, it is recommended to initialize all the ADE7880 registers
and then write 0x0001 into the Run register to start the DSP
(see the Digital Signal Processor section for details on the Run
register).
Software reset functionality is not available in PSM1, PSM2, or
PSM3 mode.
At this point, it is recommended to initialize all of the ADE7880
registers and then write 0x0001 into the Run register to start the
DSP. See the Digital Signal Processor section for details on the
Run register.
Rev. A | Page 24 of 104
Data Sheet
ADE7880
THEORY OF OPERATION
DIFFERENTIAL INPUT
V1 + V2 = 500mV MAX PEAK
ANALOG INPUTS
COMMON MODE
VCM = ±25mV MAX
V1 + V2
+500mV
V1
IAP, IBP,
ICP, OR INP
V2
IAN, IBN,
ICN, OR INN
VCM
–500mV
10193-010
VCM
Figure 35. Maximum Input Level, Current Channels, Gain = 1
All inputs have a programmable gain amplifier (PGA) with a
possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and
IC inputs is set in Bits[2:0] (PGA1[2:0]) of the Gain register.
The gain of the IN input is set in Bits[5:3] (PGA2[2:0]) of the
Gain register; thus, a different gain from the IA, IB, or IC inputs
is possible. See Table 43for details on the Gain register.
The voltage channel has three single-ended voltage inputs: VAP,
VBP, and VCP. These single-ended voltage inputs have a maximum
input voltage of ±0.5 V with respect to VN. The maximum
signal level on analog inputs for VxP and VN is also ±0.5 V
with respect to AGND. The maximum common-mode signal
allowed on the inputs is ±25 mV. Figure 36 presents a schematic
of the voltage channels inputs and their relation to the maximum
common-mode voltage.
GAIN
SELECTION
IxP, VyP
VIN
K × VIN
NOTES
1. x = A, B, C, N
y = A, B, C.
10193-012
IxN, VN
Figure 36. Maximum Input Level, Voltage Channels, Gain = 1
All inputs have a programmable gain with a possible gain
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]
(PGA3[2:0]) in the Gain register (see Table 43).
V1
VAP, VBP,
OR VCP
VCM
VCM
–500mV
VN
Figure 37. PGA in Current and Voltage Channels
ANALOG-TO-DIGITAL CONVERSION
The ADE7880 has seven sigma-delta (Σ-Δ) analog-to-digital
converters (ADCs). In PSM0 mode, all ADCs are active. In
PSM1 mode, only the ADCs that measure the Phase A, Phase B,
and Phase C currents are active. The ADCs that measure the
neutral current and the A, B, and C phase voltages are turned
off. In PSM2 and PSM3 modes, the ADCs are powered down to
minimize power consumption.
For simplicity, the block diagram in Figure 38 shows a firstorder Σ-Δ ADC. The converter is composed of the Σ-Δ modulator
and the digital low-pass filter.
CLKIN/16
ANALOG
LOW-PASS FILTER
R
INTEGRATOR
+
C
+
–
VREF
LATCHED
COMPARATOR
–
.....10100101.....
1-BIT DAC
DIGITAL
LOW-PASS
FILTER
24
10193-013
DIFFERENTIAL INPUT
V1 + V2 = 500mV MAX PEAK
+500mV
10193-011
The maximum signal level on analog inputs for the IxP/IxN
pair is also ±0.5 V with respect to AGND. The maximum
common-mode signal allowed on the inputs is ±25 mV. Figure 35
presents a schematic of the input for the current channels and
their relation to the maximum common-mode voltage.
COMMON MODE
VCM = ±25mV MAX
V1
The ADE7880 has seven analog inputs forming current and
voltage channels. The current channels consist of four pairs of
fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP
and ICN, and INP and INN. These voltage input pairs have a
maximum differential signal of ±0.5 V.
Figure 38. First-Order Σ-∆ ADC
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7880, the sampling clock is equal to 1.024 MHz
(CLKIN/16). The 1-bit DAC in the feedback loop is driven by
the serial data stream. The DAC output is subtracted from the
input signal. If the loop gain is high enough, the average value
of the DAC output (and, therefore, the bit stream) can approach
that of the input signal level. For any given input value in a
single sampling interval, the data from the 1-bit ADC is
virtually meaningless. Only when a large number of samples are
averaged is a meaningful result obtained. This averaging is
carried out in the second part of the ADC, the digital low-pass
filter. By averaging a large number of bits from the modulator,
the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
Figure 37 shows how the gain selection from the Gain register
works in both current and voltage channels.
Rev. A | Page 25 of 104
ADE7880
Data Sheet
sampling frequency, that is, 1.024 MHz, move into the band of
interest for metering, that is, 40 Hz to 3.3 kHz. To attenuate the
high frequency (near 1.024 MHz) noise and prevent the distortion
of the band of interest, a low-pass filter (LPF) must be introduced.
For conventional current sensors, it is recommended to use one
RC filter with a corner frequency of 5 kHz for the attenuation to
be sufficiently high at the sampling frequency of 1.024 MHz.
The 20 dB per decade attenuation of this filter is usually
sufficient to eliminate the effects of aliasing for conventional
current sensors. However, for a di/dt sensor such as a Rogowski
coil, the sensor has a 20 dB per decade gain. This neutralizes the
20 dB per decade attenuation produced by the LPF. Therefore,
when using a di/dt sensor, take care to offset the 20 dB per
decade gain. One simple approach is to cascade one additional
RC filter, thereby producing a −40 dB per decade attenuation.
ALIASING EFFECTS
0
ANTIALIAS FILTER
(RC)
512
FREQUENCY (kHz)
ADC Transfer Function
1024
HIGH RESOLUTION
OUTPUT FROM
DIGITAL LPF
SIGNAL
3.3 4
512
FREQUENCY (kHz)
1024
10193-014
NOISE
0
1024
Figure 40. Aliasing Effects
NOISE
3.3 4
512
IMAGE
FREQUENCIES
SHAPED NOISE
SAMPLING
FREQUENCY
0
4
FREQUENCY (kHz)
DIGITAL FILTER
SIGNAL
3.3
SAMPLING
FREQUENCY
10193-015
The Σ-Δ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The
first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than
the bandwidth of interest. For example, the sampling rate in
the ADE7880 is 1.024 MHz, and the bandwidth of interest is
40 Hz to 3.3 kHz. Oversampling has the effect of spreading the
quantization noise (noise due to sampling) over a wider
bandwidth. With the noise spread more thinly over a wider
bandwidth, the quantization noise in the band of interest is
lowered, as shown in Figure 39. However, oversampling alone is
not efficient enough to improve the signal-to-noise ratio (SNR)
in the band of interest. For example, an oversampling factor of 4 is
required just to increase the SNR by a mere 6 dB (1 bit). To keep
the oversampling ratio at a reasonable level, it is possible to
shape the quantization noise so that the majority of the noise
lies at the higher frequencies. In the Σ-Δ modulator, the noise is
shaped by the integrator, which has a high-pass-type response
for the quantization noise. This is the second technique used to
achieve high resolution. The result is that most of the noise is at
the higher frequencies where it can be removed by the digital
low-pass filter. This noise shaping is shown in Figure 39.
Figure 39. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
Antialiasing Filter
Figure 38 also shows an analog low-pass filter (RC) on the input
to the ADC. This filter is placed outside the ADE7880, and its role
is to prevent aliasing. Aliasing is an artifact of all sampled systems
as shown in Figure 40. Aliasing means that frequency components
in the input signal to the ADC, which are higher than half the
sampling rate of the ADC, appear in the sampled signal at a
frequency below half the sampling rate. Frequency components
above half the sampling frequency (also known as the Nyquist
frequency, that is, 512 kHz) are imaged or folded back down
below 512 kHz. This happens with all ADCs regardless of the
architecture. In the example shown, only frequencies near the
All ADCs in the ADE7880 are designed to produce the same
24-bit signed output code for the same input signal level. With a
full-scale input signal of 0.5 V and an internal reference of 1.2 V,
the ADC output code is nominally 5,326,737 (0x514791) and
usually varies for each ADE7880 around this value. The code
from the ADC can vary between 0x800000 (−8,388,608) and
0x7FFFFF (+8,388,607); this is equivalent to an input signal
level of ±0.787 V. However, for specified performance, do not
exceed the nominal range of ±0.5 V; ADC performance is
guaranteed only for input signals lower than ±0.5 V.
CURRENT CHANNEL ADC
Figure 41 shows the ADC and signal processing path for Input
IA of the current channels (it is the same for IB and IC). The
ADC outputs are signed twos complement 24-bit data-words
and are available at a rate of 8 kSPS (thousand samples per
second). With the specified full-scale analog input signal
of ±0.5V, the ADC produces its maximum output code value.
Figure 41 shows a full-scale voltage signal applied to the differential inputs (IAP and IAN). The ADC output swings between
−5,326,737 (0xAEB86F) and +5,326,737 (0x514791). Note that
these are nominal values and every ADE7880 varies around
these values. The input, IN, corresponds to the neutral current
of a 3-phase system. If no neutral line is present, connect this
input to AGND. The datapath of the neutral current is similar
to the path of the phase currents as shown in Figure 42.
Rev. A | Page 26 of 104
Data Sheet
ADE7880
ZX SIGNAL
DATA RANGE
ZX DETECTION
LPF1
0x514791 =
+5,326,737
CURRENT PEAK,
OVERCURRENT
DETECT
0V
PGA1 BITS
REFERENCE
GAIN[2:0]
×1, ×2, ×4, ×8, ×16
AIGAIN[23:0]
HPFEN BIT
CONFIG3[0]
IAP
VIN
PGA1
CURRENT RMS (IRMS)
CALCULATION
INTEN BIT
CONFIG[0]
DSP
ADC
IAWV WAVEFORM
SAMPLE REGISTER
DIGITAL
INTEGRATOR
0xAEB86F =
–5,326,737
TOTAL/FUNDAMENTAL
ACTIVE AND REACTIVE
POWER CALCULATION
HPF
IAN
CURRENT CHANNEL
DATA RANGE AFTER
INTEGRATION
CURRENT CHANNEL
DATA RANGE
+0.5V/GAIN
0x514791 =
+5,326,737
0x5A7540 =
+5,928,256
0V
0V
0V
–0.5V/GAIN
ANALOG INPUT RANGE
0xAEB86F =
–5,326,737
10193-016
VIN
0xA58AC0 =
–5,928,256
ANALOG OUTPUT RANGE
Figure 41. Current Channel Signal Path
ININTEN BIT
CONFIG3[3]
NIGAIN[23:0]
HPFEN BIT
CONFIG3[0]
IAP
VIN
PGA2
ADC
CURRENT RMS (IRMS)
CALCULATION
DIGITAL
INTEGRATOR
INWV WAVEFORM
SAMPLE REGISTER
HPF
IAN
10193-017
DSP
PGA2 BITS
REFERENCE
GAIN[5:3]
×1, ×2, ×4, ×8, ×16
Figure 42. Neutral Current Signal Path
28 27
24 23
0000
There is a multiplier in the signal path of each phase and
neutral current. The current waveform can be changed by
±100% by writing a corresponding twos complement number to
the 24-bit signed current waveform gain registers (AIGAIN,
BIGAIN, CIGAIN, and NIGAIN). For example, if 0x400000 is
written to those registers, the ADC output is scaled up by 50%.
To scale the input by −50%, write 0xC00000 to the registers.
Equation 4 describes mathematically the function of the current
waveform gain registers.
Current Waveform =
⎛ Content of Current Gain Register ⎞
ADC Output × ⎜⎜1 +
⎟⎟
2 23
⎠
⎝
(4)
Changing the content of the AIGAIN, BIGAIN, CIGAIN, or
INGAIN registers affects all calculations based on its current;
that is, it affects the corresponding phase active/reactive/
apparent energy and current rms calculation. In addition,
waveform samples scale accordingly.
0
24-BIT NUMBER
BITS[27:24] ARE
EQUAL TO BIT 23
BIT 23 IS A SIGN BIT
10193-018
31
Current Waveform Gain Registers
Figure 43. 24-Bit xIGAIN Transmitted as 32-Bit Words
Current Channel HPF
The ADC outputs can contain a dc offset. This offset can create
errors in power and rms calculations. High-pass filters (HPFs)
are placed in the signal path of the phase and neutral currents
and of the phase voltages. If enabled, the HPF eliminates any dc
offset on the current channel. All filters are implemented in the
DSP and, by default, they are all enabled: Bit 0 (HPFEN) of the
CONFIG3[7:0] register is set to 1. All filters are disabled by
setting Bit 0 (HPFEN) to 0.
Note that the serial ports of the ADE7880 work on 32-, 16-, or
8-bit words, and the DSP works on 28 bits. The 24-bit AIGAIN,
BIGAIN, CIGAIN, and NIGAIN registers are accessed as 32-bit
registers with the four most significant bits (MSBs) padded with
0s and sign extended to 28 bits. See Figure 43 for details.
Rev. A | Page 27 of 104
ADE7880
Data Sheet
The waveform samples of the current channel are taken at the
output of HPF and stored in the 24-bit signed registers, IAWV,
IBWV, ICWV, and INWV at a rate of 8 kSPS. All power and rms
calculations remain uninterrupted during this process. Bit 17
(DREADY) in the STATUS0 register is set when the IAWV, IBWV,
ICWV, and INWV registers are available to be read using the I2C
or SPI serial port. Setting Bit 17 (DREADY) in the MASK0
register enables an interrupt to be set when the DREADY flag is
set. See the Digital Signal Processor section for more details on
Bit DREADY.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
When the IAWV, IBWV, ICWV, and INWV 24-bit signed
registers are read from the ADE7880, they are transmitted sign
extended to 32 bits. See Figure 44 for details.
24 23 22
0
BITS[31:24] ARE
EQUAL TO BIT 23
BIT 23 IS A SIGN BIT
10193-019
24-BIT SIGNED NUMBER
Figure 44. 24-Bit IxWV Register Transmitted as 32-Bit Signed Word
The ADE7880 contains a high speed data capture (HSDC) port
that is specially designed to provide fast access to the waveform
sample registers. See the HSDC Interface section for more details.
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
The di/dt sensor detects changes in the magnetic field caused by
the ac current. Figure 45 shows the principle of a di/dt current
sensor.
Figure 46 and Figure 47 show the magnitude and phase
response of the digital integrator.
Note that the integrator has a −20 dB/dec attenuation and
approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. However, the di/dt
sensor has a 20 dB/dec gain associated with it and generates significant high frequency noise. At least a second order antialiasing
filter is needed to avoid noise aliasing back in the band of
interest when the ADC is sampling (see the Antialiasing Filter
section).
50
0
–50
0.01
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
1
10
FREQUENCY (Hz)
100
1000
PHASE (Degrees)
0
10193-020
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
0.1
–100
Figure 45. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a conductor
loop generate an electromotive force (EMF) between the two
ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the
di/dt current sensor is determined by the mutual inductance
between the current carrying conductor and the di/dt sensor.
–50
0
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
10193-021
31
allows for using a different current sensor to measure the neutral
current (for example a current transformer) from the current
sensors used to measure the phase currents (for example di/dt
sensors). The digital integrators are managed by Bit 0 (INTEN) of
the CONFIG register and by Bit 3 (ININTEN) of the CONFIG3
register. Bit 0 (INTEN) of the CONFIG register manages the
integrators in the phase current channels. Bit 3 (ININTEN) of the
CONFIG3 register manages the integrator in the neutral current
channel. When the INTEN bit is 0 (default), all integrators in the
phase current channels are disabled. When INTEN bit is 1, the
integrators in the phase currents datapaths are enabled. When the
ININTEN bit is 0 (default), the integrator in the neutral current
channel is disabled. When the ININTEN bit is 1, the integrator in
the neutral current channel is enabled.
MAGNITUDE (dB)
Current Channel Sampling
Figure 46. Combined Gain and Phase Response of the
Digital Integrator
The DICOEFF 24-bit signed register is used in the digital
integrator algorithm. At power-up or after a reset, its value is
0x000000. Before turning on the integrator, this register must be
initialized with 0xFFF8000. DICOEFF is not used when the
integrator is turned off and can remain at 0x000000 in that case.
Due to the di/dt sensor, the current signal needs to be filtered
before it can be used for power measurement. On each phase and
neutral current datapath, there are built-in digital integrators to
recover the current signal from the di/dt sensor. The digital
integrators placed on the phase currents data paths are independent
of the digital integrator placed in the neutral current data path. This
Rev. A | Page 28 of 104
Data Sheet
ADE7880
signed register is accessed as a 32-bit register with four MSBs
padded with 0s and sign extended to 28 bits, which practically
means it is transmitted equal to 0x0FFF8000.
–20
–25
–30
30
35
40
45
50
55
FREQUENCY (Hz)
60
65
When the digital integrator is switched off, the ADE7880 can
be used directly with a conventional current sensor, such as
a current transformer (CT).
70
VOLTAGE CHANNEL ADC
Figure 48 shows the ADC and signal processing chain for
Input VA in the voltage channel. The VB and VC channels
have similar processing chains. The ADC outputs are signed
twos complement 24-bit words and are available at a rate of
8 kSPS. With the specified full-scale analog input signal of
±0.5 V, the ADC produces its maximum output code value.
Figure 48 shows a full-scale voltage signal being applied to the
differential inputs (VA and VN). The ADC output swings
between −5,326,737 (0xAEB86F) and +5,326,737 (0x514791).
Note these are nominal values and every ADE7880 varies
around these values.
–89.97
–89.98
–89.99
30
35
40
45
50
55
60
65
70
FREQUENCY (Hz)
10193-022
PHASE (Degrees)
–89.96
Figure 47. Combined Gain and Phase Response of the
Digital Integrator (40 Hz to 70 Hz)
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to the registers shown in Figure 43, the DICOEFF 24-bit
VOLTAGE PEAK,
OVERVOLTAGE,
SAG DETECT
CURRENT RMS (VRMS)
CALCULATION
DSP
PGA3 BITS
GAIN[8:6]
×1, ×2, ×4, ×8, ×16
REFERENCE
HPFEN BIT
AVGAIN[23:0] CONFIG3[0]
VAP
VIN
PGA3
ADC
HPF
VAWV WAVEFORM
SAMPLE REGISTER
TOTAL/FUNDAMENTAL
ACTIVE AND REACTIVE
POWER CALCULATION
VN
VIN
VOLTAGE CHANNEL
DATA RANGE
+0.5V/GAIN
0x514791 =
+5,326,737
0V
0V
ZX DETECTION
LPF1
ZX SIGNAL
DATA RANGE
–0.5V/GAIN
ANALOG INPUT RANGE
0xAEB86F =
–5,326,737
0x514791 =
+5,326,737
ANALOG OUTPUT RANGE
0V
0xAEB86F =
–5,326,737
Figure 48. Voltage Channel Datapath
Rev. A | Page 29 of 104
10193-023
MAGNITUDE (dB)
–15
ADE7880
Data Sheet
Voltage Waveform Gain Registers
CHANGING PHASE VOLTAGE DATA PATH
There is a multiplier in the signal path of each phase voltage.
The voltage waveform can be changed by ±100% by writing
a corresponding twos complement number to the 24-bit signed
voltage waveform gain registers (AVGAIN, BVGAIN, and
CVGAIN). For example, if 0x400000 is written to those registers,
the ADC output is scaled up by 50%. To scale the input by −50%,
write 0xC00000 to the registers. Equation 5 describes mathematically the function of the current waveform gain registers.
The ADE7880 can direct one phase voltage input to the
computational data path of another phase. For example, Phase A
voltage can be introduced in the Phase B computational data path,
which means all powers computed by the ADE7880 in Phase B
are based on Phase A voltage and Phase B current.
(5)
Changing the content of the AVGAIN, BVGAIN, and CVGAIN
registers affects all calculations based on its voltage; that is, it
affects the corresponding phase active/reactive/apparent energy
and voltage rms calculation. In addition, waveform samples are
scaled accordingly.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words,
and the DSP works on 28 bits. As presented in Figure 43, the
AVGAIN, BVGAIN, and CVGAIN registers are accessed as
32-bit registers with four MSBs padded with 0s and sign
extended to 28 bits.
Voltage Channel HPF
As explained in the Current Channel HPF section, the ADC
outputs can contain a dc offset that can create errors in power
and rms calculations. HPFs are placed in the signal path of the
phase voltages, similar to the ones in the current channels. Bit 0
(HPFEN) of CONFIG3 register can enable or disable the filters.
See the Current Channel HPF section for more details.
Bits[11:10] (VTOIB[1:0]) of the CONFIG register manage the
Phase B voltage measured at the VBP pin. If VTOIB[1:0] = 00
(default value), the voltage is directed to the Phase B computational data path. If VTOIB[1:0] = 01, the voltage is directed to
the Phase C path. If VTOIB[1:0] = 10, the voltage is directed to
the Phase A path. If VTOIB[1:0] = 11, the ADE7880 behaves
as if VTOIB[1:0] = 00.
Bits[13:12] (VTOIC[1:0]) of the CONFIG register manage the
Phase C voltage measured at the VCP pin. If VTOIC[1:0] = 00
(default value), the voltage is directed to Phase C computational
data path, if VTOIC[1:0] = 01, the voltage is directed to the
Phase A path. If VTOIC[1:0] = 10, the voltage is directed to the
Phase B path. If VTOIC[1:0] = 11, the ADE7880 behaves as if
VTOIC[1:0] = 00.
IA
APHCAL
PHASE A
COMPUTATIONAL
DATAPATH
VTOIA[1:0] = 01,
PHASE A VOLTAGE
DIRECTED
TO PHASE B
VA
Voltage Channel Sampling
IB
The waveform samples of the voltage channel are taken at the
output of HPF and stored into VAWV, VBWV, and VCWV 24bit signed registers at a rate of 8 kSPS. All power and rms
calculations remain uninterrupted during this process. Bit 17
(DREADY) in the STATUS0 register is set when the VAWV,
VBWV, and VCWV registers are available to be read using the
I2C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0
register enables an interrupt to be set when the DREADY flag is
set. See the Digital Signal Processor section for more details on
Bit DREADY.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to registers presented in Figure 44, the VAWV, VBWV,
and VCWV 24-bit signed registers are transmitted sign
extended to 32 bits.
BPHCAL
PHASE B
COMPUTATIONAL
DATAPATH
VTOIB[1:0] = 01,
PHASE B VOLTAGE
DIRECTED
TO PHASE C
VB
IC
CPHCAL
VC
PHASE C
COMPUTATIONAL
DATAPATH
VTOIC[1:0] = 01,
PHASE C VOLTAGE
DIRECTED
TO PHASE A
10193-024
Voltage Waveform =
⎛ Content of VoltageGain Register ⎞
ADC Output × ⎜⎜1 +
⎟⎟
223
⎠
⎝
Bits[9:8] (VTOIA[1:0]) of the CONFIG register manage the
Phase A voltage measured at the VAP pin. If VTOIA[1:0] = 00
(default value), the voltage is directed to the Phase A computational data path. If VTOIA[1:0] = 01, the voltage is directed to
the Phase B path. If VTOIA[1:0] = 10, the voltage is directed to the
Phase C path. If VTOIA[1:0] = 11, the ADE7880 behaves as if
VTOIA[1:0] = 00.
Figure 49. Phase Voltages Used in Different Datapaths
Figure 49 presents the case in which the Phase A voltage is used
in the Phase B data path, the Phase B voltage is used in the Phase C
data path, and the Phase C voltage is used in the Phase A data path.
The ADE7880 contains an HSDC port especially designed to
provide fast access to the waveform sample registers. See the
HSDC Interface section for more details.
Rev. A | Page 30 of 104
Data Sheet
ADE7880
cleared and the IRQ1 pin is set to high by writing to the STATUS1
register with the status bit set to 1.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
The ADE7880 has a zero-crossing (ZX) detection circuit on the
phase current and voltage channels. The neutral current data
path does not contain a zero-crossing detection circuit. Zerocrossing events are used as a time base for various power quality
measurements and in the calibration process.
The output of LPF1 is used to generate zero crossing events.
The low-pass filter is intended to eliminate all harmonics of
50 Hz and 60 Hz systems, and to help identify the zero-crossing
events on the fundamental components of both current and
voltage channels.
The digital filter has a pole at 80 Hz and is clocked at 256 kHz.
As a result, there is a phase lag between the analog input signal
(one of IA, IB, IC, VA, VB, and VC) and the output of LPF1.
The error in ZX detection is 0.0703° for 50 Hz systems (0.0843°
for 60 Hz systems). The phase lag response of LPF1 results in a
time delay of approximately 31.4° or 1.74 ms (at 50 Hz) between
its input and output. The overall delay between the zero crossing
on the analog inputs and ZX detection obtained after LPF1 is
about 39.6° or 2.2 ms (at 50 Hz). The ADC and HPF introduce
the additional delay. The LPF1 cannot be disabled to assure a
good resolution of the ZX detection. Figure 50 shows how the
zero-crossing signal is detected.
PGA
DSP
REFERENCE
HPFEN BIT
GAIN[23:0] CONFIG3[0]
ADC
HPF
IA, IB, IC, IN
OR
VA, VB, VC
If a ZXTOIx or ZXTOVx bit is set in the MASK1 register, the
IRQ1 interrupt pin is driven low when the corresponding status bit
is set to 1. The status bit is cleared and the IRQ1 pin is returned to
high by writing to the STATUS1 register with the status bit set to 1.
The resolution of the ZXOUT register is 62.5 μs (16 kHz clock)
per LSB. Thus, the maximum timeout period for an interrupt is
4.096 sec: 216/16 kHz.
Figure 51 shows the mechanism of the zero-crossing timeout
detection when the voltage or the current signal stays at a fixed
dc level for more than 62.5 μs × ZXTOUT μs.
16-BIT INTERNAL
REGISTER VALUE
ZXTOUT
ZX
DETECTION
39.6° OR 2.2ms @ 50Hz
1
0.855
0V
LPF1
Every zero-crossing detection circuit has an associated timeout
register. This register is loaded with the value written into the
16-bit ZXTOUT register and is decremented (1 LSB) every
62.5 μs (16 kHz clock). The register is reset to the ZXTOUT
value every time a zero crossing is detected. The default value of
this register is 0xFFFF. If the timeout register decrements to 0
before a zero crossing is detected, one of Bits[8:3] of the STATUS1
register is set to 1. Bit 3 (ZXTOVA), Bit 4 (ZXTOVB), and Bit 5
(ZXTOVC) in the STATUS1 register refer to Phase A, Phase B,
and Phase C of the voltage channel; Bit 6 (ZXTOIA), Bit 7
(ZXTOIB), and Bit 8 (ZXTOIC) in the STATUS1 register refer
to Phase A, Phase B, and Phase C of the current channel.
ZX
ZX
ZX
VOLTAGE
OR
CURRENT
SIGNAL
ZX
10193-025
IA, IB, IC,
OR
VA, VB, VC
Zero-Crossing Timeout
LPF1 OUTPUT
0V
Figure 50. Zero-Crossing Detection on Voltage and Current Channels
The ADE7880 contains six zero-crossing detection circuits, one
for each phase voltage and current channel. Each circuit drives
one flag in the STATUS1 register. If a circuit placed in the Phase
A voltage channel detects one zero-crossing event, Bit 9 (ZXVA)
in the STATUS1 register is set to 1.
Similarly, the Phase B voltage circuit drives Bit 10 (ZXVB), the
Phase C voltage circuit drives Bit 11 (ZXVC), and circuits placed
in the current channel drive Bit 12 (ZXIA), Bit 13 (ZXIB), and
Bit 14 (ZXIC) in the STATUS1 register. If a ZX detection bit is
set in the MASK1 register, the IRQ1 interrupt pin is driven low
and the corresponding status flag is set to 1. The status bit is
ZXZOxy FLAG IN
STATUS1[31:0], x = V, A
y = A, B, C
IRQ1 INTERRUPT PIN
10193-026
To provide further protection from noise, input signals to the
voltage channel with amplitude lower than 10% of full scale do
not generate zero-crossing events at all. The Current Channel ZX
detection circuit is active for all input signals independent of their
amplitudes.
Figure 51. Zero-Crossing Timeout Detection
Phase Sequence Detection
The ADE7880 has on-chip phase sequence error detection
circuits. This detection works on phase voltages and considers
only the zero crossings determined by their negative-to-positive
transitions. The regular succession of these zero-crossing events is
Phase A followed by Phase B followed by Phase C (see Figure 53).
If the sequence of zero-crossing events is, instead, Phase A followed
by Phase C followed by Phase B, then Bit 19 (SEQERR) in the
STATUS1 register is set.
Rev. A | Page 31 of 104
ADE7880
Data Sheet
The phase sequence error detection circuit is functional only
when the ADE7880 is connected in a 3-phase, 4-wire, three voltage
sensors configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE
register, set to 00). In all other configurations, only two voltage
sensors are used; therefore, it is not recommended to use the
detection circuit. In these cases, use the time intervals between
phase voltages to analyze the phase sequence (see the Time
Interval Between Phases section for details).
Figure 52 presents the case in which Phase A voltage is not
followed by Phase B voltage but by Phase C voltage. Every time
a negative-to-positive zero crossing occurs, Bit 19 (SEQERR) in
the STATUS1 register is set to 1 because such zero crossings on
Phase C, Phase B, or Phase A cannot come after zero crossings
from Phase A, Phase C, or respectively, Phase B zero crossings.
PHASE C
PHASE B
ZX A
ZX B
PHASE C
ZX C
Figure 53. Regular Succession of Phase A, Phase B, and Phase C
When the ANGLESEL[1:0] bits are set to 00, the default value,
the delays between voltages and currents on the same phase are
measured. The delay between Phase A voltage and Phase A
current is stored in the 16-bit unsigned ANGLE0 register (see
Figure 54 for details). In a similar way, the delays between
voltages and currents on Phase B and Phase C are stored in the
ANGLE1 and ANGLE2 registers, respectively.
PHASE A
VOLTAGE
PHASE A
CURRENT
PHASE B
A, B, C PHASE
VOLTAGES AFTER
LPF1
10193-029
PHASE A
PHASE A
10193-028
If Bit 19 (SEQERR) in the MASK1 register is set to 1 and a
phase sequence error event is triggered, the IRQ1 interrupt pin
is driven low. The status bit is cleared and the IRQ1 pin is set
high by writing to the STATUS1 register with the Status Bit 19
(SEQERR) set to 1.
ANGLE0
Figure 54. Delay Between Phase A Voltage and Phase A Current Is
Stored in the ANGLE0 Register
ZX C
When the ANGLESEL[1:0] bits are set to 01, the delays between
phase voltages are measured. The delay between Phase A
voltage and Phase C voltage is stored into the ANGLE0 register.
The delay between Phase B voltage and Phase C voltage is
stored in the ANGLE1 register, and the delay between Phase A
voltage and Phase B voltage is stored in the ANGLE2 register
(see Figure 55 for details).
ZX B
BIT 19 (SEQERR) IN
STATUS1 REGISTER
IRQ1
STATUS1[19] CANCELLED
BY A WRITE TO THE
STATUS1 REGISTER WITH
SEQERR BIT SET
10193-027
STATUS1[19] SET TO 1
Figure 52. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by
Phase C Voltage
Once a phase sequence error has been detected, the time
measurement between various phase voltages (see the Time
Interval Between Phases section) can help to identify which
phase voltage should be considered with another phase current
in the computational data path. Bits[9:8] (VTOIA[1:0]),
Bits[11:10] (VTOIB[1:0]), and Bits[13:12] (VTOIC[1:0]) in the
CONFIG register can be used to direct one phase voltage to the
data path of another phase. See the Changing Phase Voltage
Data path section for details.
When the ANGLESEL[1:0] bits are set to 10, the delays between
phase currents are measured. Similar to delays between phase
voltages, the delay between Phase A and Phase C currents is
stored into the ANGLE0 register, the delay between Phase B and
Phase C currents is stored in the ANGLE1 register, and the
delay between Phase A and Phase B currents is stored into the
ANGLE2 register (see Figure 55 for details).
PHASE A
Time Interval Between Phases
ANGLE2
The ADE7880 has the capability to measure the time delay
between phase voltages, between phase currents, or between
voltages and currents of the same phase. The negative-to-positive
transitions identified by the zero-crossing detection circuit are
used as start and stop measuring points. Only one set of such
measurements is available at one time, based on Bits[10:9]
(ANGLESEL[1:0]) in the COMPMODE register.
PHASE B
PHASE C
ANGLE1
ANGLE0
10193-030
ZX A
Figure 55. Delays Between Phase Voltages (Currents)
The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit
unsigned registers with 1 LSB corresponding to 3.90625 μs
(256 kHz clock), which means a resolution of 0.0703° (360° ×
50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/
Rev. A | Page 32 of 104
Data Sheet
ADE7880
256 kHz) for 60 Hz systems. The delays between phase voltages
or phase currents are used to characterize how balanced the
load is. The delays between phase voltages and currents are
used to compute the power factor on each phase as shown in
the following Equation 6:
⎡
360o × f LINE ⎤
cosφx = cos ⎢ ANGLEx ×
⎥
256 kHz ⎦
⎣
(6)
in STATUS1 register is set to 1 to indicate the condition and the bit
VSPHASE[0] in the PHSTATUS register is set back to 0.
Bits VSPHASE[1] and VSPHASE[2] relate to the sag events on
Phase B and Phase C in the same way: when Phase B or Phase C
voltage stays below SAGLVL, they are set to 1. When the phase
voltages are above SAGLVL, they are set to 0.
PHASE B VOLTAGE
FULL SCALE
SAGLVL[23:0]
where fLINE = 50 Hz or 60 Hz.
Period Measurement
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period registers
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and
for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The
length of the registers enables the measurement of line frequencies
as low as 3.9 Hz (256 kHz/216). The period registers are stable at
±1 LSB when the line is established and the measurement does
not change.
SAGCYC[7:0] = 0x4
PHASE A VOLTAGE
BIT 16 (SAG) IN
STATUS1[31:0]
(7)
256E3
[ Hz]
PERIOD[15 :0]
(8)
fL =
Phase Voltage Sag Detection
The ADE7880 can be programmed to detect when the absolute
value of any phase voltage drops below or grows above a certain
peak value for a number of half-line cycles. The phase where
this event takes place and the state of the phase voltage relative
to the threshold is identified in Bits[14:12] (VSPHASE[x]) of
the PHSTATUS register. An associated interrupt is triggered
when any phase drops below or grows above a threshold. This
condition is illustrated in Figure 56.
Figure 56 shows Phase A voltage falling below a threshold that
is set in the SAG level register (SAGLVL) for four half-line cycles
(SAGCYC = 4). When Bit 16 (SAG) in the STATUS1 register is set
to 1 to indicate the condition, Bit VSPHASE[0] in the PHSTATUS
register is also set to 1 because the phase A voltage is below
SAGLVL. The microcontroller then writes back STATUS1 register
with Bit 16 (SAG) set to 1 to erase the bit and bring IRQ1 interrupt
pin back high. Then the phase A voltage stays above the SAGLVL
threshold for four half-line cycles (SAGCYC = 4). The Bit 16 (SAG)
STATUS[16] SET TO 1
IRQ1 PIN GOES HIGH
BECAUSE STATUS1[16]
CANCELLED BY A WRITE
TO STATUS[31:0] WITH SAG
BIT SET
IRQ1 PIN
PHSTATUS[12] SET TO 1
BECAUSE PHASE A
VOLTAGE WAS BELOW
SAGLVL FOR SAGCYC
HALF LINE CYCLES
VSPHASE[0] =
PHSTATUS[12]
PHSTATUS[12] CLEARED
TO 0 BECAUSE PHASE A
VOLTAGE WAS ABOVE
SAGLVL FOR SAGCYC
HALF LINE CYCLES
VSPHASE[1] =
PHSTATUS[13]
PHSTATUS[13] SET TO 1
The following equations can be used to compute the line period
and frequency using the period registers:
PERIOD[15:0]
[sec]
TL =
256E3
STATUS1[16] CANCELLED BY
A WRITE TO STATUS1[31:0]
WITH SAG BIT SET
SAGCYC[7:0] = 0x4
10193-031
The ADE7880 provides the period measurement of the line in
the voltage channel. The period of each phase voltage is
measured and stored in three different registers, APERIOD,
BPERIOD, and CPERIOD. The period registers are 16-bit
unsigned registers and update every line period. Because of the
LPF1 filter (see Figure 50), a settling time of 30 ms to 40 ms is
associated with this filter before the measurement is stable.
Figure 56. SAG Detection
The SAGCYC register represents the number of half-line cycles
the phase voltage must remain below or above the level indicated
in the SAGLVL register to trigger a SAG interrupt ; 0 is not a
valid number for SAGCYC. For example, when the SAG cycle
(SAGCYC[7:0]) contains 0x07, the SAG flag in the STATUS1
register is set at the end of the seventh half line cycle for which
the line voltage falls below the threshold. If Bit 16 (SAG) in
MASK1 is set, the IRQ1 interrupt pin is driven low in case of a
SAG event in the same moment the Status Bit 16 (SAG) in
STATUS1 register is set to 1. The SAG status bit in the STATUS1
register and the IRQ1 pin is returned to high by writing to the
STATUS1 register with the status bit set to 1.
When the Phase B voltage falls below the indicated threshold
into the SAGLVL register for two line cycles, Bit VSPHASE[1]
in the PHSTATUS register is set to 1 (see Figure 56). Simultaneously, Bit 16 (SAG) in the STATUS1 register is set to 1 to indicate
the condition.
Note that the internal zero-crossing counter is always active. By
setting the SAGLVL register, the first SAG detection result is,
therefore, not executed across a full SAGCYC period. Writing to
the SAGCYC register when the SAGLVL register is already initialized resets the zero-crossing counter, thus ensuring that the first
SAG detection result is obtained across a full SAGCYC period.
Rev. A | Page 33 of 104
ADE7880
Data Sheet
IPPHASE/VPPHASE BITS
2.
3.
4.
5.
27 26 25 24 23
00000
Enable SAG interrupts in the MASK1 register by setting
Bit 16 (SAG) to 1.
When a SAG event happens, the IRQ1 interrupt pin goes
low and Bit 16 (SAG) in the STATUS1 is set to 1.
The STATUS1 register is read with Bit 16 (SAG) set to 1.
The PHSTATUS register is read, identifying on which
phase or phases a SAG event happened.
The STATUS1 register is written with Bit 16 (SAG) set to 1.
Immediately, the SAG bit is erased.
PEAK DETECTED
ON PHASE C
PEAK DETECTED
ON PHASE A
PEAK DETECTED
ON PHASE B
Figure 58. Composition of IPEAK[31:0] and VPEAK[31:0] Registers
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF FIRST
PEAKCYC PERIOD
END OF FIRST
PEAKCYC = 16 PERIOD
END OF SECOND
PEAKCYC = 16 PERIOD
SAG Level Set
24 23
0000 0000
0
24-BIT NUMBER
PHASE A
CURRENT
BIT 24 OF IPEAK
CLEARED TO 0 AT
THE END OF SECOND
PEAKCYC PERIOD
BIT 24
OF IPEAK
10193-032
The content of the SAGLVL[23:0] SAG level register is compared
to the absolute value of the output from HPF. Writing 5,928,256
(0x5A7540) to the SAGLVL register, puts the SAG detection
level at full scale (see the Voltage Channel ADC section), thus;
the SAG event is triggered continuously. Writing 0x00 or 0x01
puts the SAG detection level at 0, therefore, the SAG event is
never triggered.
31
0
24-BIT UNSIGNED NUMBER
PHASE B
CURRENT
Figure 57. SAGLVL Register Transmitted as a 32-Bit Word
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
The SAGLVL register is accessed as a 32-bit register with eight
MSBs padded with 0s. See Figure 57 for details.
Peak Detection
BIT 25
OF IPEAK
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF
SECOND PEAKCYC PERIOD
BIT 25 OF IPEAK
SET TO 1 AT THE
END OF SECOND
PEAKCYC PERIOD
10193-034
1.
31
10193-033
The recommended procedure to manage SAG events is the
following:
Figure 59. Peak Level Detection
The ADE7880 records the maximum absolute values reached by
the voltage and current channels over a certain number of halfline cycles and stores them into the less significant 24 bits of the
VPEAK and IPEAK 32-bit registers.
The PEAKCYC register contains the number of half-line cycles
used as a time base for the measurement. The circuit uses the
zero-crossing points identified by the zero-crossing detection
circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE register select
the phases upon which the peak measurement is performed. Bit 2
selects Phase A, Bit 3 selects Phase B, and Bit 4 selects Phase C.
Selecting more than one phase to monitor the peak values
decreases proportionally the measurement period indicated in
the PEAKCYC register because zero crossings from more
phases are involved in the process. When a new peak value is
determined, one of Bits[26:24] (IPPHASE[2:0] or VPPHASE[2:0])
in the IPEAK and VPEAK registers is set to 1, identifying the
phase that triggered the peak detection event. For example, if a
peak value has been identified on Phase A current, Bit 24
(IPPHASE[0]) in the IPEAK register is set to 1. If next time a
new peak value is measured on Phase B, Bit 24 (IPPHASE[0])
of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1])
of the IPEAK register is set to 1. Figure 58 shows the
composition of the IPEAK and VPEAK registers.
Figure 59 shows how the ADE7880 records the peak value on the
current channel when measurements on Phase A and Phase B are
enabled (Bit PEAKSEL[2:0] in the MMODE register are 011).
PEAKCYC is set to 16, meaning that the peak measurement
cycle is four line periods. The maximum absolute value of Phase A
is the greatest during the first four line periods (PEAKCYC = 16),
so the maximum absolute value is written into the less significant 24 bits of the IPEAK register, and Bit 24 (IPPHASE[0]) of
the IPEAK register is set to 1 at the end of the period. This bit
remains at 1 for the duration of the second PEAKCYC period of
four line cycles. The maximum absolute value of Phase B is the
greatest during the second PEAKCYC period; therefore, the
maximum absolute value is written into the less significant
24 bits of the IPEAK register, and Bit 25 (IPPHASE[1]) in the
IPEAK register is set to 1 at the end of the period.
At the end of the peak detection period in the current channel,
Bit 23 (PKI) in the STATUS1 register is set to 1. If Bit 23 (PKI)
in the MASK1 register is set, the IRQ1 interrupt pin is driven low
at the end of the PEAKCYC period, and Status Bit 23 (PKI) in
the STATUS1 register is set to 1. In a similar way, at the end of
the peak detection period in the voltage channel, Bit 24 (PKV) in
the STATUS1 register is set to 1. If Bit 24 (PKV) in the MASK1
register is set, the IRQ1 interrupt pin is driven low at the end of
PEAKCYC period and Status Bit 24 (PKV) in the STATUS1
Rev. A | Page 34 of 104
Data Sheet
ADE7880
register is set to 1. To find the phase that triggered the interrupt,
one of either the IPEAK or VPEAK registers is read immediately
after reading the STATUS1 register. Next, the status bits are
cleared, and the IRQ1 pin is set to high by writing to the
STATUS1 register with the status bit set to 1.
Note that the internal zero-crossing counter is always active. By
setting Bits[4:2] (PEAKSEL[2:0]) in the MMODE register, the
first peak detection result is, therefore, not executed across a full
PEAKCYC period. Writing to the PEAKCYC register when the
PEAKSEL[2:0] bits are set resets the zero-crossing counter,
thereby ensuring that the first peak detection result is obtained
across a full PEAKCYC period.
Overvoltage and Overcurrent Detection
The ADE7880 detects when the instantaneous absolute value
measured on the voltage and current channels becomes greater
than the thresholds set in the OVLVL and OILVL 24-bit
unsigned registers. If Bit 18 (OV) in the MASK1 register is set,
the IRQ1 interrupt pin is driven low in case of an overvoltage
event. There are two status flags set when the IRQ1 interrupt
pin is driven low: Bit 18 (OV) in the STATUS1 register and one
of Bits[11:9] (OVPHASE[2:0]) in the PHSTATUS register to
identify the phase that generated the overvoltage. The Status
Bit 18 (OV) in the STATUS1 register and all Bits[11:9]
(OVPHASE[2:0]) in the PHSTATUS register are cleared, and
the IRQ1 pin is set to high by writing to the STATUS1 register
with the status bit set to 1. Figure 60 presents overvoltage
detection in the Phase A voltage.
PHASE A
VOLTAGE CHANNEL
OVERVOLTAGE
DETECTED
OVLVL[23:0]
Whenever the absolute instantaneous value of the voltage goes
above the threshold from the OVLVL register, Bit 18 (OV) in
the STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS
register are set to 1. Bit 18 (OV) of the STATUS1 register and
Bit 9 (OVPHASE[0]) in the PHSTATUS register are cancelled
when the STATUS1 register is written with Bit 18 (OV) set to 1.
The recommended procedure to manage overvoltage events is
the following:
1.
2.
3.
4.
5.
Enable OV interrupts in the MASK1 register by setting
Bit 18 (OV) to 1.
When an overvoltage event happens, the IRQ1 interrupt
pin goes low.
The STATUS1 register is read with Bit 18 (OV) set to 1.
The PHSTATUS register is read, identifying on which
phase or phases an overvoltage event happened.
The STATUS1 register is written with Bit 18 (OV) set to 1.
In this moment, Bit OV is erased and also all Bits[11:9]
(OVPHASE[2:0]) of the PHSTATUS register.
In case of an overcurrent event, if Bit 17 (OI) in the MASK1
register is set, the IRQ1 interrupt pin is driven low. Immediately,
Bit 17 (OI) in the STATUS1 register and one of Bits[5:3]
(OIPHASE[2:0]) in the PHSTATUS register, which identify
the phase that generated the interrupt, are set. To find the
phase that triggered the interrupt, the PHSTATUS register
is read immediately after reading the STATUS1 register. Next,
Status Bit 17 (OI) in the STATUS1 register and Bits[5:3]
(OIPHASE[2:0]) in the PHSTATUS register are cleared and the
IRQ1 pin is set to high by writing to the STATUS1 register with
the status bit set to 1. The process is similar with overvoltage
detection.
Overvoltage and Overcurrent Level Set
The content of the overvoltage (OVLVL), and overcurrent,
(OILVL) 24-bit unsigned registers is compared to the absolute
value of the voltage and current channels. The maximum value of
these registers is the maximum value of the HPF outputs:
+5,326,737 (0x514791). When the OVLVL or OILVL register is
equal to this value, the overvoltage or overcurrent conditions
are never detected. Writing 0x0 to these registers signifies the
overvoltage or overcurrent conditions are continuously
detected, and the corresponding interrupts are permanently
triggered.
BIT 18 (OV) OF
STATUS1
STATUS1[18] AND
PHSTATUS[9]
CANCELLED BY A
WRITE OF STATUS1
WITH OV BIT SET.
10193-035
BIT 9 (OVPHASE)
OF PHSTATUS
Figure 60. Overvoltage Detection
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 57, OILVL and
OVLVL registers are accessed as 32-bit registers with the eight
MSBs padded with 0s.
Rev. A | Page 35 of 104
ADE7880
Data Sheet
In 3-phase systems, the neutral current is equal to the algebraic
sum of the phase currents
IN(t) = IA(t) + IB(t) + IC(t)
If there is a mismatch between these two quantities, then a
tamper situation may have occurred in the system.
The ADE7880 computes the sum of the phase currents adding
the content of the IAWV, IBWV, and ICWV registers, and
storing the result into the ISUM 28-bit signed register: ISUM(t) =
IA(t) + IB(t) + IC(t). ISUM is computed every 125 μs (8 kHz
frequency), the rate at which the current samples are available,
and Bit 17 (DREADY) in the STATUS0 register is used to signal
when the ISUM register can be read. See the Digital Signal
Processor section for more details on Bit DREADY.
To recover ISUM(t) value from the ISUM register, use the
following equation:
I SUM (t ) =
ISUMLVL, the positive threshold used in the process, is a 24-bit
signed register. Because it is used in a comparison with an
absolute value, always set ISUMLVL as a positive number,
somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses
the same scale of the current ADCs outputs, so writing
+5,326,737 (0x514791) to the ISUMLVL register puts the
mismatch detection level at full scale; see the Current Channel
ADC section for details. Writing 0x000000, the default value, or
a negative value, signifies the MISMTCH event is always triggered.
The right value for the application should be written into the
ISUMLVL register after power-up or after a hardware/software
reset to avoid continuously triggering MISMTCH events.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. As presented in Figure 61, ISUM,
the 28-bit signed register, is accessed as a 32-bit register with the
four most significant bits padded with 0s.
31
ISUM[27:0]
× I FS
ADCMAX
where:
ADCMAX = 5,928,256, the ADC output when the input is at full
scale.
IFS is the full-scale ADC phase current.
Note that the ADE7880 also computes the rms of ISUM and
stores it into NIRMS register when Bit 2 (INSEL) in CONFIG3
register is set to 1 (see Current RMS Calculation section for
details).
The ADE7880 computes the difference between the absolute
values of ISUM and the neutral current from the INWV
register, take its absolute value and compare it against the
ISUMLVL threshold.
If
ISUM − INWV ≤ ISUMLVL
,
then it is assumed that the neutral current is equal to the sum
of the phase currents, and the system functions correctly.
If
ISUM − INWV > ISUMLVL
28 27
0000
,
then a tamper situation may have occurred, and Bit 20
(MISMTCH) in the STATUS1 register is set to 1. An interrupt
attached to the flag can be enabled by setting Bit 20
(MISMTCH) in the MASK1 register. If enabled, the IRQ1 pin is
set low when Status Bit MISMTCH is set to 1. The status bit is
cleared and the IRQ1 pin is set back to high by writing to the
STATUS1 register with Bit 20 (MISMTCH) set to 1.
If ISUM − INWV ≤ ISUMLVL , then MISMTCH = 0
If ISUM − INWV > ISUMLVL , then MISMTCH = 1
0
28-BIT SIGNED NUMBER
BIT 27 IS A SIGN BIT
10193-036
Neutral Current Mismatch
Figure 61. The ISUM[27:0] Register is Transmitted As a 32-Bit Word
Similar to the registers presented in Figure 43, the ISUMLVL
register is accessed as a 32-bit register with four most significant
bits padded with 0s and sign extended to 28 bits.
PHASE COMPENSATION
As described in the Current Channel ADC and Voltage Channel
ADC sections, the data path for both current and voltages is the
same. The phase error between current and voltage signals
introduced by the ADE7880 is negligible. However, the ADE7880
must work with transducers that may have inherent phase
errors. For example, a current transformer (CT) with a phase
error of 0.1° to 3° is not uncommon. These phase errors can
vary from part to part, and they must be corrected to perform
accurate power calculations.
The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE7880 provides a
means of digitally calibrating these small phase errors. The
ADE7880 allows a small time delay or time advance to be
introduced into the signal processing chain to compensate for
the small phase errors.
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are 10-bit registers that can vary the time advance
in the voltage channel signal path from −374.0 μs to +61.5 μs.
Negative values written to the PHCAL registers represent a time
advance whereas positive values represent a time delay. One LSB
is equivalent to 0.976 μs of time delay or time advance (clock
rate of 1.024 MHz). With a line frequency of 60 Hz, this gives
a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the
fundamental. This corresponds to a total correction range of
−8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is
Rev. A | Page 36 of 104
Data Sheet
ADE7880
Figure 63 illustrates how the phase compensation is used to
remove x = −1° phase lead in IA of the current channel from the
external current transducer (equivalent of 55.5 μs for 50 Hz
systems). To cancel the lead (1°) in the current channel of
Phase A, a phase lead must be introduced into the corresponding
voltage channel. Using Equation 8, APHCAL is 57 least
significant bits, rounded up from 56.8. The phase lead is
achieved by introducing a time delay of 55.73 μs into the Phase
A current.
−6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/
1.024 MHz).
Given a phase error of x degrees, measured using the phase
voltage as the reference, the corresponding LSBs are computed
dividing x by the phase resolution (0.0211°/LSB for 60 Hz and
0.0176°/LSB for 50 Hz). Results between −383 and +63 only are
acceptable; numbers outside this range are not accepted. If the
current leads the voltage, the result is negative and the absolute
value is written into the PHCAL registers. If the current lags the
voltage, the result is positive and 512 is added to the result
before writing it into xPHCAL.
APHCAL, BPHCAL, or CPHCAL
⎧
⎫
x
,x ≤ 0
⎪
⎪
⎪ phase _ resolution
⎪
=⎨
⎬
x
⎪
+ 512, x > 0 ⎪
⎪ phase _ resolution
⎪
⎩
⎭
15
(9)
10 9
0000 00
0
xPHCAL
Figure 62. xPHCAL Registers Communicated As 16-Bit Registers
IAP
IA
PGA1
ADC
IAN
PHASE
CALIBRATION
APHCAL = 57
VAP
VA
10193-037
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words. As
shown in Figure 62, APHCAL, BPHCAL, and CPHCAL 10-bit
registers are accessed as 16-bit registers with the six MSBs padded
with 0s.
PGA3
ADC
VN
1°
IA
IA
VA
10193-038
VA
PHASE COMPENSATION
ACHIEVED DELAYING
IA BY 56µs
50Hz
Figure 63. Phase Calibration on Voltage Channels
Rev. A | Page 37 of 104
ADE7880
Data Sheet
REFERENCE CIRCUIT
The nominal reference voltage at the REFIN/OUT pin is 1.2 ±
0.075% V. This is the reference voltage used for the ADCs in
the ADE7880. The REFIN/OUT pin can be overdriven by an
external source, for example, an external 1.2 V reference.
The voltage of the ADE7880 reference drifts slightly with
temperature; see the Specifications section for the temperature
coefficient specification (in ppm/°C). The value of the temperature
drift varies from part to part. Because the reference is used for
all ADCs, any x percentage drift in the reference results in a 2×
percentage deviation of the meter accuracy. The reference drift
resulting from temperature changes is usually very small and
typically much smaller than the drift of other components on a
meter. Alternatively, the meter can be calibrated at multiple
temperatures.
If Bit 0 (EXTREFEN) in the CONFIG2 register is cleared to 0 (the
default value), the ADE7880 uses the internal voltage reference.
If the bit is set to 1, the external voltage reference is used. Set the
CONFIG2 register during the PSM0 mode. Its value is maintained
during the PSM1, PSM2, and PSM3 power modes.
DIGITAL SIGNAL PROCESSOR
The ADE7880 contains a fixed function digital signal processor
(DSP) that computes all powers and rms values. It contains
program memory ROM and data memory RAM.
The program used for the power and rms computations is
stored in the program memory ROM and the processor executes
it every 8 kHz. The end of the computations is signaled by
setting Bit 17 (DREADY) to 1 in the STATUS0 register. An
interrupt attached to this flag can be enabled by setting Bit 17
(DREADY) in the MASK0 register. If enabled, the IRQ0 pin is
set low and Status Bit DREADY is set to 1 at the end of the
computations. The status bit is cleared and the IRQ0 pin is set
to high by writing to the STATUS0 register with Bit 17 (DREADY)
set to 1.
The registers used by the DSP are located in the data memory
RAM, at addresses between 0x4380 and 0x43BE. The width of
this memory is 28 bits. A two-stage pipeline is used when write
operations to the data memory RAM are executed. This means
two things: when only one register needs to be initialized, write
it two more times to ensure the value has been written into
RAM. When two or more registers need to be initialized, write
the last register in the queue two more times to ensure the value
has been written into RAM.
As explained in the Power-Up Procedure section, at power-up
or after a hardware or software reset, the DSP is in idle mode.
No instruction is executed. All the registers located in the data
memory RAM are initialized at 0, their default values and they
can be read/written without any restriction. The Run register,
used to start and stop the DSP, is cleared to 0x0000. The Run
register needs to be written with 0x0001 for the DSP to start
code execution. It is recommended to first initialize all ADE7880
registers located in the data memory RAM with their desired
values. Next, write the last register in the queue two additional
times to flush the pipeline and then write the Run register with
0x0001. In this way, the DSP starts the computations from a
desired configuration.
To protect the integrity of the data stored in the data memory
RAM of the DSP (between Address 0x4380 and Address
0x43BE), a write protection mechanism is available. By default,
the protection is disabled and registers placed between 0x4380
and 0x43BE can be written without restriction. When the
protection is enabled, no writes to these registers is allowed.
Registers can be always read, without restriction, independent
of the write protection state. To enable the protection, write
0xAD to an internal 8-bit register located at address 0xE7FE,
followed by a write of 0x80 to an internal 8-bit register located
at Address 0xE7E3. To disable the protection, write 0xAD to an
internal 8-bit register located at Address 0xE7FE, followed by a
write of 0x00 to an internal 8-bit register located at Address
0xE7E3. It is recommended to enable the write protection
before starting the DSP. If any data memory RAM based register
needs to be changed, simply disable the protection, change the
value and then enable back the protection. There is no need to
stop the DSP in order to change these registers.
The recommended procedure to initialize the registers located
in the data memory RAM is:
•
Initialize all registers. Write the last register in the queue
three times to ensure its value was written into the RAM.
All the other registers of the ADE7880 should also be
initialized here.
•
Enable the write protection by writing 0xAD to an internal
8-bit register located at Address 0xE7FE, followed by a write
of 0x80 to an internal 8-bit register located at Address 0xE7E3.
•
Read back all data memory RAM registers to ensure they
were initialized with the desired values.
•
In the remote case one or more registers are not initialized
correctly, disable the protection by writing 0xAD to an
internal 8-bit register located at Address 0xE7FE, followed
by a write of 0x00 to an internal 8-bit register located at
Address 0xE7E3. Initialize again the registers. Write the
last register in the queue three times. Enable the write
protection by writing 0xAD to an internal 8-bit register
located at Address 0xE7FE, followed by a write of 0x80 to
an internal 8-bit register located at Address 0xE7E3.
•
Start the DSP by setting Run = 1.
There is no obvious reason to stop the DSP if the ADE7880 is
maintained in PSM0 normal mode. All ADE7880 registers,
including ones located in the data memory RAM, can be
modified without stopping the DSP. However, to stop the DSP,
0x0000 has to be written into Run register. To restart the DSP,
one of the following procedures must be followed:
Rev. A | Page 38 of 104
Data Sheet
•
•
ADE7880
If the ADE7880 registers located in the data memory RAM
have not been modified, write 0x0001 into the Run register to
start the DSP.
If the ADE7880 registers located in the data memory RAM
have to be modified, first execute a software or a hardware
reset, initialize all ADE7880 registers at desired values,
enable the write protection and then write 0x0001 into the
Run register to start the DSP.
As mentioned in the Power Management section, when the
ADE7880 switch out of PSM0 power mode, it is recommended to
stop the DSP by writing 0x0000 into the Run register (see Table 10
and Table 11 for the recommended actions when changing
power modes).
ROOT MEAN SQUARE MEASUREMENT
Root mean square (rms) is a measurement of the magnitude of
an ac signal. Its definition can be both practical and mathematical.
Defined practically, the rms value assigned to an ac signal is the
amount of dc required to produce an equivalent amount of
power in the load. Mathematically, the rms value of a continuous signal f(t) is defined as
1 t 2
F rms =
∫ f (t )dt
t 0
(10)
For time sampling signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root.
1
N
F rms =
N
∑ f 2 [n]
(11)
N =1
The ADE7880 also computes the rms values of various
fundamental and harmonic components of phase currents,
phase voltages and neutral current as part of the harmonic
calculations block. Refer to Harmonics Calculations section for
details.
The first method is to low-pass filter the square of the input
signal (LPF) and take the square root of the result (see Figure 65).
∞
k =1
(12)
then,
∞
∞
k =1
k =1
f 2 (t ) = ∑ Fk2 − ∑ Fk2 cos(2kωt + 2 γ k ) +
+2
∞
∑ 2 × Fk × Fm sin(kωt + γ k )× sin(mωt + γ m )
k ,m=1
k ≠m
F=
∞
∑ Fk2
(14)
k =1
The rms calculation based on this method is simultaneously
processed on all seven analog input channels. Each result is
available in the 24-bit registers: AIRMS, BIRMS, CIRMS,
AVRMS, BVRMS, CVRMS, and NIRMS.
The second method computes the absolute value of the input
signal and then filters it to extract its dc component. It computes
the absolute mean value of the input. If the input signal in
Equation 12 has a fundamental component only, its average
value is
FDC
⎡T
⎤
T
1 ⎢2
⎥
= ⎢ ∫ 2 × F1 × sin(ωt )dt − ∫ 2 × F1 × sin(ωt )dt ⎥
T 0
T
⎢⎣
⎥⎦
2
FDC =
2
× 2 × F1
π
The calculation based on this method is simultaneously processed
only on the three phase currents. Each result is available in the
20-bit registers AIMAV, BMAV, and CMAV. Note that the
proportionality between mav and rms values is maintained for
the fundamental components only. If harmonics are present in the
current channel, the mean absolute value is no longer
proportional to rms.
Current RMS Calculation
Equation 10 implies that for signals containing harmonics, the
rms calculation contains the contribution of all harmonics, not
only the fundamental. The ADE7880 uses two different methods
to calculate rms values. The first one is very accurate and is active
only in PSM0 mode. The second one is less accurate, uses the
estimation of the mean absolute value (mav) measurement, is
active in PSM0 and PSM1 modes.
If f (t ) = ∑ Fk 2 sin(kωt + γ k )
After the LPF and the execution of the square root, the rms
value of f(t) is obtained by
(13)
This section presents the first approach to compute the rms
values of all phase and neutral currents. The ADE7880 also
computes the rms of the sum of the instantaneous values of the
phase currents if Bit 2 (INSEL) in the CONFIG3 register is set
to 1. Note that the instantaneous value of the sum is stored into
ISUM register presented in the Neutral Current Mismatch
section. In 3-phase four wired systems that only require sensing
the phase currents, this value provides a measure of the neutral
current.
Figure 65 shows the detail of the signal processing chain for the
rms calculation on one of the phases of the current channel.
The current channel rms value is processed from the samples
used in the current channel. The current rms values are signed
24-bit values and they are stored into the AIRMS, BIRMS, CIRMS,
NIRMS registers. The update rate of the current rms measurement
is 8 kHz. If Bit 2 (INSEL) of the CONFIG3 register is 0 (default),
the NIRMS register contains the rms value of the neutral
current. If the INSEL bit is 1, the NIRMS register contains the
rms value of the sum of the instantaneous values of the phase
currents.
With the specified full-scale analog input signal of 0.5 V, the
ADC produces an output code that is approximately ±5,326,737.
The equivalent rms value of a full-scale sinusoidal signal is
3,766,572 (0x39792C), independent of the line frequency. If
Rev. A | Page 39 of 104
ADE7880
Data Sheet
the integrator is enabled, that is, when Bit 0 (INTEN) in the
CONFIG register is set to 1, the equivalent rms value of a fullscale sinusoidal signal at 50 Hz is 3,759,718 (0x395E66) and at
60 Hz is 3,133,207 (0x2FCF17).
Table 12. Settling Time for I RMS Measurement
The accuracy of the current rms is typically 0.1% error from
the full-scale input down to 1/1000 of the full-scale input when
PGA = 1. Additionally, this measurement has a bandwidth of
3.3 kHz. It is recommended to read the rms registers synchronous
to the voltage zero crossings to ensure stability. The IRQ1 interrupt can be used to indicate when a zero crossing has occurred
(see the Interrupts section). Table 12 shows the settling time for
the I rms measurement, which is the time it takes for the rms
register to reflect the value at the input to the current channel
when starting from 0.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 64, the AIRMS,
BIRMS, CIRMS, NIRMS 24-bit signed registers are accessed as
32-bit registers with the eight MSBs padded with 0s.
50 Hz Input Signals
580 ms
700 ms
31
24
0000
23
0
0000
24-BIT NUMBER
Figure 64. 24-Bit AIRMS, BIRMS, CIRMS and NIRMS Registers Transmitted as
32-Bit Words
xIRMSOS[23:0]
27
x2
LPF
xIRMS[23:0]
0x514791 =
5,326,737
0V
0xAEB86F =
–5,326,737
Figure 65. Current RMS Signal Processing
Rev. A | Page 40 of 104
10193-040
CURRENT SIGNAL FROM
HPF OR INTEGRATOR
(IF ENABLED)
60 Hz Input Signals
580 ms
700 ms
10193-039
Integrator Status
Integrator Off
Integrator On
Data Sheet
ADE7880
212000
Current RMS Offset Compensation
211500
211000
210500
210000
LSB
The ADE7880 incorporates a current rms offset compensation
register for each phase: AIRMSOS, BIRMSOS, CIRMSOS, and
NIRMSOS. These are 24-bit signed registers that are used to
remove offsets in the current rms calculations. An offset can
exist in the rms calculation due to input noises that are
integrated in the dc component of I2(t). One LSB of the current
rms offset compensation register is equivalent to one LSB of the
current rms register. Assuming that the maximum value from the
current rms calculation is 3,766,572 with full-scale ac inputs
(50 Hz), one LSB of the current rms offset represents 0.00045%
209000
208500
208000
207500
⎛ 37672 + 128 / 3767 − 1⎞ × 100
⎜
⎟
⎝
⎠
45
(15)
where I rms0 is the rms measurement without offset correction.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to the register presented
in Figure 43, the AIRMSOS, BIRMSOS, CIRMSOS, and
NIRMSOS 24-bit signed registers are accessed as 32-bit registers
with four MSBs padded with 0s and sign extended to 28 bits.
Current Mean Absolute Value Calculation
xIMAV[23:0]
|X|
HPF
HPF
Figure 66. Current MAV Signal Processing for PSM1 Mode
The current channel mav value is processed from the samples
used in the current channel waveform sampling mode. The
samples are passed through a high-pass filter to eliminate the
eventual dc offsets introduced by the ADCs and the absolute
values are computed. The outputs of this block are then filtered
to obtain the average. The current mav values are unsigned 20-bit
values and they are stored in the AIMAV, BIMAV, and CIMAV
registers. The update rate of this mav measurement is 8 kHz.
10193-041
This section presents the second approach to estimate the rms
values of all phase currents using the mean absolute value (mav)
method. This approach is used in PSM1 mode, to allow energy
accumulation based on current rms values when the missing
neutral case demonstrates to be a tamper attack. This data path
is active also in PSM0 mode to allow for its gain calibration.
The gain is used in the external microprocessor during PSM1
mode. The mav value of the neutral current is not computed
using this method. Figure 66 shows the details of the signal
processing chain for the mav calculation on one of the phases of
the current channel.
55
FREQUENCY (Hz)
60
65
Figure 67. xIMAV Register Values at Full Scale, 45 Hz to 65 Hz Line
Frequencies
The mav values of full-scale sinusoidal signals of 50 Hz and
60 Hz are 209,686 and 210,921, respectively. As seen in Figure 67,
there is a 1.25% variation between the mav estimate at 45 Hz
and the one at 65 Hz for full-scale sinusoidal inputs. The accuracy
of the current mav is typically 0.5% error from the full-scale
input down to 1/100 of the full-scale input. Additionally, this
measurement has a bandwidth of 3.3 kHz. The settling time for
the current mav measurement, that is the time it takes for the
mav register to reflect the value at the input to the current
channel within 0.5% error, is 500 ms.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
As presented in Figure 68, the AIMAV, BIMAV, and CIMAV 20bit unsigned registers are accessed as 32-bit registers with the 12
MSBs padded with 0s.
31
20 19
0000 0000 0000
0
20-BIT UNSIGNED NUMBER
10193-043
I rms = I rms02 + 128 × IRMSOS
50
10193-042
207000
of the rms measurement at 60 dB down from full scale. Conduct
offset calibration at low current; avoid using currents equal to
zero for this purpose.
CURRENT SIGNAL
COMING FROM ADC
209500
Figure 68. xIMAV Registers Transmitted as 32-Bit Registers
Current MAV Gain and Offset Compensation
The current rms values stored in the AIMAV, BIMAV, and
CIMAV registers can be calibrated using gain and offset
coefficients corresponding to each phase. It is recommended to
calculate the gains in PSM0 mode by supplying the ADE7880
with nominal currents. The offsets can be estimated by
supplying the ADE7880 with low currents, usually equal to the
minimum value at which the accuracy is required. Every time
the external microcontroller reads the AIMAV, BIMAV, and
CIMAV registers, it uses these coefficients stored in its memory
to correct them.
Rev. A | Page 41 of 104
ADE7880
Data Sheet
Voltage Channel RMS Calculation
this measurement has a bandwidth of 3.3 kHz. It is
recommended to read the rms registers synchronous to the
voltage zero crossings to ensure stability. The IRQ1 interrupt
can be used to indicate when a zero crossing has occurred (see
the Interrupts section).
Figure 69 shows the detail of the signal processing chain for the
rms calculation on one of the phases of the voltage channel. The
voltage channel rms value is processed from the samples used in
the voltage channel. The voltage rms values are signed 24-bit
values and they are stored into the Registers AVRMS, BVRMS,
and CVRMS. The update rate of the current rms measurement
is 8 kHz.
The V rms measurement settling time is 580 ms for both 50 Hz
and 60 Hz input signals. The V rms measurement settling time
is the time it takes for the rms register to reflect the value at the
input to the voltage channel when starting from 0.
With the specified full-scale analog input signal of 0.5 V, the
ADC produces an output code that is approximately ±5,326,737.
The equivalent rms value of a full-scale sinusoidal signal is
3,766,572 (0x39792C), independent of the line frequency.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 57, the AVRMS,
BVRMS, and CVRMS 24-bit signed registers are accessed as
32-bit registers with the eight MSBs padded with 0s.
The accuracy of the voltage rms is typically 0.1% error from the
full-scale input down to 1/1000 of the full-scale input. Additionally,
xVRMSOS[23:0]
27
x2
LPF
xVRMS[23:0]
0x14791 =
+5,326,737
0V
0xAEB86F =
–5,326,737
Figure 69. Voltage RMS Signal Processing
Rev. A | Page 42 of 104
10193-044
VOLTAGE SIGNAL
FROM HPF
Data Sheet
ADE7880
Voltage RMS Offset Compensation
Total Active Power Calculation
The ADE7880 incorporates voltage rms offset compensation
registers for each phase: AVRMSOS, BVRMSOS, and CVRMSOS.
These are 24-bit signed registers used to remove offsets in the
voltage rms calculations. An offset can exist in the rms calculation due to input noises that are integrated in the dc component
of V2(t). One LSB of the voltage rms offset compensation register is
equivalent to one LSB of the voltage rms register. Assuming that
the maximum value from the voltage rms calculation is 3,766,572
with full-scale ac inputs (50 Hz), one LSB of the current rms offset
represents 0.00045%
Electrical power is defined as the rate of energy flow from source
to load, and it is given by the product of the voltage and current
waveforms. The resulting waveform is called the instantaneous
power signal, and it is equal to the rate of energy flow at every
instant of time. The unit of power is the watt or joules/sec. If an
ac system is supplied by a voltage, v(t), and consumes the current,
i(t), and each of them contains harmonics, then
(17)
k =1
∞
i(t ) = ∑ I k 2 sin(kωt + γ k )
⎛ 37672 + 128 / 3767 − 1⎞ × 100
⎜
⎟
⎠
(⎝
k =1
of the rms measurement at 60 dB down from full scale. Conduct
offset calibration at low current; avoid using voltages equal to zero
for this purpose.
V rms = V rms02 + 128 × VRMSOS
∞
v(t ) = ∑Vk 2 sin (kωt + φk)
(16)
where V rms0 is the rms measurement without offset correction.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to registers presented in
Figure 43, the AVRMSOS, BVRMSOS, and CVRMSOS 24-bit
registers are accessed as 32-bit registers with the four most
significant bits padded with 0s and sign extended to 28 bits.
Voltage RMS in 3-Phase Three Wire Delta Configurations
In 3-phase three wire delta configurations, Phase B is
considered the ground of the system, and Phase A and Phase C
voltages are measured relative to it. This configuration is chosen
using CONSEL bits equal to 01 in ACCMODE register (see
Table 15 for all configurations where the ADE7880 may be
used). In this situation, all Phase B active, reactive, and apparent
powers are 0.
In this configuration, the ADE7880 computes the rms value of
the line voltage between Phase A and Phase C and stores the
result into BVRMS register. BVGAIN and BVRMSOS registers
may be used to calibrate BVRMS register computed in this
configuration.
ACTIVE POWER CALCULATION
The ADE7880 computes the total active power on every phase.
Total active power considers in its calculation all fundamental
and harmonic components of the voltages and currents. In
addition, the ADE7880 computes the fundamental active power,
the power determined only by the fundamental components of
the voltages and currents.
The ADE7880 also computes the harmonic active powers, the
active powers determined by the harmonic components of the
voltages and currents. See the Harmonics Calculations section
for details.
where:
Vk, Ik are rms voltage and current, respectively, of each
harmonic.
φk, γk are the phase delays of each harmonic.
The instantaneous power in an ac system is
∞
∞
k =1
k =1
p(t) = v(t) × i(t) = ∑Vk I k cos(φk – γk) − ∑Vk I k cos(2kωt + φk + γk)
∞
+
∑Vk I m {cos[(k − m)ωt + φk – γm] – cos[(k + m)ωt + φk + γm]}
k , m =1
k≠ m
(18)
The average power over an integral number of line cycles (n) is
given by the equation in Equation 19.
P=
∞
1 nT
p(t )dt = ∑ Vk I k cos(φk – γk)
∫
nT 0
k =1
(19)
where:
T is the line cycle period.
P is referred to as the total active or total real power.
Note that the total active power is equal to the dc component of
the instantaneous power signal p(t) in Equation 18, that is,
∞
∑Vk I k cos(φk – γk)
k =1
This is the equation used to calculate the total active power in the
ADE7880 for each phase. The equation of fundamental active
power is obtained from Equation 18 with k = 1, as follows:
(20)
FP = V1I1 cos(φ1 – γ1)
Figure 70 shows how the ADE7880 computes the total active
power on each phase. First, it multiplies the current and voltage
signals in each phase. Next, it extracts the dc component of the
instantaneous power signal in each phase (A, B, and C) using
LPF2, the low-pass filter.
If the phase currents and voltages contain only the fundamental
component, are in phase (that is φ1 = γ1 = 0), and they correspond
to full-scale ADC inputs, then multiplying them results in an
instantaneous power signal that has a dc component, V1 × I1,
and a sinusoidal component, V1 × I1 cos(2ωt); Figure 71 shows
the corresponding waveforms.
Rev. A | Page 43 of 104
ADE7880
Data Sheet
HPFEN BIT
AIGAIN CONFIG3[0]
INTEN BIT
CONFIG[0]
IA
APGAIN
HPF
AVGAIN
HPFEN BIT
CONFIG3[0]
INSTANTANEOUS
PHASE A
ACTIVE POWER
LPF
VA
:
HPF
DIGITAL SIGNAL PROCESSOR
24
AWATT
10193-045
APHCAL
AWATTOS
LPSEL BIT
CONFIG3[1]
Figure 70. Total Active Power Data Path
INSTANTANEOUS
POWER SIGNAL
0
p(t)= V rms × I rms – V rms × I rms × cos(2ωt)
0x339CBBC =
54,119,356
INSTANTANEOUS
ACTIVE POWER
SIGNAL: V rms × I rms
MAGNITUDE (dB)
–5
V rms × I rms
0x19CE5DE =
27,059,678
–10
–15
0x000 0000
–25
0.1
Figure 71. Active Power Calculation
Uk
k =1 U FS
×
Ik
I FS
× cos(φk – γk) × PMAX ×
1
(21)
24
where:
UFS, IFS are the rms values of the phase voltage and current when
the ADC inputs are at full scale.
PMAX = 27,059,678 it is the instantaneous power computed
when the ADC inputs are at full scale and in phase.
–10
–20
–30
–40
0.1
1
FREQUENCY (Hz)
10
10193-173
∞
10
0
The ADE7880 stores the instantaneous total phase active
powers into the AWATT, BWATT, and CWATT registers. Their
equation is
xWATT = ∑
3
Figure 72. Frequency Response of the LPF Used to Filter Instantaneous Power
in Each Phase When the LPFSEL Bit of CONFIG3 is 0 (Default)
MAGNITUDE (dB)
Because LPF2 does not have an ideal brick wall frequency
response, the active power signal has some ripple due to the
instantaneous power signal. This ripple is sinusoidal and has a
frequency equal to twice the line frequency. Because the ripple
is sinusoidal in nature, it is removed when the active power
signal is integrated over time to calculate the energy. Bit 1
(LPFSEL) of CONFIG3 register selects the LPF2 strength. If
LPFSEL is 0 (default), the settling time is 650 ms and the ripple
attenuation is 65 dB. If LPFSEL is 1, the settling time is 1300 ms
and the ripple attenuation is 128 dB. Figure 72 shows the
frequency response of LPF2 when LPFSEL is 0 and Figure 73
shows the frequency response of LPF2 when LPFSEL is 1.
1
FREQUENCY (Hz)
10193-172
10193-046
–20
i(t) = √2 × I rms × sin(ωt)
v(t) = √2 × V rms × sin(ωt)
Figure 73. Frequency Response of the LPF Used to Filter Instantaneous Power
in Each Phase when the LPFSEL Bit of CONFIG3 is 1
The xWATT[23:0] waveform registers can be accessed using
various serial ports. Refer to the Waveform Sampling Mode
section for more details.
Rev. A | Page 44 of 104
Data Sheet
ADE7880
Fundamental Active Power Calculation
The ADE7880 computes the fundamental active power using
a proprietary algorithm that requires some initializations function
of the frequency of the network and its nominal voltage measured
in the voltage channel. Bit 14 (SELFREQ) in the COMPMODE
register must be set according to the frequency of the network in
which the ADE7880 is connected. If the network frequency is
50 Hz, clear this bit to 0 (the default value). If the network frequency is 60 Hz, set this bit to 1. In addition, initialize the VLEVEL
24-bit signed register with a positive value based on the
following equation:
U
VLEVEL = FS × 4 × 10 6
Un
(22)
where:
UFS is the rms value of the phase voltages when the ADC inputs
are at full scale.
Un is the rms nominal value of the phase voltage.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to the registers presented
in Figure 43, the VLEVEL 24-bit signed register is accessed as a
32-bit register with four most significant bits padded with 0s
and sign extended to 28 bits.
Table 13 presents the settling time for the fundamental active
power measurement.
Table 13. Settling Time for Fundamental Active Power
63% PMAX
375 ms
Input Signals
100% PMAX
875 ms
Active Power Gain Calibration
Note that the average active power result from the LPF2 output
in each phase can be scaled by ±100% by writing to the phase’s
watt gain 24-bit register (APGAIN, BPGAIN, CPGAIN). The
xPGAIN registers are placed on data paths of all powers
computed by the ADE7880: total active powers, fundamental
active and reactive powers and apparent powers. This is possible
because all power data paths have identical overall gains.
Therefore, to compensate the gain errors in various powers data
paths it is sufficient to analyze only one power data path, for
example the total active power, calculate the correspondent
APGAIN, BPGAIN and CPGAIN registers and all the power
data paths are gain compensated.
The power gain registers are twos complement, signed registers
and have a resolution of 2−23/LSB. Equation 23 describes
mathematically the function of the power gain registers.
Average Power Data =
Power Gain Register ⎞
⎛
LPF 2 Output × ⎜1 +
⎟
2 23
⎝
⎠
(23)
The output is scaled by −50% by writing 0xC00000 to the watt
gain registers, and it is increased by +50% by writing 0x400000
to them. These registers are used to calibrate the active, reactive
and apparent power (or energy) calculation for each phase.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words,
and the DSP works on 28 bits. Similar to registers presented in
Figure 43, the APGAIN, BPGAIN, and CPGAIN 24-bit signed
registers are accessed as 32-bit registers with the four MSBs
padded with 0s and sign extended to 28 bits.
Active Power Offset Calibration
The ADE7880 incorporates a watt offset 24-bit register on each
phase and on each active power. The AWATTOS, BWATTOS,
and CWATTOS registers compensate the offsets in the total
active power calculations, and the AFWATTOS, BFWATTOS,
and CFWATTOS registers compensate offsets in the fundamental
active power calculations. These are signed twos complement,
24-bit registers that are used to remove offsets in the active
power calculations. An offset can exist in the power calculation
due to crosstalk between channels on the PCB or in the chip
itself. One LSB in the active power offset register is equivalent
to 1 LSB in the active power multiplier output. With full-scale
current and voltage inputs, the LPF2 output is PMAX =
27,059,678. At −80 dB down from the full scale (active power
scaled down 104 times), one LSB of the active power offset
register represents 0.0369% of PMAX.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to registers presented in
Figure 43, the AWATTOS, BWATTOS, CWATTOS, AFWATTOS,
BFWATTOS, and CFWATTOS 24-bit signed registers are
accessed as 32-bit registers with the four MSBs padded with
0s and sign extended to 28 bits.
Sign of Active Power Calculation
The average active power is a signed calculation. If the phase
difference between the current and voltage waveform is
more than 90°, the average power becomes negative. Negative
power indicates that energy is being injected back on the grid.
The ADE7880 has sign detection circuitry for active power
calculations. It can monitor the total active powers or the
fundamental active powers. As described in the Active Energy
Calculation section, the active energy accumulation is performed
in two stages. Every time a sign change is detected in the energy
accumulation at the end of the first stage, that is, after the energy
accumulated into the internal accumulator reaches the WTHR
register threshold, a dedicated interrupt is triggered. The sign of
each phase active power can be read in the PHSIGN register.
Bit 6 (REVAPSEL) in the ACCMODE register sets the type of
active power being monitored. When REVAPSEL is 0, the
default value, the total active power is monitored. When
REVAPSEL is 1, the fundamental active power is monitored.
Rev. A | Page 45 of 104
ADE7880
Data Sheet
Bits[8:6] (REVAPC, REVAPB, and REVAPA, respectively) in the
STATUS0 register are set when a sign change occurs in the
power selected by Bit 6 (REVAPSEL) in the ACCMODE
register.
PHSIGN register is read immediately after reading the STATUS0
register. Next, the status bit is cleared and the IRQ0 pin is returned
to high by writing to the STATUS0 register with the corresponding
bit set to 1.
Bits[2:0] (CWSIGN, BWSIGN, and AWSIGN, respectively) in
the PHSIGN register are set simultaneously with the REVAPC,
REVAPB, and REVAPA bits. They indicate the sign of the
power. When they are 0, the corresponding power is positive.
When they are 1, the corresponding power is negative.
Active Energy Calculation
As previously stated, power is defined as the rate of energy flow.
This relationship can be expressed mathematically as
Power =
Bit REVAPx of STATUS0 and Bit xWSIGN in the PHSIGN
register refer to the total active power of Phase x, the power type
being selected by Bit 6 (REVAPSEL) in the ACCMODE register.
(24)
Conversely, energy is given as the integral of power, as follows:
Energy = ∫ p (t )dt
Interrupts attached to Bits[8:6] (REVAPC, REVAPB, and
REVAPA, respectively) in the STATUS0 register can be enabled
by setting Bits[8:6] in the MASK0 register. If enabled, the IRQ0
pin is set low, and the status bit is set to 1 whenever a change of
sign occurs. To find the phase that triggered the interrupt, the
(25)
Total and fundamental active energy accumulations are always
signed operations. Negative energy is subtracted from the active
energy contents.
INTEN BIT
CONFIG[0]
IA
APGAIN
AWATTOS
REVAPA BIT IN
STATUS0[31:0]
HPF
APHCAL
AVGAIN
HPFEN BIT
CONFIG3[0]
AWATTHR[31:0]
INTERNAL
ACCUMULATOR
LPF
:
VA
32-BIT REGISTER
AWATT
HPF
THRESHOLD
DIGITAL SIGNAL PROCESSOR
24
34
27 26
WTHR
Figure 74. Total Active Energy Accumulation
Rev. A | Page 46 of 104
0
0
10193-049
HPFEN BIT
AIGAIN CONFIG3[0]
dEnergy
dt
Data Sheet
ADE7880
⎧∞
⎫
Energy = ∫ p (t )dt = Lim ⎨ ∑ p (nT ) × T ⎬
T→0 ⎩n=0
⎭
The ADE7880 achieves the integration of the active power signal
in two stages (see Figure 74). The process is identical for both
total and fundamental active powers. The first stage accumulates
the instantaneous phase total or fundamental active power at
1.024MHz, although they are computed by the DSP at 8 kHz
rate. Every time a threshold is reached, a pulse is generated and
the threshold is subtracted from the internal register.
where:
n is the discrete time sample number.
T is the sample period.
In the ADE7880, the total phase active powers are accumulated in
the AWATTHR, BWATTHR, and CWATTHR 32-bit signed
registers, and the fundamental phase active powers are
accumulated in AFWATTHR, BFWATTHR, and CFWATTHR
32-bit signed registers. The active energy register content can
roll over to full-scale negative (0x80000000) and continue
increasing in value when the active power is positive. Conversely, if
the active power is negative, the energy register underflows to
full-scale positive (0x7FFFFFFF) and continues decreasing in value.
The sign of the energy in this moment is considered the sign
of the active power (see the Sign of Active Power Calculation
section for details). The second stage consists of accumulating
the pulses generated at the first stage into internal 32-bit accumulation registers. The content of these registers is transferred
to watt-hour registers, xWATTHR and xFWATTHR, when
these registers are accessed.
THRESHOLD
FIRST STAGE OF
ACTIVE POWER
ACCUMULATION
10193-050
PULSES
GENERATED
AFTER FIRST
STAGE
1 PULSE = 1LSB OF WATTHR[31:0]
Figure 75. Active Power Accumulation Inside the DSP
Figure 75 explains this process. The threshold is formed by
concatenating the WTHR 8-bit unsigned register to 27 bits
equal to 0. It is introduced by the user and is common for total
and fundamental active powers on all phases. Its value depends
on how much energy is assigned to one LSB of watt-hour registers. Supposing a derivative of Wh [10n Wh], n as an integer, is
desired as one LSB of the xWATTHR register, WTHR is
computed using the following equation:
PMAX × f S × 3600 × 10 n
WTHR =
U FS × I FS × 2 27
(26)
where:
PMAX = 27,059,678 = 0x19CE5DE as the instantaneous power
computed when the ADC inputs are at full scale.
fS = 1.024 MHz, the frequency at which every instantaneous
power computed by the DSP at 8 kHz is accumulated.
UFS, IFS are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
WTHR register is an 8-bit unsigned number, so its maximum
value is 28 − 1. Its default value is 0x3. Values lower than 3, that
is 2 or 1 should be avoided and 0 should never be used as the
threshold must be a non-zero value.
This discrete time accumulation or summation is equivalent to
integration in continuous time following the description in
Equation 27.
(27)
The ADE7880 provides a status flag to signal when one of the
xWATTHR and xFWATTHR registers is half full. Bit 0 (AEHF)
in the STATUS0 register is set when Bit 30 of one of the
xWATTHR registers changes, signifying one of these registers is
half full. If the active power is positive, the watt-hour register
becomes half full when it increments from 0x3FFF FFFF to 0x4000
0000. If the active power is negative, the watt-hour register
becomes half full when it decrements from 0xC000 0000 to
0xBFFF FFFF. Similarly, Bit 1 (FAEHF) in STATUS0 register, is
set when Bit 30 of one of the xFWATTHR registers changes,
signifying one of these registers is half full.
Setting Bits[1:0] in the MASK0 register enable the FAEHF and
AEHF interrupts, respectively. If enabled, the IRQ0 pin is set
low and the status bit is set to 1 whenever one of the energy
registers, xWATTHR (for the AEHF interrupt) or xFWATTHR
(for the FAEHF interrupt), become half full. The status bit is
cleared and the IRQ0 pin is set to logic high by writing to the
STATUS0 register with the corresponding bit set to 1.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
read-with-reset for all watt-hour accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register
is 976.5625 ns (1.024MHz frequency). With full-scale sinusoidal
signals on the analog inputs and the watt gain registers set to
0x00000, the average word value from each LPF2 is PMAX =
27,059,678 = 0x19CE5DE. If the WTHR register threshold is set
at 3, its minimum recommended value, the first stage accumulator
generates a pulse that is added to watt-hour registers every
3 × 227
PMAX × 1.024 × 106
= 14.531μ sec
The maximum value that can be stored in the watt-hour
accumulation register before it overflows is 231 − 1 or
0x7FFFFFFF. The integration time is calculated as
Time = 0x7FFF,FFFF × 14.531 μs = 8 hr 40 min 6 sec
Rev. A | Page 47 of 104
(28)
ADE7880
Data Sheet
The active power is accumulated in each watt-hour
accumulation 32-bit register (AWATTHR, BWATTHR,
CWATTHR, AFWATTHR, BFWATTHR, and CFWATTHR)
according to the configuration of Bit 5 and Bit 4 (CONSEL bits) in
the ACCMODE register. The various configurations are described
in Table 14.
Table 14. Inputs to Watt-Hour Accumulation Registers
CONSEL
00
01
AWATTHR
VA × IA
VA × IA
10
VA × IA
11
VA × IA
1
BWATTHR
VB × IB
VB × IB
VB = VA – VC1
VB × IB
VB = −VA − VC
VB × IB
VB = −VA
CWATTHR
VC × IC
VC × IC
VC × IC
VC × IC
In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the
rms value of the line voltage between Phase A and Phase C and stores the
result into BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta
Configurations section). Consequently, the ADE7880 computes powers
associated with Phase B that do not have physical meaning. To avoid any
errors in the frequency output pins (CF1, CF2, or CF3) related to the powers
associated with Phase B, disable the contribution of Phase B to the energy-tofrequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or
TERMSEL3[1] to 0 in the COMPMODE register (see the Energy-to-Frequency
Conversion section).
mode, the ADE7880 transfers the active energy accumulated in the
32-bit internal accumulation registers into the xWATHHR or
xFWATTHR registers after an integral number of line cycles, as
shown in Figure 76. The number of half line cycles is specified
in the LINECYC register.
The line cycle energy accumulation mode is activated by setting
Bit 0 (LWATT) in the LCYCMODE register. The energy accumulation over an integer number of half line cycles is written
to the watt-hour accumulation registers after LINECYC number
of half line cycles is detected. When using the line cycle
accumulation mode, the Bit 6 (RSTREAD) of the LCYCMODE
register should be set to Logic 0 because the read with reset of
watt-hour registers is not available in this mode.
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combination of the zero crossings from all three phases can be used
for counting the zero crossing. Select only one phase at a time
for inclusion in the zero crossings count during calibration.
ZXSEL[0] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN
LCYCMODE[7:0]
Depending on the polyphase meter service, choose the appropriate formula to calculate the active energy. The American
ANSI C12.10 standard defines the different configurations of
the meter. Table 15 describes which mode to choose in these
various configurations.
ZEROCROSSING
DETECTION
(PHASE B)
Configuration
3-wire delta
4-wire wye
4-wire delta
4-wire wye
CONSEL
01
10
11
00
CALIBRATION
CONTROL
ZXSEL[2] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE C)
Table 15. Meter Form Configuration
ANSI Meter Form
5S/13S
6S/14S
8S/15S
9S/16S
LINECYC[15:0]
AWGAIN
AWATTOS
AWATTHR[31:0]
OUTPUT
FROM
LPF2
INTERNAL
ACCUMULATOR
32-BIT
REGISTER
THRESHOLD
Bits[1:0] (WATTACC[1:0]) in the ACCMODE register determine
how the active power is accumulated in the watt-hour registers
and how the CF frequency output can be generated as a
function of the total and fundamental active powers. See the
Energy-to-Frequency Conversion section for details.
Line Cycle Active Energy Accumulation Mode
In line cycle energy accumulation mode, the energy accumulation is synchronized to the voltage channel zero crossings such
that active energy is accumulated over an integral number of
half line cycles. The advantage of summing the active energy
over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any
ripple in the energy calculation and allows the energy to be
accumulated accurately over a shorter time. By using the line
cycle energy accumulation mode, the energy calibration can be
greatly simplified, and the time required to calibrate the meter
can be significantly reduced. In line cycle energy accumulation
34
27 26
WTHR
0
0
10193-051
Energy Accumulation Modes
Figure 76. Line Cycle Active Energy Accumulation Mode
The number of zero crossings is specified by the LINECYC 16-bit
unsigned register. The ADE7880 can accumulate active power
for up to 65,535 combined zero crossings. Note that the internal
zero-crossing counter is always active. By setting Bit 0 (LWATT)
in the LCYCMODE register, the first energy accumulation
result is, therefore, incorrect. Writing to the LINECYC register
when the LWATT bit is set resets the zero-crossing counter, thus
ensuring that the first energy accumulation result is accurate.
At the end of an energy calibration cycle, Bit 5 (LENERGY) in
the STATUS0 register is set. If the corresponding mask bit in
the MASK0 interrupt mask register is enabled, the IRQ0 pin
also goes active low. The status bit is cleared and the IRQ0 pin is
Rev. A | Page 48 of 104
Data Sheet
ADE7880
∞
set to high again by writing to the STATUS0 register with the
corresponding bit set to 1.
Because the active power is integrated on an integer number of
half-line cycles in this mode, the sinusoidal components are
reduced to 0, eliminating any ripple in the energy calculation.
Therefore, total energy accumulated using the line cycle
accumulation mode is
e=
t +nT
∞
t
k =1
∫ p (t )dt = nT ∑Vk I k
cos(φk – γk)
∑V kI m {cos[(k – m)ωt + φk − γk −
k ,m=1
k ≠m
cos[(k + m)ωt + φk + γk +
(29)
FUNDAMENTAL REACTIVE POWER CALCULATION
The ADE7880 computes the fundamental reactive power, the
power determined only by the fundamental components of the
voltages and currents.
The ADE7880 also computes the harmonic reactive powers, the
reactive powers determined by the harmonic components of the
voltages and currents. See Harmonics Calculations section for
details. A load that contains a reactive element (inductor or
capacitor) produces a phase difference between the applied ac
voltage and the resulting current. The power associated with
reactive elements is called reactive power, and its unit is VAR.
Reactive power is defined as the product of the voltage and current
waveforms when all harmonic components of one of these
signals are phase shifted by 90°.
Equation 31 is an example of the instantaneous reactive power
signal in an ac system when the phase of the current channel is
shifted by +90°.
∞
v(t ) = ∑ Vk 2 sin(kωt + φk)
(30)
k =1
∞
i(t ) = ∑ I k 2 sin(kωt + γk )
(31)
k =1
∞
π
i' (t ) = ∑ I k 2 sin⎛⎜ kωt + γ k + ⎞⎟
2⎠
⎝
k =1
Q=
Next, the instantaneous reactive power, q(t), can be expressed as
q(t) = v(t) × iʹ(t)
(32)
∞
q(t ) = ∑ Vk I k × 2 sin(kωt + φk) × sin(kωt + γk +
k =1
∞
∑Vk I m × 2sin(kωt + φk) × sin(mωt + γm +
π
)+
2
π
)
2
k ,m=1
k ≠m
Note that q(t) can be rewritten as
k =1
π
2
∞
1 nT
π
q(t )dt = ∑Vk I k cos(φk – γk −
)
∫
nT 0
2
k =1
(33)
(34)
) − cos(2 kωt + φ + γ +
k
Q = ∑ Vk I k sin(φk – γk)
k =1
where:
T is the period of the line cycle.
Q is referred to as the total reactive power. Note that the total
reactive power is equal to the dc component of the instantaneous
reactive power signal q(t) in Equation 32, that is,
∞
∑ Vk I k
k =1
sin(φk – γk)
This is the relationship used to calculate the total reactive power
for each phase. The instantaneous reactive power signal, q(t), is
generated by multiplying each harmonic of the voltage signals by
the 90° phase-shifted corresponding harmonic of the current in
each phase.
The expression of fundamental reactive power is obtained from
Equation 33 with k = 1, as follows:
FQ = V1I1 sin(φ1 – γ1)
The ADE7880 computes the fundamental reactive power using
a proprietary algorithm that requires some initialization
function of the frequency of the network and its nominal
voltage measured in the voltage channel. These initializations
are introduced in the Active Power Calculation section and are
common for both fundamental active and reactive powers.
The ADE7880 stores the instantaneous fundamental phase
reactive powers into the AFVAR, BFVAR, and CFVAR registers.
Their equation is
xFVAR =
where i’(t) is the current waveform with all harmonic
components phase shifted by 90°.
{
]}
∞
Note that line cycle active energy accumulation uses the same
signal path as the active energy accumulation. The LSB size of
these two methods is equivalent.
∞
]−
The average total reactive power over an integral number of line
cycles (n) is shown in Equation 34.
where nT is the accumulation time.
q(t ) = ∑ Vk I k cos(φk − γk −
π
2
π
2
k
π
2
)} +
U1
I
× 1 × sin(φ1 – γ1) × PMAX × 14
2
U FS I FS
(35)
where:
UFS, IFS are the rms values of the phase voltage and current when
the ADC inputs are at full scale.
PMAX = 27,059,678, the instantaneous power computed when
the ADC inputs are at full scale and in phase.
The xFVAR waveform registers are not mapped with an address
in the register space and can be accessed only through HSDC
port in the waveform sampling mode (see Waveform Sampling
Mode section for details). Fundamental reactive power
information is also available through the harmonic calculations
of the ADE7880 (see Harmonics Calculations section for details).
Rev. A | Page 49 of 104
ADE7880
Data Sheet
Fundamental Reactive Power Offset Calibration
Table 16 presents the settling time for the fundamental reactive
power measurement, which is the time it takes the power to
reflect the value at the input of the ADE7880.
The ADE7880 provides a fundamental reactive power offset
register on each phase. The AFVAROS, BFVAROS, and CFVAROS
registers compensate the offsets in the fundamental reactive
power calculations. These are signed twos complement, 24-bit
registers that are used to remove offsets in the fundamental
reactive power calculations. An offset can exist in the power
calculation due to crosstalk between channels on the PCB or in
the chip itself. The resolution of the registers is the same as for
the active power offset registers (see the Active Power Offset
Calibration section).
Table 16. Settling Time for Fundamental Reactive Power
Input Signals
100% PMAX
875 ms
Fundamental Reactive Power Gain Calibration
The average fundamental reactive power from the LPF output in
each phase can be scaled by ±100% by writing to one of the phase’s
VAR gain 24-bit register (APGAIN, BPGAIN, or CPGAIN). Note
that these registers are the same gain registers used to
compensate the other powers computed by the ADE7880. See
the Active Power Gain Calibration section for details on these
registers.
HPFEN BIT
AIGAIN CONFIG3[0]
DIGITAL
INTEGRATOR
IA
APGAIN
HPF
APHCAL
AVGAIN
HPFEN BIT
CONFIG3[0]
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to the registers presented
in Figure 43, the AFVAROS, BFVAROS, and CFVAROS 24-bit
signed registers are accessed as 32-bit registers with the four
MSBs padded with 0s and sign extended to 28 bits.
AFVAROS
REVFRPA BIT IN
STATUS0[31:0]
FUNDAMENTAL
REACTIVE
POWER
ALGORITHM
AFVARHR[31:0]
INTERNAL
ACCUMULATOR
:
VA
32-BIT REGISTER
AFVAR
HPF
THRESHOLD
DIGITAL SIGNAL PROCESSOR
24
34
27 26
VARTHR
Figure 77. Fundamental Reactive Energy Accumulation
Rev. A | Page 50 of 104
0
0
10193-052
63% PMAX
375 ms
Data Sheet
ADE7880
Sign of Fundamental Reactive Power Calculation
Note that the fundamental reactive power is a signed calculation.
Table 17 summarizes the relationship between the phase difference
between the voltage and the current and the sign of the resulting
reactive power calculation.
The ADE7880 has sign detection circuitry for reactive power
calculations that can monitor the fundamental reactive powers.
As described in the Fundamental Reactive Energy Calculation
section, the reactive energy accumulation is executed in two
stages. Every time a sign change is detected in the energy
accumulation at the end of the first stage, that is, after the energy
accumulated into the internal accumulator reaches the VARTHR
register threshold, a dedicated interrupt is triggered. The sign of
each phase reactive power can be read in the PHSIGN register.
Bits[12:10] (REVFRPC, REVFRPB, and REVFRPA, respecttively) in the STATUS0 register are set when a sign change
occurs in the fundamental reactive power.
Bits[6:4] (CFVARSIGN, BFVARSIGN, and AFVARSIGN,
respectively) in the PHSIGN register are set simultaneously with
the REVFRPC, REVFRPB, and REVFRPA bits. They indicate the
sign of the fundamental reactive power. When they are 0, the
reactive power is positive. When they are 1, the reactive power
is negative.
Bit REVFRPx of the STATUS0 register and Bit xFVARSIGN in
the PHSIGN register refer to the reactive power of Phase x.
Setting Bits[12:10] in the MASK0 register enables the REVFRPC,
REVFRPB, and REVFRPA interrupts, respectively. If enabled,
the IRQ0 pin is set low and the status bit is set to 1 whenever a
change of sign occurs. To find the phase that triggered the
interrupt, the PHSIGN register is read immediately after reading the STATUS0 register. Next, the status bit is cleared and the
IRQ0 pin is set to high by writing to the STATUS0 register with
the corresponding bit set to 1.
Table 17. Sign of Reactive Power Calculation
Φ1
Between 0 to +180
Between −180 to 0
1
Similar to active power, the ADE7880 achieves the integration
of the reactive power signal in two stages (see Figure 77).
•
•
Figure 77 explains this process. The threshold is formed by
concatenating the VARTHR 8-bit unsigned register to 27 bits
equal to 0 and it is introduced by the user. Its value depends on
how much energy is assigned to one LSB of var-hour registers.
Supposing a derivative of a volt ampere reactive hour (varh) [10n
varh] where n is an integer, is desired as one LSB of the VARHR
register, the VARTHR register can be computed using the
following equation:
VARTHR =
Φ is defined as the phase angle of the voltage signal minus the current
signal; that is, Φ is positive if the load is inductive and negative if the load is
capacitive.
(37)
where:
PMAX = 27,059,678 = 0x19CE5DE, the instantaneous power
computed when the ADC inputs are at full scale.
fS = 1.024 MHz, the frequency at which every instantaneous
power computed by the DSP at 8 kHz is accumulated.
UFS, IFS are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
This discrete time accumulation or summation is equivalent to
integration in continuous time, shown in Equation 38:
Fundamental Reactive Energy Calculation
⎧∞
⎫
ReactiveEnergy = ∫ q (t )dt = Lim ⎨ ∑ q (nT ) × T ⎬
T→0 ⎩n=0
⎭
Fundamental reactive energy is defined as the integral of
fundamental reactive power.
The fundamental reactive energy accumulation is always a
signed operation. Negative energy is subtracted from the
reactive energy contents.
PMAX × f s × 3600 × 10 n
U FS × I FS × 2 27
VARTHR register is an 8-bit unsigned number, so its maximum
value is 28 − 1. Its default value is 0x3. Values lower than 3, that
is 2 or 1 should be avoided and 0 should never be used as the
threshold must be a non-zero value.
Sign of Reactive Power
Positive
Negative
Reactive Energy = ∫q(t)dt
The first stage accumulates the instantaneous phase
fundamental reactive power at 1.024 MHz, although they
are computed by the DSP at 8 kHz rate. Every time a
threshold is reached, a pulse is generated and the threshold
is subtracted from the internal register. The sign of the
energy in this moment is considered the sign of the
reactive power (see the Sign of Fundamental Reactive
Power Calculation section for details).
The second stage consists in accumulating the pulses
generated after the first stage into internal 32-bit
accumulation registers. The content of these registers is
transferred to the var-hour registers (xFVARHR) when these
registers are accessed. AFWATTHR, BFWATTHR, and
CFWATTHR represent phase fundamental reactive energies.
(36)
where:
n is the discrete time sample number.
T is the sample period.
Rev. A | Page 51 of 104
(38)
ADE7880
Data Sheet
On the ADE7880, the fundamental phase reactive powers are
accumulated in the AFVARHR, BFVARHR, and CFVARHR 32bit signed registers. The reactive energy register content can roll
over to full-scale negative (0x80000000) and continue increasing in
value when the reactive power is positive. Conversely, if the reactive
power is negative, the energy register underflows to full-scale
positive (0x7FFFFFFF) and continues to decrease in value.
Table 18. Inputs to Var-Hour Accumulation Registers
The ADE7880 provides a status flag to signal when one of the
xFVARHR registers is half full. Bit 3 (FREHF) in the STATUS0
register is set when Bit 30 of one of the xFVARHR registers
changes, signifying one of these registers is half full. If the reactive
power is positive, the var-hour register becomes half full when it
increments from 0x3FFF FFFF to 0x4000 0000. If the reactive
power is negative, the var-hour register becomes half full when it
decrements from 0xC000 0000 to 0xBFFF FFFF.
Setting Bit3 in the MASK0 register enables the FREHF
interrupt. If enabled, the IRQ0 pin is set low and the status bit
is set to 1 whenever one of the energy registers, xFVARHR,
becomes half full. The status bit is cleared and the IRQ0 pin is
set to high by writing to the STATUS0 register with the
corresponding bit set to 1.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
read-with-reset for all var-hour accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register
is 976.5625 ns (1.024 MHz frequency). With full-scale
sinusoidal signals on the analog inputs and a 90° phase difference
between the voltage and the current signal (the largest possible
reactive power), the average word value representing the reactive
power is PMAX = 27,059,678 = 0x19CE5DE. If the VARTHR
threshold is set at 3, its minimum recommended value, the first
stage accumulator generates a pulse that is added to var-hour
registers every
3 × 227
PMAX × 1.024 × 106
= 14.531μ sec
The maximum value that can be stored in the var-hour
accumulation register before it overflows is 231 − 1 or
0x7FFFFFFF. The integration time is calculated as
Time = 0x7FFF,FFFF × 14.531 μs = 8 hr 40 min 6 sec
(39)
Energy Accumulation Modes
CONSEL[1:0]
00
01
AFVARHR
VA × IA’
VA × IA’
10
VA × IA’
11
VA × IA’
1
BFVARHR
VB × IB’
VB × IB’
VB = VA − VC1
VB × IB’
VB = −VA − VC
VB × IB’
VB = −VA
CFVARHR
VC × IC’
VC × IC’
VC x IC’
VC × IC’
In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the
rms value of the line voltage between phases A and C and stores the result
into BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta
Configurations section). Consequently, the ADE7880 computes powers
associated with Phase B that do not have physical meaning. To avoid any
errors in the frequency output pins (CF1, CF2, or CF3) related to the powers
associated with Phase B, disable the contribution of Phase B to the energy to
frequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or
TERMSEL3[1] to 0 in COMPMODE register (see the Energy-to-Frequency
Conversion section).
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine
how the reactive power is accumulated in the var-hour registers
and how the CF frequency output can be generated function of
total and fundamental active and reactive powers. See the Energyto-Frequency Conversion section for details.
Line Cycle Reactive Energy Accumulation Mode
As mentioned in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage
channel zero crossings so that reactive energy can be
accumulated over an integral number of half line cycles.
In this mode, the ADE7880 transfers the reactive energy
accumulated in the 32-bit internal accumulation registers into
the xFVARHR registers after an integral number of line cycles,
as shown in Figure 78. The number of half line cycles is
specified in the LINECYC register.
The line cycle reactive energy accumulation mode is activated by
setting Bit 1 (LVAR) in the LCYCMODE register. The
fundamental reactive energy accumulated over an integer
number of half line cycles or zero crossings is available in the varhour accumulation registers after the number of zero crossings
specified in the LINECYC register is detected. When using the
line cycle accumulation mode, Bit 6 (RSTREAD) of the
LCYCMODE register should be set to Logic 0 because a read
with the reset of var-hour registers is not available in this mode.
The fundamental reactive power accumulated in each var-hour
accumulation 32-bit register (AFVARHR, BFVARHR, and
CFVARHR) depends on the configuration of Bits[5:4]
(CONSEL[1:0]) in the ACCMODE register, in correlation with
the watt-hour registers. The different configurations are
described in Table 18. Note that IA’/IB’/IC’ are the phaseshifted current waveforms.
Rev. A | Page 52 of 104
Data Sheet
ADE7880
ZXSEL[0] IN
LCYCMODE[7:0]
power is by multiplying the voltage rms value by the current
rms value (also called the arithmetic apparent power).
ZEROCROSSING
DETECTION
(PHASE A)
S = V rms × I rms
ZXSEL[1] IN
LCYCMODE[7:0]
where:
S is the apparent power.
V rms and I rms are the rms voltage and current, respectively.
LINECYC[15:0]
ZEROCROSSING
DETECTION
(PHASE B)
CALIBRATION
CONTROL
The ADE7880 computes the arithmetic apparent power on each
phase. Figure 79 illustrates the signal processing in each phase
for the calculation of the apparent power in the ADE7880.
Because V rms and I rms contain all harmonic information, the
apparent power computed by the ADE7880 is total apparent
power. The ADE7880 computes fundamental and harmonic
apparent powers determined by the fundamental and harmonic
components of the voltages and currents. See the Harmonics
Calculations section for details.
ZXSEL[2] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE C)
APGAIN
AFVAROS
AFVARHR[31:0]
INTERNAL
ACCUMULATOR
OUTPUT FROM
FUNDAMENTAL REACTIVE
POWER ALGORITHM
32-BIT
REGISTER
THRESHOLD
27 26
VARTHR
0
The ADE7880 stores the instantaneous phase apparent powers
into the AVA, BVA, and CVA registers. Their equation is
10193-053
34
0
(40)
xVA =
Figure 78. Line Cycle Fundamental Reactive Energy Accumulation Mode
1
U
I
×
× PMAX × 4
2
U FS I FS
(41)
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half line cycles by
setting Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any
combination of the zero crossings from all three phases can be
used for counting the zero crossing. Select only one phase at a
time for inclusion in the zero-crossings count during calibration.
where:
U, I are the rms values of the phase voltage and current.
UFS, IFS are the rms values of the phase voltage and current when
the ADC inputs are at full scale.
PMAX = 27,059,678, the instantaneous power computed when
the ADC inputs are at full scale and in phase.
For details on setting the LINECYC register and the Bit 5
(LENERGY) in the MASK0 interrupt mask register associated
with the line cycle accumulation mode, see the Line Cycle
Active Energy Accumulation Mode section.
The xVA[23:0] waveform registers may be accessed using
various serial ports. Refer to the Waveform Sampling Mode
section for more details.
The ADE7880 can compute the apparent power in an alternative
way by multiplying the phase rms current by an rms voltage
introduced externally. See the Apparent Power Calculation
Using VNOM section for details.
APPARENT POWER CALCULATION
Apparent power is defined as the maximum active power that
can be delivered to a load. One way to obtain the apparent
APGAIN
AIRMS
AVAHR[31:0]
INTERNAL
ACCUMULATOR
:
DIGITAL SIGNAL
PROCESSOR
32-BIT REGISTER
AVA
THRESHOLD
24
34
27 26
VATHR
0
0
Figure 79. Apparent Power Data Flow and Apparent Energy Accumulation
Rev. A | Page 53 of 104
10193-054
AVRMS
ADE7880
Data Sheet
Apparent Power Gain Calibration
The average apparent power result in each phase can be scaled
by ±100% by writing to one of the phase’s PGAIN 24-bit
registers (APGAIN, BPGAIN, or CPGAIN). Note that these
registers are the same gain registers used to compensate the
other powers computed by the ADE7880. See the Active Power
Gain Calibration section for details on these registers.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value
(see the Root Mean Square Measurement section). The voltage
and current rms values are multiplied together in the apparent
power signal processing. As no additional offsets are created in
the multiplication of the rms values, there is no specific offset
compensation in the apparent power signal processing. The offset
compensation of the apparent power measurement in each phase is
accomplished by calibrating each individual rms measurement.
Apparent Power Calculation Using VNOM
The ADE7880 can compute the apparent power by multiplying
the phase rms current by an rms voltage introduced externally in
the VNOM 24-bit signed register.
When one of Bits[13:11] (VNOMCEN, VNOMBEN, or
VNOMAEN) in the COMPMODE register is set to 1, the
apparent power in the corresponding phase (Phase x for
VNOMxEN) is computed in this way. When the VNOMxEN
bits are cleared to 0, the default value, then the arithmetic
apparent power is computed.
The VNOM register contains a number determined by U, the
desired rms voltage, and UFS, the rms value of the phase voltage
when the ADC inputs are at full scale:
U
VNOM =
× 3,766,572
U FS
(42)
where U is the nominal phase rms voltage.
As stated in the Current Waveform Gain Registers, the serial
ports of the ADE7880 work on 32-, 16-, or 8-bit words. Similar
to the register presented in Figure 57, the VNOM 24-bit signed
register is accessed as a 32-bit register with the eight MSBs
padded with 0s.
Apparent Energy Calculation
Apparent energy is defined as the integral of apparent power.
Apparent Energy = ∫s(t)dt
(43)
Similar to active and reactive powers, the ADE7880 achieves
the integration of the apparent power signal in two stages (see
Figure 79). The first stage accumulates the instantaneous
apparent power at 1.024 MHz, although they are computed by
the DSP at 8 kHz rate. Every time a threshold is reached, a pulse
is generated and the threshold is subtracted from the internal
register. The second stage consists in accumulating the pulses
generated after the first stage into internal 32-bit accumulation
registers. The content of these registers is transferred to the VAhour registers, xVAHR, when these registers are accessed.
Figure 79 illustrates this process. The threshold is formed by the
VATHR 8-bit unsigned register concatenated to 27 bits equal to
0. It is introduced by the user and is common for all phase total
active and fundamental powers. Its value depends on how much
energy is assigned to one LSB of VA-hour registers. When a
derivative of apparent energy (VAh) [10n VAh], where n is an
integer, is desired as one LSB of the xVAHR register, the
xVATHR register can be computed using the following equation:
VATHR =
PMAX × f s × 3600 × 10 n
U FS × I FS × 2 27
(44)
where:
PMAX = 27,059,678 = 0x19CE5DE, the instantaneous power
computed when the ADC inputs are at full scale.
fS = 1.024 MHz, the frequency at which every instantaneous
power computed by the DSP at 8 kHz is accumulated.
UFS, IFS are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
The VATHR register is an 8-bit unsigned number, so its
maximum value is 28 − 1. Its default value is 0x3. Values lower
than 3, that is 2 or 1 should be avoided and 0 should never be
used as the threshold must be a non-zero value.
This discrete time accumulation or summation is equivalent to
integration in continuous time following the description in
Equation 45.
⎧∞
⎫
ApparentEnergy = ∫ s (t )dt = Lim ⎨ ∑ s (nT ) × T ⎬
T→0 ⎩n=0
⎭
(45)
where:
n is the discrete time sample number.
T is the sample period.
In the ADE7880, the phase apparent powers are accumulated in
the AVAHR, BVAHR, and CVAHR 32-bit signed registers. The
apparent energy register content can roll over to full-scale
negative (0x80000000) and continue increasing in value when the
apparent power is positive. Conversely, if because of offset
compensation in the rms data path, the apparent power is
negative, the energy register underflows to full-scale positive
(0x7FFFFFFF) and continues to decrease in value.
The ADE7880 provides a status flag to signal when one of the
xVAHR registers is half full. Bit 4 (VAEHF) in the STATUS0
register is set when Bit 30 of one of the xVAHR registers changes,
signifying one of these registers is half full. As the apparent
power is always positive and the xVAHR registers are signed, the
VA-hour registers become half full when they increment from
0x3FFFFFFF to 0x40000000. Interrupts attached to Bit VAEHF in
the STATUS0 register can be enabled by setting Bit 4 in the MASK0
register. If enabled, the IRQ0 pin is set low and the status bit is
set to 1 whenever one of the Energy Registers xVAHR becomes
half full. The status bit is cleared and the IRQ0 pin is set to high
Rev. A | Page 54 of 104
Data Sheet
ADE7880
ZXSEL[0] IN
LCYCMODE[7:0]
by writing to the STATUS0 register with the corresponding bit
set to 1.
ZEROCROSSING
DETECTION
(PHASE A)
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation.
ZEROCROSSING
DETECTION
(PHASE B)
Integration Time Under Steady Load
The discrete time sample period for the accumulation register
is 976.5625 ns (1.024 MHz frequency). With full-scale pure
sinusoidal signals on the analog inputs, the average word value
representing the apparent power is PMAX. If the VATHR
threshold register is set at 3, its minimum recommended value,
the first stage accumulator generates a pulse that is added to the
PMAX × 1.024 × 106
AVRMS × AIRMS
AVAHR[31:0]
BVAHR
BVRMS × BIRMS
BVRMS × BIRMS
VB = VA – VC1
BVRMS × BIRMS
VB = −VA − VC
BVRMS × BIRMS
VB = −VA
THRESHOLD
34
27 26
VATHR
(46)
Table 19. Inputs to VA-Hour Accumulation Registers
11
APGAIN
32-BIT REGISTER
The apparent power accumulated in each accumulation register
depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the
ACCMODE register. The various configurations are described
in Table 19.
AVRMS × AIRMS
AIRMS
AVRMS
Energy Accumulation Mode
10
ZEROCROSSING
DETECTION
(PHASE C)
= 14.531μ sec
Time = 0x7FFFFFFF × 14.531 μs = 8 hr 40 min 6 sec
AVAHR
AVRMS × AIRMS
AVRMS × AIRMS
ZXSEL[2] IN
LCYCMODE[7:0]
INTERNAL
ACCUMULATOR
The maximum value that can be stored in the xVAHR
accumulation register before it overflows is 231 − 1 or
0x7FFFFFFF. The integration time is calculated as
CONSEL[1:0]
00
01
CALIBRATION
CONTROL
CVAHR
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
1
In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the
rms value of the line voltage between Phase A and Phase C and stores the
result into the BVRMS register (see the Voltage RMS in 3-Phase Three Wire
Delta Configurations section). Consequently, the ADE7880 computes powers
associated with Phase B that do not have physical meaning. To avoid any
errors in the frequency output pins (CF1, CF2, or CF3) related to the powers
associated with Phase B, disable the contribution of phase B to the energy to
frequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or
TERMSEL3[1] to 0 in COMPMODE register (see the Energy-to-Frequency
Conversion section).
Line Cycle Apparent Energy Accumulation Mode
As described in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage channel
zero crossings allowing apparent energy to be accumulated over an
integral number of half line cycles. In this mode, the ADE7880
transfers the apparent energy accumulated in the 32-bit internal
accumulation registers into the xVAHR registers after an
integral number of line cycles, as shown in Figure 80. The
number of half line cycles is specified in the LINECYC register.
0
0
10193-055
xVAHR registers every
3 × 227
LINECYC[15:0]
ZXSEL[1] IN
LCYCMODE[7:0]
Figure 80. Line Cycle Apparent Energy Accumulation Mode
The line cycle apparent energy accumulation mode is activated
by setting Bit 2 (LVA) in the LCYCMODE register. The apparent
energy accumulated over an integer number of zero crossings is
written to the xVAHR accumulation registers after the number
of zero crossings specified in LINECYC register is detected. When
using the line cycle accumulation mode, set Bit 6 (RSTREAD) of
the LCYCMODE register to Logic 0 because a read with the reset of
xVAHR registers is not available in this mode.
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combination of the zero crossings from all three phases can be used
for counting the zero crossing. Select only one phase at a time
for inclusion in the zero-crossings count during calibration.
For details on setting the LINECYC register and Bit 5 (LENERGY)
in the MASK0 interrupt mask register associated with the line
cycle accumulation mode, see the Line Cycle Active Energy
Accumulation Mode section.
POWER FACTOR CALCULATION
The ADE7880 provides a direct power factor measurement
simultaneously on all phases. Power factor in an ac circuit is
defined as the ratio of the total active power flowing to the load
to the apparent power. The absolute power factor measurement
is defined in terms of leading or lagging referring to whether the
current is leading or lagging the voltage waveform. When the
current is leading the voltage, the load is capacitive and this is
defined as a negative power factor. When the current is lagging
the voltage, the load is inductive and this defined as a positive
power factor. The relationship of the current to the voltage
waveform is illustrated in Figure 81.
Rev. A | Page 55 of 104
ADE7880
Data Sheet
ACTIVE (–)
REACTIVE (–)
PF (+)
enabled on both the active and apparent energies. This is done
by setting the xLWATT and xLVA bits in the LCYCMODE
register (Address 0xE702). The update rate of the power factor
measurement is now an integral number of half line cycles that
can be programmed into the LINECYC register (Address 0xE60C).
For full details on setting up the line cycle accumulation mode
see the Line Cycle Active Energy Accumulation Mode and Line
Cycle Apparent Energy Accumulation Mode sections.
ACTIVE (+)
REACTIVE (–)
PF (–)
CAPACITIVE:
CURRENT LEADS
VOLTAGE
θ = +60°
PF = –0.5
θ = –60°
PF = +0.5
V
ACTIVE (+)
REACTIVE (+)
PF (+)
10193-056
I
ACTIVE (–)
REACTIVE (+)
PF (–)
INDUCTIVE:
CURRENT LAGS
VOLTAGE
Figure 81. Capacitive and Inductive Loads
As shown in Figure 81, the reactive power measurement is
negative when the load is capacitive, and positive when the load
is inductive. The sign of the reactive power can therefore be
used to reflect the sign of the power factor. Note that the ADE7880
computes the fundamental reactive power, so its sign is used as
the sign of the absolute power factor. If the fundamental
reactive power is in no load state, then the sign of the power
factor is the sign of the total active power.
The mathematical definition of power factor is shown in
Equation 47:
Power Factor = (Sign Fundamental Reactive Power) ×
Total Active Power
(47)
Apparent Power
As previously mentioned, the ADE7880 provides a power factor
measurement on all phases simultaneously. These readings are
provided into three 16-bit signed registers, APF (Address
0xE609 ) for Phase A, BPF (Address 0xE60A) for Phase B, and
CPF (Address 0xE60B) for Phase C. The registers are signed
twos complement register with the MSB indicating the polarity
of the power factor. Each LSB of the APF, BPF, and CPF
registers equates to a weight of 2−15, hence the maximum
register value of 0x7FFF equating to a power factor value of 1.
The minimum register value of 0x8000 corresponds to a power
factor of −1. If because of offset and gain calibrations, the power
factor is outside the −1 to +1 range, the result is set at −1 or +1
depending on the sign of the fundamental reactive power.
By default the instantaneous total phase active and apparent
powers are used to calculate the power factor and the registers
are updated at a rate of 8 kHz. The sign bit is taken from the
instantaneous fundamental phase reactive energy measurement
on each phase.
Should a measurement with more averaging be required, the
ADE7880 provides an option of using the line cycle accumulation
measurement on the active and apparent energies to determine
the power factor. This option provides a more stable power
factor reading. This mode is enabled by setting the PFMODE
bit (Bit 7) in the LCYCMODE register (Address 0xE702). When
this mode is enabled the line cycle accumulation mode must be
Note that the power factor measurement is effected by the no
load condition if it is enabled (see the No Load Condition
section). If the apparent energy no load is true, then the power
factor measurement is set to 1. If the no load condition based
on total active and apparent energies is true, the power factor
measurement is set at 0.
The ADE7880 also computes the power factor on the
fundamental and harmonic components based on the
fundamental and harmonic active, reactive and apparent
powers. See the Harmonics Calculations section for details.
HARMONICS CALCULATIONS
The ADE7880 contains a harmonic engine that analyzes one
phase at a time. Harmonic information is computed with a no
attenuation pass band of 2.8 kHz (corresponding to a −3 dB
bandwidth of 3.3 kHz) and it is specified for line frequencies
between 45 Hz and 66 Hz. Neutral current can also be analyzed
simultaneously with the sum of the phase currents. Figure 82
presents a synthesized diagram of the harmonic engine, its
settings and its output registers.
Theory of Operation
Consider an nonsinusoidal ac system supplied by a voltage, v(t)
that consumes the current i(t). Then
∞
v(t ) = ∑Vk 2 sin (kωt + φk)
k =1
(48)
∞
i (t ) = ∑ I k 2 sin(kωt + γ k )
k =1
where:
Vk, Ik are rms voltage and current, respectively, of each
harmonic.
Φk, γk are the phase delays of each harmonic.
ω is the angular velocity at the fundamental (line) frequency f.
The ADE7880 harmonics calculations are specified for line
frequencies between 45 Hz and 66 Hz. The phase nominal
voltage used as time base must have an amplitude greater than
20% of full scale.
The number of harmonics N that can be analyzed within the
2.8 kHz pass band is the whole number of 2800/f. The absolute
maximum number of harmonics accepted by the ADE7880
is 63.
⎡ 2800 ⎤
N =⎢
⎥ , N≤63
⎣ f ⎦
Rev. A | Page 56 of 104
Data Sheet
ADE7880
When the ADE7880 analyzes a phase, the following metering
quantities are computed:



pf z  sgnQz  
Fundamental phase current rms: I1
Fundamental phase voltage rms: V1
RMS of up to three harmonics of phase current:
Ix, Iy, Iz, x,y,z=2, 3,…, N
RMS of up to three harmonics of phase voltage:
Vx, Vy, Vz, x,y,z=2, 3,…, N
Fundamental phase active power
P1 = V1I1cos(φ1 − γ1)
Fundamental phase reactive power
Q1 = V1I1sin(φ1 − γ1)


Fundamental phase apparent power
S1 = V 1 I1


Power factor of the fundamental



pf1  sgn Q1  
P1
S1


Reactive power of up to three harmonics:
Qx = VxIxsin(φx – γx), x=2, 3,…, N
Qy = VyIysin(φy – γy), y=2, 3,…, N
Qz = VzIzsin(φz – γz), z=2, 3,…, N
Apparent power of up to three harmonics:
Sx = VxIx, x = 2, 3, …, N
Sy = VyIy, y = 2 , 3, …, N
Sz = VzIz, z = 2, 3, …, N
Power factor of up to three harmonics:

P
pf x  sgnQx   x
S x , x = 2, 3,…, N
 
pf y  sgn Qy 
Py
Sy
, y = 2, 3,…, N
Rev. A | Page 57 of 104

I 2  I12
I1
Total harmonic distortion of the phase voltage
THDV
Active power of up to three harmonics:
Px = VxIxcos(φx – γx), x=2, 3,…, N
Py = VyIycos(φy – γy), y=2, 3,…, N
Pz = VzIzcos(φz – γz), z=2, 3,…, N

Total harmonic distortion of the phase current
THDI

Pz
, z = 2, 3,…, N
Sz

V 2  V12
V1
Harmonic distortion of up to three harmonics on the phase
current
HDI x 
Ix
I1 , x = 2, 3,…, N
HDI y 
Iy
HDI z 
Iz
I1 , z = 2, 3,…, N
I1 , y = 2, 3,…, N
Harmonic distortion of up to three harmonics on the phase
voltage:
HDVx 
Vx
V1 , x = 2, 3,…, N
HDVy 
Vy
HDVz 
Vz
V1 , z = 2, 3,…, N
V1 , y = 2, 3,…, N
Data Sheet
ADE7880
ACTPHSEL BITS HCONFIG[9,8] SELECT
HPHASE BITS THE PHASE USED TO AS TIME BASE
HCONFIG[2,1]
SELECT THE PHASE
BEING MONITORED
IA, VA
IB, VB
ADE7880 HARMONIC
CALCULATIONS
IC, VC
IN, ISUM
HX, HY, HZ REGISTERS SELECT THE
HARMONICS TO MONITOR
OUTPUT REGISTERS USED WHEN ONE OF PHASES A, B, C IS ANALYZED
FVRMS
FIRMS
FWATT
FVAR
FVA
FPF
VTHD
ITHD
HXVRMS
HXIRMS
HXWATT
HXVAR
HXVA
HXPF
HXVHD
HXIHD
HYVRMS
HYIRMS
HYWATT
HYVAR
HYVA
HYPF
HYVHD
HYIHD
HZVRMS
HZIRMS
HZWATT
HZVAR
HZVA
HZPF
HZVHD
HZIHD
HXVRMS
HXIRMS
HXVHD
HXIHD
HYVRMS
HYIRMS
HYVHD
HYIHD
HZVRMS
HZIRMS
HZVHD
HZIHD
OUTPUT REGISTERS
USED WHEN NEUTRAL
CURRENT IS ANALYZED
ISUM
IN
ISUM
IN
RESULTS RESULTS RESULTS RESULTS
HRATE BITS HCONFIG[7:5] SELECT THE
UPDATE RATE OF HARMONIC
REGISTERS
10193-057
HSTIME BITS HCONFIG[4,3] SELECT
THE DELAY IN TRIGGERING HREADY
INTERRUPT
HRCFG BIT HCONFIG[0] SELECTS IF
HREADY FLAG IN STATUS0 IS SET
IMMEDIATELY OF AFTER HSTIME
Figure 82. ADE7880 Harmonic Engine Block Diagram
When the neutral current and the sum of the three phase
currents represented by ISUM register are analyzed, the
following metering quantities are computed for both currents:
•
•
RMS of fundamental and of up to 2 harmonics or rms of
up to three harmonics: Ix, Iy, Iz, x, y, z = 1,2, 3,…, N.
Harmonic distortions of the analyzed harmonics.
Configuring the Harmonic Calculations
The ADE7880 requires a time base provided by a phase voltage.
Bit 9 and Bit 8 (ACTPHSEL) of HCONFIG[15:0]register select
this phase voltage. If ACTPHSEL = 00, the phase A is used. If
ACTPHSEL = 01, the Phase B is used and if ACTPHSEL = 10,
the Phase C is used. If the phase voltage used as time base is
down, select another phase, and the harmonic engine continues
to work properly.
The phase under analysis is selected by Bit 2 and Bit 1
(HPHASE) of HCONFIG[15:0]register. If HPHASE = 00, the
Phase A is monitored. If HPHASE = 01, the Phase B is
monitored and if HPHASE = 10, the Phase C is monitored. If
HPHASE = 11, the neutral current together with the sum of the
phase currents represented by ISUM register are monitored.
Harmonic Calculations When a Phase is Monitored
When a phase is monitored, fundamental information together
with information about up to three harmonics is computed. The
indexes of the three additional harmonics simultaneously
monitored by the ADE7880 are provided by the 8-bit registers
HX, HY, and HZ. Simply write the index of the harmonic into
the register for that harmonic to be monitored. If the second
harmonic is monitored, write 2. If harmonic 51 is desired, write
51. The fundamental components are always monitored,
independent of the values written into HX, HY, or HZ.
Therefore, if one of these registers is made equal to 1, the
ADE7880 monitors the fundamental components multiple times.
The maximum index allowed in HX, HY, and HZ registers is 63.
The no attenuation pass band is 2.8 kHz, corresponding to a −3
dB bandwidth of 3.3 kHz, thus all harmonics of frequency lower
than 2800 Hz are supported without attenuation.
The rms of the phase voltage and phase current fundamental
components are stored into FVRMS and FIRMS 24-bit signed
registers. The associated data path is presented in Figure 83.
Similar to the rms current and voltage rms data paths presented
in Root Mean Square Measurement section, the data path
contains 24-bit signed offset compensation registers xIRMSOS,
xVRMSOS, x = A, B, C for each phase quantity. The rms of the
phase current and phase voltage three harmonic components
are stored into HXVRMS, HXIRMS, HYVRMS, HYIRMS,
HZVRMS, and HZIRMS 24-bit signed registers. The associated
data path is presented in Figure 84 and contains the following
24-bit signed offset compensation registers: HXIRMSOS,
HYIRMSOS, HZIRMSOS, HXVRMSOS, HYVRMSOS, and
HZVRMSOS.
It is recommended to leave the offset compensation registers at
0, the default value.
Rev. A | Page 58 of 104
Data Sheet
ADE7880
Table 20. Harmonic Engine Outputs When Phase A, Phase B, or Phase C is Analyzed and the Registers Where the Values are Stored
Quantity
RMS of the Fundamental Component
RMS of a Harmonic Component
Active Power of the Fundamental Component
Active Power of a Harmonic Component
Reactive Power of the Fundamental Component
Reactive Power of a Harmonic Component
Apparent Power of the Fundamental Component
Apparent Power of a Harmonic Component
Definition
V1, I1
Vx, Ix, x = 2, 3,…, N
Vy, Iy, y = 2, 3,…, N
Vz , Iz, z = 2, 3,…, N
P1 = V1I1cos(φ1 − γ1)
Px = VxIxcos(φx – γx), x = 2, 3,…, N
Py = VyIycos(φy – γy), y = 2, 3,…, N
Pz = VzIzcos(φz – γz), z = 2, 3,…, N
Q1 = V1I1sin(φ1 − γ1)
Qx = VxIxsin(φ1 − γ1), x = 2, 3,…, N
Qy = VyIysin(φy – γy), y = 2, 3,…, N
Qz = VzIzsin(φz – γz), z = 2, 3,…, N
S1 = V1I1
Sx = VxIx, x = 2, 3, …, N
Sy = VyIy, y = 2, 3, …, N
Sz = VzIz, z = 2, 3, …, N
ADE7880 Register
FVRMS, FIRMS
HXVRMS, HXIRMS
HYVRMS, HYIRMS
HZVRMS, HZIRMS
FWATT
HXWATT
HYWATT
HZWATT
FVAR
HXVAR
HYVAR
HZVAR
FVA
HXVA
HYVA
HZVA
FPF
Power Factor of the Fundamental Component
pf1 = sgn(Q1 ) ×
P1
S1
Power Factor of a Harmonic Component
pf x = sgn(Qx ) ×
Px
, x = 2, 3,…, N
Sx
HXPF
Py
HYPF
( )
pf y = sgn Q y ×
Sy
pf z = sgn(Qz ) ×
Total Harmonic Distortion
Harmonic Distortion of a Harmonic Component
, y = 2, 3,…, N
Pz
, z = 2, 3,…, N
Sz
HZPF
VTHD
V 2 − V12
(THD )V
=
(THD)I
=
HDVx =
Vx
I
, HDI x = x , x = 2, 3,…, N
V1
I1
HXVHD, HXIHD
HDV y =
Vy
Iy
HYVHD, HYIHD
HDV z =
I
Vz
, HDI z = z ,z = 2, 3,…, N
V1
I1
V1
V1
ITHD
I 2 − I12
I1
, HDI y =
Rev. A | Page 59 of 104
I1
,y = 2, 3,…, N
HZVHD, HZIHD
ADE7880
Data Sheet
Table 21. Harmonic Engine Outputs when Neutral Current and ISUM are Analyzed and the Registers Where the Values are Stored
Quantity
RMS of a Harmonic Component (Including the Fundamental) of the Neutral Current
RMS of a Harmonic Component (Including the Fundamental) of ISUM
Harmonic Distortion of a Harmonic Component (Including the Fundamental) of the
Neutral Current (Note that the HX Register Must be Set to 1 for These Calculations to be
Executed)
Definition
Ix, x = 1,2, 3,…, N
Iy, y = 1,2, 3,…, N
Iz, z = 1,2, 3,…, N
ISUMx, x = 1,2,3,…,N
ISUMy, y = 1,2,3,…,N
ISUMz, z = 1,2,3,…,N
HDI x =
HDI y =
HDI z =
Harmonic Distortion of a Harmonic Component (Including the Fundamental) of ISUM.
(Note that the HX Register Must be Set to 1 for These Calculations to be Executed)
Ix
I1 , x = 1,2,3,…,N
Iy
ADE7880
Register
HXIRMS
HYIRMS
HZIRMS
HXVRMS
HYVRMS
HZVRMS
HXIHD
HYIHD
I1 , y = 1,2,3,…,N
Iz
I1 , z = 1,2,3,…,N
HZIHD
ISUM x
ISUM1 ,
HXVHD
HDISUM x =
x = 1,2,3,…,N
HDISUM y =
ISUM y
ISUM 1
HYVHD
,
y = 1,2,3,…,N
HDISUM z =
ISUM z
,
ISUM 1
z = 1,2,3,…,N
Rev. A | Page 60 of 104
HZVHD
Data Sheet
ADE7880
HPHASE BITS
HCONFIG[2, 1] SELECT THE
PHASE BEING MONITORED
AIRMSOS
27
BIRMSOS
27
FIRMS
CIRMSOS
HPHASE BITS
HCONFIG[2, 1] SELECT THE
GAIN BEING USED
27
FUNDAMENTAL
COMPONENTS
CALCULATIONS
APGAIN OR
BPGAIN OR
CPGAIN
HPHASE BITS
HCONFIG[2, 1] SELECT THE
PHASE BEING MONITORED
FVA
AVRMSOS
27
BVRMSOS
27
FVRMS
CVRMSOS
10193-058
27
Figure 83. Fundamental RMS Signal Processing
The active, reactive, and apparent powers of the fundamental
component are stored into the FWATT, FVAR, and FVA 24-bit
signed registers. Figure 85 presents the associated data path.
The active, reactive and apparent powers of the 3 harmonic
components are stored into the HXWATT, HXVAR, HXVA,
HYWATT, HYVAR, HYVA, HZWATT, HZVAR, and HZVA
24-bit signed registers. Figure 86 presents the associated data path.
The power factor of the fundamental component is stored into
FPF 24-bit signed register. The power factors of the three
harmonic components are stored into the HXPF, HYPF, and
HZPF 24-bit signed registers.
The total harmonic distortion ratios computed using the rms of
the fundamental components and the rms of the phase current
and the phase voltage (see Root Mean Square Chapter for
details about these measurements) are stored into the VTHD
and ITHD 24-bit registers in 3.21 signed format. This means
the ratios are limited to +3.9999 and all greater results are
clamped to it.
Rev. A | Page 61 of 104
ADE7880
Data Sheet
HXIRMSOS
27
HXIRMS
HYIRMSOS
27
HYIRMS
HZIRMSOS
HARMONIC
COMPONENTS
CALCULATIONS
27
HZIRMS
HXVRMSOS
27
HXVRMS
HYVRMSOS
27
HYVRMS
HXVRMSOS
HZVRMS
10193-059
27
Figure 84. Harmonic RMS Signal Processing
HPHASE BITS
HCONFIG[2, 1] SELECT THE
PHASE BEING MONITORED
APGAIN
AFWATTOS
22
÷
BPGAIN
BFWATTOS
22
÷
FUNDAMENTAL
COMPONENTS
CALCULATIONS
CPGAIN
CFWATTOS
FWATT
22
÷
HPHASE BITS
HCONFIG[2, 1] SELECT THE
PHASE BEING MONITORED
APGAIN
AFVAROS
22
÷
BFVAROS
22
÷
CPGAIN
CFVAROS
FVAR
22
÷
10193-060
BPGAIN
Figure 85. Fundamental Active and Reactive Powers Signal Processing
Rev. A | Page 62 of 104
Data Sheet
ADE7880
HXWATTOS
22
÷
HPGAIN
HYWATTOS
22
÷
HARMONIC
COMPONENTS
CALCULATIONS
HPGAIN
HZWATTOS
HXVAROS
HYVAROS
HZVAROS
HXVAR
22
÷
HPGAIN
HZWATT
22
÷
HPGAIN
HYWATT
22
÷
HPGAIN
HXWATT
HYVAR
22
÷
HZVAR
10193-061
HPGAIN
Figure 86. Harmonic Active and Reactive Powers Signal Processing
The harmonic distortions of the three harmonic components
are stored into the HXVHD, HXIHD, HYVHD, HYIHD,
HZVHD, and HZIHD 24-bit registers in 3.21 signed format.
This means the ratios are limited to +3.9999 and all greater
results are clamped to it.
As a reference, Table 20 presents the ADE7880 harmonic engine
outputs when one phase is analyzed and the registers in which
the outputs are stored.
Harmonic Calculations When the Neutral is Monitored
When the neutral current and the sum of phase currents are
monitored, only the harmonic rms related registers are updated.
The registers HX, HY and HZ identify the index of the harmonic,
including the fundamental. When a phase is analyzed, the
fundamental rms values are calculated continuously and the
results are stored in dedicated registers FIRMS and FVRMS.
When the neutral is analyzed, the fundamental information is
calculated by setting one of the harmonic index registers HX,
HY or HZ to 1 and the results are stored in harmonic registers.
The maximum index allowed in HX, HY and HZ registers is 63.
The no attenuation pass band is 2.8 kHz, corresponding to a
−3 dB bandwidth of 3.3 kHz, thus all harmonics of frequency
lower than 2800 Hz are supported without attenuation.
HXIRMS, HYIRMS and HZIRMS registers contain the harmonic
rms components of the neutral current and HXVRMS, HYVRMS
and HZVRMS registers contain the harmonic rms components
of ISUM. Note that in this case, the rms of the fundamental
component is not computed into FIRMS or FVRMS registers,
but it is computed if one of the index registers HX, HY and HZ
is initialized with 1.
If the HX register is initialized to 1, the ADE7880 computes the
harmonic distortions of the other harmonics identified into HY
and HZ registers and stores them in 3.21 signed format into the
HYVHD, HYIHD, HZVHD, and HZIHD 24-bit registers. The
distortions of the neutral current are saved into HYIHD and
HZIHD registers and the distortions of the ISUM are stored
into the HYVHD and HZVHD registers. As HX is set to 1, the
HXIHD and HXVHD registers contain 0x1FFFFF, a number
representing 1 in 3.21 signed format.
As a reference, Table 21 presents the ADE7880 harmonic engine
outputs when the neutral current and ISUM are analyzed and
the registers in which the outputs are stored.
Configuring Harmonic Calculations Update Rate
The ADE7880 harmonic engine functions at 8 kHz rate. From
the moment the HCONFIG register is initialized and the
harmonic indexes are set in the HX, HY and HZ index registers,
the ADE7880 calculations take typically 750 ms to settle within
the specification parameters.
The update rate of the harmonic engine output registers is
managed by Bits[7:5] (HRATE) in HCONFIG register and is
independent of the engine’s calculations rate of 8 kHz. The default
value of 000 means the registers are updated every 125 μsec
(8 kHz rate). Other update periods are: 250 μsec (HRATE =
001), 1 ms (010), 16 ms (011), 128 ms (100), 512 ms (101),
1.024 sec (110). If HRATE bits are 111, then the harmonic
calculations are disabled.
The ADE7880 provides two ways to manage the harmonic
computations. The first approach, enabled when Bit 0 (HRCFG)
of HCONFIG register is cleared to its default value of 0, sets Bit
19 (HREADY) in STATUS0 register to 1 after a certain period
of time and then every time the harmonic calculations are updated
at HRATE frequency. This allows an external microcontroller to
access the harmonic calculations only after they have settled.
The time period is determined by the state of Bits[4:3] (HSTIME)
in the HCONFIG register. The default value of 01 sets the time
Rev. A | Page 63 of 104
ADE7880
Data Sheet
to 750 ms, the settling time of the harmonic calculations. Other
possible values are 500 ms (HSTIME = 00), 1 sec (10) and 1250
ms (11).
The second approach, enabled when Bit 0 (HRCFG) of
HCONFIG register is set to 1, sets Bit 19 (HREADY) in
STATUS0 register to 1 every time the harmonic calculations are
updated at the update frequency determined by HRATE bits
without waiting for the harmonic calculations to settle. This
allows an external microcontroller to access the harmonic
calculations immediately after they have been started. If the
corresponding mask bit in the MASK0 interrupt mask register
is enabled, the IRQ pin also goes active low. The status bit is
cleared and the pin IRQ is set to high again by writing to the
STATUS0 register with the corresponding bit set to 1.
Additionally, the ADE7880 provides a periodical output signal
called HREADY at the CF2/HREADY pin synchronous to the
moment the harmonic calculations are updated in the harmonic
registers. This functionality is chosen if Bit 2 (CF2DIS) is set to
1 in the CONFIG register. If CF2DIS is set to 0 (default value),
the CF2 energy to frequency converter output is provided at
CF2/HREADY pin. The default state of this signal is high. Ever y
time the harmonic registers are updated based on HRATE bits
in HCONFIG register, the signal HREADY goes low for
approximately 10 μsec and then goes back high. If Bit 0
(HRCFG) in the HCONFIG register is 0, that is the HREADY
bit in the STATUS1 register is set to 1 every HRATE period
right after the harmonic calculations have started, the signal
HREADY toggles high, low and back synchronously. If the
HRCFG bit is 1, that is, Bit HREADY in the STATUS1 register
is set to 1 after the HSTIME period, the HREADY signal toggles
high, low and back synchronously. The HREADY signal allows
fast access to the harmonic registers without having to use
HREADY interrupt in MASK1 register.
In order to facilitate the fast reading of the registers in which
the harmonic calculations are stored, a special burst registers
reading has been implemented in the serial interfaces. See the
I2C Read Operation of Harmonic Calculations Registers and the
SPI Read Operation sections for details.
•
Initialize the gain registers used in the harmonic
calculations. Leave the offset registers to 0.
•
Read the registers in which the harmonic information is
stored using the burst or regular reading mode at high to
low transitions of CF2/HREADY pin.
WAVEFORM SAMPLING MODE
The waveform samples of the current and voltage waveform,
the active, reactive, and apparent power outputs are stored
every 125 μs (8 kHz rate) into 24-bit signed registers that can be
accessed through various serial ports of the ADE7880. Table 22
provides a list of registers and their descriptions.
Table 22. Waveform Registers List
Register
IAWV
VAWV
IBWV
VBWV
ICWV
VCWV
INWV
AVA
BVA
CVA
AWATT
BWATT
CWATT
Description
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Phase C current
Phase C voltage
Neutral current
Phase A apparent power
Phase B apparent power
Phase C apparent power
Phase A active power
Phase B active power
Phase C active power
Bit 17 (DREADY) in the STATUS0 register can be used to
signal when the registers listed in Table 22 can be read using
I2C or SPI serial ports. An interrupt attached to the flag can be
enabled by setting Bit 17 (DREADY) in the MASK0 register. (see
the Digital Signal Processor section for more details on
Bit DREADY).
The ADE7880 contains a high speed data capture (HSDC) port
that is specially designed to provide fast access to the waveform
sample registers. Read the HSDC Interface section for more
details.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
All registers listed in Table 22 are transmitted signed extended
from 24 bits to 32 bits (see Figure 44).
Recommended Approach to Managing Harmonic
Calculations
The recommended approach to managing the ADE7880
harmonic calculations is the following:
•
Set up Bit 2 (CF2DIS) in the CONFIG register. Set the
CF2DIS bit to 1 to use the CF2/HREADY pin to signal
when the harmonic calculations have settled and are
updated. The high to low transition of HREADY signal
indicates when to read the harmonic registers. Use the
burst reading mode to read the harmonic registers as it is
the most efficient way to read them.
•
Choose the harmonics to be monitored by setting HX, HY
and HZ appropriately.
•
Select all the HCONFIG register bits.
ENERGY-TO-FREQUENCY CONVERSION
The ADE7880 provides three frequency output pins: CF1, CF2,
and CF3. The CF2 pin is multiplexed with the HREADY pin of
the harmonic calculations block. When HREADY is enabled,
the CF2 functionality is disabled at the pin. The CF3 pin is
multiplexed with the HSCLK pin of the HSDC interface. When
HSDC is enabled, the CF3 functionality is disabled at the pin.
CF1 pin is always available. After initial calibration at manufacturing, the manufacturer or end customer verifies the energy
meter calibration. One convenient way to verify the meter
calibration is to provide an output frequency proportional to the
Rev. A | Page 64 of 104
Data Sheet
ADE7880
active, reactive, or apparent powers under steady load conditions.
This output frequency can provide a simple, single-wire,
optically isolated interface to external calibration equipment.
Figure 87 illustrates the energy-to-frequency conversion in the
ADE7880.
The DSP computes the instantaneous values of all phase powers:
total active, fundamental active, fundamental reactive, and
apparent. The process in which the energy is sign accumulated
in various xWATTHR, xFVARHR, and xVAHR registers has
already been described in the energy calculation sections: Active
Energy Calculation, Fundamental Reactive Energy Calculation,
and Apparent Energy Calculation. In the energy-to-frequency
conversion process, the instantaneous powers generate signals
at the frequency output pins (CF1, CF2, and CF3). One digitalto-frequency converter is used for every CFx pin. Every converter
sums certain phase powers and generates a signal proportional
to the sum. Two sets of bits decide what powers are converted.
First, Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),
and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register
decide which phases, or which combination of phases, are added.
The TERMSEL1 bits refer to the CF1 pin, the TERMSEL2 bits
refer to the CF2 pin, and the TERMSEL3 bits refer to the CF3
pin. The TERMSELx[0] bits manage Phase A. When set to 1,
Phase A power is included in the sum of powers at the CFx
converter. When cleared to 0, Phase A power is not included.
The TERMSELx[1] bits manage Phase B, and the TERMSELx[2]
bits manage Phase C. Setting all TERMSELx bits to 1 means all
3-phase powers are added at the CFx converter. Clearing all
TERMSELx bits to 0 means no phase power is added and no
CF pulse is generated.
Second, Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and
Bits[8:6] (CF3SEL[2:0]) in the CFMODE register decide what
type of power is used at the inputs of the CF1, CF2, and CF3
converters, respectively. Table 23 shows the values that CFxSEL
can have: total active, apparent, fundamental active, or fundamental
reactive powers.
Table 23. CFxSEL Bits Description
CFxSEL
000
001
010
011
100
101 to 111
Description
CFx signal proportional to the sum of total phase active powers
Reserved
CFx signal proportional to the sum of phase apparent powers
CFx signal proportional to the sum of fundamental phase active
powers
CFx signal proportional to the sum of fundamental phase reactive
powers
Reserved
Rev. A | Page 65 of 104
Registers Latched When CFxLATCH = 1
AWATTHR, BWATTHR, CWATTHR
AVAHR, BVAHR, CVAHR
AFWATTHR, BFWATTHR, CFWATTHR
AFVARHR, BFVARHR, CFVARHR
ADE7880
Data Sheet
By default, the TERMSELx bits are all 1 and the CF1SEL bits are
000, the CF2SEL bits are 100, and the CF3SEL bits are 010. This
means that by default, the CF1 digital-to-frequency converter
produces signals proportional to the sum of all 3-phase total
active powers, CF2 produces signals proportional to fundamental
reactive powers, and CF3 produces signals proportional to
apparent powers.
CFxDEN =
103
MC[imp/kwh] × 10n
(49)
The derivative of wh must be chosen in such a way to obtain a
CFxDEN register content greater than 1. If CFxDEN = 1, then
the CFx pin stays active low for only 1 μs. Thus, CFxDEN
register should not be set to 1. The frequency converter cannot
accommodate fractional results; the result of the division must be
rounded to the nearest integer. If CFxDEN is set equal to 0, then
the ADE7880 considers it to be equal to 1.
Similar to the energy accumulation process, the energy-tofrequency conversion is accomplished in two stages. The first
stage is the same stage illustrated in the energy accumulation
sections of active, reactive and apparent powers (see Active
Energy Calculation, Fundamental Reactive Energy Calculation,
Apparent Energy Calculation sections). The second stage
consists of the frequency divider by the CFxDEN 16-bit
unsigned registers. The values of CFxDEN depend on the meter
constant (MC), measured in impulses/kWh and how much
energy is assigned to one LSB of various energy registers:
xWATTHR, xFVARHR, and so forth. Suppose a derivative of
Wh [10n Wh] where n is a positive or negative integer, is desired
as one LSB of xWATTHR register. Then, CFxDEN is as follows:
The CFx pulse output stays low for 80 ms if the pulse period is
larger than 160 ms (6.25 Hz). If the pulse period is smaller than
160 ms and CFxDEN is an even number, the duty cycle of the
pulse output is exactly 50%. If the pulse period is smaller than
160 ms and CFxDEN is an odd number, the duty cycle of the
pulse output is
(1+1/CFxDEN) × 50%
TERMSELx BITS IN
COMPMODE
INSTANTANEOUS
PHASE A
ACTIVE POWER
CFxSEL BITS IN
CFMODE
VA
27
WATT
INTERNAL
ACCUMULATOR
FWATT
INSTANTANEOUS
PHASE C
ACTIVE POWER
DIGITAL SIGNAL
PROCESSOR
REVPSUMx BIT OF
STATUS0[31:0]
FREQ DIVIDER
FVAR
THRESHOLD
34
27 26
WTHR
CFx PULSE
OUTPUT
CFxDEN
0
27
0
Figure 87. Energy-to-Frequency Conversion
Rev. A | Page 66 of 104
10193-062
INSTANTANEOUS
PHASE B
ACTIVE POWER
Data Sheet
ADE7880
The CFx pulse output is active low and preferably connected to
an LED, as shown in Figure 88.
Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the
CFMODE register enable this process when set to 1. When
cleared to 0, the default state, no latch occurs. The process is
available even if the CFx output is not enabled by the CFxDIS
bits in the CFMODE register.
VDD
CFx PIN
10193-063
Energy Registers and CF Outputs for Various
Accumulation Modes
Figure 88. CFx Pin Recommended Connection
Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE
register decide if the frequency converter output is generated at
the CF3, CF2, or CF1 pin. When Bit CFxDIS is set to 1 (the
default value), the CFx pin is disabled and the pin stays high.
When Bit CFxDIS is cleared to 0, the corresponding CFx pin
output generates an active low signal.
Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask register
MASK0 manage the CF3, CF2, and CF1 related interrupts.
When the CFx bits are set, whenever a high-to-low transition at
the corresponding frequency converter output occurs, an
interrupt IRQ0 is triggered and a status bit in the STATUS0
register is set to 1. The interrupt is available even if the CFx
output is not enabled by the CFxDIS bits in the CFMODE
register.
ACTIVE ENERGY
The ADE7880 contains a feature that allows synchronizing the
content of phase energy accumulation registers with the
generation of a CFx pulse. When a high-to-low transition at one
frequency converter output occurs, the content of all internal
phase energy registers that relate to the power being output at
CFx pin is latched into hour registers and then resets to 0.
See Table 23 for the list of registers that are latched based on
the CFxSEL[2:0] bits in the CFMODE register. All 3-phase
registers are latched independent of the TERMSELx bits of the
COMPMODE register. The process is shown in Figure 89 for
CF1SEL[2:0] = 010 (apparent powers contribute at the CF1 pin)
and CFCYC = 2.
The CFCYC 8-bit unsigned register contains the number of
high to low transitions at the frequency converter output between
two consecutive latches. Avoid writing a new value into the
CFCYC register during a high-to-low transition at any CFx pin.
AVAHR, BVAHR,
CVAHR LATCHED
ENERGY REGISTERS
RESET
AVAHR, BVAHR,
CVAHR LATCHED
ENERGY REGISTERS
RESET
Figure 89. Synchronizing AVAHR and BVAHR with CF1
10193-064
CFCYC = 2
NO-LOAD
THRESHOLD
ACTIVE POWER
NO-LOAD
THRESHOLD
REVAPx BIT
IN STATUS0
xWSIGN BIT
IN PHSIGN
APNOLOAD
SIGN = POSITIVE
POS
NEG POS
NEG
10193-065
Synchronizing Energy Registers with CFx Outputs
CF1 PULSE
BASED ON
PHASE A AND
PHASE B
APPARENT
POWERS
Bits[1:0] (WATTACC[1:0]) in the ACCMODE register determine the accumulation modes of the total and fundamental active
powers when signals proportional to the active powers are chosen
at the CFx pins (the CFxSEL[2:0] bits in the CFMODE register
equal 000 or 011). They also determine the accumulation modes
of the watt-hour energy registers (AWATTHR, BWATTHR,
CWATTHR, AFWATTHR, BFWATTHR and CFWATTHR).
When WATTACC[1:0] = 00 (the default value), the active powers
are sign accumulated in the watt-hour registers and before entering
the energy-to-frequency converter. Figure 90 shows how signed
active power accumulation works. In this mode, the CFx pulses
synchronize perfectly with the active energy accumulated in
xWATTHR registers because the powers are sign accumulated in
both data paths.
Figure 90. Active Power Signed Accumulation Mode
When WATTACC[1:0] = 01, the active powers are accumulated
in positive only mode. When the powers are negative, the watthour energy registers are not accumulated. CFx pulses are
generated based on signed accumulation mode. In this mode,
the CFx pulses do not synchronize perfectly with the active
energy accumulated in xWATTHR registers because the powers are
accumulated differently in each data path. Figure 91 shows how
positive only active power accumulation works.
WATTACC[1:0] = 10 setting is reserved and the ADE7880
behaves identically to the case when WATTACC[1:0] = 00.
When WATTACC[1:0] = 11, the active powers are accumulated
in absolute mode. When the powers are negative, they change
sign and accumulate together with the positive power in the
watt-hour registers and before entering the energy-to-frequency
Rev. A | Page 67 of 104
ADE7880
Data Sheet
converter. In this mode, the CFx pulses synchronize perfectly
with the active energy accumulated in xWATTHR registers because
the powers are accumulated in the same way in both data paths.
Figure 92 shows how absolute active power accumulation works.
ACTIVE ENERGY
NO-LOAD
THRESHOLD
ACTIVE ENERGY
NO-LOAD
THRESHOLD
NO-LOAD
THRESHOLD
ACTIVE POWER
REVAPx BIT
IN STATUS0
NO-LOAD
THRESHOLD
xWSIGN BIT
IN PHSIGN
REVAPx BIT
IN STATUS0
APNOLOAD
SIGN = POSITIVE
xWSIGN BIT
IN PHSIGN
POS
NEG POS
NEG
10193-067
ACTIVE POWER
POS
NEG POS NEG
Figure 91. Active Power Positive Only Accumulation Mode
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine the
accumulation modes of the fundamental reactive powers when
signals proportional to the fundamental reactive powers are
chosen at the CFx pins (the CFxSEL[2:0] bits in the CFMODE
register equal 100). When VARACC[1:0] = 00, the default value,
the fundamental reactive powers are sign accumulated in the
var-hour energy registers and before entering the energy-tofrequency converter. Figure 93 shows how signed fundamental
reactive power accumulation works. In this mode, the CFx
pulses synchronize perfectly with the fundamental reactive
energy accumulated in the xFVARHR registers because the
powers are sign accumulated in both data paths.
VARACC[1:0] = 01 setting is reserved and ADE7880 behaves
identically to the case when VARACC[1:0] = 00.
When VARACC[1:0] = 10, the fundamental reactive powers are
accumulated depending on the sign of the corresponding active
power in the var-hour energy registers and before entering the
energy-to-frequency converter. If the fundamental active power
is positive or considered 0 when lower than the no load threshold,
the fundamental reactive power is accumulated as is. If the
fundamental active power is negative, the sign of the fundamental
reactive power is changed for accumulation. Figure 94 shows how
the sign adjusted fundamental reactive power accumulation
mode works. In this mode, the CFx pulses synchronize perfectly
with the fundamental reactive energy accumulated in xFVARHR
registers because the powers are accumulated in the same way in
both data paths.
REACTIVE
ENERGY
NO-LOAD
THRESHOLD
REACTIVE
POWER
NO-LOAD
THRESHOLD
REVRPx BIT
IN STATUS0
xVARSIGN BIT
IN PHSIGN
VARNOLOAD
SIGN = POSITIVE
POS
NEG POS
NEG
10193-068
APNOLOAD
SIGN = POSITIVE
10193-066
Figure 92. Active Power Absolute Accumulation Mode
Figure 93. Fundamental Reactive Power Signed Accumulation Mode
When VARACC[1:0] = 11, the fundamental reactive powers are
accumulated in absolute mode. When the powers are negative,
they change sign and accumulate together with the positive
power in the var-hour registers. CFx pulses are generated based
on signed accumulation mode. In this mode, the CFx pulses do
not synchronize perfectly with the fundamental reactive energy
accumulated in x VARHR registers because the powers are
accumulated differently in each data path. Figure 95 shows how
absolute fundamental reactive power accumulation works.
Sign of Sum-of-Phase Powers in the CFx Datapath
The ADE7880 has sign detection circuitry for the sum of phase
powers that are used in the CFx data path. As seen in the
beginning of the Energy-to-Frequency Conversion section, the
energy accumulation in the CFx data path is executed in two
stages. Every time a sign change is detected in the energy
accumulation at the end of the first stage, that is, after the
Rev. A | Page 68 of 104
Data Sheet
ADE7880
energy accumulated into the accumulator reaches one of the
WTHR, VARTHR, or VATHR thresholds, a dedicated interrupt
can be triggered synchronously with the corresponding CFx
pulse. The sign of each sum can be read in the PHSIGN register.
REACTIVE
ENERGY
NO-LOAD
THRESHOLD
REACTIVE
POWER
NO-LOAD
THRESHOLD
indicate the sign of the sum of phase powers. When cleared to
0, the sum is positive. When set to 1, the sum is negative.
Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,
REVPSUM2, and REVPSUM1, respectively) in the STATUS0
register are enabled by setting Bit 18, Bit 13, and Bit 9 in the
MASK0 register. If enabled, the IRQ0 pin is set low, and the
status bit is set to 1 whenever a change of sign occurs. To find
the phase that triggered the interrupt, the PHSIGN register is
read immediately after reading the STATUS0 register. Next, the
status bit is cleared, and the IRQ0 pin is set high again by writing
to the STATUS0 register with the corresponding bit set to 1.
NO LOAD CONDITION
NO-LOAD
THRESHOLD
The no load condition is defined in metering equipment standards
as occurring when the voltage is applied to the meter and no current flows in the current circuit. To eliminate any creep effects in
the meter, the ADE7880 contains three separate no load
detection circuits: one related to the total active power, one
related to the fundamental active and reactive powers, and one
related to the apparent powers.
ACTIVE
POWER
xVARSIGN BIT
IN PHSIGN
VARNOLOAD
SIGN = POSITIVE
POS
NEG POS
10193-069
REVRPx BIT
IN STATUS0
No Load Detection Based On Total Active Power and
Apparent Power
Figure 94. Fundamental Reactive Power Accumulation in Sign
Adjusted Mode
This no load condition uses the total active energy and the
apparent energy to trigger this no load condition. The apparent
energy is proportional to the rms values of the corresponding
phase current and voltage. If neither total active energy nor
apparent energy are accumulated for a time indicated in the
respective APNOLOAD and VANOLOAD unsigned 16-bit
registers, the no load condition is triggered, the total active
energy of that phase is not accumulated and no CFx pulses are
generated based on the total active energy.
REACTIVE ENERGY
NO-LOAD
THRESHOLD
The equations used to compute the APNOLOAD and
VANOLOAD unsigned 16-bit values are
REACTIVE POWER
NO-LOAD
THRESHOLD
APNOLOAD = 216 −
REVAPx BIT
IN STATUS0
VANOLOAD = 216 −
VARNOLOAD
SIGN = POSITIVE
POS
NEG POS NEG
10193-070
xVARSIGN BIT
IN PHSIGN
Figure 95. Fundamental Reactive Power Accumulation in Absolute Mode
Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and
REVPSUM1, respectively) of the STATUS0 register are set
to 1 when a sign change of the sum of powers in CF3, CF2,
or CF1 data paths occurs. To correlate these events with the
pulses generated at the CFx pins, after a sign change occurs,
Bit REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 are set
in the same moment in which a high-to-low transition at the
CF3, CF2, and CF1 pin, respectively, occurs.
Y ×WTHR × 217
PMAX
Y ×VATHR × 217
PMAX
(50)
where:
Y is the required no load current threshold computed relative to
full scale. For example, if the no load threshold current is set
10,000 times lower than full scale value, then Y = 10,000.
WTHR and VATHR represent values stored in the WTHR and
VATHR registers and are used as the thresholds in the first stage
energy accumulators for active and apparent energy, respectively
(see Active Energy Calculation section). PMAX = 27,059,678 =
0x19CE5DE, the instantaneous active power computed when
the ADC inputs are at full scale.
Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and SUM1SIGN,
respectively) of the PHSIGN register are set in the same moment
with Bit REVPSUM3, Bit REVPSUM2, and Bit EVPSUM1 and
Rev. A | Page 69 of 104
ADE7880
Data Sheet
The VANOLOAD register usually contains the same value
as the APNOLOAD register. When APNOLOAD and
VANOLOAD are set to 0x0, the no load detection circuit
is disabled. If only VANOLOAD is set to 0, then the no load
condition is triggered based only on the total active power
being lower than APNOLOAD. In the same way, if only
APNOLOAD is set to 0x0, the no load condition is triggered
based only on the apparent power being lower than VANOLOAD.
Bit 0 (NLOAD) in the STATUS1 register is set when a no load
condition in one of the three phases is triggered. Bits[2:0]
(NLPHASE[2:0]) in the PHNOLOAD register indicate the state
of all phases relative to a no load condition and are set simultaneously with Bit NLOAD in the STATUS1 register. NLPHASE[0]
indicates the state of Phase A, NLPHASE[1] indicates the state
of Phase B, and NLPHASE[2] indicates the state of Phase C.
When Bit NLPHASE[x] is cleared to 0, it means the phase is out
of a no load condition. When set to 1, it means the phase is in a
no load condition.
An interrupt attached to Bit 0 (NLOAD) in the STATUS1
register can be enabled by setting Bit 0 in the MASK1 register.
If enabled, the IRQ1 pin is set to low, and the status bit is set
to 1 whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Next, the status bit is cleared, and the IRQ1
pin is set to high by writing to the STATUS1 register with the
corresponding bit set to 1.
No Load Detection Based on Fundamental Active and
Reactive Powers
This no load condition is triggered when no less significant bits
are accumulated into the fundamental active and reactive energy
registers on one phase (xFWATTHR and xFVARHR, x = A, B,
or C) for a time indicated in the respective APNOLOAD and
VARNOLOAD unsigned 16-bit registers. In this case, the
fundamental active and reactive energies of that phase are not
accumulated and no CFx pulses are generated based on these
energies. APNOLOAD is the same no load threshold set for
the total active powers. The VARNOLOAD register usually
contains the same value as the APNOLOAD register. If only
APNOLOAD is set to 0x0, then the fundamental active power
is accumulated without restriction. In the same way, if only
VARNOLOAD is set to 0x0, the fundamental reactive power is
accumulated without restriction.
Bit 1 (FNLOAD) in the STATUS1 register is set when this no
load condition in one of the three phases is triggered. Bits[5:3]
(FNLPHASE[2:0]) in the PHNOLOAD register indicate the
state of all phases relative to a no load condition and are set
simultaneously with Bit FNLOAD in the STATUS1 register.
FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]
indicates the state of Phase B, and FNLPHASE[2] indicates the
state of Phase C. When Bit FNLPHASE[x] is cleared to 0, it
means the phase is out of the no load condition. When set to 1,
it means the phase is in a no load condition.
An interrupt attached to the Bit 1 (FNLOAD) in the STATUS1
register can be enabled by setting Bit 1 in the MASK1 register. If
enabled, the IRQ1 pin is set low and the status bit is set to 1
whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Then the status bit is cleared and the IRQ1
pin is set back high by writing to the STATUS1 register with the
corresponding bit set to 1.
No Load Detection Based on Apparent Power
This no load condition is triggered when no less significant bits
are accumulated into the apparent energy register on one phase
(xVAHR, x = A, B, or C) for a time indicated by the VANOLOAD
unsigned 16-bit register. In this case, the apparent energy of that
phase is not accumulated and no CFx pulses are generated based
on this energy.
The equation used to compute the VANOLOAD unsigned
16-bit value is
VANOLOAD = 216 −
Y ×VATHR × 217
PMAX
(51)
where:
Y is the required no load current threshold computed relative to
full scale. For example, if the no load threshold current is set
10,000 times lower than full scale value, then Y=10,000.
VATHR is the VATHR register used as the threshold of the first
stage energy accumulator (see Apparent Energy Calculation
section) PMAX = 27,059,678 = 0x19CE5DE, the instantaneous
apparent power computed when the ADC inputs are at full
scale. When the VANOLOAD register is set to 0x0, the no load
detection circuit is disabled.
Bit 2 (VANLOAD) in the STATUS1 register is set when this no
load condition in one of the three phases is triggered. Bits[8:6]
(VANLPHASE[2:0]) in the PHNOLOAD register indicate the
state of all phases relative to a no load condition and they are set
simultaneously with Bit VANLOAD in the STATUS1 register:
•
•
•
Bit VANLPHASE[0] indicates the state of Phase A.
Bit VANLPHASE[1] indicates the state of Phase B.
Bit VANLPHASE[2] indicates the state of Phase C.
When Bit VANLPHASE[x] is cleared to 0, it means the phase is
out of no load condition. When set to 1, it means the phase is in
no load condition.
An interrupt attached to Bit 2 (VANLOAD) in the STATUS1
register is enabled by setting Bit 2 in the MASK1 register. If
enabled, the IRQ1 pin is set low and the status bit is set to 1
whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Next, the status bit is cleared, and the IRQ1
pin is set to high by writing to the STATUS1 register with the
corresponding bit set to 1.
Rev. A | Page 70 of 104
Data Sheet
ADE7880
•
CHECKSUM REGISTER
The ADE7880 has a checksum 32-bit register, CHECKSUM, that
ensures the configuration registers maintain their desired value
during Normal Power Mode PSM0.
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 +
(52)
x5 + x4 + x2 + x + 1
The registers covered by this register are MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,
all registers located in the DSP data memory RAM between
Address 0x4380 and Address 0x43BE and another eight 8-bit
reserved internal registers that always have default values. The
ADE7880 computes the cyclic redundancy check (CRC) based
on the IEEE802.3 standard. The registers are introduced one-byone into a linear feedback shift register (LFSR) based generator
starting with the least significant bit (as shown in Figure 96).
The 32-bit result is written in the CHECKSUM register. After
power-up or a hardware/software reset, the CRC is computed
on the default values of the registers giving a result equal to
0xAFFA63B9.
g0 = g1 = g2 = g4 = g5 = g7 = 1
g8 = g10 = g11 = g12 = g16 = g22 = g26 = 1
FB(j) = aj – 1 XOR b31(j − 1)
(54)
b0(j) = FB(j) AND g0
(55)
bi(j) = FB(j) AND gi XOR bi – 1(j – 1), i = 1, 2, 3, ..., 31
(56)
Equation 54, Equation 55, and Equation 56 must be repeated for
j = 1, 2, …, 2272. The value written into the CHECKSUM register
contains the Bit bi(2272), i = 0, 1, …, 31.
Every time a configuration register of the ADE7880 is written or
changes value inadvertently, the Bit 25 (CRC) in STATUS1 register
is set to 1 to signal CHECKSUM value has changed. If Bit 25 (CRC)
in MASK1 register is set to 1, then the IRQ1 interrupt pin is driven
low and the status flag CRC in STATUS1 is set to 1. The status bit is
cleared and the IRQ1 pin is set to high by writing to the STATUS1
register with the status bit set to 1.
0
10193-071
When Bit CRC in STATUS1 is set to 1 without any register
being written, it can be assumed that one of the registers has
changed value and therefore, the ADE7880 has changed
configuration. The recommended response is to initiate a
hardware/software reset that sets the values of all registers to the
default, including the reserved ones, and then reinitialize the
configuration registers.
bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that
form the CRC. Bit b0 is the least significant bit, and Bit b31
is the most significant.
2271
LFSR
GENERATOR
ARRAY OF 2272 BITS
Figure 96. CHECKSUM Register Calculation
g0
g1
g2
g3
g31
FB
b0
b1
(53)
All of the other gi coefficients are equal to 0.
Figure 97 shows how the LFSR works: the MASK0, MASK1,
COMPMODE, Gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG
registers, the registers located between Address 0x4380, and
Address 0x43BE and the eight 8-bit reserved internal registers
form the bits [a2271, a2270,…, a0] used by LFSR. Bit a0 is the least
significant bit of the first register to enter LFSR; Bit a2271 is the
most significant bit of the last register to enter LFSR. The
formulas that govern LFSR are as follows:
b2
b31
LFSR
a1767, a1766,....,a2, a1, a0
Figure 97. LFSR Generator Used in CHECKSUM Register Calculation
Rev. A | Page 71 of 104
10193-072
•
gi, i = 0, 1, 2, …, 31 are the coefficients of the generating
polynomial defined by the IEEE802.3 standard as follows:
ADE7880
Data Sheet
INTERRUPTS
The ADE7880 has two interrupt pins, IRQ0 and IRQ1. Each of the
pins is managed by a 32-bit interrupt mask register, MASK0 and
MASK1, respectively. To enable an interrupt, a bit in the MASKx
register must be set to 1. To disable it, the bit must be cleared
to 0. Two 32-bit status registers, STATUS0 and STATUS1, are
associated with the interrupts. When an interrupt event occurs
in the ADE7880, the corresponding flag in the interrupt status
register is set to a logic 1 (see Table 36 and Table 37). If the mask
bit for this interrupt in the interrupt mask register is logic 1,
then the IRQx logic output goes active low. The flag bits in the
interrupt status register are set irrespective of the state of the mask
bits. To determine the source of the interrupt, the MCU should
perform a read of the corresponding STATUSx register and
identify which bit is set to 1. To erase the flag in the status register,
write back to the STATUSx register with the flag set to 1. After an
interrupt pin goes low, the status register is read and the source of
the interrupt is identified. Then, the status register is written back
without any change to clear the status flag to 0. The IRQx pin
remains low until the status flag is cancelled.
By default, all interrupts are disabled. However, the RSTDONE
interrupt is an exception. This interrupt can never be masked
(disabled) and, therefore, Bit 15 (RSTDONE) in the MASK1
register does not have any functionality. The IRQ1 pin always
goes low, and Bit 15 (RSTDONE) in the STATUS1 register is set
to 1 whenever a power-up or a hardware/software reset process
ends. To cancel the status flag, the STATUS1 register has to be
written with Bit 15 (RSTDONE) set to 1.
Certain interrupts are used in conjunction with other status
registers. The following bits in the MASK1 register work in
conjunction with the status bits in the PHNOLOAD register:
•
•
•
Bit 0 (NLOAD)
Bit 1 (FNLOAD)
Bit 2 (VANLOAD)
Bit 16, (SAG)
Bit 17 (OI)
Bit 18 (OV)
The following bits in the MASK1 register work with the status bits
in the IPEAK and VPEAK registers, respectively:
•
•
Bit 23 (PKI)
Bit 24 (PKV)
When the STATUSx register is read and one of these bits is set
to 1, the status register associated with the bit is immediately
read to identify the phase that triggered the interrupt and only
at that time can the STATUSx register be written back with the bit
set to 1.
Using the Interrupts with an MCU
Figure 98 shows a timing diagram that illustrates a suggested
implementation of the ADE7880 interrupt management using an
MCU. At Time t1, the IRQx pin goes active low indicating that
one or more interrupt events have occurred in the ADE7880, at
which point the following steps should be taken:
1.
2.
3.
4.
5.
The following bits in the MASK1 register work with the status bits
in the PHSTATUS register:
•
•
•
The following bits in the MASK0 register work with the status bits
in the PHSIGN register:
• Bits[6:8] (REVAPx)
• Bits[10:12] (REVRPx)
• Bit 9, Bit 13, and Bit 18 (REVPSUMx)
Tie the IRQx pin to a negative-edge-triggered external
interrupt on the MCU.
On detection of the negative edge, configure the MCU to
start executing its interrupt service routine (ISR).
On entering the ISR, disable all interrupts using the global
interrupt mask bit. At this point, the MCU external
interrupt flag can be cleared to capture interrupt events
that occur during the current ISR.
When the MCU interrupt flag is cleared, a read from
STATUSx, the interrupt status register, is carried out. The
interrupt status register content is used to determine the
source of the interrupt(s) and, hence, the appropriate
action to be taken.
The same STATUSx content is written back into the
ADE7880 to clear the status flag(s) and reset the IRQx line
to logic high (t2).
If a subsequent interrupt event occurs during the ISR (t3), that
event is recorded by the MCU external interrupt flag being
set again.
On returning from the ISR, the global interrupt mask bit is
cleared (same instruction cycle) and the external interrupt flag
uses the MCU to jump to its ISR once again. This ensures that
the MCU does not miss any external interrupts.
Figure 99 shows a recommended timing diagram when the
status bits in the STATUSx registers work in conjunction with
bits in other registers. When the IRQx pin goes active low, the
STATUSx register is read, and if one of these bits is 1, a second
status register is read immediately to identify the phase that
triggered the interrupt. The name, PHx, in Figure 99 denotes
one of the PHSTATUS, IPEAK, VPEAK, or PHSIGN registers.
Then, STATUSx is written back to clear the status flag(s).
Rev. A | Page 72 of 104
Data Sheet
ADE7880
t1
t2
MCU
INTERRUPT
FLAG SET
t3
PROGRAM
SEQUENCE
GLOBAL
INTERRUPT
MASK
JUMP
TO ISR
CLEAR MCU
INTERRUPT
FLAG
READ
STATUSx
WRITE
BACK
STATUSx
ISR ACTION
(BASED ON STATUSx CONTENTS)
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
JUMP
TO ISR
10193-073
IRQx
Figure 98. Interrupt Management
t1
t2
t3
MCU
INTERRUPT
FLAG SET
PROGRAM
SEQUENCE
JUMP
TO ISR
GLOBAL
INTERRUPT
MASK
CLEAR MCU
INTERRUPT
FLAG
READ
STATUSx
READ
PHx
WRITE
BACK
STATUSx
ISR RETURN
ISR ACTION
JUMP
(BASED ON STATUSx CONTENTS) GLOBAL INTERRUPT TO ISR
MASK RESET
10193-074
IRQx
Figure 99. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved
SERIAL INTERFACES
The ADE7880 has three serial port interfaces: one fully licensed
I2C interface, one serial peripheral interface (SPI), and one high
speed data capture port (HSDC). As the SPI pins are multiplexed
with some of the pins of the I2C and HSDC ports, the ADE7880
accepts two configurations: one using the SPI port only and one
using the I2C port in conjunction with the HSDC port.
Serial Interface Choice
After reset, the HSDC port is always disabled. Choose between
the I2C and SPI ports by manipulating the SS/has pin after
power-up or after a hardware reset. If the SS/HSA pin is kept
high, then the ADE7880 uses the I2C port until a new hardware
reset is executed. If the SS/HSA pin is toggled high to low three
times after power-up or after a hardware reset, the ADE7880
uses the SPI port until a new hardware reset is executed. This
manipulation of the SS/HSA pin can be accomplished in two
ways. First, use the SS/HSA pin of the master device (that is, the
microcontroller) as a regular I/O pin and toggle it three times.
Second, execute three SPI write operations to a location in the
address space that is not allocated to a specific ADE7880 register
(for example 0xEBFF, where eight bit writes can be executed).
These writes allow the SS/HSA pin to toggle three times. See the
SPI Write Operation section for details on the write protocol
involved.
After the serial port choice is completed, it needs to be locked.
Consequently, the active port remains in use until a hardware
reset is executed in PSM0 normal mode or until a power-down.
If I2C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2
register must be set to 1 to lock it in. From this moment, the
ADE7880 ignores spurious toggling of the SS pin and an eventual
switch into using the SPI port is no longer possible. If the SPI is
the active serial port, any write to the CONFIG2 register locks
the port. From this moment, a switch into using the I2C port is
no longer possible. Once locked, the serial port choice is
maintained when the ADE7880 changes PSMx power modes.
read using either the I2C or SPI interfaces. The HSDC port
provides the state of up to 16 registers representing instantaneous
values of phase voltages and neutral currents, and active, reactive,
and apparent powers.
Communication Verification
The ADE7880 includes a set of three registers that allow any
communication via I2C or SPI to be verified. The LAST_OP
(Address 0xEA01), LAST_ADD (Address 0xE9FE) and
LAST_RWDATA registers record the nature, address and data
of the last successful communication respectively. The
LAST_RWDATA register has three separate addresses
depending on the length of the successful communication.
Table 24. LAST_RWDATA Register Locations
Communication type
8-Bit Read/Write
16-Bit Read/Write
24-Bit Read/Write
Address
0xE7FD
0xE9FF
0xE5FF
After each successful communication with the ADE7880, the
address of the register that was last accessed is stored in the
16-bit LAST_ADD register (Address 0xE9FE). This is a read
only register that stores the value until the next successful read
or write is complete. The LAST_OP register (Address 0xEA01)
stores the nature of the operation. That is, it indicates whether a
read or a write was performed. If the last operation is a write,
the LAST_OP register stores the value 0xCA. If the last
operation is a read, the LAST_OP register stores the value 0x35.
The LAST_RWDATA register stores the data that was written
or read from the register. Any unsuccessful read or write
operation is not reflected in these registers.
When LAST_OP, LAST_ADD and LAST_RWDATA registers
are read, their values are not stored into themselves.
The functionality of the ADE7880 is accessible via several onchip registers. The contents of these registers can be updated or
Rev. A | Page 73 of 104
ADE7880
Data Sheet
I2C-Compatible Interface
I2C Write Operation
2
The ADE7880 supports a fully licensed I C interface. The I C
interface is implemented as a full hardware slave. SDA is the
data I/O pin, and SCL is the serial clock. These two pins are
shared with the MOSI and SCLK pins of the on-chip SPI
interface. The maximum serial clock frequency supported by this
interface is 400 kHz.
The write operation using the I2C interface of the ADE7880
initiate when the master generates a start condition and consists
in one byte representing the address of the ADE7880 followed
by the 16-bit address of the target register and by the value of
the register.
The most significant seven bits of the address byte constitute
the address of the ADE7880 and they are equal to 0111000b.
Bit 0 of the address byte is a read/write bit. Because this is a
write operation, it has to be cleared to 0; therefore, the first byte
of the write operation is 0x70. After every byte is received, the
ADE7880 generates an acknowledge. As registers can have 8, 16,
or 32 bits, after the last bit of the register is transmitted and the
ADE7880 acknowledges the transfer, the master generates a
stop condition. The addresses and the register content are sent
with the most significant bit first. See Figure 100 for details of
the I2C write operation.
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND’ed format that allows arbitration in a multimaster
system.
START
The transfer sequence of an I2C system consists of a master device
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition, and the bus
becomes idle.
15
8
7
0
31
24
23
16
15
8
7
STOP
2
0
ACK GENERATED
BY ADE7880
Figure 100. I2C Write Operation of a 32-Bit Register
Rev. A | Page 74 of 104
BYTE 1 OF REGISTER
BYTE 0 (LESS
SIGNIFICANT) OF
REGISTER
10193-075
BYTE 2 OF REGISTER
ACK
BYTE 3 (MOST
SIGNIFICANT)
OF REGISTER
ACK
LESS SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
ACK
SLAVE ADDRESS
ACK
S
ACK
S 0 1 1 1 0 0 0 0
Data Sheet
ADE7880
I2C Read Operation
with the master generating a new start condition followed by an
address byte. The most significant seven bits of this address byte
constitute the address of the ADE7880, and they are equal to
0111000b. Bit 0 of the address byte is a read/write bit. Because this
is a read operation, it must be set to 1; thus, the first byte of the
read operation is 0x71. After this byte is received, the ADE7880
generates an acknowledge. Then, the ADE7880 sends the value
of the register, and after every eight bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. Because registers can have 8, 16, or 32 bits,
after the last bit of the register is received, the master does not
acknowledge the transfer but generates a stop condition.
The read operation using the I2C interface of the ADE7880 is
accomplished in two stages. The first stage sets the pointer to
the address of the register. The second stage reads the content of
the register.
START
As seen in Figure 101, the first stage initiates when the master
generates a start condition and consists in one byte representing
the address of the ADE7880 followed by the 16-bit address of the
target register. The ADE7880 acknowledges every byte received.
The address byte is similar to the address byte of a write operation
and is equal to 0x70 (see the I2C Write Operation section for
details). After the last byte of the register address has been sent
and acknowledged by the ADE7880, the second stage begins
15
8
7
0
LESS SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
SLAVE ADDRESS
ACK
S 0 1 1 1 0 0 0 0
1
1
0
0
0 1
ACK
SLAVE ADDRESS
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER
7
8
0
BYTE 2 OF
REGISTER
BYTE 1 OF
REGISTER
STOP
15
16
S
BYTE 0
(LESS SIGNIFICANT)
OF REGISTER
10193-076
1
23
ACK
0
24
ACK
S
31
ACK
START
ACKNOWLEDGE
GENERATED BY
MASTER
NOACK
ACK GENERATED
BY ADE7880
ACK GENERATED
BY ADE7880
START
Figure 101. I2C Read Operation of a 32-Bit Register
8
15
7
0
LESS SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
SLAVE ADDRESS
ACK
S 0 1 1 1 0 0 0 0
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER 0
BYTE 0
(LESS SIGNIFICANT)
OF REGISTER 0
0
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER 1
STOP
7
ACK
24
S
BYTE 0
(LESS SIGNIFICANT)
OF REGISTER n
10193-077
SLAVE ADDRESS
31
0
ACK
S 0 1 1 1 0 0 0 1
7
24
ACK
31
ACK
START
ACKNOWLEDGE
GENERATED BY
MASTER
NOACK
ACK GENERATED
BY ADE7880
ACK GENERATED
BY ADE7880
Figure 102. I2C Read Operation of n 32-Bit Harmonic Calculations Registers
Rev. A | Page 75 of 104
ADE7880
Data Sheet
The registers containing the harmonic calculation results are
located starting at Address 0xE880 and are all 32-bit width.
They can be read in two ways: one register at a time (see the I2C
Read Operation section for details) or multiple consecutive
registers at a time in a burst mode. This burst mode is
accomplished in two stages. As seen in Figure 102, the first
stage sets the pointer to the address of the register and is
identical to the first stage executed when only one register is
read. The second stage reads the content of the registers. The
second stage begins with the master generating a new start
condition followed by an address byte equal to the address byte
used when one single register is read, 0x71. After this byte is
received, the ADE7880 generates an acknowledge. Then, the
ADE7880 sends the value of the first register located at the
pointer, and after every eight bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. After the bytes of the first register are sent, if
the master acknowledges the last byte, the ADE7880 increments
the pointer by one location to position it at the next register and
begins to send it out byte by byte, most significant bit first. If the
master acknowledges the last byte, the ADE7880 increments the
pointer again and begins to send data from the next register.
The process continues until the master ceases to generate an
acknowledge at the last byte of the register and then generates a
stop condition. It is recommended to not allow locations greater
then 0xE89F, the last location of the harmonic calculations
registers.
SPI-Compatible Interface
The SPI of the ADE7880 is always a slave of the communication
and consists of four pins (with dual functions): SCLK/SCL,
MOSI/SDA, MISO/HSD, and SS/HSA. The functions used in
the SPI-compatible interface are SCLK, MOSI, MISO, and SS.
The serial clock for a data transfer is applied at the SCLK logic
input. All data transfer operations synchronize to the serial
clock. Data shifts into the ADE7880 at the MOSI logic input
on the falling edge of SCLK and the ADE7880 samples it on
the rising edge of SCLK. Data shifts out of the ADE7880 at
the MISO logic output on a falling edge of SCLK and can be
sampled by the master device on the raising edge of SCLK. The
most significant bit of the word is shifted in and out first. The
maximum serial clock frequency supported by this interface
is 2.5 MHz. MISO stays in high impedance when no data is
transmitted from the ADE7880. See Figure 103 for details of the
connection between the ADE7880 SPI and a master device
containing an SPI interface.
The SS logic input is the chip select input. This input is used
when multiple devices share the serial bus. Drive the SS input
low for the entire data transfer operation. Bringing SS high
during a data transfer operation aborts the transfer and places
the serial bus in a high impedance state. A new transfer can
then be initiated by returning the SS logic input to low.
However, because aborting a data transfer before completion
leaves the accessed register in a state that cannot be guaranteed,
every time a register is written, its value should be verified by
reading it back. The protocol is similar to the protocol used in
I2C interface.
ADE7880
SPI DEVICE
MOSI
MOSI
MISO
MISO
SCLK
SCK
SS
SS
10193-078
I2C Read Operation of Harmonic Calculations Registers
Figure 103. Connecting ADE7880 SPI with an SPI Device
SPI Read Operation
The read operation using the SPI interface of the ADE7880
initiate when the master sets the SS/HSA pin low and begins
sending one byte, representing the address of the ADE7880, on
the MOSI line. The master sets data on the MOSI line starting
with the first high-to-low transition of SCLK. The SPI of the
ADE7880 samples data on the low-to-high transitions of SCLK.
The most significant seven bits of the address byte can have any
value, but as a good programming practice, they should be
different from 0111000b, the seven bits used in the I2C protocol.
Bit 0 (read/write) of the address byte must be 1 for a read
operation. Next, the master sends the 16-bit address of the
register that is read. After the ADE7880 receives the last bit of
address of the register on a low-to-high transition of SCLK, it
begins to transmit its contents on the MISO line when the next
SCLK high-to-low transition occurs; thus, the master can
sample the data on a low-to-high SCLK transition. After the
master receives the last bit, it sets the SS and SCLK lines high
and the communication ends. The data lines, MOSI and MISO,
go into a high impedance state. See Figure 104 for details of the
SPI read operation.
Rev. A | Page 76 of 104
Data Sheet
ADE7880
SS
SCLK
15 14
0 0 0 0 0 0 0 1
REGISTER ADDRESS
31 30
MISO
1 0
10193-079
MOSI
1 0
REGISTER VALUE
Figure 104. SPI Read Operation of a 32-Bit Register
SS
SCLK
0 0 0 0 0 0 0 1
REGISTER
ADDRESS
31
0
REGISTER 0
VALUE
MISO
31
0
REGISTER n
VALUE
10193-080
MOSI
Figure 105. SPI Read Operation of n 32-Bit Harmonic Calculations Registers
SPI Read Operation of Harmonic Calculations Registers
The registers containing the harmonic calculation results are
located starting at Address 0xE880 and are all 32-bit width.
They can be read in two ways: one register at a time (see the SPI
Read Operation section for details) or multiple consecutive
registers at a time in a burst mode. The burst mode initiates
when the master sets the SS/HSA pin low and begins sending
one byte, representing the address of the ADE7880, on the
MOSI line. The address is the same address byte used for
reading only one register. The master sets data on the MOSI line
starting with the first high-to-low transition of SCLK. The SPI
of the ADE7880 samples data on the low-to-high transitions of
SCLK. Next, the master sends the 16-bit address of the first
harmonic calculations register that is read. After the ADE7880
receives the last bit of the address of the register on a low-tohigh transition of SCLK, it begins to transmit its contents on the
MISO line when the next SCLK high-to-low transition occurs;
thus, the master can sample the data on a low-to-high SCLK
transition. After the master receives the last bit of the first
register, the ADE7880 sends the harmonic calculations register
placed at the next location and so forth until the master sets the
SS and SCLK lines high and the communication ends. The data
lines, MOSI and MISO, go into a high impedance state. See
Figure 105 for details of the SPI read operation of harmonic
calculations registers.
SPI Write Operation
The write operation using the SPI interface of the ADE7880
initiates when the master sets the SS/HSA pin low and begins
sending one byte representing the address of the ADE7880 on
the MOSI line. The master sets data on the MOSI line starting
with the first high-to-low transition of SCLK. The SPI of the
ADE7880 samples data on the low-to-high transitions of SCLK.
The most significant seven bits of the address byte can have any
value, but as a good programming practice, they should be
different from 0111000b, the seven bits used in the I2C protocol.
Bit 0 (read/write) of the address byte must be 0 for a write
operation. Next, the master sends both the 16-bit address of the
register that is written and the 32-, 16-, or 8-bit value of that
register without losing any SCLK cycle. After the last bit is
transmitted, the master sets the SS and SCLK lines high at the
end of the SCLK cycle and the communication ends. The data
lines, MOSI and MISO, go into a high impedance state. See
Figure 106 for details of the SPI write operation.
Rev. A | Page 77 of 104
ADE7880
Data Sheet
SS
SCLK
MOSI
0 0 0 0 0 0 0 0
1 0 31 30
REGISTER ADDRESS
1 0
REGISTER VALUE
10193-081
15 14
Figure 106. SPI Write Operation of a 32-Bit Register
HSDC Interface
The high speed data capture (HSDC) interface is disabled after
default. It can be used only if the ADE7880 is configured with an
I2C interface. The SPI interface of ADE7880 cannot be used at
the same time with HSDC.
Bit 6 (HSDCEN) in the CONFIG register activates HSDC when
set to 1. If Bit HSDCEN is cleared to 0, the default value, the
HSDC interface is disabled. Setting Bit HSDCEN to 1 when SPI
is in use does not have any effect. HSDC is an interface for
sending to an external device (usually a microprocessor or a
DSP) up to sixteen 32-bit words. The words represent the
instantaneous values of the phase currents and voltages, neutral
current, and active, reactive, and apparent powers. The registers
being transmitted include IAWV, VAWV, IBWV, VBWV, ICWV,
VCWV, AVA, INWV, BVA, CVA, AWATT, BWATT, CWATT,
AFVAR, BFVAR, and CFVAR. All are 24-bit registers that are
sign extended to 32-bits (see Figure 44 for details).
HSDC can be interfaced with SPI or similar interfaces. HSDC is
always a master of the communication and consists of three
pins: HSA, HSD, and HSCLK. HSA represents the select signal.
It stays active low or high when a word is transmitted and it is
usually connected to the select pin of the slave. HSD sends data
to the slave and it is usually connected to the data input pin of
the slave. HSCLK is the serial clock line that is generated by the
ADE7880 and it is usually connected to the serial clock input of
the slave. Figure 107 shows the connections between the
ADE7880 HSDC and slave devices containing an SPI interface.
HSD
HSCLK
HSA
SPI DEVICE
MISO
SCK
SS
10193-082
ADE7880
Figure 107. Connecting the ADE7880 HSDC with an SPI
The HSDC communication is managed by the HSDC_CFG
register (see Table 52). It is recommended to set the HSDC_CFG
register to the desired value before enabling the port using Bit 6
(HSDCEN) in the CONFIG register. In this way, the state of
various pins belonging to the HSDC port do not take levels inconsistent with the desired HSDC behavior. After a hardware reset
or after power-up, the MISO/HSD and SS/HSA pins are set high.
Bit 0 (HCLK) in the HSDC_CFG register determines the serial
clock frequency of the HSDC communication. When HCLK is
0 (the default value), the clock frequency is 8 MHz. When HCLK
is 1, the clock frequency is 4 MHz. A bit of data is transmitted
for every HSCLK high-to-low transition. The slave device that
receives data from HSDC samples the HSD line on the low-tohigh transition of HSCLK.
The words can be transmitted as 32-bit packages or as 8-bit
packages. When Bit 1 (HSIZE) in the HSDC_CFG register is 0 (the
default value), the words are transmitted as 32-bit packages. When
Bit HSIZE is 1, the registers are transmitted as 8-bit packages. The
HSDC interface transmits the words MSB first.
Bit 2 (HGAP) introduces a gap of seven HSCLK cycles between
packages when Bit 2 (HGAP) is set to 1. When Bit HGAP is
cleared to 0 (the default value), no gap is introduced between
packages and the communication time is shortest. In this case,
HSIZE does not have any influence on the communication and
a data bit is placed on the HSD line with every HSCLK high-tolow transition.
Bits[4:3] (HXFER[1:0]) decide how many words are transmitted.
When HXFER[1:0] is 00, the default value, then all 16 words are
transmitted. When HXFER[1:0] is 01, only the words representing
the instantaneous values of phase and neutral currents and phase
voltages are transmitted in the following order: IAWV, VAWV,
IBWV, VBWV, ICWV, VCWV, and one 32-bit word that is always
equal to INWV. When HXFER[1:0] is 10, only the instantaneous
values of phase powers are transmitted in the following order:
AVA, BVA, CVA, AWATT, BWATT, CWATT, AFVAR, BFVAR,
and CFVAR. The value, 11, for HXFER[1:0] is reserved and
writing it is equivalent to writing 00, the default value.
Bit 5 (HSAPOL) determines the polarity of HSA function of the
SS/HSA pin during communication. When HSAPOL is 0 (the
default value), HSA is active low during the communication.
This means that HSA stays high when no communication is in
progress. When a communication is executed, HSA is low when
the 32-bit or 8-bit packages are transferred, and it is high during
the gaps. When HSAPOL is 1, the HSA function of the SS/HSA
pin is active high during the communication. This means that
HSA stays low when no communication is in progress. When a
communication is executed, HSA is high when the 32-bit or
8-bit packages are transferred, and it is low during the gaps.
Bits[7:6] of the HSDC_CFG register are reserved. Any value
written into these bits does not have any consequence on HSDC
behavior.
Rev. A | Page 78 of 104
Data Sheet
ADE7880
Figure 108 shows the HSDC transfer protocol for HGAP = 0,
HXFER[1:0] = 00 and HSAPOL = 0. Note that the HSDC
interface sets a data bit on the HSD line every HSCLK high-tolow transition and the value of Bit HSIZE is irrelevant.
Figure 109 shows the HSDC transfer protocol for HSIZE = 0,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 32-bit word.
Figure 110 shows the HSDC transfer protocol for HSIZE = 1,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 8-bit word.
See Table 52 for the HSDC_CFG register and descriptions for
the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.
Table 25 lists the time it takes to execute an HSDC data transfer
for all HSDC_CFG register settings. For some settings, the
transfer time is less than 125 μs (8 kHz), the waveform sample
registers update rate. This means the HSDC port transmits data
every sampling cycle. For settings in which the transfer time is
greater than 125 μs, the HSDC port transmits data only in the
first of two consecutive 8 kHz sampling cycles. This means it
transmits registers at an effective rate of 4 kHz.
Table 25. Communication Times for Various HSDC Settings
HXFER[1:0]
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
HCLK
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Communication Time (μs)
64
128
77.125
154.25
119.25
238.25
28
56
33.25
66.5
51.625
103.25
36
72
43
86
66.625
133.25
N/A means not applicable.
HSCLK
31
HSD
0 31
IAVW (32-BIT)
0 31
VAWV (32-BIT)
0
IBWV (32-BIT)
31
0
CFVAR (32-BIT)
10193-083
1
HSIZE 1
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
HGAP
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
HSA
Figure 108. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
Rev. A | Page 79 of 104
ADE7880
Data Sheet
HSCLK
31
0
IAVW (32-BIT)
31
7 HCLK
CYCLES
0
VAWV (32-BIT)
31
0
31
IBWV (32-BIT)
7 HCLK
CYCLES
0
CFVAR (32-BIT)
10193-084
HSDATA
HSA
Figure 109. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
HSCLK
31
24
IAVW (BYTE 3)
23
7 HCLK
CYCLES
16
IAVW (BYTE 2)
15
7 HCLK
CYCLES
IAVW (BYTE 1)
8
7
0
CFVAR (BYTE 0)
10193-085
HSDATA
HSA
Figure 110. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
ADE7880 QUICK SETUP AS ENERGY METER
5.
An energy meter is usually characterized by the nominal
current In, nominal voltage Vn, nominal frequency fn, and the
meter constant MC.
Initialize WTHR, VARTHR, VATHR, VLEVEL and
VNOM registers based Equation 26, Equation 37, Equation
44, Equation 22, and Equation 42, respectively.
6.
Enable the data memory RAM protection, by writing
0xAD to an internal 8-bit register located at Address
0xE7FE, followed by a write of 0x80 to an internal 8-bit
register located at Address 0xE7E3.
7.
Start the DSP by setting Run = 1.
To quickly set up the ADE7880, execute the following steps:
1.
2.
Select the PGA gains in the phase currents, voltages and
neutral current channels: Bits[2:0] (PGA1), Bits[5:3]
(PGA2) and Bits[8:6] (PGA3) in the Gain register.
If Rogowski coils are used, enable the digital integrators in
the phase or neutral currents channels: Bit 0 (INTEN) in
CONFIG register and Bit 3 (ININTEN) in CONFIG3
register.
For a quick setup of the ADE7880 harmonic calculations,
see the Recommended Approach to Managing Harmonic
Calculations section.
ADE7880 EVALUATION BOARD
3.
If fn = 60 Hz, set Bit 14 (SELFREQ) to 1 in the
COMPMODE register.
An evaluation board built upon the ADE7880 configuration
is available. Visit www.analog.com/ADE7880 for details.
4.
Initialize CF1DEN, CF2DEN, and CF3DEN registers based
in Equation 49.
DIE VERSION
The register named version identifies the version of the die.
It is an 8-bit, read-only register located at Address 0xE707.
Rev. A | Page 80 of 104
Data Sheet
ADE7880
SILICON ANOMALY
This anomaly list describes the known issues with the ADE7880 silicon identified by the Version register (Address 0xE707) being equal to 1.
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
ADE7880 FUNCTIONALITY ISSUES
Silicon Revision
Identifier
Version = 1
Chip Marking
ADE7880ACPZ
Silicon Status
Preliminary
Anomaly Sheet
Rev. A
No. of Reported Issues
4 (er001, er002, er003, er004)
FUNCTIONALITY ISSUES
Table 26. LAST_ADD Register Shows Wrong Value for Harmonic Calculations Registers in SPI Mode [er001, Version = 1 Silicon]
Background
Issue
Workaround
Related Issues
When any ADE7880 register is read using SPI or I2C communication, the address is stored in the LAST_ADD register
When the harmonic calculation registers located between Address 0xE880 and Address 0xE89F are read using SPI
communication, the LAST_ADD register contains the address of the register incremented by 1. The issue is not present if
the I2C communication is used.
If the LAST_ADD register is read after one of the registers located between Address 0xE880 and Address 0xE89F was read
using SPI communication, subtract 1 from it to recover the right address.
None.
Table 27. To Obtain Best Accuracy Performance, Internal Setting Must Be Changed [er002, Version = 1 Silicon]
Background
Issue
Workaround
Related Issues
Internal default settings provide best accuracy performance for ADE7880.
It was found that if a different setting is used, the accuracy performance can be improved.
To enable a new setting for this internal register, execute three consecutive write operations:
The first write operation is to an 8-bit location: 0xAD is written to Address 0xE7FE.
The second write operation is to a 16-bit location: 0x3BD is written to Address 0xE90C.
The third write operation is to an 8-bit location: 0x00 is written to Address 0xE7EF.
The write operations must be executed consecutively without any other read/write operation in between. As a
verification that the value was captured correctly, a simple 16-bit read of Address 0xE90C should show the 0x3BD value.
None.
Table 28. High-Pass Filter Cannot be Disabled in Phase C Voltage Data Path [er003, Version = 1 Silicon]
Background
Issue
Workaround
Related Issues
When Bit 0 (HPFEN) of the CONFIG3 register is 0, all high-pass filters (HPF) in the phase and neutral currents and phase
voltages data paths are disabled (see the ADE7880 data sheet for more information about the current channel HPF and
the voltage channel HPF).
The HPF in the Phase C voltage data path remains enabled independent of the state of Bit HPFEN.
There is no workaround.
None.
Rev. A | Page 81 of 104
ADE7880
Data Sheet
Table 29. No Load Condition Does Not Function as Defined [er004, Version = 1 Silicon]
Background
Issue
Workaround
Related Issues
Total active power no load uses the total active energy and the apparent energy to trigger the no load condition. If
neither total active energy nor apparent energy are accumulated for a time indicated in the respective APNOLOAD and
VANOLOAD unsigned, 16-bit registers, the no load condition is triggered, the total active energy of that phase is not
accumulated and no CF pulses are generated based on the total active energy.
Fundamental active and reactive powers no load uses the fundamental active and reactive energies to trigger the no load
condition. If neither the fundamental active energy nor the fundamental reactive energy are accumulated for a time
indicated in the respective APNOLOAD and VARNOLOAD unsigned 16-bit registers, the no load condition is triggered, the
fundamental active and reactive energies of that phase are not accumulated, and no CF pulses are generated based on
the fundamental active and reactive energies.
When the total active energy on Phase x (x = A, B, or C) is lower than APNOLOAD and the apparent energy is above
VANOLOAD, the no load condition should not be triggered. It was observed that although CF pulses continue to be
generated, the Bit 0 (NLOAD) and Bits[2:0] (NLPHASE) in STATUS1 and PHNOLOAD registers continue to be cleared to 0
indicating an out of no load condition, the xWATTHR register stops accumulating energy.
It was observed that the fundamental active energy no load functions independently of the fundamental reactive energy
no load. If, for example, the fundamental active energy is below APNOLOAD and the fundamental reactive energy is
above VARNOLOAD, both energies should continue to accumulate because the phase is out of no load condition. Instead,
the CF pulses, based on the phase fundamental active energy, are not generated and the FWATTHR registers are blocked,
while the CF pulses, based on the fundamental reactive energy, are generated. Thus, the FVARHR registers continue to
accumulate and the Bit 1 (FNLOAD) in the STATUS1 register and Bits[5:3] (FNLPHASE) in the PHNOLOAD register are
cleared to 0.
Because both no load conditions use the APNOLOAD threshold, a workaround for both issues is presented as follows:

Clear APNOLOAD and VARNOLOAD to 0.

Set VANOLOAD at desired value.
When the Phase x (x = A, B, or C) apparent energy becomes smaller then VANOLOAD, the Bit 2 (VANLOAD) in STATUS1 is
set to 1, together with one of the Bits[2:0] (VANLPHASE) in PHNOLOAD. Then, set APNOLOAD and VARNOLOAD equal to
VANOLOAD.
The Phase x (x = A, B, or C) total active energy enters no load condition.

CF pulses stop.

Bit 0 (NLOAD) in the STATUS1 register is set to 1.

One of the Bits[2:0], (NLPHASE[2:0]), in the PHNOLOAD register is set to 1.

The xWATTHR register stops accumulating energy.
The Phase x (x = A, B, or C) fundamental active and reactive energies enter no load condition.

CF pulses stop.

Bit 1 (FNLOAD) in the STATUS1 register is set to 1.

One of the Bits[5:3], (FNLPHASE[2:0]), in the PHNOLOAD register is set to 1.

The xFWATTHR and xVARHR registers stop accumulating energy.
None.
SECTION 1. ADE7880 FUNCTIONALITY ISSUES
Reference Number
er001
er002
er003
er004
Description
The LAST_ADD register shows the wrong value for the harmonic calculations registers in SPI mode.
To obtain the best accuracy performance, the internal setting must be changed.
The high-pass filter cannot be disabled in the Phase C voltage data path
The no load condition does not function as defined.
Rev. A | Page 82 of 104
Status
Identified
Identified
Identified
Identified
Data Sheet
ADE7880
REGISTERS LIST
Table 30. Registers Located in DSP Data Memory RAM
Address
0x4380
0x4381
0x4382
0x4383
0x4384
0x4385
0x4386
0x4387
Register
Name
AIGAIN
AVGAIN
BIGAIN
BVGAIN
CIGAIN
CVGAIN
NIGAIN
Reserved
R/W 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Length
24
24
24
24
24
24
24
24
Bit Length During
Communication 2
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
Type 3
S
S
S
S
S
S
S
S
Default Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x4388
DICOEFF
R/W
24
32 ZPSE
S
0x0000000
0x4389
0x438A
0x438B
0x438C
0x438D
0x438E
0x438F
0x4390
0x4391
0x4392
0x4393
0x4394
0x4395
0x43960x4397
0x4398
0x4399
APGAIN
AWATTOS
BPGAIN
BWATTOS
CPGAIN
CWATTOS
AIRMSOS
AVRMSOS
BIRMSOS
BVRMSOS
CIRMSOS
CVRMSOS
NIRMSOS
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
24
24
24
24
24
24
24
24
24
24
24
24
24
N/A
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
N/A
S
S
S
S
S
S
S
S
S
S
S
S
S
N/A
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
HPGAIN
ISUMLVL
R/W
R/W
24
24
32 ZPSE
32 ZPSE
S
S
0x000000
0x000000
0x439A0x439E
0x439F
Reserved
N/A
N/A
N/A
N/A
0x000000
VLEVEL
R/W
24
32 ZPSE
S
0x000000
0x43A00x43A1
0x43A2
0x43A3
0x43A4
0x43A5
0x43A6
0x43A7
0x43A8
0x43A9
0x43AA
0x43AB
0x43AC
0x43AD
0x43AE
Reserved
N/A
N/A
N/A
N/A
0x000000
AFWATTOS
BFWATTOS
CFWATTOS
AFVAROS
BFVAROS
CFVAROS
AFIRMSOS
BFIRMSOS
CFIRMSOS
AFVRMSOS
BFVRMSOS
CFVRMSOS
HXWATTOS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
24
24
24
24
24
24
24
24
24
24
24
24
24
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
S
S
S
S
S
S
S
S
S
S
S
S
S
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x43AF
HYWATTOS
R/W
24
32 ZPSE
S
0x000000
Rev. A | Page 83 of 104
Description
Phase A current gain adjust.
Phase A voltage gain adjust.
Phase B current gain adjust.
Phase B voltage gain adjust.
Phase C current gain adjust.
Phase C voltage gain adjust.
Neutral current gain adjust.
This location should not be written for proper
operation.
Register used in the digital integrator algorithm.
If the integrator is turned on, it must be set at
0xFF8000. In practice, it is transmitted as
0xFFF8000.
Phase A power gain adjust.
Phase A total active power offset adjust.
Phase B power gain adjust.
Phase B total active power offset adjust.
Phase C power gain adjust.
Phase C total active power offset adjust.
Phase A current rms offset.
Phase A voltage rms offset.
Phase B current rms offset.
Phase B voltage rms offset.
Phase C current rms offset.
Phase C voltage rms offset.
Neutral current rms offset.
These memory locations should not be written for
proper operation.
Harmonic powers gain adjust.
Threshold used in comparison between the sum
of phase currents and the neutral current.
These memory locations should not be written for
proper operation.
Register used in the algorithm that computes the
fundamental active and reactive powers.
These memory locations should not be written for
proper operation.
Phase A fundamental active power offset adjust.
Phase B fundamental active power offset adjust.
Phase C fundamental active power offset adjust.
Phase A fundamental reactive power offset adjust.
Phase B fundamental reactive power offset adjust.
Phase C fundamental reactive power offset adjust.
Phase A fundamental current rms offset.
Phase B fundamental current rms offset.
Phase C fundamental current rms offset.
Phase A fundamental voltage rms offset.
Phase B fundamental voltage rms offset.
Phase C fundamental voltage rms offset.
Active power offset adjust on harmonic X
(see Harmonics Calculations section for details).
Aactive power offset adjust on harmonic Y
(see Harmonics Calculations section for details).
ADE7880
Data Sheet
Address
0x43B0
Register
Name
HZWATTOS
R/W 1
R/W
Bit
Length
24
Bit Length During
Communication 2
32 ZPSE
Type 3
S
Default Value
0x000000
0x43B1
HXVAROS
R/W
24
32 ZPSE
S
0x000000
0x43B2
HYVAROS
R/W
24
32 ZPSE
S
0x000000
0x43B3
HZVAROS
R/W
24
32 ZPSE
S
0x000000
0x43B4
HXIRMSOS
R/W
24
32 ZPSE
S
0x000000
0x43B5
HYIRMSOS
R/W
24
32 ZPSE
S
0x000000
0x43B6
HZIRMSOS
R/W
24
32 ZPSE
S
0x000000
0x43B7
HXVRMSOS
R/W
24
32 ZPSE
S
0x000000
0x43B8
HYVRMSOS
R/W
24
32 ZPSE
S
0x000000
0x43B9
HZVRMSOS
R/W
24
32 ZPSE
S
0x000000
0x43BA
to
0x43BF
0x43C0
0x43C1
0x43C2
0x43C3
0x43C4
0x43C5
0x43C6
0x43C7
0x43C8
to
0x43FF
Reserved
N/A
N/A
N/A
N/A
0x000000
AIRMS
AVRMS
BIRMS
BVRMS
CIRMS
CVRMS
NIRMS
ISUM
Reserved
R
R
R
R
R
R
R
R
N/A
24
24
24
24
24
24
24
24
N/A
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
N/A
S
S
S
S
S
S
S
S
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Active power offset adjust on harmonic Z
(see Harmonics Calculations section for details).
Aactive power offset adjust on harmonic X
(see Harmonics Calculations section for details).
Active power offset adjust on harmonic Y
(see Harmonics Calculations section for details).
Aactive power offset adjust on harmonic Z
(see Harmonics Calculations section for details).
Current rms offset on harmonic X
(see Harmonics Calculations section for details).
Current rms offset on harmonic Y
(see Harmonics Calculations section for details).
Current rms offset on harmonic Z
(see Harmonics Calculations section for details).
Voltage rms offset on harmonic X
(see Harmonics Calculations section for details).
Voltage rms offset on harmonic Y
(see Harmonics Calculations section for details).
Voltage rms offset on harmonic Z
(see Harmonics Calculations section for details).
These memory locations should not be written for
proper operation.
Phase A current rms value.
Phase A voltage rms value.
Phase B current rms value.
Phase B voltage rms value.
Phase C current rms value.
Phase C voltage rms value.
Neutral current rms value.
Sum of IAWV, IBWV and ICWV registers.
These memory locations should not be written for
proper operation.
1
R is read, and W is write.
32 ZPSE = 24-bit signed register that is transmitted as a 32-bit word with four MSBs padded with 0s and sign extended to 28 bits. Whereas 32 ZP = 28- bit or 24-bit
signed or unsigned register that is transmitted as a 32-bit word with four or eight MSBs, respectively, padded with 0s.
3
U is unsigned register, and S is signed register in twos complement format.
2
Table 31. Internal DSP Memory RAM Registers
Address
0xE203
Register
Name
Reserved
0xE228
Run
1
2
R/W 1
R/W
Bit
Length
16
Bit Length
During
Communication
16
Type 2
U
Default
Value
0x0000
R/W
16
16
U
0x0000
R is read, and W is write.
U is unsigned register, and S is signed register in twos complement format.
Rev. A | Page 84 of 104
Description
This memory location should not be written for
proper operation.
Run register starts and stops the DSP. See the
Digital Signal Processor section for more details.
Data Sheet
ADE7880
Table 32. Billable Registers
R/W 1, 2
R
R
R
R
Bit
Length2
32
32
32
32
Bit Length
During
Communication2
32
32
32
32
Type2, 3
S
S
S
S
Default
Value
0x00000000
0x00000000
0x00000000
0x00000000
BFWATTHR
R
32
32
S
0x00000000
0xE405
CFWATTHR
R
32
32
S
0x00000000
0xE406
to
0xE408
0xE409
Reserved
R
32
32
S
0x00000000
AFVARHR
R
32
32
S
0x00000000
0xE40A
BFVARHR
R
32
32
S
0x00000000
0xE40B
CFVARHR
R
32
32
S
0x00000000
0xE40C
0xE40D
0xE40E
AVAHR
BVAHR
CVAHR
R
R
R
32
32
32
32
32
32
S
S
S
0x00000000
0x00000000
0x00000000
Address
0xE400
0xE401
0xE402
0xE403
Register
Name
AWATTHR
BWATTHR
CWATTHR
AFWATTHR
0xE404
1
2
3
Description
Phase A total active energy accumulation.
Phase B total active energy accumulation.
Phase C total active energy accumulation.
Phase A fundamental active energy
accumulation.
Phase B fundamental active energy
accumulation.
Phase C fundamental active energy
accumulation.
Phase A fundamental reactive energy
accumulation.
Phase B fundamental reactive energy
accumulation.
Phase C fundamental reactive energy
accumulation.
Phase A apparent energy accumulation.
Phase B apparent energy accumulation.
Phase C apparent energy accumulation.
R is read, and W is write.
N/A is not applicable.
U is unsigned register, and S is signed register in twos complement format.
Table 33. Configuration and Power Quality Registers
Bit Length
During
Communication 2
32
Type 3
U
Default
Value 4
N/A
Address
0xE500
Register Name
IPEAK
R/W 1
R
Bit
Length
32
0xE501
VPEAK
R
32
32
U
N/A
0xE502
0xE503
0xE504
STATUS0
STATUS1
AIMAV
R/W
R/W
R
32
32
20
32
32
32 ZP
U
U
U
N/A
N/A
N/A
0xE505
BIMAV
R
20
32 ZP
U
N/A
0xE506
CIMAV
R
20
32 ZP
U
N/A
0xE507
0xE508
0xE509
0xE50A
0xE50B
0xE50C
0xE50D
0xE50E
OILVL
OVLVL
SAGLVL
MASK0
MASK1
IAWV
IBWV
ICWV
R/W
R/W
R/W
R/W
R/W
R
R
R
24
24
24
32
32
24
24
24
32 ZP
32 ZP
32 ZP
32
32
32 SE
32 SE
32 SE
U
U
U
U
U
S
S
S
0xFFFFFF
0xFFFFFF
0x000000
0x00000000
0x00000000
N/A
N/A
N/A
Rev. A | Page 85 of 104
Description
Current peak register. See Figure 58 and
Table 34 for details about its
composition.
Voltage peak register. See Figure 58 and
Table 35 for details about its
composition.
Interrupt Status Register 0. See Table 36.
Interrupt Status Register 1. See Table 37.
Phase A current mean absolute value
computed during PSM0 and PSM1
modes.
Phase B current mean absolute value
computed during PSM0 and PSM1
modes.
Phase C current mean absolute value
computed during PSM0 and PSM1
modes.
Overcurrent threshold.
Overvoltage threshold.
Voltage SAG level threshold.
Interrupt Enable Register 0. See Table 38.
Interrupt Enable Register 1. See Table 39.
Instantaneous value of Phase A current.
Instantaneous value of Phase B current.
Instantaneous value of Phase C current.
ADE7880
Data Sheet
Bit Length
During
Communication 2
32 SE
32 SE
32 SE
32 SE
32 SE
Type 3
S
S
S
S
S
Default
Value 4
N/A
N/A
N/A
N/A
N/A
Address
0xE50F
0xE510
0xE511
0xE512
0xE513
Register Name
INWV
VAWV
VBWV
VCWV
AWATT
R/W 1
R
R
R
R
R
Bit
Length
24
24
24
24
24
0xE514
BWATT
R
24
32 SE
S
N/A
0xE515
CWATT
R
24
32 SE
S
N/A
0xE516 to
0xE518
0xE519
Reserved
R
24
32 SE
S
0x000000
AVA
R
24
32 SE
S
N/A
0xE51A
BVA
R
24
32 SE
S
N/A
0xE51B
CVA
R
24
32 SE
S
N/A
0xE51F
CHECKSUM
R
32
32
U
0xAFFA63B9
0xE520
VNOM
R/W
24
32 ZP
S
0x000000
0xE521 to
0xE5FE
0xE5FF
Reserved
LAST_RWDATA32
R
32
32
U
N/A
0xE600
0xE601
PHSTATUS
ANGLE0
R
R
16
16
16
16
U
U
N/A
N/A
0xE602
ANGLE1
R
16
16
U
N/A
0xE603
ANGLE2
R
16
16
U
N/A
0xE604 to
0xE607
0xE608
0xE609 to
0xE60B
0xE60C
0xE60D
0xE60E
0xE60F
0xE610
0xE611
0xE612
0xE613
0xE614
0xE615
0xE616
0xE617
0xE618
Reserved
PHNOLOAD
Reserved
R
16
16
U
N/A
LINECYC
ZXTOUT
COMPMODE
Gain
CFMODE
CF1DEN
CF2DEN
CF3DEN
APHCAL
BPHCAL
CPHCAL
PHSIGN
CONFIG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
16
16
16
16
16
16
16
16
10
10
10
16
16
16
16
16
16
16
16
16
16
16 ZP
16 ZP
16 ZP
16
16
U
U
U
U
U
U
U
U
U
U
U
U
U
0xFFFF
0xFFFF
0x01FF
0x0000
0x0EA0
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
0x0002
0xE700
0xE701
MMODE
ACCMODE
R/W
R/W
8
8
8
8
U
U
0x1C
0x80
Rev. A | Page 86 of 104
Description
Instantaneous value of neutral current.
Instantaneous value of Phase A voltage.
Instantaneous value of Phase B voltage.
Instantaneous value of Phase C voltage.
Instantaneous value of Phase A total
active power.
Instantaneous value of Phase B total
active power.
Instantaneous value of Phase C total
active power.
Instantaneous value of Phase A
apparent power.
Instantaneous value of Phase B
apparent power.
Instantaneous value of Phase C
apparent power.
Checksum verification. See the
Checksum Register section for details.
Nominal phase voltage rms used in the
alternative computation of the
apparent power.
These addresses should not be written
for proper operation.
Contains the data from the last successful
32-bit register communication.
Phase peak register. See Table 40.
Time Delay 0. See the Time Interval
Between Phases section for details.
Time Delay 1. See the Time Interval
Between Phases section for details.
Time Delay 2. See the Time Interval
Between Phases section for details.
These address should not be written for
proper operation.
Phase no load register. See Table 41.
These address should not be written for
proper operation.
Line cycle accumulation mode count.
Zero-crossing timeout count.
Computation-mode register. See Table 42.
PGA gains at ADC inputs. See Table 43.
CFx configuration register. See Table 44.
CF1 denominator.
CF2 denominator.
CF3 denominator.
Phase calibration of Phase A. See Table 45.
Phase calibration of Phase B. See Table 45.
Phase calibration Phase of C. See Table 45.
Power sign register. See Table 46.
ADE7880 configuration register.
See Table 47.
Measurement mode register. See Table 48.
Accumulation mode register.
Data Sheet
ADE7880
Bit Length
During
Communication 2
Type 3
Default
Value 4
Address
Register Name
R/W 1
Bit
Length
0xE702
LCYCMODE
R/W
8
8
U
0x78
0xE703
0xE704
0xE705
PEAKCYC
SAGCYC
CFCYC
R/W
R/W
R/W
8
8
8
8
8
8
U
U
U
0x00
0x00
0x01
0xE706
0xE707
0xE7FD
HSDC_CFG
Version
LAST_RWDATA8
R/W
R
R
8
8
8
8
8
8
U
U
U
0x00
0xE880
FVRMS
R
24
32
S
N/A
0xE881
FIRMS
R
24
32
S
N/A
0xE882
FWATT
R
24
32
S
N/A
0xE883
FVAR
R
24
32
S
N/A
0xE884
FVA
R
24
32
S
N/A
0xE885
FPF
R
24
32
S
N/A
0xE886
VTHD
R
24
32
S
N/A
0xE887
ITHD
R
24
32
S
N/A
0xE888
HXVRMS
R
24
32
S
N/A
0xE889
HXIRMS
R
24
32
S
N/A
0xE88A
0xE88B
0xE88C
0xE88D
0xE88E
HXWATT
HXVAR
HXVA
HXPF
HXVHD
R
R
R
R
R
24
24
24
24
24
32
32
32
32
32
S
S
S
S
S
N/A
N/A
N/A
N/A
N/A
0xE88F
HXIHD
R
24
32
S
N/A
0xE890
HYVRMS
R
24
32
S
N/A
0xE891
HYIRMS
R
24
32
S
N/A
0xE892
0xE893
0xE894
0xE895
0xE896
HYWATT
HYVAR
HYVA
HYPF
HYVHD
R
R
R
R
R
24
24
24
24
24
32
32
32
32
32
S
S
S
S
S
N/A
N/A
N/A
N/A
N/A
0xE897
HYIHD
R
24
32
S
N/A
Rev. A | Page 87 of 104
N/A
Description
See Table 49.
Line accumulation mode behavior.
See Table 51.
Peak detection half line cycles.
SAG detection half line cycles.
Number of CF pulses between two
consecutive energy latches. See the
Synchronizing Energy Registers with
CFx Outputs section.
HSDC configuration register. See Table 52.
Version of die.
Contains the data from the last
successful 8-bit register
communication.
The rms value of the fundamental
component of the phase voltage.
The rms value of the fundamental
component of the phase current
The active power of the fundamental
component.
The reactive power of the fundamental
component.
The apparent power of the fundamental
component.
The power factor of the fundamental
component.
Total harmonic distortion of the phase
voltage.
Total harmonic distortion of the phase
current.
The rms value of the phase voltage
harmonic X.
The rms value of the phase current
harmonic X.
The active power of the harmonic X.
The reactive power of the harmonic X.
The apparent power of the harmonic X.
The power factor of the harmonic X.
Harmonic distortion of the phase
voltage harmonic X relative to the
fundamental.
Harmonic distortion of the phase
current harmonic X relative to the
fundamental.
The rms value of the phase voltage
harmonic Y.
The rms value of the phase current
harmonic Y.
The active power of the harmonic Y.
The reactive power of the harmonic Y.
The apparent power of the harmonic Y.
The power factor of the harmonic Y.
Harmonic distortion of the phase
voltage harmonic Y relative to the
fundamental.
Harmonic distortion of the phase
ADE7880
Data Sheet
Bit Length
During
Communication 2
Type 3
Default
Value 4
Address
Register Name
R/W 1
Bit
Length
0xE898
HZVRMS
R
24
32
S
N/A
0xE899
HZIRMS
R
24
32
S
N/A
0xE89A
0xE89B
0xE89C
0xE89D
0xE89E
HZWATT
HZVAR
HZVA
HZPF
HZVHD
R
R
R
R
R
24
24
24
24
24
32
32
32
32
32
S
S
S
S
S
N/A
N/A
N/A
N/A
N/A
0xE89F
HZIHD
R
24
32
S
N/A
0xE8A0 to
0xE8FF
0xE900
Reserved
24
32
HCONFIG
R/W
16
16
U
0x08
0xE902
0xE903
0xE904
0xE905
0xE906
0xE907
0xE908
APF
BPF
CPF
APERIOD
BPERIOD
CPERIOD
APNOLOAD
R
R
R
R
R
R
R/W
16
16
16
16
16
16
16
16
16
16
16
16
16
16
U
U
U
U
U
U
U
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0xE909
VARNOLOAD
R/W
16
16
U
0x0000
0xE90A
VANOLOAD
R/W
16
16
U
0x0000
0xE9FE
LAST_ADD
R
16
16
U
N/A
0xE9FF
LAST_RWDATA16
R
16
16
U
N/A
0xEA00
0xEA01
CONFIG3
LAST_OP
R/W
R
8
8
8
8
U
U
0x01
N/A
0xEA02
WTHR
R/W
8
8
U
0x03
0xEA03
VARTHR
R/W
8
8
U
0x03
0xEA04
VATHR
R/W
8
8
U
0x03
0xEA05 to
0xEA07
0xEA08
Reserved
8
8
HX
R/W
8
8
U
3
0xEA09
HY
R/W
8
8
U
5
0xEA0A
HZ
R/W
8
8
U
7
Rev. A | Page 88 of 104
Description
current harmonic Y relative to the
fundamental.
The rms value of the phase voltage
harmonic Z.
The rms value of the phase current
harmonic Z.
The active power of the harmonic Z.
The reactive power of the harmonic Z.
The apparent power of the harmonic Z.
The power factor of the harmonic Z.
Harmonic distortion of the phase
voltage harmonic Z relative to the
fundamental.
Harmonic distortion of the phase
current harmonic Z relative to the
fundamental.
Reserved. These registers are always 0.
Harmonic Calculations Configuration
register. See Table 54.
Phase A power factor.
Phase B power factor.
Phase C power factor.
Line period on Phase A voltage.
Line period on Phase B voltage.
Line period on Phase C voltage.
No load threshold in the total/
fundamental active power data paths.
No load threshold in the total/
fundamental reactive power data path.
No load threshold in the apparent
power data path.
The address of the register successfully
accessed during the last read/write
operation.
Contains the data from the last successful
16-bit register communication.
Configuration register. See Table 53.
Indicates the type, read or write, of the
last successful read/write operation.
Threshold used in phase total/
fundamental active power data path.
Threshold used in phase total/
fundamental reactive power data path.
Threshold used in phase apparent
power data path.
Reserved. These registers are always 0.
Selects an index of the harmonic
monitored by the harmonic
computations.
Selects an index of the harmonic
monitored by the harmonic
computations.
Selects an index of the harmonic
monitored by the harmonic
Data Sheet
ADE7880
R/W 1
Bit
Length
Bit Length
During
Communication 2
Type 3
Default
Value 4
Address
Register Name
0xEA0B to
0xEBFE
0xEBFF
Reserved
8
8
Reserved
8
8
0xEC00
LPOILVL
R/W
8
8
U
0x07
0xEC01
CONFIG2
R/W
8
8
U
0x00
Description
computations.
Reserved. These registers are always 0.
This address can be used in manipulating
the SS/HSA pin when SPI is chosen as
the active port. See the Serial Interfaces
section for details.
Overcurrent threshold used during
PSM2 mode. See Table 55 in which the
register is detailed.
Configuration register used during
PSM1 mode. See Table 56.
1
R is read, and W is write.
32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that
is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
3
U is unsigned register, and S is signed register in twos complement format.
4
N/A is not applicable.
2
Table 34. IPEAK Register (Address 0xE500)
Bit
23:0
24
25
26
31:27
Mnemonic
IPEAKVAL[23:0]
IPPHASE[0]
IPPHASE[1]
IPPHASE[2]
Default Value
0
0
0
0
00000
Description
These bits contain the peak value determined in the current channel.
When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.
These bits are always 0.
Table 35. VPEAK Register (Address 0xE501)
Bit
23:0
24
25
26
31:27
Mnemonic
VPEAKVAL[23:0]
VPPHASE[0]
VPPHASE[1]
VPPHASE[2]
Default Value
0
0
0
0
00000
Description
These bits contain the peak value determined in the voltage channel.
When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.
These bits are always 0.
Table 36. STATUS0 Register (Address 0xE502)
Bit
0
Mnemonic
AEHF
Default Value
0
1
FAEHF
0
2
3
Reserved
FREHF
0
0
4
VAEHF
0
5
LENERGY
0
6
REVAPA
0
7
REVAPB
0
8
REVAPC
0
Description
When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy
registers (AWATTHR, BWATTHR, or CWATTHR) has changed.
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active
energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed.
This bit is always 0.
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental
reactive energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed.
When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, or CVAHR) has changed.
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an
integration over an integer number of half line cycles set in the LINECYC register.
When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The
sign itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 46).
When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The
sign itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 46).
When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The
sign itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 46).
Rev. A | Page 89 of 104
ADE7880
Data Sheet
Bit
9
Mnemonic
REVPSUM1
Default Value
0
10
REVFRPA
0
11
REVFRPB
0
12
REVFRPC
0
13
REVPSUM2
0
14
CF1
15
CF2
16
CF3
17
DREADY
0
18
REVPSUM3
0
19
HREADY
0
31:18
Reserved
0 0000 0000 0000
Description
When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data
path has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN
register (see Table 46).
When this bit is set to 1, it indicates that the Phase A fundamental reactive power
has changed sign. The sign itself is indicated in Bit 4 (AFVARSIGN) of the PHSIGN
register (see Table 46).
When this bit is set to 1, it indicates that the Phase B fundamental reactive power
has changed sign. The sign itself is indicated in Bit 5 (BFVARSIGN) of the PHSIGN
register (see Table 46).
When this bit is set to 1, it indicates that the Phase C fundamental reactive power
has changed sign. The sign itself is indicated in Bit 6 (CFVARSIGN) of the PHSIGN
register (see Table 46).
When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 data
path has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN
register (see Table 46).
When this bit is set to 1, it indicates a high-to-low transition has occurred at CF1 pin;
that is, an active low pulse has been generated. The bit is set even if the CF1 output
is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power
used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register
(see Table 44).
When this bit is set to 1, it indicates a high-to-low transition has occurred at the CF2
pin; that is, an active low pulse has been generated. The bit is set even if the CF2
output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of
power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE
register (see Table 44).
When this bit is set to 1, it indicates a high-to-low transition has occurred at CF3 pin;
that is, an active low pulse has been generated. The bit is set even if the CF3 output
is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power
used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see
Table 44).
When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP
computations have finished.
When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 data
path has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN
register (see Table 46).
When this bit is set to 1, it indicates the harmonic block output registers have been
updated. If Bit 1 (HRCFG) in the HCONFIG register is cleared to 0, this flag is set to 1
every time the harmonic block output registers are updated at 8 kHz rate. If Bit
HRCFG is set to 1, the HREADY flag is set to 1 every time the harmonic block output
registers are updated at 8 kHz rate starting 750 ms after the harmonic block setup .
Reserved. These bits are always 0.
Rev. A| Page 90 of 104
Data Sheet
ADE7880
Table 37. STATUS1 Register (Address 0xE503)
Bit
0
Mnemonic
NLOAD
Default Value
0
Description
When this bit is set to 1, it indicates that at least one phase entered no load
condition determined by the total active power and apparent power. The phase is
indicated in Bits[2:0] (NLPHASE[x]) in the PHNOLOAD register (see Table 41.)
When this bit is set to 1, it indicates that at least one phase entered no load
condition based on fundamental active and reactive powers. The phase is indicated
in Bits[5:3] (FNLPHASE[x]) in the PHNOLOAD register (see Table 41).
When this bit is set to 1, it indicates that at least one phase entered no load
condition based on apparent power. The phase is indicated in Bits[8:6]
(VANLPHASE[x]) in the PHNOLOAD register (see Table 41).
When this bit is set to 1, it indicates a zero crossing on Phase A voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase B voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase C voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase A current is missing.
When this bit is set to 1, it indicates a zero crossing on Phase B current is missing.
When this bit is set to 1, it indicates a zero crossing on Phase C current is missing.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase A
voltage.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase B
voltage.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase C
voltage.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase A
current.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase B
current.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase C
current.
In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG register,
or a transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set
to 1 at the end of the transition process and after all registers changed value to
default. The IRQ1 pin goes low to signal this moment because this interrupt cannot
be disabled.
When this bit is set to 1, it indicates one of phase voltages entered or exited a sag
state. The phase is indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register
(see Table 40).
When this bit is set to 1, it indicates an overcurrent event has occurred on one of the
phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 40).
When this bit is set to 1, it indicates an overvoltage event has occurred on one of the
phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 40).
When this bit is set to 1, it indicates a negative-to-positive zero crossing on Phase A
voltage was not followed by a negative-to-positive zero crossing on Phase B voltage
but by a negative-to-positive zero crossing on Phase C voltage.
1
FNLOAD
0
2
VANLOAD
0
3
4
5
6
7
8
9
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
0
0
0
0
0
0
0
10
ZXVB
0
11
ZXVC
0
12
ZXIA
0
13
ZXIB
0
14
ZXIC
0
15
RSTDONE
1
16
SAG
0
17
OI
0
18
OV
0
19
SEQERR
0
20
MISMTCH
0
When this bit is set to 1, it indicates ISUM − INWV > ISUMLVL , where
21
22
23
Reserved
Reserved
PKI
1
0
0
ISUMLVL is indicated in the ISUMLVL register.
Reserved. This bit is always set to 1.
Reserved. This bit is always set to 0.
When this bit is set to 1, it indicates that the period used to detect the peak value in
the current channel has ended. The IPEAK register contains the peak value and the
phase where the peak has been detected (see Table 34).
Rev. A| Page 91 of 104
ADE7880
Data Sheet
Bit
24
Mnemonic
PKV
Default Value
0
25
CRC
0
31:26
Reserved
000 0000
Description
When this bit is set to 1, it indicates that the period used to detect the peak value in
the voltage channel has ended. VPEAK register contains the peak value and the
phase where the peak has been detected (see Table 35).
When this bit is set to 1, it indicates the ADE7880 has computed a different
checksum relative to the one computed when the Run register was set to 1.
Reserved. These bits are always 0.
Table 38. MASK0 Register (Address 0xE50A)
Bit
0
Mnemonic
AEHF
Default Value
0
1
FAEHF
0
2
3
Reserved
FREHF
0
0
4
VAEHF
0
5
LENERGY
0
6
REVAPA
0
7
REVAPB
0
8
REVAPC
0
9
REVPSUM1
0
10
REVFRPA
0
11
REVFRPB
0
12
REVFRPC
0
13
REVPSUM2
0
14
CF1
15
CF2
16
CF3
17
DREADY
0
Description
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total
active energy registers (AWATTHR, BWATTHR, or CWATTHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the
fundamental active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR)
changes.
This bit does not manage any functionality.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the
fundamental reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the
apparent energy registers (AVAHR, BVAHR, or CVAHR) changes.
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at
the end of an integration over an integer number of half line cycles set in the
LINECYC register.
When this bit is set to 1, it enables an interrupt when the Phase A active power
identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)
changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B active power
identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)
changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C active power
identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)
changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in
the CF1 data path changes sign.
When this bit is set to 1, it enables an interrupt when the Phase A fundamental
reactive power changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B fundamental
reactive power changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C fundamental
reactive power changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in
the CF2 data path changes sign.
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs
at the CF1 pin, that is an active low pulse is generated. The interrupt can be enabled
even if the CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE
register. The type of power used at the CF1 pin is determined by Bits[2:0]
(CF1SEL[2:0]) in the CFMODE register (see Table 44).
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs
at CF2 pin, that is an active low pulse is generated. The interrupt may be enabled
even if the CF2 output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE
register. The type of power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0])
in the CFMODE register (see Table 44).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs
at CF3 pin, that is an active low pulse is generated. The interrupt may be enabled
even if the CF3 output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE
register. The type of power used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0])
in the CFMODE register (see Table 44).
When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate)
DSP computations finish.
Rev. A| Page 92 of 104
Data Sheet
ADE7880
Bit
18
Mnemonic
REVPSUM3
Default Value
0
19
HREADY
0
31:19
Reserved
00 0000 0000
0000
Description
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in
the CF3 data path changes sign.
When this bit is set to 1, it enables an interrupt when the harmonic block output
registers have been updated. If Bit 1 (HRCFG) in HCONFIG register is cleared to 0, the
interrupt is triggered every time the harmonic calculations are updated at 8 kHz
rate. If Bit HRCFG is set to 1, the interrupt is triggered every time the harmonic
calculations are updated at 8 kHz rate starting 750 ms after the harmonic block
setup.
Reserved. These bits do not manage any functionality.
Table 39. MASK1 Register (Address 0xE50B)
Bit
0
Mnemonic
NLOAD
Default Value
0
1
FNLOAD
0
2
VANLOAD
0
3
ZXTOVA
0
4
ZXTOVB
0
5
ZXTOVC
0
6
ZXTOIA
0
7
ZXTOIB
0
8
ZXTOIC
0
9
ZXVA
0
10
ZXVB
0
11
ZXVC
0
12
ZXIA
0
13
ZXIB
0
14
ZXIC
0
15
RSTDONE
0
16
SAG
0
17
OI
0
18
OV
0
19
SEQERR
0
Description
When this bit is set to 1, it enables an interrupt when at least one phase enters no
load condition determined by the total active power and VNOM based apparent
power.
When this bit is set to 1, it enables an interrupt when at least one phase enters no
load condition based on fundamental active and reactive powers.
When this bit is set to 1, it enables an interrupt when at least one phase enters no
load condition based on apparent power.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A
voltage is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B
voltage is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C
voltage is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A
current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B
current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C
current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase A voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase B voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase C voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase A current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase B current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase C current.
Because the RSTDONE interrupt cannot be disabled, this bit does not have any
functionality attached. It can be set to 1 or cleared to 0 without having any effect.
When this bit is set to 1, it enables an interrupt when one of the phase voltages
entered or exited a sag state. The phase is indicated by Bits[14:12] (VSPHASE[x]) in
the PHSTATUS register (see Table 40).
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs
on one of the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register
(see Table 40).
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs
on one of the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register
(see Table 40).
When this bit is set to 1, it enables an interrupt when a negative-to-positive zero
crossing on Phase A voltage is not followed by a negative-to-positive zero crossing
on Phase B voltage, but by a negative-to-positive zero crossing on Phase C voltage.
Rev. A| Page 93 of 104
ADE7880
Data Sheet
Bit
20
Mnemonic
MISMTCH
Default Value
0
22:21
23
Reserved
PKI
00
0
24
PKV
0
25
CRC
0
31:26
Reserved
000 0000
Description
When this bit is set to 1, it enables an interrupt
when ISUM − INWV > ISUMLVL is greater than the value indicated in
ISUMLVL register.
Reserved. These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the period used to detect the
peak value in the current channel has ended.
When this bit is set to 1, it enables an interrupt when the period used to detect the
peak value in the voltage channel has ended.
When this bit is set to 1, it enables an interrupt when the latest checksum value is
different from the checksum value computed when Run register was set to 1.
Reserved. These bits do not manage any functionality.
Table 40. PHSTATUS Register (Address 0xE600)
Bit
2:0
3
4
5
8:6
9
10
11
12
Mnemonic
Reserved
OIPHASE[0]
OIPHASE[1]
OIPHASE[2]
Reserved
OVPHASE[0]
OVPHASE[1]
OVPHASE[2]
VSPHASE[0]
Default Value
000
0
0
0
000
0
0
0
0
13
VSPHASE[1]
0
14
VSPHASE[2]
0
15
Reserved
0
Description
Reserved. These bits are always 0.
When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
Reserved. These bits are always 0.
When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
0: Phase A voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase A voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase A voltage generates Bit 16
(SAG) in the STATUS1 register.
0: Phase B voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase B voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase B voltage generates Bit 16
(SAG) in the STATUS1 register.
0: Phase C voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase C voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase C voltage generates Bit 16
(SAG) in the STATUS1 register.
Reserved. This bit is always 0.
Table 41. PHNOLOAD Register (Address 0xE608)
Bit
0
Mnemonic
NLPHASE[0]
Default Value
0
1
NLPHASE[1]
0
2
NLPHASE[2]
0
3
FNLPHASE[0]
0
Description
0: Phase A is out of no load condition determined by the Phase A total active power and
apparent power.
1: Phase A is in no load condition determined by phase A total active power and apparent
power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase B is out of no load condition determined by the Phase B total active power and
apparent power.
1: Phase B is in no load condition determined by the Phase B total active power and
apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase C is out of no load condition determined by the Phase C total active power and
apparent power.
1: Phase C is in no load condition determined by the Phase C total active power and
apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase A is out of no load condition based on fundamental active/reactive powers.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
Rev. A| Page 94 of 104
Data Sheet
ADE7880
Bit
4
Mnemonic
FNLPHASE[1]
Default Value
0
5
FNLPHASE[2]
0
6
VANLPHASE[0]
0
7
VANLPHASE[1]
0
8
VANLPHASE[2]
0
15:9
Reserved
000 0000
Description
0: Phase B is out of no load condition based on fundamental active/reactive powers.
1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
0: Phase C is out of no load condition based on fundamental active/reactive powers.
1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
0: Phase A is out of no load condition based on apparent power.
1: Phase A is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
0: Phase B is out of no load condition based on apparent power.
1: Phase B is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
0: Phase C is out of no load condition based on apparent power.
1: Phase C is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
Reserved. These bits are always 0.
Table 42. COMPMODE Register (Address 0xE60E)
Bit
0
Mnemonic
TERMSEL1[0]
Default Value
1
1
2
3
TERMSEL1[1]
TERMSEL1[2]
TERMSEL2[0]
1
1
1
4
5
6
TERMSEL2[1]
TERMSEL2[2]
TERMSEL3[0]
1
1
1
7
8
10:9
TERMSEL3[1]
TERMSEL3[2]
ANGLESEL[1:0]
1
1
00
11
VNOMAEN
0
12
VNOMBEN
0
13
VNOMCEN
0
14
SELFREQ
0
15
Reserved
0
Description
Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1
output. Phase A is included in the CF1 outputs calculations.
Phase B is included in the CF1 outputs calculations.
Phase C is included in the CF1 outputs calculations.
Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2
output. Phase A is included in the CF2 outputs calculations.
Phase B is included in the CF2 outputs calculations.
Phase C is included in the CF2 outputs calculations.
Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3
output. Phase A is included in the CF3 outputs calculations.
Phase B is included in the CF3 outputs calculations.
Phase C is included in the CF3 outputs calculations.
00: the angles between phase voltages and phase currents are measured.
01: the angles between phase voltages are measured.
10: the angles between phase currents are measured.
11: no angles are measured.
When this bit is 0, the apparent power on Phase A is computed regularly.
When this bit is 1, the apparent power on Phase A is computed using VNOM register instead
of regular measured rms phase voltage.
When this bit is 0, the apparent power on Phase B is computed regularly.
When this bit is 1, the apparent power on Phase B is computed using VNOM register instead of
regular measured rms phase voltage.
When this bit is 0, the apparent power on Phase C is computed regularly.
When this bit is 1, the apparent power on Phase C is computed using VNOM register instead of
regular measured rms phase voltage.
When the ADE7880 is connected to 50 Hz networks, this bit should be cleared to 0 (default
value). When the ADE7880 is connected to 60 Hz networks, this bit should be set to 1.
This bit is 0 by default and it does not manage any functionality.
Rev. A| Page 95 of 104
ADE7880
Data Sheet
Table 43. Gain Register (Address 0xE60F)
Bit
2:0
Mnemonic
PGA1[2:0]
Default Value
000
5:3
PGA2[2:0]
000
8:6
PGA3[2:0]
000
15:9
Reserved
000 0000
Description
Phase currents gain selection.
000: gain = 1.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7880 behaves like PGA1[2:0] =
000.
Neutral current gain selection.
000: gain = 1.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7880 behaves like PGA2[2:0] =
000.
Phase voltages gain selection.
000: gain = 1.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7880 behaves like PGA3[2:0] =
000.
Reserved. These bits do not manage any functionality.
Table 44. CFMODE Register (Address 0xE610)
Bit
2:0
Mnemonic
CF1SEL[2:0]
Default Value
000
5:3
CF2SEL[2:0]
100
Description
000: the CF1 frequency is proportional to the sum of total active powers on
each phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
010: the CF1 frequency is proportional to the sum of apparent powers on
each phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
011: the CF1 frequency is proportional to the sum of fundamental active
powers on each phase identified by Bits[2:0] (TERMSEL1[x]) in the
COMPMODE register.
100: the CF1 frequency is proportional to the sum of fundamental reactive
powers on each phase identified by Bits[2:0] (TERMSEL1[x]) in the
COMPMODE register.
001, 101, 110, 111: reserved.
000: the CF2 frequency is proportional to the sum of total active powers on
each phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
010: the CF2 frequency is proportional to the sum of apparent powers on
each phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
011: the CF2 frequency is proportional to the sum of fundamental active
powers on each phase identified by Bits[5:3] (TERMSEL2[x]) in the
COMPMODE register.
100: the CF2 frequency is proportional to the sum of fundamental reactive
powers on each phase identified by Bits[5:3] (TERMSEL2[x]) in the
COMPMODE register.
001, 101,110,111: reserved.
Rev. A| Page 96 of 104
Data Sheet
ADE7880
Bit
8:6
Mnemonic
CF3SEL[2:0]
Default Value
010
Description
000: the CF3 frequency is proportional to the sum of total active powers on
each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
010: the CF3 frequency is proportional to the sum of apparent powers on
each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
011: CF3 frequency is proportional to the sum of fundamental active powers
on each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE
register.
100: CF3 frequency is proportional to the sum of fundamental reactive
powers on each phase identified by Bits[8:6] (TERMSEL3[x]) in the
COMPMODE register.
001, 101,110,111: reserved.
9
CF1DIS
1
10
CF2DIS
1
11
CF3DIS
1
12
CF1LATCH
0
13
CF2LATCH
0
14
CF3LATCH
0
15
Reserved
0
When this bit is set to 1, the CF1 output is disabled. The respective digital to
frequency converter remains enabled even if CF1DIS = 1.
When this bit is set to 0, the CF1 output is enabled.
When this bit is set to 1, the CF2 output is disabled. The respective digital to
frequency converter remains enabled even if CF2DIS = 1.
When this bit is set to 0, the CF2 output is enabled.
When this bit is set to 1, the CF3 output is disabled. The respective digital to
frequency converter remains enabled even if CF3DIS = 1.
When this bit is set to 0, the CF3 output is enabled.
When this bit is set to 1, the content of the corresponding energy registers is
latched when a CF1 pulse is generated. See the Synchronizing Energy
Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is
latched when a CF2 pulse is generated. See the Synchronizing Energy
Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is
latched when a CF3 pulse is generated. See the Synchronizing Energy
Registers with CFx Outputs section.
Reserved. This bit does not manage any functionality.
Table 45. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit
9:0
Mnemonic
PHCALVAL
Default Value
0000000000
15:10
Reserved
000000
Description
If current channel compensation is necessary, these bits can vary only between 0 and 383.
If voltage channel compensation is necessary, these bits can vary only between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
Reserved. These bits do not manage any functionality.
Table 46. PHSIGN Register (Address 0xE617)
Bit
0
Mnemonic
AWSIGN
Default Value
0
1
BWSIGN
0
2
CWSIGN
0
Description
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of
fundamental) on Phase C is negative.
Rev. A| Page 97 of 104
ADE7880
Data Sheet
Bit
3
Mnemonic
SUM1SIGN
Default Value
0
4
AFVARSIGN
0
5
BFVARSIGN
0
6
CFVARSIGN
0
7
SUM2SIGN
0
8
SUM3SIGN
0
15:9
Reserved
000 0000
Description
0: if the sum of all phase powers in the CF1 data path is positive.
1: if the sum of all phase powers in the CF1 data path is negative. Phase powers in the CF1
data path are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
0: if the fundamental reactive power on Phase A is positive.
1: if the fundamental reactive power on Phase A is negative.
0: if the fundamental reactive power on Phase B is positive.
1: if the fundamental reactive power on Phase B is negative.
0: if the fundamental reactive power on Phase C is positive.
1: if the fundamental reactive power on Phase C is negative.
0: if the sum of all phase powers in the CF2 data path is positive.
1: if the sum of all phase powers in the CF2 data path is negative. Phase powers in the CF2
data path are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by
Bits[5:3] (CF2SEL[x]) of the CFMODE register.
0: if the sum of all phase powers in the CF3 data path is positive.
1: if the sum of all phase powers in the CF3 data path is negative. Phase powers in the CF3
data path are identified by Bits[8:6] (TERMSEL3[x]) of the COMPMODE register and by
Bits[8:6] (CF3SEL[x]) of the CFMODE register.
Reserved. These bits are always 0.
Table 47. CONFIG Register (Address 0xE618)
Bit
0
Mnemonic
INTEN
Default Value
0
1
2
Reserved
CF2DIS
1
0
3
SWAP
0
4
MOD1SHORT
0
5
MOD2SHORT
0
6
HSDCEN
0
7
9:8
SWRST
VTOIA[1:0]
0
00
11:10
VTOIB[1:0]
00
Description
This bit manages the integrators in the phase current channels.
If INTEN=0, then the integrators in the phase current channels are always disabled.
If INTEN=1, then the integrators in the phase currents channels are enabled.
The neutral current channel integrator is managed by Bit 3 (ININTEN ) of CONFIG3 register.
Reserved. This bit should be maintained at 1 for proper operation.
When this bit is cleared to 0, the CF2 functionality is chosen at CF2/HREADY pin.
When this bit is set to 1, the HREADY functionality is chosen at CF2/HREADY pin.
When this bit is set to 1, the voltage channel outputs are swapped with the current channel
outputs. Thus, the current channel information is present in the voltage channel registers
and vice versa.
When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put
to ground.
When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put
to ground.
When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at
CF3/HSCLK pin.
When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at CF3/HSCLK pin.
When this bit is set to 1, a software reset is initiated.
These bits decide what phase voltage is considered together with Phase A current in the
power path.
00 = Phase A voltage.
01 = Phase B voltage.
10 = Phase C voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIA[1:0] = 00.
These bits decide what phase voltage is considered together with Phase B current in the
power path.
00 = Phase B voltage.
01 = Phase C voltage.
10 = Phase A voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIB[1:0] = 00.
Rev. A| Page 98 of 104
Data Sheet
Bit
13:12
Mnemonic
VTOIC[1:0]
15:14
Reserved
ADE7880
Default Value
00
Description
These bits decide what phase voltage is considered together with Phase C current in the
power path.
00 = Phase C voltage.
01 = Phase A voltage.
10 = Phase B voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIC[1:0] = 00.
Reserved.
Table 48. MMODE Register (Address 0xE700)
Bit
1:0
2
Mnemonic
Reserved
PEAKSEL[0]
Default Value
3
4
7:5
PEAKSEL[1]
PEAKSEL[2]
Reserved
1
1
000
1
Description
Reserved.
PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three
phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak
measurement period indicated in the PEAKCYC register decreases accordingly because zero
crossings are detected on more than one phase.
When this bit is set to 1, Phase A is selected for the voltage and current peak registers.
When this bit is set to 1, Phase B is selected for the voltage and current peak registers.
When this bit is set to 1, Phase C is selected for the voltage and current peak registers.
Reserved. These bits do not manage any functionality.
Table 49. ACCMODE Register (Address 0xE701)
Bit
1:0
Mnemonic
WATTACC[1:0]
Default Value
00
3:2
VARACC[1:0]
00
5:4
CONSEL[1:0]
00
Description
00: signed accumulation mode of the total and fundamental active powers. The total and
fundamental active energy registers and the CFx pulses are generated in the same way.
01: positive only accumulation mode of the total and fundamental active powers. In this
mode, although the total and fundamental active energy registers are accumulated in
positive only mode, the CFx pulses are generated in signed accumulation mode.
10: reserved. When set, the device behaves like WATTACC[1:0] = 00.
11: absolute accumulation mode of the total and fundamental active powers. The total and
fundamental energy registers and the CFx pulses are generated in the same way.
00: signed accumulation of the fundamental reactive powers. The fundamental reactive
energy registers and the CFx pulses are generated in the same way.
01: reserved. When set, the device behaves like VARACC[1:0] = 00.
10: the fundamental reactive power is accumulated, depending on the sign of the
fundamental active power: if the active power is positive, the reactive power is accumulated
as is, whereas if the active power is negative, the reactive power is accumulated with reversed
sign. In this mode, although the total and fundamental reactive energy registers are
accumulated in absolute mode, the CFx pulses are generated in signed accumulation mode.
11: absolute accumulation mode of the fundamental reactive powers. In this mode,
although the total and fundamental reactive energy registers are accumulated in absolute
mode, the CFx pulses are generated in signed accumulation mode.
These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB, and
IC shifted respectively by −90°. See Table 50.
00: 3-phase four wires with three voltage sensors.
01: 3-phase three wires delta connection. In this mode, BVRMS register contains the rms
value of VA-VC.
10: 3-phase four wires with two voltage sensors.
11: 3-phase four wires delta connection.
Rev. A| Page 99 of 104
ADE7880
Data Sheet
Bit
6
Mnemonic
REVAPSEL
Default Value
0
7
Reserved
1
Description
0: The total active power on each phase is used to trigger a bit in the STATUS0 register as
follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB), and on
Phase C triggers Bit 8 (REVAPC).
1: The fundamental active power on each phase is used to trigger a bit in the STATUS0
register as follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB),
and on Phase C triggers Bit 8 (REVAPC).
Reserved. This bit does not manage any functionality.
Table 50. CONSEL[1:0] Bits in Energy Registers1
Energy Registers
AWATTHR, AFWATTHR
BWATTHR, BFWATTHR
CONSEL[1:0] = 00
VA × IA
VB × IB
CWATTHR, CFWATTHR
AVARHR, AFVARHR
BVARHR, BFVARHR
VC × IC
VA × IA’
VB × IB’
CVARHR, CFVARHR
AVAHR
BVAHR
VC ×IC’
VA rms × IA rms
VB rms × IB rms
CVAHR
VC rms × IC rms
1
CONSEL[1:0] = 01
VA × IA
VB = VA – VC
VB ×IB1
VC × IC
VA × IA’
VB = VA – VC
VB × IB’1
VC × IC’
VA rms × IA rms
VB rms × IB rms
VB = VA – VC1
VC rms × IC rms
CONSEL[1:0] = 10
VA × IA
VB = −VA – VC
VB × IB
VC × IC
VA × IA’
VB = −VA – VC
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
CONSEL[1:0] = 11
VA × IA
VB = −VA
VB × IB
VC × IC
VA × IA’
VB = −VA
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
VC rms × IC rms
In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the rms value of the line voltage between Phase A and and Phase C and stores the result into
BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta Configurations section). Consequently, the ADE7880 computes powers associated with Phase B that
do not have physical meaning. To avoid any errors in the frequency output pins CF1, CF2 or CF3 related to the powers associated with Phase B, disable the
contribution of Phase B to the energy to frequency converters by setting bits TERMSEL1[1], or TERMSEL2[1], or TERMSEL3[1] to 0 in the COMPMODE register (see the
Energy-to-Frequency Conversion section).
Table 51. LCYCMODE Register (Address 0xE702)
Bit
0
Mnemonic
LWATT
Default Value
0
1
LVAR
0
2
LVA
0
3
ZXSEL[0]
1
4
ZXSEL[1]
1
5
ZXSEL[2]
1
6
RSTREAD
1
Description
0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed in regular accumulation mode.
1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed into line cycle accumulation mode.
0: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed in regular
accumulation mode.
1: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed into linecycle accumulation mode.
0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed in regular
accumulation mode.
1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed into line-cycle
accumulation mode.
0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.
0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.
0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,
LVAR, and LVA) are set to 1.
1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR registers.
This means a read of those registers resets them to 0.
Rev. A| Page 100 of 104
Data Sheet
Bit
7
Mnemonic
PFMODE
ADE7880
Default Value
0
Description
0: power factor calculation uses instantaneous values of various phase powers used in its
expression.
1: power factor calculation uses phase energies values calculated using line cycle accumulation
mode. Bits LWATT and LVA in LCYCMODE register must be enabled for the power factors to be
computed correctly. The update rate of the power factor measurement in this case is the integral
number of half line cycles that are programmed into the LINECYC register.
Table 52. HSDC_CFG Register (Address 0xE706)
Bit
0
Mnemonic
HCLK
Default Value
0
1
HSIZE
0
2
HGAP
0
4:3
HXFER[1:0]
00
5
HSAPOL
0
7:6
Reserved
00
Description
0: HSCLK is 8 MHz.
1: HSCLK is 4 MHz.
0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
0: no gap is introduced between packages.
1: a gap of seven HCLK cycles is introduced between packages.
00 = HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV,
VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT, AFVAR, BFVAR, and CFVAR.
01 = HSDC transmits seven instantaneous values of currents and voltages: IAWV, VAWV,
IBWV, VBWV, ICWV, VCWV, and INWV.
10 = HSDC transmits nine instantaneous values of phase powers: AVA, BVA, CVA, AWATT,
BWATT, CWATT, AFVAR, BFVAR, and CFVAR.
11 = reserved. If set, the ADE7880 behaves as if HXFER[1:0] = 00.
0: SS/has output pin is active low.
1: SS/HSA output pin is active high.
Reserved. These bits do not manage any functionality.
Table 53. CONFIG3 Register (Address 0xEA00)
Bit
0
Mnemonic
HPFEN
Default Value
1
1
LPFSEL
0
2
INSEL
0
3
ININTEN
0
4
7:5
Reserved
Reserved
0
000
Description
When HPFEN = 1, then all high-pass filters in voltage and current channels are enabled.
When HPFEN = 0, then all high-pass filters are disabled.
When LPFSEL = 0, the LPF in the total active power data path introduces a settling time of
650 ms.
When LPFSEL = 1, the LPF in the total active power data path introduces a settling time of
1300 ms.
When INSEL = 0, the register NIRMS contains the rms value of the neutral current.
When INSEL = 1, the register NIRMS contains the rms value of ISUM, the instantaneous value
of the sum of all 3 phase currents, IA, IB, and IC.
This bit manages the integrator in the neutral current channel.
If ININTEN = 0, then the integrator in the neutral current channel is disabled.
If ININTDIS = 1, then the integrator in the neutral channel is enabled.
The integrators in the phase currents channels are managed by Bit 0 (INTEN) of CONFIG
register.
Reserved. This bit should be maintained at 0 for proper operation.
Reserved. These bits do not manage any functionality.
Rev. A| Page 101 of 104
ADE7880
Data Sheet
Table 54. HCONFIG Register (Address 0xE900)
Bit
0
Mnemonic
HRCFG
Default Value
0
2:1
HPHASE
00
4:3
HSTIME
01
7:5
HRATE
000
9:8
ACTPHSEL
00
15:10
Reserved
0
Description
When this bit is cleared to 0, the bit 19 (HREADY) interrupt in MASK0 register is triggered
after a certain delay period. The delay period is set by bits HSTIME. The update frequency
after the settling time is determined by bits HRATE.
When this bit is set to 1, the bit 19 (HREADY) interrupt in MASK0 register is triggered starting
immediately after the harmonic calculations block has been setup. The update frequency is
determined by bits HRATE.
These bits decide what phase or neutral is analyzed by the harmonic calculations block.
00 = Phase A voltage and current.
01 = Phase B voltage and current.
10 = Phase C voltage and current.
11 = neutral current.
These bits decide the delay period after which, if HRCFG bit is set to 1, bit 19 (HREADY)
interrupt in MASK0 register is triggered.
00 = 500 ms.
01 = 750 ms.
10 = 1000 ms.
11 = 1250 ms.
These bits manage the update rate of the harmonic registers.
000 = 125 μsec (8 kHz rate).
001 = 250 μsec (4 kHz rate).
010 = 1 ms (1 kHz rate).
011 = 16 ms (62.5 Hz rate).
100 = 128 ms (7.8125 Hz rate).
101 = 512 ms (1.953125 Hz rate).
110 = 1.024 sec (0.9765625 Hz rate).
111 = harmonic calculations disabled.
These bits select the phase voltage used as time base for harmonic calculations.
00 = Phase A voltage.
01 = Phase B voltage.
10 = Phase C voltage.
11 = reserved. If selected, phase C voltage is used.
Reserved. These bits do not manage any functionality.
Table 55. LPOILVL Register (Address 0xEC00)
Bit
2:0
7:3
Mnemonic
LPOIL[2:0]
LPLINE[4:0]
Default Value
111
00000
Description
Threshold is put at a value corresponding to full scale multiplied by LPOIL/8.
The measurement period is (LPLINE + 1)/50 seconds.
Table 56. CONFIG2 Register (Address 0xEC01)
Bit
0
Mnemonic
EXTREFEN
Default Value
0
1
I2C_LOCK
0
7:2
Reserved
0
Description
When this bit is 0, it signifies that the internal voltage reference is used in the ADCs.
When this bit is 1, an external reference is connected to the Pin 17 REFIN/OUT.
When this bit is 0, the SS/HSA pin can be toggled three times to activate the SPI port. If I2C is the
active serial port, this bit must be set to 1 to lock it in. From this moment on, toggling of the SS
/HSA pin and an eventual switch into using the SPI port is no longer possible. If SPI is the active serial
port, any write to CONFIG2 register locks the port. From this moment on, a switch into using I2C
port is no longer possible. Once locked, the serial port choice is maintained when the ADE7880
changes PSMx power modes.
Reserved. These bits do not manage any functionality.
Rev. A| Page 102 of 104
Data Sheet
ADE7880
OUTLINE DIMENSIONS
0.30
0.23
0.18
31
40
30
0.50
BSC
1
TOP VIEW
0.80
0.75
0.70
10
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4.45
4.30 SQ
4.25
EXPOSED
PAD
21
0.45
0.40
0.35
PIN 1
INDICATOR
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
05-06-2011-A
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 111. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADE7880ACPZ
ADE7880ACPZ-RL
EVAL-ADE7880EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead LFCSP_WQ
40-Lead LFCSP_WQ, 13” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. A| Page 103 of 104
Package Option
CP-40-10
CP-40-10
ADE7880
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10193-0-3/12(A)
Rev. A| Page 104 of 104