ICM7228 8-Digit, MicroprocessorCompatible, LED Display Decoder Driver August 1997 Features Description • Improved 2nd Source to Maxim ICM7218 The Intersil ICM7228 display driver interfaces microprocessors to an 8-digit, 7-segment, numeric LED display. Included on chip are two types of 7-segment decoder, multiplex scan circuitry, LED display segment drivers, LED display digit drivers and an 8-byte static memory as display RAM. • Fast Write Access Time of 200ns • Multiple Microprocessor Compatible Versions • Hexadecimal, Code B and No Decode Modes • Individual Segment Control with “No Decode” Feature • Digit and Segment Drivers On-Chip • Non-Overlapping Digits Drive • Common Anode and Common Cathode LED Versions • Low Power CMOS Architecture • Single 5V Supply Applications • Instrumentation • Test Equipment • Hand Held Instruments • Bargraph Displays • Numeric and Non-Numeric Panel Displays • High and Low Temperature Environments where LCD Display Integrity is Compromised Data can be written to the ICM7228A and ICM7228B’s display RAM in sequential 8-digit update or in single-digit update format. Data is written to the ICM7228C and ICM7228D display RAM in parallel random access format. The ICM7228A and ICM7228C drive common anode displays. The ICM7228B and ICM7228D drive common cathode displays. All versions can display the RAM data as either Hexadecimal or Code B format. The ICM7228A and ICM7228B incorporate a No Decode mode allowing each bit of each digit's RAM word to drive individual display segments resulting in independent control of all display segments. As a result, bargraph and other irregular display segments and formats can be driven directly by this chip. The Intersil ICM7228 is an alternative to both the Maxim ICM7218 and the Intersil ICM7218 display drivers. Notice that the ICM7228A/B has an additional single digit access mode. This could make the Intersil ICM7218A/B software incompatible with ICM7228A/B operation. Ordering Information PART NUMBER DATA ENTRY PROTOCOL DISPLAY TYPE TEMP. RANGE (oC) PACKAGE PKG. NO. ICM7228AIPI Sequential Common Anode -40 to 85 28 Ld PDIP E28.6 ICM7228BIPI Sequential Common Cathode -40 to 85 28 Ld PDIP E28.6 ICM7228CIPI Random Common Anode -40 to 85 28 Ld PDIP E28.6 ICM7228DIPI Random Common Cathode -40 to 85 28 Ld PDIP E28.6 ICM7228AIJI Sequential Common Anode -40 to 85 28 Ld CERDIP F28.6 ICM7228BIJI Sequential Common Cathode -40 to 85 28 Ld CERDIP F28.6 ICM7228CIJI Random Common Anode -40 to 85 28 Ld CERDIP F28.6 ICM7228DIJI Random Common Cathode -40 to 85 28 Ld CERDIP F28.6 ICM7228AIBI Sequential Common Anode -40 to 85 28 Ld SOIC M28.3 ICM7228BIBI Sequential Common Cathode -40 to 85 28 Ld SOlC M28.3 ICM7228CIBI Random Common Anode -40 to 85 28 Ld SOlC M28.3 ICM7228DIBI Random Common Cathode -40 to 85 28 Ld SOlC M28.3 ICM7228AMJI883B Sequential Common Anode -55 to 125 28 Ld CERDIP F28.6 ICM7228BMJI883B Sequential Common Cathode -55 to 125 28 Ld CERDIP F28.6 ICM7228CMJI883B Random Common Anode -55 to 125 28 Ld CERDIP F28.6 ICM7228DMJI883B Random Common Cathode -55 to 125 28 Ld CERDIP F28.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 9-17 File Number 3160.1 ICM7228 Pinouts ICM7228A (CERDIP, PDIP, SOIC) COMMON ANODE TOP VIEW ICM7228B (CERDIP, PDIP, SOIC) COMMON CATHODE TOP VIEW SEG c 1 28 VSS DIGIT 4 1 28 VSS SEG e 2 27 SEG a DIGIT 6 2 27 DIGIT 7 SEG b 3 26 SEG g DIGIT 3 3 26 DIGIT 5 DP 4 25 SEG d DIGIT 1 4 25 DIGIT 2 ID6 (HEXA/CODE B) 5 24 DIGIT 8 24 SEG f ID6 (HEXA/CODE B) 5 ID5 (DECODE) 6 23 DIGIT 3 23 SEG g ID5 (DECODE) 6 7 22 DIGIT 6 7 22 SEG f WRITE 8 21 DIGIT 7 WRITE 8 21 SEG e MODE 9 20 DIGIT 4 MODE 9 20 SEG c ID7 (DATA COMING) ID7 (DATA COMING) 19 VDD ID4 (SHUTDOWN) 10 19 VDD ID4 (SHUTDOWN) 10 ID1 11 18 DIGIT 8 ID1 11 18 SEG d ID0 12 17 DIGIT 5 ID0 12 17 SEG b ID2 13 16 DIGIT 2 ID2 13 16 SEG a ID3 14 15 DIGIT 1 ID3 14 15 DP ICM7228C (CERDIP, PDIP, SOIC) COMMON ANODE TOP VIEW ICM7228D (CERDIP, PDIP, SOIC) COMMON CATHODE TOP VIEW SEG c 1 28 VSS DIGIT 4 1 28 VSS SEG e 2 27 SEG a DIGIT 6 2 27 DIGIT 7 SEG b 3 26 SEG g DIGIT 3 3 26 DIGIT 5 DP 4 25 SEG d DIGIT 1 4 25 DIGIT 2 DA0 (DIGIT ADDRESS 0) 5 24 SEG f DA0 (DIGIT ADDRESS 0) 5 24 DIGIT 8 DA1 (DIGIT ADDRESS 1) 6 23 DIGIT 3 DA1 (DIGIT ADDRESS 1) 6 23 SEG g ID7 (INPUT DP) 7 22 DIGIT 6 ID7 (INPUT DP) 7 22 SEG f WRITE 8 21 DIGIT 7 WRITE 8 21 SEG e 9 20 DIGIT 4 9 20 SEG c HEXA/CODE B/SHUTDOWN DA2 (DIGIT ADDRESS 2) 10 HEXA/CODE B/SHUTDOWN 19 VDD DA2 (DIGIT ADDRESS 2) 10 19 VDD ID1 11 18 DIGIT 8 ID1 11 18 SEG d ID0 12 17 DIGIT 5 ID0 12 17 SEG b ID2 13 16 DIGIT 2 ID2 13 16 SEG a ID3 14 15 DIGIT 1 ID3 14 15 DP 9-18 ICM7228 Functional Block Diagram ICM7228A, ICM7228B ID0 - ID7 INPUT DATA 8 8 ICM7228C, ICM7228D ID4 - ID7 CONTROL INPUTS MODE 1 4 DA0 - DA2 ID0 - ID3 DIGIT ID7 DATA INPUT WRITE ADDRESS 3 5 1 HEXADECIMAL/ CODE B/ SHUTDOWN WRITE 1 1 DECODE SHUTDOWN CONTROL LOGIC HEXA/CODE B 1 1 1 SHUTDOWN 1 8 WRITE ADDRESS COUNTER 8 8-BYTE STATIC RAM 1 THREE LEVEL INPUT LOGIC 8-BYTE STATIC RAM 8 1 1 WRITE ADDRESS COUNTER 8 7 8 4 HEXADECIMAL/ CODE B DECODER READ ADDRESS, DIGIT MULTIPLEXER READ ADDRESS MULTIPLEXER 8 4 3 5 7 MULTIPLEX OSCILLATOR 7 1 HEXADECIMAL/ CODE B DECODER MULTIPLEX OSCILLATOR 1 DECODE NO-DECODE 8 7 DECIMAL POINT 8 SEGMENT DRIVERS 1 8 INTERDIGIT BLANKING 7 8 DIGIT DRIVERS INTERDIGIT BLANKING DECIMAL POINT 8 SEGMENT DRIVERS 9-19 1 8 DIGIT DRIVERS ICM7228 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Digit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Segment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Input Voltage (Note 1) (Any Terminal). . .(VSS -0.3V)<VIN <(VDD +0.3V) Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 55 12 PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 75 N/A Maximum Junction Temperature IPI, IBI Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC MJI, IJI Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Operating Temperature Range IPI, IJI, IBI Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC MJl Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than VDD or less then VSS may cause destructive device latchup. For this reason, it is recommended that no inputs row sources operating on a different power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM7228 should be turned on first. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = +5.0V ±10%, VSS = 0V, Unless Otherwise Specified INDUSTRIAL TEMPERATURE RANGE, IPI, IJI, LBI DEVICES TA = 25oC PARAMETER Supply Voltage Range, VSUPPLY Quiescent Supply Current, IQ Operating Supply Current, IDD Digit Drive Current, IDIG Digit Leakage Current, IDLK Peak Segment Drive Current, ISEG Segment Leakage Current, ISLK Input Leakage Current, IIL TEST CONDITIONS -40oC TO 85oC MIN TYP MAX MIN TYP MAX UNITS Operating 4 - 6 4 - 6 V Power Down Mode 2 - - 2 - - Shutdown, ICM7228A, IMC7228B - 1 100 - 1 100 Shutdown, 7228C, 7228D - 2.5 100 - 2.5 100 Common Anode, ICM7228A/C Segments = ON; Outputs = OPEN - 200 450 - 200 450 Common Anode, ICM7228A/C Segments = OFF; Outputs = OPEN - 100 450 - 100 450 Common Cathode, ICM7228B/D Segments = ON; Outputs = OPEN - 250 450 - 250 450 Common Cathode, ICM7228B/D Segments = OFF; Outputs = OPEN - 175 450 - 175 450 Common Anode, ICM7228A/C VOUT = VDD - 2.0V 200 - - 175 - - Common Cathode, ICM7228B/D VOUT = VSS + 1.0V 50 - - 40 - - Shutdown Mode, VOUT = 2.0V Common Anode, ICM7228A/C - 1 100 - 1 100 Shutdown Mode, VOUT = 5.0V Common Cathode, 7228B/D - 1 100 - 1 100 Common Anode, ICM7228A/C VOUT = VSS + 1.0V 20 25 - 20 - - Common Cathode, 7228B/D VOUT = VDD - 2.0V 10 12 - 10 - - Shutdown Mode, VOUT = VDD Common Anode, ICM7228A/C - 1 50 - 1 50 Shutdown Mode, VOUT = VSS Common Cathode, ICM7228B/D - 1 50 - 1 50 All Inputs Except Pin 9 ICM7228C, ICM7228D VIN = VSS - - 1 - - 1 All Inputs Except Pin 9 ICM7228C, ICM7228D VIN = 5.0V - - -1 - - -1 9-20 µA µA mA µA mA µA µA ICM7228 Electrical Specifications VDD = +5.0V ±10%, VSS = 0V, Unless Otherwise Specified INDUSTRIAL TEMPERATURE RANGE, IPI, IJI, LBI DEVICES (Continued) TA = 25oC PARAMETER Display Scan Rate, fMUX TEST CONDITIONS Per Digit -40oC TO 85oC MIN TYP MAX MIN TYP MAX UNITS - 390 - - 390 - Hz 2 10 - 2 - - µs Logical “1” Input Voltage, VINH Three Level Input: Pin 9 ICM7228C, ICM7228D Hexadecimal VDD = 5V 4.2 - - 4.2 - - V Floating Input, VINF Three Level Input: Pin 9 ICM7228C, ICM7228D Code B VDD = 5V 2.0 - 3.0 2.0 - 3.0 V Logical “0” Input Voltage, VINL Three Level Input: Pin 9 ICM7228C, ICM7228D Shutdown VDD = 5V - - 0.8 - - 0.8 V Three Level Input Impedance, ZIN VCC = 5V Pin 9 of ICM7228C and ICM7228D 50 - - 50 - - kΩ Logical “1” Input Voltage, VIH All Inputs Except Pin 9 of ICM7228C, ICM7228D VDD = 5V 2.0 - - 2.0 - - V Logical “0” Input Voltage, VIL All Inputs Except Pin 9 of ICM7228C, ICM7228D VDD = 5V - - 0.8 - - 0.8 V Inter-Digit Blanking Time, tIDB SWITCHING SPECIFICATIONS VDD = +5.0V ±10%, VSS = 0V, VIL = +0.4V, VIH = +2.4V Write Pulsewidth (Low), tWL 200 100 - 250 - - ns Write Pulsewidth (High), tWH 850 540 - 1200 - - ns Mode Hold Time, tMH ICM7228A, ICM7228B 0 -65 - 0 - - ns Mode Setup Time, tMS ICM7228A, ICM7228B 250 150 - 250 - - ns Data Setup Time, tDS 250 160 - 250 - - ns Data Hold Time, tDH 0 -60 - 0 - - ns Digit Address Setup Time, tAS ICM7228C, ICM7228D 250 110 - 250 - - ns Digit Address Hold Time, tAH ICM7228C, ICM7228D 0 -60 - 0 - - ns Electrical Specifications VDD = +5.0V ±10%, VSS = 0V, Unless Otherwise Specified MILITARY TEMPERATURE RANGE, MJI, DEVICES TA = 25oC PARAMETER Supply Voltage Range, VSUPPLY Quiescent Supply Current, IQ Operating Supply Current, IDD -55oC TO 125oC MIN TYP MAX MIN TYP MAX UNITS Operating 4 - 6 4 - 6 V Power Down Mode 2 - - 2 - - V Shutdown, ICM7228A, IMC7228B - 1 100 - 1 100 µA TEST CONDITIONS Shutdown, 7228C, 7228D - 2.5 100 - 2.5 100 µA Common Anode, ICM7228A/C Segments = ON; Outputs = OPEN - 200 450 - 200 550 µA Common Anode, ICM7228A/C Segments = OFF; Outputs = OPEN - 100 450 - 100 450 µA Common Cathode, ICM7228B/D Segments = ON; Outputs = OPEN - 250 450 - 250 550 µA Common Cathode, ICM7228B/D Segments = OFF; Outputs = OPEN - 175 450 - 175 450 µA 9-21 ICM7228 Electrical Specifications VDD = +5.0V ±10%, VSS = 0V, Unless Otherwise Specified MILITARY TEMPERATURE RANGE, MJI, DEVICES (Continued) TA = 25oC PARAMETER Digit Drive Current, IDIG Digit Leakage Current, IDLK Peak Segment Drive Current, ISEG Segment Leakage Current, ISLK Input Leakage Current, IIL Display Scan Rate, fMUX TEST CONDITIONS -55oC TO 125oC MIN TYP MAX MIN TYP MAX UNITS Common Anode, VDD = 5V VOUT = VDD - 2.0V 200 - - 170 - - mA Common Cathode, VDD = 5V VOUT = VSS + 1.0V 50 - - 35 - - mA Shutdown Mode, VOUT = 2.0V Common Anode, ICM7228A/C - 1 100 - 1 100 µA Shutdown Mode, VOUT = 5.0V Common Cathode, 7228B/D - 1 100 - 1 100 µA Common Anode, ICM7228A/C VOUT = VSS + 1.0V, VDD = 5V 20 25 - 20 25 - mA Common Cathode, 7228B/D VOUT = VDD - 2.0V, VDD = 5V 10 12 - 10 12 - mA Shutdown Mode, VOUT = VDD Common Anode, ICM7228A/C - 1 50 - 1 50 µA Shutdown Mode, VOUT = VSS Common Cathode, ICM7228B/D - 1 50 - 1 50 µA All Inputs Except Pin 9 ICM7228C, ICM7228D VIN = VSS - - 1 - - 1 µA All Inputs Except Pin 9 ICM7228C, ICM7228D VIN = 5.0V - - -1 - - -1 µA Per Digit Inter-Digit Blanking Time, tIDB - 390 - - 390 Hz 2 10 - 2 10 µs V Logical “1” Input Voltage, VINH Three Level Input: Pin 9 ICM7228C, ICM7228D Hexadecimal VDD = 5V 4.2 - - 4.2 - Floating Input, VINF Three Level Input: Pin 9 ICM7228C, ICM7228D Code B VDD = 5V 2.0 - 3.0 2.4 - 3.0 V Logical “0” Input Voltage, VINL Three Level Input: Pin 9 ICM7228C, ICM7228D Shutdown VDD = 5V - - 0.8 - - 0.4 V Three Level Input Impedance, ZIN VCC = 5V Pin 9 of ICM7228C and ICM7228D 50 - - 50 - - kΩ Logical “1” Input Voltage, VIH All Inputs Except Pin 9 of ICM7228C, ICM7228D VDD = 5V 2.0 - - 2.0 - - V Logical “0” Input Voltage, VIL All Inputs Except Pin 9 of ICM7228C, ICM7228D VDD = 5V - - 0.8 - - 0.8 V SWITCHING SPECIFICATIONS VDD = +5.0V ±10%, VSS = 0V, VIL = +0.4V, VIH = +2.4V Write Pulsewidth (Low), tWL 200 100 - 250 115 - ns Write Pulsewidth (High), tWH 850 540 - 1200 840 - ns Mode Hold Time, tMH ICM7228A, ICM7228B 0 -65 - 0 -65 - ns Mode Setup Time, tMS ICM7228A, ICM7228B 250 150 - 250 165 - ns 250 160 - 250 160 - ns Data Setup Time, tDS 0 -60 - 0 -60 - ns Digit Address Setup Time, tAS ICM7228C, ICM7228D 250 110 - 250 100 - ns Digit Address Hold Time, tAH ICM7228C, ICM7228D 0 -60 - 0 -60 - ns Data Hold Time, tDH 9-22 ICM7228 Timing Diagrams MODE tMS tMH WRITE MODE tWH tWL WRITE INPUT DATA VALID FIGURE 1. ICM7228A/B WRITE CYCLE DIGIT ADDRESS DAO-DAZ (D8) CONTROL WORD TYPE OF DECODER?ID6 DECODE/NO DECODE? ID5 SHUTDOWN?ID4 DATA COMING ID7 tDH tDS WRITE DATA 8 PULSES (D1) DON’T CARE CONTROL WORD TYPE OF DECODER?ID6 DECODE/NO DECODE? ID5 SHUTDOWN? ID4 DATA COMING ID7 FIGURE 2. ICM7228A/B SEQUENTIAL 8-DIGIT RAM UPDATE VALID tAS tAH tWL WRITE tWH tDH tDS DATA VALID DATA FIGURE 3. ICM7228C/D WRITE CYCLE 10µs (TYP) FREE RUNNING 320µs (TYP) FREE RUNNING (PER DIGIT) INTERDIGIT BLANKING INTERNAL SIGNAL D2 D5 INTERDIGIT BLANKING D1 D7 D8 TYPICAL DIGITS OUTPUT PULSES D6 D4 D3 FIGURE 4. DISPLAY DIGITS MULTIPLEX (COMMON ANODE DISPLAY) Typical Performance Curves -55oC 0 25oC 125oC 100 ISEG (mA) 125oC 300 IDIG (mA) 25oC -55oC 80 200 25oC 60 400 40 500 20 125oC -55oC 5.0 4.0 3.0 2.0 1.0 0 0 0 VDD-VDIG (V) 1.0 2.0 3.0 4.0 5.0 VSEG (V) FIGURE 5. COMMON ANODE DIGIT DRIVER IDIG vs (VDD - VDIG) FIGURE 6. COMMON ANODE SEGMENT DRIVER ISEG vs VSEG 9-23 ICM7228 Typical Performance Curves (Continued) 25oC 0 -55oC 10 125oC 30 300 -55oC 200 40 25oC 125oC 100 ISEG (mA) IDIG (mA) 20 50 0 0 1.0 2.0 3.0 4.0 5.0 5.0 VDIG (V) 4.0 3.0 2.0 1.0 0 VDD-VSEG (V) FIGURE 7. COMMON CATHODE DIGIT DRIVER IDIG vs VDIG FIGURE 8. COMMON CATHODE SEGMENT DRIVER ISEG vs (VDD - VSEG) TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME FUNCTION Output DESCRIPTION 1 SEG c LED Display Segments c, e, b and Decimal Point Drive Lines. 2 SEG e 3 SEG b 4 DP 5 ID6, (HEXA/CODE B) Input When “MODE” Low: Display Data Input, Bit 7. When “MODE” High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 ID5, (DECODE) Input When “MODE” Low: Display Data Input, Bit 6. When “MODE” High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode. 7 ID7, (DATA COMING) Input When “MODE” Low: Display Data Input, Bit 8, Decimal Point Data. When “MODE” High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, No Data Coming. 8 WRITE Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE. 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. 10 ID4, (SHUTDOWN) Input When “MODE” Low: Display Data Input, Bit 5. When “MODE” High: Control Bit, Low Power Mode Select: High, Normal Operation; Low, Oscillator and Display Disabled. 11 ID1 Input When “MODE” Low: Display Data Input, Bit 2. When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, Bit 2, Single Digit Update Mode. 12 ID0 Input When “MODE” Low: Display Data Input, Bit 1. When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, LSB, Single Digit Update Mode. 13 ID2 Input When “MODE” Low: Display Data Input, Bit 3. When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, MSB, Single Digit Update Mode. 14 ID3 Input When “MODE” Low: Display Data Input, Bit 4. When “MODE” High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B 9-24 ICM7228 TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS (Continued) PIN NO. NAME 15 DIGIT 1 16 DlGlT 2 17 DIGIT 5 18 DlGlT 8 19 FUNCTION DESCRIPTION Output LED Display Digits 1, 2, 5 and 8 Drive Lines. VDD Supply Device Positive Power Supply Rail. 20 DIGIT 4 Output LED Display Digits 4, 7, 6 and 3 Drive Lines. 21 DlGlT 7 22 DlGlT 6 23 DIGlT 3 24 SEG f Output LED Display Segments f, d, g and a Drive Lines. 25 SEG d 26 SEG g 27 SEG a 28 VSS Supply Device Ground or Negative Power Supply Rail. TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME FUNCTION Output DESCRIPTION 1 DIGIT 4 LED Display Digits 4, 6, 3 and 1 Drive Lines. 2 DlGlT 6 3 DIGIT 3 4 DlGlT 1 5 ID6, (HEXA/CODE B) Input When “MODE” Low: Display Data Input, Bit 7. When “MODE” High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 ID5, (DECODE) Input When “MODE” Low: Display Data Input, Bit 6. When “MODE” High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode. 7 ID7, (DATA COMING) Input When “MODE” Low: Display Data Input, Bit 8, Decimal Point Data. When “MODE” High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, No Data Coming. 8 WRITE Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE. 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. 10 ID4, (SHUTDOWN) Input When “MODE” Low: Display Data Input, Bit 5. When “MODE” High: Control Bit, Low Power Mode Select: High, Normal Operation; Low, Oscillator and Display Disabled. 11 ID1 Input When “MODE” Low: Display Data Input, Bit 2. When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, Bit 2, Single Digit Update Mode. 12 ID0 Input When “MODE” Low: Display Data Input, Bit 1. When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, LSB, Single Digit Update Mode. 13 ID2 Input When “MODE” Low: Display Data Input, Bit 3. When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, MSB, Single Digit Update Mode. 9-25 ICM7228 TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS (Continued) PIN NO. NAME FUNCTION DESCRIPTION When “MODE” Low: Display Data Input, Bit 4. When “MODE” High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B. 14 ID3 Input 15 DP Output LED Display Decimal Point and Segments a, b, and d Drive Lines 16 SEG a 17 SEG b 18 SEG d 19 VDD Supply Device Positive Power Supply Rail. 20 SEG c Output LED Display Segments c, e, f and g Drive Lines. 21 SEG e 22 SEG f 23 SEG g 24 DIGIT 8 Output LED Display Digits 8, 2, 5 and 7 Drive Lines. 25 DIGIT 2 26 DIGIT 5 27 DIGIT 7 28 VSS Supply Device Ground or Negative Power Supply Rail. TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME FUNCTION Output DESCRIPTION 1 SEG c LED Display Segments c, e, band Decimal Point Drive Lines. 2 SEG e 3 SEG b 4 DP 5 DA0 Input Digit Address Input, Bit 1 LSB. 6 DA1 Input Digit Address Input, Bit 2. 7 ID7, (INPUT DP) Input Display Decimal Point Data Input, Negative True. 8 WRITE Input Data Input Will Be Written to Display RAM on Rising Edge of WRITE. 9 HEXA/CODE B/SHUTDOWN Input Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator, and Display Disabled. 10 DA2 Input Digit Address Input, Bit 3, MSB. 11 ID1 Input Display Data Inputs. 12 ID0 13 ID2 14 ID3 15 DIGIT 1 16 DlGlT 2 17 DIGIT 5 18 DlGlT 8 19 VDD Output LED Display Digits 1, 2, 5 and 8 Drive Lines. Supply Device Positive Power Supply Rail. 9-26 ICM7228 TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS (Continued) PIN NO. NAME 20 DIGIT 4 21 DlGlT 7 22 DlGlT 6 23 DIGlT 3 24 SEG f 25 SEG d 26 SEG g 27 SEG a 28 VSS FUNCTION DESCRIPTION Output LED Display Digits 4, 7, 6 and 3 Drive Lines. Output LED Display Segments f, d, g and a Drive Lines. Supply Device Ground or Negative Power Supply Rail. TABLE 4. ICM7228D PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME FUNCTION Output DESCRIPTION 1 DIGIT 4 2 DlGlT 6 3 DIGIT 3 4 DlGlT 1 5 DA0 6 DA1 Input Digit Address Input, Bit 2. 7 ID7, (INPUT DP) Input Display Decimal Point Data Input, Negative True. 8 WRITE Input Data Input Will Be Written to Display RAM on Rising Edge of WRITE. 9 HEXA/CODE B/SHUTDOWN Input Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator and Display Disabled. 10 DA2 Input Digit Address Input, Bit 3, MSB. 11 ID1 Input Display Data Inputs. 12 ID0 13 ID2 14 ID3 15 DP 16 SEG a 17 SEG b 18 SEG d 19 Input LED Display Digits 4, 6, 3 and 1 Drive Lines. Digit Address Input, Bit 1 LSB. Output LED Display Decimal Point and Segments a, b, and d Drive Lines. VDD Supply Device Positive Power Supply Rail. 20 SEG c Output LED Display Segments c, e, f and g Drive Lines. 21 SEG e 22 SEG f 23 SEG g 24 DIGIT 8 Output LED Display Digits 8, 2, 5 and 7 Drive Lines. 25 DIGIT 2 26 DIGIT 5 27 DIGIT 7 28 VSS Supply Device Ground or Negative Power Supply Rail. 9-27 ICM7228 Detailed Description System Interfacing and Data Entry Modes, ICM7228A and ICM7228B The ICM7228A/B devices are compatible with the architectures of most microprocessor systems. Their fast switching characteristics makes it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM7228A/B inputs, including MODE, feature a 250ns minimum setup and 0ns hold time with a 200ns minimum WRITE pulse. Input logic levels are TTL and CMOS compatible. Figure 9 shows a generic method of driving the ICM7228A/B from a microprocessor bus. To the microprocessor, each device appears to be 2 separate I/O locations; the Control Register and the Display RAM. Selection between the two is accomplished by the MODE input driven by address line A0. Input data is placed on the lD0 - lD7 lines. The WRITE input acts as both a device select and write cycle timing pulse. See Figure 1 and Switching Specifications Table for write cycle timing parameters. The ICM7228A/B have three data entry modes: Control Register update without RAM update, sequential 8-digit update and single digit update. In all three modes a control word is first written by pulsing the WRITE input while the MODE input is high, thereby latching data into the Control Register. The logic level of individual bits in the Control Register select Shutdown, Decode/No Decode, Hex/Code B, RAM bank A/B and Display RAM digit address as shown in Tables 1 and 2. The ICM7228A/B Display RAM is divided into 2 banks, called bank A and B. When using the Hexadecimal or code B display modes, these RAM banks can be selected separately. This allows two separate sets of display data to be stored and displayed alternately. Notice that the RAM bank selection is not possible in No-Decode mode, this is because the display data in the No-Decode mode has 8 bits, but in Decoded schemes (Hex/Code B) is only 4 bits (lD0 - lD3 data). It should also be mentioned that the decimal point is independent of selected bank, a turned on decimal point will remain on for either bank. Selection of the RAM banks is controlled by lD3 input. The lD3 logic level (during Control Register update) selects which bank of the internal RAM to be written to and/or displayed. Control Register Update without RAM Update The Control Register can be updated without changing the display data by a single pulse on the WRITE input, with MODE high and DATA COMING low. If the display is being decoded (Hex/Code B), then the value of lD3 determines which RAM bank will be selected and displayed for all eight digits. Sequential 8-Digit Update The logic state of DATA COMING (lD7) is also latched during a Control Register update. If the latched value of DATA COMING (lD7) is high, the display becomes blanked and a sequential 8-digit update is initiated. Display data can now be written into RAM with 8 successive WRITE pulses, starting with digit 1 and ending with digit 8 (See Figure 2). After all 8 RAM locations have been written to, the display turns on again and the new data is displayed. Additional write pulses are ignored until a new Control Register update is performed. All 8 digits are displayed in the format (Hex/Code B or No Decode) specified by the control word that preceded the 8 digit update. If a decoding scheme (Hex/Code B) is to be used, the value of lD3 during the control word update determines which RAM bank will be written to. Single Digit Update In this mode each digit data in the display RAM can be updated individually without changing the other display data. First, with MODE input high, a control word is written to the Control Register carrying the following information; DATA COMING (lD7) low, the desired display format data on lD4 - lD6, the RAM bank selected by lD3 (if decoding is selected) and the address of the digit to be updated on data lines lD0 - lD2 (See Table 5). A second write to the ICM7228A/B, this time with MODE input low, transfers the data at the lD0 - lD7 inputs into the selected digit’s RAM location. In single digit update mode, each individual digit’s data can be specified independently for being displayed in Decoded or No-Decode mode. For those digits which decoding scheme (Hex/Code B) is selected, only one can be effective at a time. Whenever a control word is written, the specified decoding scheme will be applied to all those digits which selected to be displayed in Decoded mode. DATA BUS D0-D7 MICROPROCESSOR SYSTEM ID0 D0 - D7 I/O OR MEMORY WRITE PULSE ID7 DECODER ENABLE INTERSIL ICM7228A/B DEVICE SELECT AND WRITE PULSE SEGMENTS DRIVE WRITE ADDRESS DECODER A0 MODE A1-A15 DIGITS DRIVE ADDRESS BUS A0 - A15 FIGURE 9. ICM7228A/B MICROPROCESSOR SYSTEM INTERFACING 9-28 LED DISPLAY ICM7228 accordingly called HEXA/CODE B/SHUTDOWN. See Tables 3 and 4 for input and output definitions of the ICM7228C/D devices. TABLE 5. DIGITS ADDRESS, ICM7228A/B INPUT DATA LINES Display Formats 1D2 lD2 lD0 SELECTED DIGIT 0 0 0 DlGlT 1 0 0 1 DlGlT 2 0 1 0 DIGlT 3 0 1 1 DlGlT 4 1 0 0 DIGIT 5 1 0 1 DlGlT 6 The display formats of the ICM7228A/B are selected by writing data to bits ID4, ID5 and ID6 of the Control Register (See Table 1 and 2 for input Definitions). Hexadecimal and Code B data is entered via ID0-lD3 and ID7 controls the decimal point. 1 1 0 DlGlT 7 TABLE 6. DISPLAY CHARACTER SETS 1 1 1 DlGlT 8 The ICM7228A and ICM7228B have three possible display formats; Hexadecimal, Code B and No Decode. Table 6 shows the character sets for the decode modes and their corresponding input code. INPUT DATA CODE DISPLAY CHARACTERS ID3 ID2 ID1 ID0 HEXADECIMAL CODE B System Interfacing, ICM7228C and ICM7228D 0 0 0 0 0 0 The ICM7228C/D devices are directly compatible with the architecture of most microprocessor systems. Their fast switching characteristics make it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM7228C/D inputs, excluding HEXA/CODE B/SHUTDOWN, feature a 250ns minimum setup and 0ns hold time with a 200ns minimum WRITE pulse. Input logic levels are TTL and CMOS compatible. Figure 10 shows a generic method of driving the ICM7228C/D from a microprocessor bus. To the microprocessor, the 8 bytes of the Display RAM appear to be 8 separate I/O locations. Loading the ICM7228C/D is quite similar to a standard memory write cycle. The address of the digit to be updated is placed on lines DA0 - DA2, the data to be written is placed on lines ID0 - lD3 and ID7, then a low pulse on WRITE input will transfer the data in. See Figure 3 and Switching Characteristics Table for write cycle timing parameters. 0 0 0 1 1 1 0 0 1 0 2 2 0 0 1 1 3 3 0 1 0 0 4 4 0 1 0 1 5 5 0 1 1 0 6 6 0 1 1 1 7 7 1 0 0 0 8 8 1 0 0 1 9 9 1 0 1 0 A - 1 0 1 1 b E 1 1 0 0 C H The ICM7228C/D devices do not have any control register, and also they do not provide the No Decode display format. Hexadecimal or Code B character selection and shutdown mode are directly controlled through the three level input at Pin 9, which is 1 1 0 1 d L 1 1 1 0 E P 1 1 1 1 F (Blank) MICROPROCESSOR SYSTEM DATA BUS D0 - D7 I/O OR MEMORY WRITE PULSE DECODER ENABLE 5 DEVICE SELECT AND WRITE PULSE ID0 - ID3 AND ID7 INTERSIL ICM7228C/D SEGMENTS DRIVE WRITE ADDRESS DECODER A0 - A2 A3 - A15 DA0 - DA2 DIGITS DRIVE ADDRESS BUS A0 - A15 FIGURE 10. ICM7228C/D MICROPROCESSOR SYSTEM INTERFACING 9-29 LED DISPLAY ICM7228 minimum of 200mA drive capability. The N-Channel segment driver’s output impedance of 50Ω limits the segment current to approximately 25mA peak current per segment. Both the segment and digit outputs can directly drive the display, current limiting resistors are not required. a f b g e c d DP FIGURE 11. DIGITS SEGMENT ASSIGNMENTS The No Decode mode of the ICM7228A and ICM7228B allows the direct segment-by-segment control of all 64 segments driven by the device. In the No Decode mode, the input data directly control the outputs as shown in Table 7. TABLE 7. NO DECODE SEGMENT LOCATIONS DATA INPUT ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Controlled Segment Decimal Point a b c e g f d An input high level turns on the respective segment, except for the decimal point, which is turned on by an input low level on ID7. The No Decode mode can be used in different applications such as bar graph or status panel driving where each segment controls an individual LED. The ICM7228C and ICM7228D have only the Hexadecimal and Code B character sets. The HEXA/CODE B/SHUTDOWN input, pin 9, requires a three level input. Pin 9 selects the Hexadecimal format when pulled high, the Code B format when floating or driven to mid-supply, and the shutdown mode when pulled low (See Tables 3 and 4). Table 6 also applies to the ICM7228C/D devices. Shutdown and Display Banking When shutdown, the ICM7228 enters a low power standby mode typically consuming only 1µA of supply current for the ICM7228A/B and 2.5µA for the ICM7228C/D. In this mode the ICM7228 turns off the multiplex scan oscillator as well as the digit and segment drivers. However, input data can still be entered when in the shutdown mode. Data is retained in memory even with the supply voltage as low as 2V. The ICM7228A/B is shutdown by writing a control word with Shutdown (lD4) low. The ICM7228C/D is put into shutdown mode by driving pin 9, HEXA/CODE B/SHUTDOWN, low. The ICM7228 operating current with the display blanked is within 100µA - 200µA for all versions. All versions of the ICM7228 can be blanked by writing Hex FF to all digits and selecting Code B format. The ICM7228A and ICM7228B can also be blanked by selecting No Decode mode and writing Hex 80 to all digits (See Tables 6 and 7). Individual segment current is not significantly affected by whether other segments are on or off. This is because the segment driver output impedance is much higher than that of the digit driver. This feature is important in bar graph applications where each bar graph element should have the same brightness, independent of the number of elements being turned on. Common Cathode Display Drivers, ICM7228B and ICM7228D The common cathode digit and segment driver output schematics are shown in Figure 13. The N-channel digit drivers have an output impedance of approximately 15Ω. Each digit has a minimum of 50mA drive capability. The segment drivers have an output impedance of approximately 100Ω with typically 10mA peak current drive for each segment. The common cathode display driver output currents are only 1/ of the common anode display driver currents. Therefore, 4 the ICM7228A and ICM7228C common anode display drivers are recommended for those applications where high display brightness is desired. The ICM7228B and ICM7228D common cathode display drivers are suitable for driving bubble-lensed monolithic 7 segment displays. They can also drive individual LED displays up to 0.3 inches in height when high brightness is not required. Display Multiplexing Each digit of the ICM7228 is on for approximately 320µs, with a multiplexing frequency of approximately 390Hz. The ICM7228 display drivers provide interdigit blanking. This ensures that the segment information of the previous digit is gone and the information of the next digit is stable before the next digit is driven on. This is necessary to eliminate display ghosting (a faint display of data from previous digit superimposed on the next digit). The interdigit blanking time is 10µs typical with a guaranteed 2µs minimum. The ICM7228 turns off both the digit drivers and the segment drivers during the interdigit blanking period. The digit multiplexing sequence is: D2, D5, D1, D7, D8, D6, D4 and D3. A typical digit’s drive pulses are shown on Figure 4. Due to the display multiplexing, the driving duty cycle for each digit is 12% (100 x 1/8) This means the average current for each segment is 1/8 of its peak current. This must be considered while designing and selecting the displays. Driving Larger Displays and If very high display brightness is desired, the ICM7228 display driver outputs can be externally buffered. Figures 14 thru 16 show how to drive either common anode or common cathode displays using the ICM7228 and external driver circuit for higher current displays. The common anode digit and segment driver output schematics are shown in Figure 12. The common anode digit driver output impedance is approximately 4Ω. This provides a nearly constant voltage to the display digits. Each digit has a Another method of increasing display currents is to connect two digit outputs together and load the same data into both digits. This drives the display with the same peak current, but the average current doubles because each digit of the display is on for twice as long, i.e., 1/4 duty cycle versus 1/8 . Common Anode ICM7228C Display Drivers, ICM7228A 9-30 ICM7228 VDD VDD DIGIT STROBE SEGMENT DATA P ≈200mA INTERDIGIT BLANKING ≈200mA P INTERDIGIT BLANKING 100Ω N N N ≈2kΩ N COMMON ANODE DIGIT OUTPUT N ≈2kΩ VSS N ≈2kΩ SHUTDOWN VSS N VSS ≈2kΩ SHUTDOWN NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also stays low. VSS NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also stays low. FIGURE 13B. SEGMENT DRIVER FIGURE 13. COMMON CATHODE DISPLAY DRIVERS FIGURE 12A. DIGIT DRIVER VDD VDD INTERDIGIT BLANKING ≈2kΩ N ≈75Ω SHUTDOWN VDD UP TO 4A DIGIT OUTPUT P SEGMENT DATA COMMON CATHODE SEGMENT OUTPUT COMMON ANODE SEGMENT OUTPUT ICM7228A/B VDD VDD SEGMENT OUTPUT VSS 10K FIGURE 12B. SEGMENT DRIVER FIGURE 12. COMMON ANODE DISPLAY DRIVERS VSS VSS FIGURE 14. DRIVING HIGH CURRENT DISPLAY, COMMON ANODE ICM7228A/C TO COMMON ANODE DISPLAY VDD P INTERDIGIT BLANKING VDD ≈2kΩ DIGIT STROBE N ≈15Ω SHUTDOWN VSS COMMON CATHODE DIGIT OUTPUT VDD SEGMENT OUTPUT 100Ω 2N2219 ICM7228C/D VDD 14Ω (100mAPEAK) DIGIT OUTPUT FIGURE 13A. DIGIT DRIVER 14mA 2N6034 N ≈15Ω VSS 1.4APEAK VSS FIGURE 15. DRIVING HIGH CURRENT DISPLAY, COMMON CATHODE ICM7228B/D TO COMMON CATHODE DISPLAY 9-31 ICM7228 VDD VDD VDD 74C126 THREE-STATE BUFFER HIGH = HEX 1.4APEAK 1K PIN 9 LOW = SHUTDOWN 2N6034 HIGH = HEX OR SHUTDOWN LOW = CODE B 100Ω ICM7228C/D VDD CD4016 CD4066 HIGH = HEX SEGMENT OUTPUT PIN 9 LOW = SHUTDOWN HIGH = HEX OR SHUTDOWN DIGIT OUTPUT 300Ω 1K LOW = CODE B 25Ω CD4069 HIGH = CODE B (100mAPEAK) 1N4148 PIN 9 LOW = HEX 2N2219 N ≈15Ω CONTROL 1K CD4069 HIGH = SHUTDOWN 1N4148 PIN 9 LOW = CODE B VSS VSS CD4069 HIGH = SHUTDOWN LOW = HEX FIGURE 16. DRIVING HIGH CURRENT DISPLAY, COMMON CATHODE ICM7228B/D TO COMMON CATHODE DISPLAY PIN 9 OPEN DRAIN OR OPEN COLLECTOR OUTPUT HIGH = SHUTDOWN PIN 9 LOW = CODE B FIGURE 17. ICM7228C/D PIN 9 DRIVE CIRCUITS Three Level Input, ICM7228C and ICM7228D As mentioned before, pin 9 is a three level input and controls three functions: Hexadecimal display decoding, Code B display decoding and shutdown mode. In many applications, pin 9 will be left open or permanently wired to one state. When pin 9 can not be permanently left in one state, the circuits illustrated in Figure 17 can be used to drive this three level input. Power Supply Bypassing Connect a minimum of 47µF in parallel with 0.1µF capacitors between VDD and VSS of ICM7228. These capacitors should be placed in close proximity to the device to reduce the power supply ripple caused by the multiplexed LED display drive current pulses. Test Circuits ID6 (HEXA/CODE B) ID5 (DECODE) ID7 (DATA COMING) WRITE MODE ID4 (SHUTDOWN) ID1 ID0 ID2 ID3 VDD + 5V VSS 1 28 2 27 3 26 4 25 5 24 6 23 22 7 8 ICM7228A 21 9 20 10 19 11 18 12 17 13 16 14 15 f VDD d 47µF +0.1µF g a VSS c D8 D7 D6 D5 D4 D3 D2 D1 e b COMMON ANODE DISPLAY DP FIGURE 18. FUNCTIONAL TEST CIRCUIT #1 9-32 ICM7228 Test Circuits (Continued) DIGIT ADDRESS 0 DIGIT ADDRESS 1 ID7 (D.P.) WRITE HEXA/CODE B/SHUTDOWN DIGIT ADDRESS 2 ID1 ID0 ID2 ID3 1 28 2 27 3 26 4 25 5 24 6 23 22 7 8 ICM7228D 21 9 20 10 19 11 18 12 17 13 16 14 15 VDD VDD + 5V VSS 47µF +0.1µF VSS g f e c d b a D8 DP D7 D6 D5 D4 D3 D2 D1 COMMON ANODE DISPLAY FIGURE 19. FUNCTIONAL TEST CIRCUIT #2 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 9-33