IGNS DES W E T ® DUC OR N ED F TE PRO 6 D N 8 r at ME ITU 51 COM SUBST 85, HC5 rt Cente c E R 1 E o 5 /ts pp NOT SSIBL HC5 Sheet ,Data l Su l.com PO 5171 echnica .intersi 5 C H w T r ww t our ntac ERSIL o o c r T o 8-IN 1-88 3 REN Ringing SLIC For ISDN Modem/TA and WLL • Sinusoidal Ringing Capability • DI Process Provides Substrate Latch Up Immunity when Driving Inductive Ringers • Adjustable On-Hook Voltage for Fax and Answering Machine Compatibility • Resistive and Complex Impedance Matching • Programmable Loop Current Limit • Switch Hook and Adjustable Ring Trip Detection • Pulse Metering Capability • Single Low Voltage Positive Supply (+5V) Applications • Solid State Line Interface Circuit for Wireless Local Loop, Hybrid Fiber Coax, Set Top Box, Voice/Data Modems • Related Literature - AN9606, Operation of the HC5517 Evaluation Board - AN9607, Impedance Matching Design Equations - AN9628, AC Voltage Gain - AN9608, Implementing Pulse Metering - AN9636, Implementing an Analog Port for ISDN Using the HC5517 - AN549, The HC-5502S/4X Telephone Subscriber Line Interface Circuits (SLIC) A thermal shutdown with an alarm output and line fault protection are also included for operation in harsh environments. Part Number Information HC5517IM PACKAGE PKG. NO. -40 to 85 28 Ld PLCC N28.45 HC5517CM 0 to 75 28 Ld PLCC N28.45 HC5517IB -40 to 85 28 SOIC M28.3 HC5517CB 0 to 75 28 SOIC M28.3 4147.3 • Thru-SLIC Open Circuit Ringing Voltage up to 77VPEAK/54VRMS , 3 REN Capability at 44V RMS The device is manufactured in a high voltage Dielectric Isolation (DI) process with an operating voltage range from -16V, for offhook operation and -80V for ring signal injection. The DI process provides substrate latch up immunity, resulting in a robust system design. Together with a secondary protection diode bridge and “feed” resistors, the device will withstand 1000V lightning induced surges, in a plastic package. TEMP. RANGE (oC) File Number October 2000 Features The HC5517 is a ringing SLIC designed to accommodate a wide variety of local loop applications. The various applications include, basic POTS lines with answering machines and fax capabilities, ISDN networks, wireless local loop, and hybrid fiber coax (HFC) terminals. The HC5517 provides a high degree of flexibility with open circuit tip to ring DC voltages, user defined ringing waveforms (sinusoidal to square wave), ring trip detection thresholds and loop current limits that can be tailored for many applications. Additional features of the HC5517 are complex impedance matching, pulse metering and transhybrid balance. The HC5517 is designed for use in systems where a separate ring generator is not economically feasible. PART NUMBER HC5517 Block Diagram TIP FEED TIP SENSE RING FEED 2-WIRE INTERFACE LOOP CURRENT DETECTOR RING SENSE 1 VREF RTI VRING - - IN 1 FAULT DETECTOR OUT 1 CURRENT LIMIT SHD ALM ILMT RING TRIP DETECTOR VBAT BIAS RTD AGND IIL LOGIC INTERFACE BGND F1 1 VTX + RING SENSE 2 VCC VRX 4-WIRE INTERFACE F0 RS TST RELAY DRIVER RDO RDI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HC5517 Absolute Maximum Ratings TA = 25oC Thermal Information Maximum Supply Voltages (V CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V (VCC)-(VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V Thermal Resistance (Typical, Note 1) Operating Conditions Operating Temperature Range HC5517IM, HC5517IB . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC HC5517CM, HC5517CB . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V Positive Power Supply (VCC). . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Negative Power Supply (V BAT) . . . . . . . . . . . . . . . . . . . -16V to -80V θJA (oC/W) PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC, PLCC - Lead Tips Only) Die Characteristics Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VBAT Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. All grounds (AGND, BGND) must be applied before VCC or VBAT . Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RINGING TRANSMISSION PARAMETERS VRING Input Impedance (Note 3) - 5.4 - kΩ 4-Wire to 2-Wire Gain VRING to Vt-r (Note 3) - 40 - V/V RX Input Impedance 300Hz to 3.4kHz (Note 3) - 108 - kΩ TX Output Impedance 300Hz to 3.4kHz (Note 3) - - 20 Ω 4-Wire Input Overload Level 300Hz to 3.4kHz RL = 1200Ω, 600Ω Reference (Note 3) +1.0 - - VPEAK 2-Wire Return Loss Matched for 600Ω (Note 3) SRL LO 26 35 - dB ERL 30 40 - dB SRL HI 30 40 - dB AC TRANSMISSION PARAMETERS 2-Wire Longitudinal to Metallic Balance Off Hook Per ANSI/IEEE STD 455-1976 (Note 3) 300Hz to 3400Hz 58 63 - dB 4-Wire Longitudinal Balance Off Hook 300Hz to 3400Hz (Note 3) 50 55 - dB Low Frequency Longitudinal Balance - 10 23 dBrnC Longitudinal Current Capability ILINE = 40mA TA = 25oC (Note 3) ILINE = 40mA TA = 25oC (Note 3) - - 40 mARMS Insertion Loss 0dBm at 1kHz, Referenced 600Ω 2-Wire/4-Wire (Includes external transhybrid amplifier with a gain of 3) - ±0.05 ±0.2 dB 4-Wire/2-Wire - ±0.05 ±0.2 dB 4-Wire/4-Wire (Includes external transhybrid amplifier with a gain of 3) - - ±0.25 dB 2 HC5517 Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - ±0.02 ±0.06 dB +3 to -40dBm - - ±0.08 dB -40 to -50dBm - - ±0.12 dB -50 to -55dBm - - ±0.3 dB Frequency Response 300Hz to 3400Hz (Note 3) Referenced to Absolute Level at 1kHz, 0dBm Referenced 600Ω Level Linearity Referenced to -10dBm (Note 3) 2-Wire to 4-Wire and 4-Wire to 2-Wire Absolute Delay (Note 3) 2-Wire/4-Wire 300Hz to 3400Hz - - 1.0 µs 4-Wire/2-Wire 300Hz to 3400Hz - - 1.0 µs 4-Wire/4-Wire 300Hz to 3400Hz - 0.95 1.5 µs Transhybrid Loss VIN = 1VP-P at 1kH (Notes 3, 4) 30 40 Total Harmonic Distortion 2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire Reference Level 0dBm at 600Ω 300Hz to 3400Hz (Note 3) - - -50 dB Idle Channel Noise 2-Wire and 4-Wire (Note 3) C-Message - 3 - dBrnC Psophometric (Note 3) - -87 - dBmp 20 40 - dB VCC to 4-Wire 20 40 - dB VBAT to 2-Wire 20 40 - dB V BAT to 4-Wire 20 50 - dB 30 40 - dB 20 28 - dB VBAT to 2-Wire 20 50 - dB V BAT to 4-Wire 20 50 - dB 20 (Note 5) - 60 mA 10 - - % - ±4 ±7 mA TIP to Ground (Note 3) - 30 - mA RING to Ground - 120 - mA TIP and RING to Ground (Note 3) - 150 - mA - 12 15 mA -0.28 -0.24 -0.22 V 160 oC Power Supply Rejection Ratio (Note 3) 30Hz to 200Hz, RL = 600Ω VCC to 2-Wire V CC to 2-Wire (Note 3) 200Hz to 16kHz, RL = 600Ω VCC to 4-Wire dB DC PARAMETERS Loop Current Programming Limit Range Accuracy Loop Current During Power Denial RL = 200Ω Fault Currents Switch Hook Detection Threshold Ring Trip Comparator Voltage Threshold Thermal ALARM Output (Note 3) 3 Safe Operating Die Temperature Exceeded 140 - HC5517 Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 0.1 0.5 ms - 0.2 0.5 V - ±10 ±100 µA Logic ‘0’ VIL 0 - 0.8 V Logic ‘1’ VIH 2.0 - 5.5 V Dial Pulse Distortion (Note 3) Uncommitted Relay Driver IOL (RDO) = 30mA On Voltage V OL Off Leakage Current TTL/CMOS Logic Inputs (F0, F1, RS, TST, RDI) Input Current (F0, F1, RS, TST, RDI) IIH, 0V ≤ VIN ≤ 5V - - -1 µA Input Current (F0, F1, RS, TST, RDI) IIL, 0V ≤ VIN ≤ 5V - - -100 µA Logic ‘0’ VOL ILOAD = 800µA - 0.1 0.5 V Logic ‘1’ VOH ILOAD = 40µA 2.7 - - V Logic Outputs Power Dissipation On Hook VCC = +5V, VBAT = -80V, RLOOP = ∞ - 300 - mW VCC = +5V, VBAT = -48V, RLOOP = ∞ - 150 - mW - 280 - mW Power Dissipation Off Hook VCC = +5V, VBAT = -24V, RLOOP = 600Ω, IL = 25mA ICC VCC = +5V, VBAT = -80V, RLOOP = ∞ - 3 6 mA VCC = +5V, VBAT = -48V, RLOOP = ∞ - 2 5 mA VCC = +5V, VBAT = -24V, RLOOP = ∞ - 1.9 4 mA VCC = +5V, VB- = -80V, RLOOP = ∞ - 3.6 7 mA VCC = +5V, VB- = -48V, RLOOP = ∞ - 2.6 6 mA VCC = +5V, VB- = -24V, RLOOP = ∞ - 1.8 4 mA Input Offset Voltage - ±5 - mV Input Offset Current - ±10 - nA Differential Input Resistance (Note 3) - 1 - MΩ - ±3 - VP-P - 1 - MHz IBAT UNCOMMITTED OP AMP PARAMETERS Output Voltage Swing (Note 3) RL = 10kΩ Small Signal GBW (Note 3) NOTES: 3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 4. For transhybrid circuit as shown in Figure 10. 5. Application limitation based on maximum switch hook detect limit and metallic currents. Not a part limitation. 4 HC5517 Functional Diagram PLCC/SOIC R TF 25 TF OUT 1 VRX R + 17 12 R VRING -IN 1 13 24 VCC VTX 19 AGND 2 + OP AMP 1 BIAS NETWORK R/2 22 27 +2V BGND VBAT R/20 R 4 2R F1 R 14 TA R + R 2R F0 SH SHD RS THERM LTD 4.5K RING SENSE 1 RING SENSE 2 15 16 TSD 25K 100K 100K 6 + 100K 25K GK RTD RA 100K IIL LOGIC INTERFACE TIP SENSE 5 FAULT DET 4.5K 9 TST 7 SHD 8 90K RFC 90K RF 26 RF R = 108kΩ 10 + GM 90K 3 VREF VB/2 REF 18 + 11 28 NU 21 RF2 RTI RTD ALM RDO 20 ILMT RDI HC5517 TRUTH TABLE F1 F0 0 0 Loop power Denial Active 0 1 Power Down Latch RESET 0 1 Power on RESET 1 0 RD Active 1 1 Normal Loop feed Over Voltage Protection and Longitudinal Current Protection ACTION . TABLE 1. PERFORMANCE (MAX) UNITS 10µs Rise/ 1000µs Fall ±1000 (Plastic) VPEAK Metallic Surge 10µs Rise/ 1000µs Fall ±1000 (Plastic) VPEAK T/GND 10µs Rise/ 1000µs Fall ±1000 (Plastic) VPEAK T/GND 11 Cycles 700 (Plastic) VRMS R/GND Limited to 10A RMS The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. Longitudinal Surge High voltage surge conditions are as specified in Table 1. The SLIC will withstand longitudinal currents up to a maximum or 30mARMS , 15mARMS per leg, without any performance degradation PARAMETER R/GND TEST CONDITION 50/60Hz Current 5 HC5517 Circuit Operation and Design Information The HC5517 is a voltage feed current sense Subscriber Line Interface Circuit (SLIC). This means that for long loop applications the SLIC provides a constant voltage to the tip and ring terminals while sensing the tip to ring current. For short loops, where the loop current limit is exceeded, the tip to ring voltage decreases as a function of loop resistance. The following discussion separates the SLIC’s operation into its DC and AC path, then follows up with additional circuit design and application information. DC Operation of Tip and Ring Amplifiers SLIC in the Active Mode The tip and ring amplifiers are voltage feedback op amps that are connected to generate a differential output (e.g. if tip sources 20mA then ring sinks 20mA). Figure 1 shows the connection of the tip and ring amplifiers. The tip DC voltage is set by an internal +2V reference, resulting in -4V at the output. The ring DC voltage is set by the tip DC output voltage and an internal VBAT/2 reference, resulting in VBAT +4V at the output. (See Equation 1, Equation 2 and Equation 3.) R V TIPFEED = V C = – 2V ----------- = – 4V R ⁄ 2 (EQ. 1) V BAT R R V RINGFEED = V D = --------------- 1 + ---- – V TI PF EED ---- R R 2 (EQ. 2) V RINGFEED = V D = VBAT + 4 (EQ. 3) Current Limit The tip feed to ring feed voltage (Equation 1 minus Equation 3) is equal to the battery voltage minus 8V. Thus, with a 48 (24) volt battery and a 600Ω loop resistance, including the feed resistors, the loop current is 66.6mA (26.6mA). On short loops the line resistance often approaches zero and the need exists to control the maximum DC loop current. Current limiting is achieved by a feedback network (Figure 1) that modifies the ring feed voltage (VD) as a function of the loop current. The output of the Transversal Amplifier (TA) has a DC voltage that is directly proportional to the loop current. This voltage is scaled by R10 and R 28 . The scaled voltage is the input to a transconductance amplifier (GM) that compares it to an internal reference level. When the scaled voltage exceeds the internal reference level, the transconductance amplifier sources current. This current charges C 16 in the positive direction causing the ring feed voltage (V D) to approach the tip feed voltage (VC ). This effectively reduces the tip feed to ring feed voltage (V T-R), and holds the maximum loop current constant. The maximum loop current is programed by resistors R10 and R28 as shown in Equation 4 (Note: R10 is typically 100kΩ). ( 0.6 ) ( R 10 + R 28 ) I LIMIT = --------------------------------------------( 200xR 28 ) (EQ. 4) 0 VRX R R TIP AND RING VOLTAGE (V) VTIP FEED = -4V R OUT1 TIP FEED TIP R11 R13 R/20 VRING - + R/2 - V + C TRANSVERSAL AMP TA + INTERNAL - +2V REF VTX + R10 - GM + R28 RF2 90kΩ RING FEED RING R12 R14 - 90kΩ + VOUT1, VRX GROUNDED FOR DC ANALYSIS + C16 - VD - + VBAT 2 FIGURE 1. OPERATION OF THE TIP AND RING AMPLIFIERS 6 CONSTANT VOLTAGE REGION -10 -15 VRING FEED = -20V -20 CURRENT LIMIT REGION ILOOP = 25mA -25 0 - 90kΩ -5 250 500 750 LOOP RESISTANCE (Ω) ∞ FIGURE 2. VT-R vs RL (VBAT = -24V, ILIMIT = 25mA) Figure 2 illustrates the relationship between V T-R and the loop resistance. The conditions are shown for a battery voltage of -24V and the loop current limit set to 25mA. For a infinite loop resistance both tip feed and ring feed are at -4V and -20V respectively. When the loop resistance decreases from infinity to about 640Ω the loop current (obeying Ohm’s Law) increases from 0mA to the set loop current limit. As the loop resistance continues to decrease, the ring feed voltage approaches the tip feed voltage as a function of the programed loop current limit (Equation 4). HC5517 AC Voltage Gain Design Equations 4R S ∆I L R 8 VRX I R = – -------------------- ------- + ----------R R R 9 The HC5517 uses feedback to synthesize the impedance at the 2-wire tip and ring terminals. This feedback network defines the AC voltage gains for the SLIC. The AC voltage at VC is then equal to: The 4-wire to 2-wire voltage gain (VRX to VTR) is set by the feedback loop shown in Figure 3. The feedback loop senses the loop current through resistors R13 and R14 , sums their voltage drop and multiplies it by 2 to produce an output voltage at the VTX pin equal to +4RS∆IL. The VTX voltage is then fed into the -IN1 input of the SLIC’s internal op amp. This signal is multiplied by the ratio R8 /R9 and fed into the tip current summing node via the OUT1 pin. (Note: the internal VBAT/2 reference (ring feed amplifier) and the internal +2V reference (tip feed amplifier) are grounded for the AC analysis.) - (EQ. 9) V C – VD ∆IL = -------------------------------------------------------------------------R L + R 11 + R 12 + R 13 + R 14 R IR R + ∆IL - OUT1 R/20 IOUT1 = VRING R11 R13 - R/2 + + VC VC = ∆VIN - + VRX +RS∆IL R8 R9 +2 R11 = R 12 = R13 = R14 = R S + - ∆IL + 90kΩ -IN1 VTX - + + 2V DC - + ∆IL + RL R8 –4 R S ∆I L ------- R9 - - 4RS∆I L R8 2R R9 † - A (EQ. 11) 1VP VRX TIP VTR (EQ. 10) The loop current (∆IL) with respect to the feedback network, is calculated in Equations 11 through 14. Where R8 = 40kΩ, R9 = 40kΩ, RL = 600Ω, R11 = R12 = R13 = R 14 = 50Ω. (EQ. 6) R + ∆IL R 8 V C = – 4 R S ∆IL ------- + VRX R 9 The values for R 8 and R9 are selected to match the impedance requirements on tip and ring, for more information reference AN9607 “Impedance Matching Design Equations for the HC5509 Series of SLICs”. The following loop current calculations will assume the proper R8 and R9 values for matching a 600Ω load. Equation 6 is the node equation for the tip amplifier summing node. The current in the tip feedback resistor (IR) is given in Equation 7. –4 ( R S ∆I L ) R 8 V RX I R = ------------------------------ ------- + ------------R R R 9 (EQ. 8) R 8 V D = 4R S ∆IL ------- – VRX R 9 (EQ. 5) 4R S ∆IL R 8 VRX – I R – -------------------- ------- + ----------- = 0 R R R 9 VC = (IR) (R ) and the AC voltage at V D is: The current into the OUT1 pin is equal to: 4R S ∆IL R 8 I OUT1 = – -------------------- ------- R R 9 (EQ. 7) R8 4RS∆I L R9 + + 4RS∆IL -RS∆IL - 90kΩ - + B R12 R14 - RING † + - ∆IL + - ∆IL + + - VD V D R 8 = 4R ∆I ------- – V S LR RX 9 - + VBAT † GROUNDED FOR AC ANALYSIS 2 FIGURE 3. AC VOLTAGE GAIN AND IMPEDANCE MATCHING 7 HC5517 Substituting the expressions for VC and VD : 2× R 8 – 4 R S ∆I L ------- R 9 + VR X ∆IL = -------------------------------------------------------------------------R L + R 11 + R 12 + R 13 + R 14 (EQ. 12) The net effect cancels out the voltage drop across the feed resistors. By nullifying the effects of the feed resistors the feedback circuitry becomes relatively easy to match the impedance at points “A” and “B”. IMPEDANCE MATCHING DESIGN EQUATIONS Equation 12 simplifies to: 2V R X – 400 ∆IL ∆IL = ---------------------------------------800 (EQ. 13) Solving for ∆IL results in: VR X ∆IL = ----------600 (EQ. 14) Equation 14 is the loop current with respect to the feedback network. From this, the 4-wire to 2-wire and the 2-wire to 4-wire AC voltage gains are calculated. Equation 15 shows the 4-wire to 2-wire AC voltage gain is equal to one. VR X ----------- ( 600 ) ∆I L ( R L ) V TR 600 A 4W – 2W = ----------- = --------------------- = --------------------------- = 1 VRX V RX VRX (EQ. 15) Matching the impedance of the SLIC to the load is accomplished by writing a loop equation starting at VD and going around the loop to VC . The loop equation to match the impedance of any load is as follows (Note: VRX = 0 for this analysis): R 8 – 4R S ∆I L ------- + 2R S ∆IL – ∆V IN + R 9 R 8 R L ∆IL + 2R S ∆IL – 4R S ∆IL ------- = 0 R 9 (EQ. 17) R 8 ∆V IN = – 8R S ∆I L ------- + 4R S ∆I L + R L ∆IL R 9 (EQ. 18) R 8 ∆V IN = ∆I L –8R S ------- + 4R S + R L R (EQ. 19) Equation 16 shows the 2-wire to 4-wire AC voltage gain is equal to negative one-third. R 8 VR X – 4 R S ∆I L ------- – 200 ----------- ( 1 ) V OUT1 R 9 1 600 A 2W – 4W = ------------------- = ------------------------------------- = ---------------------------------- = – --3 VRX V TR ∆IL ( R L ) ----------- ( 600 ) 600 (EQ. 16) 9 Equation 19 can be separated into two terms, the feedback (-8RS(R8/R9)) and the loop impedance (+4RS+RL). ∆V I N R 8 ------------- = – 8 R S ------- + 4R S + R L ∆I L R 9 (EQ. 20) The result is shown in Equation 20. Figure 4 is a schematic representation of Equation 15. Impedance Matching RL The feedback network, described above, is capable of synthesizing both resistive and complex loads. Matching the SLIC’s 2-wire impedance to the load is important to maximize power transfer and minimize the 2-wire return loss. The 2-wire return loss is a measure of the similarity of the impedance of a transmission line (tip and ring) and the impedance at it’s termination. It is a ratio, expressed in decibels, of the power of the outgoing signal to the power of the signal reflected back from an impedance discontinuity. Requirements for Impedance Matching Impedance matching of the HC5517 application circuit to the transmission line requires that the impedance be matched to points “A” and “B” in Figure 3. To do this, the sense resistors R11 , R12 , R13 and R14 must be accounted for by the feedback network to make it appear as if the output of the tip and ring amplifiers are at points “A” and “B”. The feedback network takes a voltage that is equal to the voltage drop across the sense resistors and feeds it into the summing node of the tip amplifier. The effect of this is to cause the tip feed voltage to become more negative by a value that is proportional to the voltage drop across the sense resistors R11 and R13 . At the same time the ring amplifier becomes more positive by the same amount to account for resistors R12 and R14 . 8 LOAD ∆VIN + - SLIC R 8 8RS ------- + 4R S R 9 FIGURE 4. SCHEMATIC REPRESENTATION OF EQUATION 20 To match the impedance of the SLIC to the impedance of the load, set: R 8 R L = 8R S ------- + 4R S R 9 (EQ. 21) If R9 is made to equal 8RS then: R L = R 8 + 4R S (EQ. 22) Therefore to match the HC5517, with RS equal to 50Ω, to a 600Ω load: R 9 = 8R S = 8 ( 50Ω ) = 400Ω (EQ. 23) and: R 8 = R L – 4 R S = 600Ω – 200Ω = 400Ω (EQ. 24) HC5517 To prevent loading of the VTX output, the value of R8 and R9 are typically scaled by a factor of 100: KR 8 = 40kΩ KR 9 = 40k Ω +5V (EQ. 25) R24 Since the impedance matching is a function of the voltage gain, scaling of the resistors to achieve a standard value is recommended. Reactive KR 8 = 100 ( Resistive – 200 ) + -------------------------100 (EQ. 26) TO ZENER DIODE D11 R D13 R/20 VRING - TF R/2 D6 + TIP FEED AMPLIFIER Reference application note AN9607 (“Impedance Matching Design Equations for the HC5509 Series of SLICs”) for the values of KR9 and KR8 for several worldwide Typical line impedances. Tip-to-Ring Open-Circuit Voltage T2 RC For complex impedances the above analysis is the same. KR 9 = 40kΩ R19 90kΩ - RF + The tip-to-ring open-circuit voltage, VOC , of the HC5517 is programmable to meet a variety of applications. The design of the HC5517 defaults the value of VOC to: +2V +- R18 VC 90kΩ 90kΩ V BAT ----------------2 RING FEED AMPLIFIER FIGURE 5. CENTERING VOLTAGE APPLICATION CIRCUIT V OC ≅ VBAT – 8 The HC5517 application circuit overrides the default VOC operation when operating from a -80V battery. While operating from a -80V battery, the SLIC will be in either the ringing mode or on-hook standby mode. In the ringing mode, VOC is designed to switch from 0V (centering voltage) to 47V (Maintenance Termination Unit voltage). The centering voltage is active during the ringing portion of the ringing waveform and the Maintenance Termination Unit (MTU) voltage is active during the silent portion of the ringing signal. In the on-hook standby mode, the application circuit is designed to maintain VOC at the MTU voltage. Centering Voltage Application Circuit Overview The centering voltage is used during ringing to center the DC outputs of the tip feed and ring feed amplifiers. Centering the amplifier outputs allows for the maximum undistorted voltage swing of the ringing signal. Without centering, the output of each amplifier would saturate at ground or VBAT , minimizing the ringing capability of the HC5517. The required centering voltage, V C , is +1.8V DC when operating from a -80V battery. Centering Voltage Application Circuit Operation The circuit used to generate the centering voltage is shown in Figure 5. 9 The circuitry within the dotted lines is internal to the HC5517. The value of the resistor designated as R is 108kΩ and the resistor R/20 is 5.4kΩ. The tip amplifier gain of 20V/V amplifies the +1.8VDC at VC to +36VDC and adds it to the internal 4VDC offset, generating -40VDC at the tip amplifier output. The 40VDC offset also sums into the ring amplifier, adding to the battery voltage, achieving -40V at the ring amplifier output. Centering Voltage Design Equations The centering voltage (VC) is dependent on the battery voltage. A battery voltage of -80V requires a +1.8VDC centering voltage. The equation used to calculate the centering voltage is shown below. VC = VBAT --------------- – 4 ⁄ 20 2 (EQ. 27) The DC voltage at the outputs of the centered tip and ring amplifiers can be calculated from Equation 28 and Equation 29. V TC = – ( 20V C + 4 ) (EQ. 28) V RC = V BAT + ( 20V C + 4 ) (EQ. 29) The shunt resistor of the divider network, R18 , is not determined from a design equation. It is selected based on the trade-off of power dissipation in the voltage divider (low value of R18) and loading affects of the internal R/20 resistor (high value of R18). The suggested range of R 18 is between 1.0kΩ and 2.0kΩ. The application circuit design equation used to calculate the value of R19 of the divider network is as follows: HC5517 (EQ. 30) where:VD13 forward drop of D13 , 0.63V. VD6 forward drop of D 6 , 0.54V. R18 is the shunt resistor of the divider, 1.1kΩ. RIN is the input impedance of VRING , 5.4kΩ. VC is the required centering voltage, 1.8V, VBAT = -80V. VCC is the +5V supply. Centering Voltage Logic Control The pnp transistor T2 is used to defeat the voltage divider formed by R 19 , R18 , D13 and D6 . When T2 is off (RC is logic high), +5VDC is divided to produce +1.8V DC at the VRING input. When T2 is on (RC is logic low), its emitter base voltage of +0.9V DC is divided resulting in +0.2V at the anode of D 6 , hence reverse biasing the diode (D6) and floating the VRING pin. MTU Voltage Application Circuit Overview According to Bellcore specification TR-NWT-000057, an MTU voltage may be required by some operating companies. The minimum allowable voltage to meet MTU requirements is 42.75V, which is used by measurement equipment to verify an active line. Also, some facsimile and answering machines use the MTU voltage as an indication that the telephone is on-hook or not answered. In addition to the Bellcore specification, FCC Part 68.306 requires that the maximum tip to ground or ring to ground voltage not exceed -56.5V for hazardous voltage limitations. These two requirements have been combined and the resulting range is defined as the MTU voltage. The HC5517 application circuit can be programmed to any voltage within this range using the zener clamping circuit. MTU Voltage Application Circuit Operation The circuit used to generate the MTU voltage is shown in Figure 6. 90K Internal to the HC5517 are connections to the tip feed amplifier output and VBAT/2 reference. The DC voltage at the tip feed output, VTDC , is a constant -4V during on-hook standby. MTU Voltage Design Equations The following equations are used to predict the DC output of the ring feed amplifier, VRDC . V BAT --------------- < VZ 2 V BAT V R DC = 2 --------------- + 4 2 (EQ. 31) V BAT --------------- ≥ VZ 2 V R DC = 2 ( – V Z + ( VCE – V BE ) ) + 4 (EQ. 32) Where VZ is the zener diode voltage of D 11 and VCE and VBE are the saturation voltages of T2 . Using Equations 31 and 32, the tip-to-ring open-circuit voltage can be calculated for any value of zener diode and battery voltage. V BAT --------------- < VZ 2 VBAT V OC = VTDC – 2 --------------- – 4 2 V BAT --------------- ≥ VZ 2 V OC = VTDC – 2 ( – V Z + ( V CE – VBE ) ) – 4 (EQ. 33) (EQ. 34) Figure 7 plots VOC as a function of battery voltage. The graph illustrates the clamping function of the zener circuitry. TIP TO RING OPEN CIRCUIT VOLTAGE (V) ( V CC – V D13 – VD6 – V C ) ( R 18 • R IN ) R 19 = ---------------------------------------------------------------------------------------------------( V C + V D 6 )R I N + V C R 18 +50 +40 +30 +20 +10 0 -16 -28 -40 -52 -58 -68 -80 FIGURE 7. VOC AS A FUNCTION OF BATTERY VOLTAGE 90K TIP FEED OUTPUT - RF 90K + RING FEED AMPLIFIER VREF 3 C16 MTU Voltage Logic Control V BAT ----------------2 +5V R24 R19 D11 T2 RC FIGURE 6. RING FEED AMPLIFIER CIRCUIT CONNECTIONS The ring feed amplifier DC output voltage, VRDC , is a function of the internal VBAT/2 reference and external zener diode D11 . When the magnitude of VBAT/2 is less than the zener voltage, the zener is off and the input to the ring feed amplifier is VBAT/2. When the magnitude of VBAT/2 is greater than the zener voltage, the zener conducts and clamps the noninverting terminal of the ring amplifier to the zener voltage. 10 The same pnp transistor, T2 , that is used to control the centering voltage is also used to control the MTU voltage. The application circuit uses T2 to ground or float the anode of the zener diode D11 . When RC is a logic low (T2 on) the anode of D11 is referenced to ground through the collector base junction of the transistor. Current then flows through the zener, allowing the ring amplifier input to be clamped. When RC is a logic high (T2 off) the anode of D 11 floats, inhibiting the clamping action of the zener. HC5517 Modes of Operation The four modes of operation of the HC5517 Ringing SLIC are ringing, on-hook standby, off-hook active and power denial. Three control signals select the operating mode of the SLIC. The signals are Battery Switch, F1 and Ring Cadence (RC). The active application circuit and active supervisory function are different for each mode, as shown in the Table 2. HC5517 Mode Control Signals The Battery Switch selects between the -80V and -24V supplies. The Battery Switch circuitry is described in the “Operation of the Battery Switch” section. A system alternative to the battery switch signal is to use a buffered version of the SHD output to select the battery voltage. Another alternative is to control the output of a programmable battery supply, removing the battery switch entirely from the application circuit. F1 is used to put the SLIC in the power denial mode. RC drives the base of T2 , which is the transistor used to control the centering voltage and MTU voltage. The three control signals can be driven from a TTL logic source or an open collector output. Ringing Mode The ringing state, as the name indicates, is used to ring the telephone with a -80V battery supply. The SLIC is designed for balanced ringing with a differential gain of 40V/V across tip and ring. Voltage feed amplifiers operating in the linear mode are used to amplify the ringing signal. The linear amplifier approach allows the system designer to define the shape and amplitude of the ringing waveform. Both supervisory function outputs, SHD and RTD, are active during ringing. Spectral Content of the Ringing Signal The shape of the waveform can range from sinusoidal to trapezoidal. Sinusoidal waveforms are spectrally cleaner than trapezoidal waveforms, although the latter does result in lower power dissipation across the SLIC for a given RMS amplitude. Systems where the ringing signal will be in proximity to digital data lines will benefit from the sinusoidal ringing capability of the HC5517. The slow edge rates of a sinusoid will minimize coupling of the large amplitude ringing signal. The linear amplifier architecture of the HC5517 allows the system designer to optimize the design for power dissipation and spectral purity. the 4-wire side that is amplified by the SLIC to ring the telephone. The centering voltage, as previously discussed, is a positive DC offset that is applied to the VRING input along with the ringing waveform. The HC5517 application circuit provides the centering voltage, simplifying the system interface to an AC coupled ringing waveform. Ringer Equivalence Number Before any further discussion, the Ringer Equivalence Number or REN must be discussed. Based on FCC Part 68.313 a single REN can be defined as 5kΩ, 7kΩ or 8kΩ of AC impedance at the ringing frequency. The ringing frequency is based on the ringing types listed in Table 1 of the FCC specification. The impedance of multiple REN is the paralleling of a single REN. Therefore 5 REN can either be 1kΩ, 1.4kΩ or 1.6kΩ. The 7kΩ model of a single REN will be used throughout the remainder of the data sheet. Ringing Waveform An amplitude of 1.2VRMS will deliver approximately 46VRMS to a 1 REN load, and 42V RMS to a 3 REN load. The amplitude is REN dependent and is slightly attenuated by the feedback scheme used for impedance matching. The ringing waveform is cadenced, alternating between a 20Hz burst and a silent portion between bursts. Bellcore specification TR-NWT-000057 defines seven distinct ringing waveforms or alerting (ringing) patterns. The following table lists each type. TABLE 2. DISTINCTIVE ALERTING PATTERNS INTERVAL DURATION IN SECONDS PATTERN RINGING SILENT RINGING SILENT RINGING SILENT A 0.4 0.2 0.4 0.2 0.8 4.0 B 0.2 0.1 0.2 0.1 0.6 4.0 C 0.8 0.4 0.8 0.4 D 0.4 0.2 0.6 4.0 E 1.2 4.0 Amplitude of the Ringing Signal F 1 ± 0.2 3 ± 0.3 Amplitude control is another benefit of the linear amplifier architecture. Systems that require less ringing amplitude are able to do so by driving the HC5517 with a lower level ringing waveform. Solutions that use saturated amplifiers can only vary the amplitude of the ringing signal by changing the negative battery voltage to the SLIC. G 0.3 0.2 1.0 0.2 0.3 4.0 HC5517 Through SLIC Ringing The HC5517 is designed with a high gain input, VRING , that the system drives while ringing the phone. V RING is one of many signals summed at the inverting input to the tip feed amplifier. The gain of the VRING signal through the tip feed amplifier is set to 20V/V. The output of the tip feed amplifier is summed at the inverting input of the ring feed amplifier, configured for unity gain. The result is a differential gain of 40V/V across tip and ring of the ringing signal. The ringing function requires an input ringing waveform and a centering voltage. The ringing waveform is the signal from 11 Figure 8 shows the relationship of the cadenced ringing waveform and the Battery Switch and RC control signals. Also shown are the states of the MTU voltage and the centering voltage. The state of Battery Switch is indicated by the desired battery voltage to the SLIC. The RC signal is used to enable and disable the centering voltage and MTU voltage. RC follows the ring signal in that it is high during the 20Hz burst and low during the static part of the waveform. Open Circuit Voltage During the Ringing Mode The mutually exclusive relationship of the centering voltage and MTU implies that both functions will not exist at the same time. During the silent portion of the ringing waveform the HC5517 application circuit meets the hazardous voltage requirements of FCC Part 68.306 by forcing the MTU voltage. Without the zener clamping solution, a HC5517 CADENCED WAVEFORM 47.00 46.00 45.00 MAXIMUM RINGING AMPLITUDE (RMS) programmable power supply would have to be designed. The intervals listed in Table 1 would require the power supply to switch voltages and settle to stable operation well within 100ms. The design of such a power supply may prove quite a challenge. The zener solution provides a cost effective, low impact to meeting a wide variety of tip to ring open circuit voltages. 44.00 43.00 42.00 41.00 40.00 BATTERY -80V SWITCH -24V 39.00 1 REN 2 REN 3 REN 4 REN 5 REN RC CENTERING VOLTAGE MTU OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON FIGURE 8. RINGING WAVEFORM AND CONTROL SIGNALS Ringing Design Equations The differential tip to ring voltage during ringing, as a function of REN, can be approximated from Equation 35. V R ING ( 0.702 ) ( 200 )VTRO V TR ( R L ) ≅ 2 × ------------------ – --------------------------------------------------- • 108e3 5.4e3 ( 108e 3)R L FIGURE 9. MAXIMUM RINGING OUTPUT VOLTAGE (VRING = 1.2V RMS) ON-Hook Standby Mode On-hook standby mode is with the phone on-hook (i.e., not answered) and ready to accept an incoming voice signal or electronic data. The HC5517 application circuit is designed to maintain the MTU voltage during this mode of operation. During this mode, the SHD output is valid and the RTD output is invalid. (EQ. 35) The voltage VRING is defined as the RMS amplitude of the input ringing signal. VTRO is the open circuit tip to ring differential output voltage, calculated as VRING multiplied by the differential gain of 40V/V. The REN impedance is shown as RL. Figure 9 shows the relationship of REN load to maximum differential tip to ring RMS voltage during ringing. The maximum ringing signal amplitude herein assumes an infinite source and sink capability of the tip feed and ring feed amplifiers. Due to the amplifier output design, the HC5517 is limited to 3 REN ringing capability for this reason. Off-Hook Active Mode Off-hook active accommodates voice and data communications, including pulse metering, with a battery voltage of -24V. The MTU voltage during this mode is defeated by the zener clamp design regardless of the state of RC. It is important to have RC low to disable the ringing voltage. Only the SHD output is valid during this mode. Power Denial Mode The HC5517 will enter the power denial mode whenever F1 is a logic low. During power denial, the tip and ring amplifiers are active. The DC voltages of both amplifiers are near ground, resulting in a maximum loop current of 7mA. Both the SHD and the RTD detector output are invalid. Table 2 summarizes the operating modes of the HC5517 application circuit. The table indicates the valid detectors in each mode as well as valid application circuit operation. 12 HC5517 TABLE 3. HC5517 APPLICATION CIRCUIT OPERATING MODES SUMMARY DETECTORS VALID BATTERY SWITCH F1 RC MODE -24V 0 0 Power Denial -24V 0 1 Invalid -24V 1 0 Off-Hook Active 1 -24V SHD APPLICATION CIRCUIT VALID RTD MTU CENTERING √ 1 Invalid -80V 0 0 Power Denial -80V 0 1 Invalid -80V 1 0 On-Hook Standby √ -80V 1 1 Ringing (Note) √ √ √ √ NOTE: During Ringing, the SHD output will be active for both on-hook and off-hook conditions. The AC current, for the on-hook condition, exceeds the SHD threshold of 12mA. Valid off-hook detection during ringing is provided by the RTD output only. Operation of the Battery Switch The battery switch is used to select between the off-hook battery of -24V and the ringing/standby battery of -80V. When T1 is off (battery switch is logic low) the MOSFET T3 is off and the -24V battery is supplied to the SLIC through D10 . When T1 is on (battery switch is logic high) current flows through the collector of T1 turning on the zener D9 . When D9 turns on, the gate of the MOSFET is positive with respect to the drain (-80V) and T3 turns on. Turning T3 on connects the -80V battery to the SLIC through D7 . This in turn reverse biases D10 , isolating the two supplies. Transhybrid Balance VRX C8 - The external transhybrid circuit is shown in Figure 10. The effects of capacitors C5 , C7 and C8 are negligible and therefore omitted from the analysis. The input signal (VREC) will be subtracted from the output signal (V-XMIT) if I1 equals I2 are equal and opposite in phase. A node analysis yields the following equation: (EQ. 36) The value of R2 is then: INCOMING AC TRANSMISSION C5 + 180 PHASE SHIFT OF AC SIGNAL V-REC C7 R9 -IN1 R2 I1 R1 R8 OUT1 (Voice Signal) The purpose of the transhybrid circuit is to remove the receive signal (V-REC) from the transmit signal (V-XMIT), thereby preventing an echo on the transmit side. This is accomplished by using an external op amp (usually part of the CODEC) and by the inversion of the signal from the SLIC’s 4-wire receive port (VRX) to the SLIC’s 4-wire transmit port (OUT1). V – REC O UT1 --------------------- + ----------------- = 0 R3 R2 EXTERNAL TRANSHYBRID CIRCUIT HC5517 R3 V-XMIT - + I2 OUTGOING AC TRANSMISSION SUMMING NODE CANCELS OUT INCOMING AC TRANSMISSION FROM OUT GOING TRANSMISSION FIGURE 10. TRANSHYBRID CIRCUIT (VOICE SIGNAL) Transhybrid Balance (Pulse Metering) Transhybrid balance of the pulse metering signal is accomplished in 2 stages. The first stage uses the SLIC’s internal op amp to invert the phase of the pulse metering signal. The second stage sums the inverted pulse metering signal with the incoming signal for cancellation in the transhybrid amplifier. A third network can be added to offset both tip and ring by the peak amplitude of the pulse metering signal. This will allow both the maximum voice and pulse metering signals to occur at the same time with no distortion. Pulse Metering V – REC R 2 = – R 3 • --------------------OUT1 (EQ. 37) Given that OUT1 is equal to -1/3 of V-REC (Equation 16) and V-REC is equal to VTR (A 4-Wire-2-Wire = 1, Equation 15), then R 2 = 3R3. A transhybrid balance greater than 30dB can be achieved by using 1% resistors values. 13 Pulse metering or Teletax is used outside the United States for billing purposes at pay phones. A 12kHz or 16kHz burst is injected into the 4-wire side of the SLIC and transmitted across the tip and ring lines from the central office to the pay phone. For more information about pulse metering than covered here reference application note AN9608 “Implementing Pulse Metering for the HC5509 Series of SLICs”. HC5517 Inverting Amplifier (A1) The pulse metering signal is injected in the -IN1 pin of the SLIC. This pin is the inverting input of the internal amplifier (A1) that is used to invert the pulse metering signal for later cancellation. The components required for pulse metering are C 6 and R 5 , are shown in Figure 11. The pulse metering signal is AC coupled to prevent a DC offset on the input of the internal amplifier. The value of C6 should be 10µF. The expression for the voltage at OUT1 is given in Equation 38 VPM C6 R5 C8 R9 TO EXTERNAL TRANSHYBRID AMP For a 600Ω termination and a pulse metering gain (GPM ) of 1, the feedback voltage (VTX) is equal to one third the injected pulse metering signal of the 4-wire side. Note, depending upon the line impedance characteristics and the degree of impedance matching, the pulse metering gain may differ from the voice gain. The pulse metering gain (G PM) must be accounted for in the transhybrid balance circuit. The polarity of the signal at OUT1 (Equation 38) is opposite of V PM allowing the circuit of Figure 12 to perform the final stage of transhybrid cancellation. VRX R8 R2 VTX OUT1 -IN1 - R3 R1 OUT1 VPM A1 R4 + - + CA741C VTXO FIGURE 12. CANCELLATION OF THE PULSE METERING SIGNAL FIGURE 11. PULSE METERING PHASE SHIFT AMPLIFIER DESIGN . R8 R8 V OU T1 = – V T X • ------- – V PM • ------R R 9 (EQ. 38) 5 The first term is the gain of the feedback voltage from the 2-wire side and the second term is the gain of the injected pulse metering signal. The effects of C6 and C8 are negligible and therefore omitted from the analysis. The injected pulse metering output term of Equation 38 is shown below in Equation 39 and rearranged to solve for R 5 in Equation 40. R8 V OU T1 ( injected ) = VPM • ------- = 1 R (EQ. 39) 5 (EQ. 40) R 5 = R8 The ratio of R8 to R 5 is set equal to one and results in unity gain of the pulse metering signal from 4-wire side to 2-wire side. The value of R8 is considered to be a constant since it is selected based on impedance matching requirements. The following equations do not require much discussion. They are based on inverting amplifier design theory. The voice path VRX signal has been omitted for clarity. All reference designators refer to components of Figures 11 and 12. R 1 V TX V PM R 1 VTXO = – R 8 • – ----------- – ------------ • ------- – V PM • ------- R5 R3 R 4 R9 The first term refers to the signal at OUT1 and the second term refers to the 4-wire side pulse metering signal. Since ideal transhybrid cancellation implies VTXO equals zero when a signal is injected on the 4-wire side, V TXO is set to zero and the resulting equation is shown below. R 1 V TX V PM R 1 0 = R 8 • ----------- + ------------ • ------- – V PM • ------- R5 R3 R 4 R9 NOTE: The CA741C operational amplifier is used in the application as a “stand in” for the operational amplifier that is traditionally located in the CODEC, where transhybrid cancellation is performed. Referring to Figure 3, VTX is the 2-wire feedback used to drive the internal amplifier (A1) which in turn drives the OUT1 pin of the SLIC. The voltage measured at VTX is related to the loop impedance as follows: – 200 V TX = ------------- • V PM • G PM RL (EQ. 41) 14 (EQ. 43) Rearranging terms of Equation 43 and solving for R4 results in Equation 44. This is the only value to be calculated for the transhybrid cancellation. All other values either exist in the application circuit or have been calculated in previous sections of this data sheet. Cancellation of the Pulse Metering Signal The transhybrid cancellation technique that is used for the voice signal is also implemented for pulse metering. The technique is to drive the transhybrid amplifier with the signal that is injected on the 4-wire side, then adjust its level to match the amplitude of the feedback signal, and cancel the signals at the summing node of an amplifier. (EQ. 42) R4 = R8 ------ R3 –1 – 200 • G PM 1 • -------------------------------- + ------- R • R R L 9 5 (EQ. 44) The value of R 4 (Figure 12) is 12.37kΩ given the following set of values: R8 = 40kΩ R9 = 40kΩ RL = 600Ω R3 = 8.25kΩ R5 = 40kΩ GPM = 1 Substituting the same values into Equation 41 and Equation 42, it can be shown that the signal at OUT1 is equal to -2/3VPM . This result, along with Equation 44 where R3 equals to 2/3R4, indicates the signal levels into the transhybrid amplifier are equalized by the amplifier gains and opposite in polarity, thereby achieving transhybrid balance at VTXO . HC5517 Additional Tip and Ring Offset Voltage A DC offset is required to level shift tip and ring from ground and VBAT respectively. By design, the tip amplifier is offset 4V below ground and the ring amplifier is offset 4V above VBAT . The 4V offset was designed so that the peak voice signal could pass through the SLIC without distortion. Therefore, to maintain distortion free transmission of pulse metering and voice, an additional offset equal to the peak of the pulse metering signal is required. The tip and ring voltages are offset by a voltage divider network on the VRX pin. The VRX pin is a unity gain input designed as the 4-wire side voice input for the SLIC. Figure 13 details the circuit used to generate the additional offset voltage. +5V VPMO R R6 C 7 R - VRX + R7 2-WIRE SIDE 4-WIRE SIDE C5 VOICE INPUT standard value without significantly changing the offset voltage. Single Low Voltage Supply Operation The application circuit shown Figure 15 requires 2 low voltage supplies (+5V, -5V). The following application offers away to make use of a 2.5V reference, provided with some CODEC, to operate the transhybrid balance amplifier from a single +5V supply. The implementation is shown in Figure 14. Notice that the three inputs from the SLIC must all be AC coupled to insure the proper DC gain through the CODECs internal op amp. The resistor Ra is not used for gain setting and is only intended to balance the DC offsets generated by the input bias current of the CODEC amplifier. If the DC offsets generated by the input bias currents are negligible, then Ra may be omitted from the circuit. Ca may be required for decoupling of the voltage reference pin and does not contribute to the response of the amplifier. 0.1µF VRX TO VOICE INPUT OF TRANSHYBRID AMP FIGURE 13. PULSE METERING OFFSET GENERATION The amplifier shown is the tip amplifier. Other signals are connected to the summing node of the amplifier but only those components used for the offset generation are shown. The offset generated at the output of the tip amplifier is summed at the ring amplifier inverting input to provide a positive offset from the battery voltage. The connection to the ring amplifier was omitted from Figure 13 for clarity, refer to Figure 3 for details. The term VPMO is defined to be the offset required for the pulse metering signal. The value of the offset voltage is calculated as the peak value of the pulse metering signal. Equation 45 assumes the amplitude of the pulse metering signal is expressed as an RMS voltage. V PMO = 2 • V PM (EQ. 45) The value of R 6 can be calculated from the following equation: R 7 R 5 – V PMO R 6 = ------------------ -------------------------- R 7 + R V PMO (EQ. 46) The component labeled R is the internal summing resistor of the tip amplifier and has a typical value of 108kΩ. The value of R 7 should be selected in the range of 4.99kΩ and 10kΩ. Staying within these limits will minimize the parallel loading effects of the internal resistor R on R 7 as well as minimize the constant power dissipation introduced by the divider. Solving Equation 45 for 1VRMS results in a 1.414V requirement for VPMO . Setting R7 of Equation 46 to 10kΩ and substituting the values for VPMO and R yields 23.2kΩ for R6 . The value of R6 can be rounded to the nearest 15 CODEC R2 R1 0.1µF R3 0.1µF R4 24.9kΩ OUT1 VPM + Ra 24.9kΩ Ca 0.1µF 2.4V REF FIGURE 14. SINGLE LOW VOLTAGE SUPPLY OPERATION Layout Guidelines and Considerations The printed circuit board trace length to all high impedance nodes should be kept as short as possible. Minimizing length will reduce the risk of noise or other unwanted signal pickup. The short lead length also applies to all high gain inputs. The set of circuit nodes that can be categorized as such are: • VRX pin 27, the 4-wire voice input. • -IN1 pin 13, the inverting input of the internal amplifier. • VREF pin 3, the noninverting input to ring feed amplifier. • VRING pin 24, the 20V/V input for the ringing signal. • U1 pin 2, inverting input of external amplifier. For multi layer boards, the traces connected to tip should not cross the traces connected to ring. Since they will be carrying high voltages, and could be subject to lightning or surge depending on the application, using a larger than minimum trace width is advised. The 4-wire transmit and receive signal paths should not cross. The receive path is any trace associated with the VRX input and the transmit path is any trace associated with V TX output. The physical distance between the two signal paths should be maximized to reduce crosstalk. The mode control signals and detector outputs should be routed away from the analog circuitry. Though the digital HC5517 signals are nearly static, care should be taken to minimize coupling of the sharp digital edges to the analog signals. The part has two ground pins, one is labeled AGND and the other BGND. Both pins should be connected together as close as possible to the SLIC. If a ground plane is available, then both AGND and BGND should be connected directly to the ground plane. A ground plane that provides a low impedance return path for the supply currents should be used. A ground plane provides isolation between analog and digital signals. If the layout density does not accommodate a ground plane, a single point grounding scheme should be used. Application Pin Descriptions PLCC SYMBOL DESCRIPTION 1 AGND Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output and receive input terminals. 2 VCC Positive Voltage Source - Most Positive Supply. 3 V REF Ring amplifier reference override. An external voltage connected to this pin will override the internal V BAT/2 reference. 4 F1 Power Denial -A low active TTL compatible logic control input. When enabled, the output of the ring amplifier will ramp close to the output voltage of the tip amplifier. 5 F0 TTL compatible logic control input that must be tied high for proper SLIC operation. 6 RS TTL compatible logic control input that must be tied high for proper SLIC operation. 7 SHD Switch Hook Detection - An active low TTL compatible logic output. Indicates an offhook condition. 8 RTD Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is ringing. 9 TST A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with the ALM pin can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system controller that monitors the ALM pin. When the ALM pin is active (low) the system controller issues a command to the TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller. 10 ALM A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die temperature has been exceeded. 11 ILMT Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions using a resistive voltage divider. 12 OUT1 13 -IN1 14 TIP SENSE An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor and ring relay contact. Functions with the RING terminal to receive voice signals from the telephone and for loop monitoring purpose. 15 RING SENSE 1 An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions with the TIP terminal to receive voice signals from the telephone and for loop monitoring purposes. 16 RING SENSE 2 This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation. 17 VRX Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and Ring Feed amplifiers deferentially. 18 NU Not used in this application.This pin should be left floating. 19 VTX Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is necessary. 20 RDI TTL compatible input to drive the uncommitted relay driver. 21 RDO This is the output of the uncommitted relay driver. 22 BGND The analog output of the spare operational amplifier. The inverting analog input of the spare operational amplifier. Note that the non-inverting input of the amplifier is internally connected to AGND. Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this terminal. 23 NU 24 VRING Not used in this application. This pin should be either grounded or left floating. 25 TF This is the output of the tip amplifier. 26 RF This is the output of the ring amplifier. 27 VBAT Ring signal input (0V to 3V PEAK at 20Hz). The negative battery source. 16 HC5517 Application Pin Descriptions PLCC SYMBOL 28 RTI (Continued) DESCRIPTION Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection. Pinouts 3 1 28 VBAT RTI AGND VCC 2 HC5517 (SOIC) TOP VIEW 27 RF 4 VREF F1 HC5517 (PLCC) TOP VIEW AGND 1 26 VCC 2 26 RF F1 4 25 TF 24 VRING F0 5 24 VRING 7 23 NU RS 6 23 NU 8 22 BGND SHD 7 22 BGND 21 RDO RTD 8 21 RDO TST 9 20 RDI ALM 10 19 VTX ILMT 11 18 NU 5 25 TF RS 6 SHD RTD ALM 27 VBAT VREF 3 F0 TST 28 RTI 9 20 RDI 10 ILMT 11 14 15 16 -IN 1 TIP SENSE RING SENSE 1 RING SENSE 2 Applications Circuit 17 17 18 OUT 1 12 NU 13 VTX VRX 12 OUT 1 19 -IN 1 13 16 RING SENSE 2 TIP SENSE 14 15 RING SENSE 1 17 VRX HC5517 +5V R6 R11 14 TIP SENSE TIP V-REC 25 TF C17 D4 †† C8 R14 15 RING SENSE 1 RING C15 V-XMIT V-TELETAX C6 F1 R31 +5V +5V FO 5 R19 R24 T2 1 AGND 22 BGND RC D13 RDI 20 C 12 RDO 21 27 VBAT C11 D6 D11 VRING 24 D7 R18 T3 D9 -80V SHD 7 †† Diode bridge optional for in-house use. D5 RTI 28 RTD ALM TST RS 8 10 9 6 † Not required for MOSFETs with body diodes. R29 R30 R16 R15 R17 VRING C10 +5V FIGURE 15. APPLICATION CIRCUIT 18 C16 HC5517 † D8 R21 R4 VR EF 3 C13 D10 C4 C3 F1 4 D12 -24V -5V OUT1 12 C 14 T1 C1 U1 7 2 - 6 + 3 4 R8 R22 BAT SWITCH R5 +5V -IN1 13 2 VCC VCC R3 R9 R1 C2 R2 VTX 19 26 RF R 12 BGND R28 R10 16 RING SENSE 2 C18 C5 R7 ILIMT 11 D1 VBAT D3 C9 C7 VRX 17 R13 D2 PULSE METERING OPTION HC5517 HC5517EVAL Evaluation Board Parts List COMPONENT VALUE TOLERANCE RATING SLIC HC5517 n/a n/a R1 , R2 24.9kΩ 1% R3 8.25kΩ R4 COMPONENT VALUE TOLERANCE RATING C2 , C4 , C15 0.1µF 20% 50V 1/4W C5 , C7 10µF 20% 20V 1% 1/4W C6 , C8 0.47µF 20% 20V 12.1kΩ 1% 1/4W C9 , C12 0.01µF 20% 100V R 5 , R 8 , R9 40kΩ 1% 1/4W C10 1.0µF 20% 50V R 6 (Not Provided) 23.2kΩ 1% 1/4W C11 100µF 20% 5V R 7 (Not Provided) 10kΩ 1% 1/4W C13 0.1µF 20% 100V R 10 100kΩ 5% 1/4W C16 0.5µF 20% 50V R 11-14 50Ω 1% 1/4W C17 , C18 3300pF 20% 100V R 15 47kΩ 1% 1/4W D1-4 , D7 , D8 , D10 1N4007 100V, 1A R 16 1.5MΩ 1% 1/4W D5 , D6 , D12 , D13 1N914 100V, 1A R 17 56.2kΩ 1% 1/4W D9 1N4744 15V, 1W R 18 1.1kΩ 1% 1/4W D11 1N5255 28V, 1/2Wire R 19 825Ω 1% 1/4W T1 NTE 383 100V, 1A R 22 , R29 , R30 , R31 10kΩ 5% 1/4W T2 2N2907 60V,150mA R 24 47kΩ 5% 1/4W T3 RFP2N10 or equivalent R 25-27 560Ω 5% 1/4W F1, RC, Battery SPDT Toggle Switches, Center Off. R 28 20kΩ Potentiometer 1/4W U1 CA741C OpAmp R 21 47kΩ 5% 1/4W Textool Socket 228-5523 C 1 , C 3 , C14 0.01µF 20% 50V 19 100V, 2A