INTERSIL EL5372IUZ

EL5172, EL5372
®
Data Sheet
August 3, 2005
250MHz Differential Line Receivers
Features
The EL5172 and EL5372 are single and triple high
bandwidth amplifiers designed to extract the difference
signal from noisy environments. They are primarily targeted
for applications such as receiving signals from twisted-pair
lines or any application where common mode noise injection
is likely to occur.
•
•
•
•
•
•
•
The EL5172 and EL5372 are stable for a gain of one and
requires two external resistors to set the voltage gain.
The output common mode level is set by the reference pin
(VREF), which has a -3dB bandwidth of over 120MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
The output can deliver a maximum of ±60mA and is short
circuit protected to withstand a temporary overload
condition.
Differential input range ±2.3V
250MHz 3dB bandwidth
800V/µs slew rate
60mA maximum output current
Single 5V or dual ±5V supplies
Low power - 5mA to 6mA per channel
Pb-Free plus anneal available (RoHS compliant)
Applications
•
•
•
•
•
•
Twisted-pair receivers
Differential line receivers
VGA over twisted-pair
ADSL/HDSL receivers
Differential to single-ended amplification
Reception of analog signals in a noisy environment
The EL5172 is available in the 8-pin SO and 8-pin MSOP
packages and the EL5372 in a 24-pin QSOP package. Both
are specified for operation over the full -40°C to +85°C
temperature range.
Ordering Information
Pinouts
FB 1
IN+ 2
IN- 3
REF 4
+
-
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL5172IS
8-Pin SO
-
MDP0027
EL5172IS-T7
8-Pin SO
7”
MDP0027
EL5172IS-T13
8-Pin SO
13”
MDP0027
EL5172ISZ
(See Note)
8-Pin SO
(Pb-free)
-
MDP0027
EL5172ISZ-T7
(See Note)
8-Pin SO
(Pb-free)
7”
MDP0027
24 NC
23 FB1
EL5172ISZ-T13
(See Note)
8-Pin SO
(Pb-free)
13”
MDP0027
22 OUT1
EL5172IY
8-Pin MSOP
-
MDP0043
EL5172IY-T7
8-Pin MSOP
7”
MDP0043
EL5172IY-T13
8-Pin MSOP
13”
MDP0043
20 VSP
EL5172IYZ
(See Note)
8-Pin MSOP
(Pb-free)
-
MDP0043
19 VSN
EL5172IYZ-T7
(See Note)
8-Pin MSOP
(Pb-free)
7”
MDP0043
EL5172IYZ-T13
(See Note)
8-Pin MSOP
(Pb-free)
13”
MDP0043
EL5372IU
24-Pin QSOP
-
MDP0040
EL5372IU-T7
24-Pin QSOP
7”
MDP0040
15 EN
EL5372IU-T13
24-Pin QSOP
13”
MDP0040
14 FB3
EL5372IUZ
(See Note)
24-Pin QSOP
(Pb-free)
-
MDP0040
EL5372IUZ-T7
(See Note)
24-Pin QSOP
(Pb-free)
7”
MDP0040
EL5372IUZ-T13
(See Note)
24-Pin QSOP
(Pb-free)
13”
MDP0040
EL5372
(24-PIN QSOP)
TOP VIEW
EL5172
(8-PIN SO, MSOP)
TOP VIEW
8 OUT
REF1 1
7 VS-
INP1 2
6 VS+
INN1 3
5 EN
+
-
21 NC
NC 4
REF2 5
INP2 6
+
-
18 NC
INN2 7
17 FB2
NC 8
16 OUT2
REF3 9
INP3 10
INN3 11
NC 12
+
-
FN7311.6
13 OUT3
PART
NUMBER
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL5172, EL5372
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = 25°C, VIN = 0V, RL = 500Ω, RF = 0, RG = OPEN, CL = 2.7pF, unless otherwise
specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV =1, CL = 2.7pF
250
MHz
AV =2, RF = 1000Ω, CL = 2.7pF
70
MHz
AV =10, RF = 1000Ω, CL = 2.7pF
10
MHz
25
MHz
BW
±0.1dB Bandwidth
AV =1, CL = 2.7pF
SR
Slew Rate
VOUT = 3VP-P, 20% to 80%, EL5172
550
800
1000
V/µs
VOUT = 3VP-P, 20% to 80%, EL5372
550
700
1000
V/µs
TSTL
Settling Time to 0.1%
TOVR
GBWP
VOUT = 2VP-P
10
ns
Output Overdrive Recovery time
20
ns
Gain Bandwidth Product
100
MHz
VREFBW (-3dB) VREF -3dB Bandwidth
AV =1, CL = 2.7pF
120
MHz
VREFSR
VREF Slew Rate
VOUT = 2VP-P, 20% to 80%
600
V/µs
VN
Input Voltage Noise
at f = 11kHz
26
nV/√Hz
IN
Input Current Noise
at f = 11kHz
2
pA/√Hz
HD2
Second Harmonic Distortion
VOUT = 1VP-P, 5MHz
-66
dBc
VOUT = 2VP-P, 50MHz
-63
dBc
VOUT = 1VP-P, 5MHz
-84
dBc
VOUT = 2VP-P, 50MHz
-76
dBc
HD3
Third Harmonic Distortion
dG
Differential Gain at 3.58MHz
RL = 150Ω, AV =2
0.04
%
dθ
Differential Phase at 3.58MHz
RL = 150Ω, AV =2
0.41
°
eS
Channel Separation at 100kHz
EL5372 only
90
dB
INPUT CHARACTERISTICS
VOS
Input Referred Offset Voltage
IIN
Input Bias Current (VIN, VINB, VREF)
RIN
Differential Input Resistance
300
kΩ
CIN
Differential Input Capacitance
1
pF
DMIR
Differential Input Range
±2.1
CMIR
Common Mode Input Range at VIN+, VIN-
VREFIN
Reference Input Voltage Range
2
-14
VIN+ = VIN- = 0V
±7
±25
mV
-6
-3
µA
±2.38
±2.5
V
-4.3
3.3
V
-3.6
3.3
V
FN7311.6
August 3, 2005
EL5172, EL5372
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = 25°C, VIN = 0V, RL = 500Ω, RF = 0, RG = OPEN, CL = 2.7pF, unless otherwise
specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
CMRR
Input Common Mode Rejection Ratio
VIN = ±2.5V
Gain
Gain Accuracy
VIN = 1
MIN
TYP
75
95
0.985
1
3.3
3.63
MAX
UNIT
dB
1.015
V
OUTPUT CHARACTERISTICS
VOUT
Positive Output Voltage Swing
RL = 500Ω to GND
Negative Output Voltage Swing
RL = 500Ω to GND
IOUT(Max)
Maximum Output Current
RL = 10Ω
ROUT
Output Impedance
-3.87
±60
V
-3.5
V
±95
mA
100
mΩ
SUPPLY
VSUPPLY
Supply Operating Range
IS (on)
Power Supply Current Per Channel Enabled
IS (off)+
11
V
5.6
7
mA
Positive Power Supply Current - Disabled EN pin tied to 4.8V, EL5172
80
100
µA
EN pin tied to 4.8V, EL5372
1.7
5
µA
-150
-120
-90
µA
50
58
dB
IS (off)-
Negative Power Supply Current Disabled
PSRR
Power Supply Rejection Ratio
VS+ to VS-
4.75
4.6
VS from ±4.5V to ±5.5V
ENABLE
tEN
Enable Time
150
ns
tDS
Disable Time
1.4
µs
VIH
EN Pin Voltage for Power-up
VIL
EN Pin Voltage for Shut-down
IIH-EN
EN Pin Input Current High Per Channel
At VEN = 5V
IIL-EN
EN Pin Input Current Low Per Channel
At VEN = 0V
3
VS+
-1.5
VS+
-0.5
V
40
-10
V
-3
60
µA
µA
FN7311.6
August 3, 2005
EL5172, EL5372
Pin Descriptions
EL5172
EL5372
PIN NAME
PIN FUNCTION
1
FB
Feedback input
2
IN+
Non-inverting input
3
IN-
Inverting input
4
REF
5
EN
Enabled when this pin is floating or the applied voltage ≤ VS+ - 1.5
6
VS+
Positive supply voltage
7
VS-
Negative supply voltage
8
OUT
Output voltage
Sets the common mode output voltage level
1, 5, 9
REF1, 2, 3
Reference input, controls common-mode output voltage
2, 6, 10
INP1, 2, 3
Non-inverting inputs
3, 7, 11
INN1, 2, 3
Inverting inputs
4, 8, 12, 18, 21, 24
NC
13, 16, 22
OUT1, 2, 3
14, 17, 23
FB1, 2, 3
15
EN
19
VSN
Negative supply
20
VSP
Positive supply
4
No connect, grounded for best crosstalk performance
Non-inverting outputs
Feedback from outputs
Enabled when this pin is floating or the applied voltage ≤ VS+ - 1.5
FN7311.6
August 3, 2005
Connection Diagrams
RG
RF=0Ω
-5V
1 FB
OUT 8
VOUT
5
CL
2.7pF
INP
2 INP
VSN 7
INN
3 INN
VSP 6
REF
4 REF
EN 5
RS2
50Ω
RS2
50Ω
RS3
50Ω
RL
500Ω
EN
EL5172
+5V
REF1
1 REF1
NC 24
INP1
2 INP1
FB1 23
INN1
3 INN1
OUT1 22
+5V
RF
NC 21
4 NC
REF2
5 REF2
VSP 20
INP2
6 INP2
VSN 19
INN2
7 INN2
NC 18
OUT1
CL1
2.7pF
RL1
500Ω
RG
RF
FB2 17
8 NC
REF3
9 REF3
OUT2
OUT2 16
INP3
10 INP3
EN 15
INN3
11 INN3
FB3 14
RL2
500Ω
RG
RF
RSP1
50Ω
RSN1
50Ω
RSR1
50Ω
RSP2
50Ω
RSN2
50Ω
RSR2
50Ω
RSP3
50Ω
RSN3
50Ω
RSR3
50Ω
12 NC
OUT3 13
FN7311.6
August 3, 2005
EL5372
-5V
ENABLE
CL2
2.7pF
CL3
2.7pF
RL3
500Ω
OUT3
EL5172, EL5372
RG
EL5172, EL5372
Typical Performance Curves
AV = 1, RL = 500Ω, CL = 2.7pF
AV = 1, RL = 100Ω, CL = 2.7pF
4
3
3
2
2
MAGNITUDE (dB)
MAGNITUDE (dB)
4
1
0
VS = ±5V
-1
-2
-3
-4
1
0
-1
-2
VS = ±5V
-3
-4
VS = ±2.5V
VS = ±2.5V
-5
-5
-6
1M
10M
100M
-6
1M
1G
FREQUENCY (Hz)
VS = ±5V, AV = 1, RL = 500Ω
5
3
4
2
3
MAGNITUDE (dB)
NORMALIZED GAIN (dB)
VS = ±5V, RL = 500Ω, CL = 2.7pF
1
0
AV = 1
-1
-2
AV = 2
AV = 5
AV = 10
CL = 56pF
CL = 33pF
2
CL = 15pF
1
0
-1
CL = 10pF
-2
CL = 2.7pF
-3
-4
-5
-6
1M
10M
100M
-5
1M
1G
FIGURE 3. FREQUENCY RESPONSE vs VARIOUS GAIN
VS = ±5V, AV = 1, RL = 500Ω
1G
VS = ±5V, AV=2, RL = 500Ω, CL = 2.7pF
4
CL = 56pF
3
3
CL = 33pF
2
1
CL = 15pF
0
CL = 10pF
-2
CL = 2.7pF
-3
-4
NORMALIZED GAIN (dB)
4
-5
1M
100M
FIGURE 4. FREQUENCY RESPONSE vs CL
5
-1
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
MAGNITUDE (dB)
1G
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
4
-4
100M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
-3
10M
2
1
RF = 1kΩ
0
RF = 500Ω
-1
-2
RF = 200Ω
-3
-4
-5
10M
100M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE vs CL
6
1G
-6
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RF
FN7311.6
August 3, 2005
EL5172, EL5372
Typical Performance Curves
(Continued)
270
50
225
2
40
180
1
30
135
20
90
10
45
0
0
0
VS = ±5V
-1
-2
VS = ±2.5V
-3
-10
-45
-4
-20
-90
-5
-30
-135
-6
1M
-40
10K
10M
100M
1G
1M
100K
FREQUENCY (Hz)
10M
PHASE (°)
60
3
GAIN (dB)
NORMINALIZED GAIN (dB)
AV = 1, RL = 500Ω, CL = 2.7pF
4
-180
500M
100M
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE FOR VREF
FIGURE 8. OPEN LOOP GAIN
100
0
-10
IMPEDENCE (Ω)
-20
10
PSRR (dB)
-30
1
-40
PSRR+
-50
-60
-70
PSRR-
-80
0.1
10K
100K
1M
10M
100M
-90
1K
10K
FREQUENCY (Hz)
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
100
1K
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
90
80
CMRR (dB)
70
60
50
40
30
20
100
EN
10
IN
10
0
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 11. CMRR vs FREQUENCY
7
1G
1
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FN7311.6
August 3, 2005
EL5172, EL5372
Typical Performance Curves
(Continued)
VS = ±5V, RL = 500Ω, f = 5MHz
0
-45
-10
-50
DISTORTION (dB)
-20
GAIN (dB)
-30
-40
CH1 <=> CH2, CH2 <=> CH3
-50
-60
-70
HD
-60
-65
(
HD2
AV =
-90
HD3 (AV = 2)
1)
HD3 (AV = 1)
-85
10M
1M
100M
2
1
1G
4
3
FIGURE 13. CHANNEL ISOLATION vs FREQUENCY
-40
HD
3 (A
-55
)
HD2 (A
V = 2)
-60
-65
HD2 (AV = 1)
-70
-75
-80
200
300
HD2
400
500
600
700
800
(A V =
2)
HD3 (A V
-60
HD2 (A V
-70
= 2)
= 1)
HD3 (AV = 1)
-80
-90
HD3 (AV = 1)
-85
-80
100
VS = ±5V, RL = 500Ω, VOP-P = 1V for AV = 1,
VOP-P = 2V for AV = 2
-50
DISTORTION (dB)
V =2
7
6
FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE
VS = ±5V, f = 5MHz, VOP-P = 1V @AV = 1,
VOP-P = 2 V @AV = 2
-50
5
VOP-P (V)
FREQUENCY (Hz)
DISTORTION (dB)
= 2)
-80
-100
100K
-45
2 (A V
-70
-75
CH1 <=> CH3
-80
-55
900 1000
-100
RLOAD (Ω)
FIGURE 15. HARMONIC DISTORTION vs LOAD RESISTANCE
50mV/DIV
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
0.5V/DIV
10ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
8
10ns/DIV
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
FN7311.6
August 3, 2005
EL5172, EL5372
Typical Performance Curves
(Continued)
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
M = 100ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
CH1
CH1
CH2
CH2
100ns/DIV
400ns/DIV
FIGURE 19. ENABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
870mW
0.8
QSOP24
θJA=115°C/W
625mW
0.6
SO8
θJA=160°C/W
0.4 486mW
MSOP8
θJA=206°C/W
0.2
0
1.4
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.2
FIGURE 20. DISABLED RESPONSE
0
25
50
75 85 100
125
1.2
1.136W
1
909mW
0.8
QSOP24
θJA=88°C/W
870mW
SO8
θJA=110°C/W
0.6
MSOP8/10
θJA=115°C/W
0.4
0.2
0
150
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
25
AMBIENT TEMPERATURE (°C)
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Simplified Schematic
VS+
I1
VIN+
Q1
I2
RD1
VINQ2
I3
FBP
Q3
I4
RD2
FBN
Q4
R3
R4
Q8
Q7
VB1
Q9
x1
VOUT
Q6
25
VB2
CC
R1
R2
VS-
9
FN7311.6
August 3, 2005
EL5172, EL5372
Description of Operation and Application
Information
Product Description
The EL5172 and EL5372 are wide bandwidth, low power
and single/differential ended to single ended output
amplifiers. The EL5172 is a single channel differential to
single ended amplifier. The EL5372 is a triple channel
differential to single ended amplifier. The EL5172 and
EL5372 are internally compensated for closed loop gain of
+1 of greater. Connected in gain of 1 and driving a 500Ω
load, the EL5172 and EL5372 have a -3dB bandwidth of
250MHz. Driving a 150Ω load at gain of 2, the bandwidth is
about 50MHz. The bandwidth at the REF input is about
450MHz. The EL5172 and EL5372 is available with a power
down feature to reduce the power while the amplifier is
disabled.
Input, Output, and Supply Voltage Range
The EL5172 and EL5372 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.3V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is about from -2.3V to +2.3V. The
input voltage range at the REF pin is from -3.6V to 3.3V. If
the input common mode or differential mode signal is outside
the above-specified ranges, it will cause the output signal
distorted.
The output of the EL5172 and EL5372 can swing from -3.8V
to 3.6V at 500Ω load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced respectively.
Over All Gain Settings
The gain setting for the EL5172 and EL5372 is similar to the
conventional operational amplifier. The output voltage is
equal to the difference of the inputs plus VREF and then
times the gain.
RF 

V O = ( V IN + – V IN - + V REF ) ×  1 + --------
R

G
EN
VIN+
VIN-
+
Σ
VREF
FB
G/B
+
RF
VO
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT pin to FB pin. For
gains greater than +1, the feedback resistor forms a pole
with the parasitic capacitance at the inverting input. As this
pole becomes smaller, the amplifier's phase margin is
reduced. This causes ringing in the time domain and
peaking in the frequency domain. Therefore, RF has some
maximum value that should not be exceeded for optimum
performance. If a large value of RF must be used, a small
capacitor in the few Pico farad range in parallel with RF can
help to reduce the ringing and peaking at the expense of
reducing the bandwidth.
The bandwidth of the EL5172 and EL5372 depends on the
load and the feedback network. RF and RG appear in
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, RF also has a minimum value that should not
be exceeded for optimum bandwidth performance. For gain
of +1, RF = 0 is optimum. For the gains other than +1,
optimum response is obtained with RF between 500Ω to
1kΩ. For AV = 2 and RF = RG = 1kΩ, the BW is about 80MHz
and the frequency response is very flat.
The EL5172 and EL5372 have a gain bandwidth product of
100MHz. For gains ≥5, its bandwidth can be predicted by the
following equation:
Gain × BW = 100MHz
Driving Capacitive Loads and Cables
The EL5172 and EL5372 can drive 56pF capacitance in
parallel with 500Ω load to ground with 4dB of peaking at gain
of +1. If less peaking is desired in applications, a small
series resistor (usually between 5Ω to 50Ω) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
than 1, the gain resistor RG can then be chosen to make up
for any gain loss which may be created by the additional
series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
RG
FIGURE 23.
10
The EL5172 and EL5372 can be disabled and placed its
outputs in a high impedance state. The turn off time is about
1.4µs and the turn on time is about 150ns. When disabled,
the amplifier's supply current is reduced to 80µA for IS+ and
FN7311.6
August 3, 2005
EL5172, EL5372
120µA for IS- typically, thereby effectively eliminating the
power consumption. The amplifier's power down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to VS+ pin. Letting the
EN pin float or applying a signal that is less than 1.5V below
VS+ will enable the amplifier. The amplifier will be disabled
when the signal at EN pin is above VS+ - 0.5V. If a TTL
signal is used to control the enabled/disabled function,
Figure 24 could be used to convert the TTL signal to CMOS
signal.
V OUT
PD MAX = V S × I SMAX + ( V S + – V OUT ) × -------------------- × i
R
LOAD
For sinking:
PD MAX = [ V S × I SMAX + ( V OUT – V S - ) × I LOAD ] × i
Where:
5V
• VS = Total supply voltage
10K
EN
1K
For sourcing:
• ISMAX = Maximum quiescent supply current per channel
• VOUT = Maximum output voltage of the application
CMOS/TTL
• RLOAD = Load resistance
FIGURE 24.
Output Drive Capability
The EL5172 and EL5372 have internal short circuit
protection. Its typical short circuit current is ±95mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL5172 and
EL5372. It is possible to exceed the 135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = --------------------------------------------Θ JA
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• ILOAD = Load current
• i = Number of channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Assume the REF pin is tired to GND for VS = ±5V
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
11
FN7311.6
August 3, 2005
EL5172, EL5372
Typical Applications
0Ω
50
VFB
50Ω
EL5173/
EL5373
or
EL5172/
EL5372
VIN
50
VINB
50Ω
ZO = 100Ω
EL5172/
EL5372
VOUT
VREF
FIGURE 25. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
R3
R1
this loss is to boost the high frequency gain at the receiver
side.
R2
Gain
(dB)
C1
1 + R2 / R 1
VFB
50Ω
ZO = 100Ω
VIN
VINB
50Ω
EL5172/
EL5372
VOUT
1 + R2 / (R1 + R3)
VREF
fA
fC
f
FIGURE 26. COMPENSATED LINE RECEIVER
Level Shifter and Signal Summer
The EL5172 and EL5372 contains two pairs of differential
pair input stages. It makes the inputs are all high impedance
inputs. To take advantage of the two high impedance inputs,
the EL5172 and EL5372 can be used as a signal summer to
add two signals together. Like, one signal can be applied to
VIN+, the second signal can be applied to REF and VIN- is
ground. The output is equal to:
V O = ( V IN + + V REF ) × Gain
Also, the EL5172 and EL5372 can be used as a level shifter
by applying a level control signal to the REF input.
12
FN7311.6
August 3, 2005
EL5172, EL5372
SO Package Outline Drawing
13
FN7311.6
August 3, 2005
EL5172, EL5372
MSOP Package Outline Drawing
14
FN7311.6
August 3, 2005
EL5172, EL5372
QSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN7311.6
August 3, 2005