TI SN10501DBVT

www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
FEATURES
D High Speed
− 100 MHz Bandwidth (−3 dB, G= 2)
− 900 V/µs Slew Rate
D Excellent Video Performance
− 50 MHz Bandwidth (0.1 dB, G = 2)
− 0.007% Differential Gain
− 0.007° Differential Phase
APPLICATIONS
D Video Line Driver
D Imaging
D DVD / CD ROM
D Active Filtering
D General Purpose Signal Chain Conditioning
VIDEO DRIVE CIRCUIT
VS+
D Rail-to-Rail Output Swing
− VO = −4.5 / 4.5 (RL = 150 Ω)
D High Output Drive, IO = 100 mA (typ)
D Ultralow Distortion
− HD2 = −78 dBc (f = 5 MHz, RL = 150Ω)
− HD3 = −85 dBc (f = 5 MHz, RL = 150Ω)
+
10 µF
Video In
3
75 Ω
4
0.1 µF
5
SN10501
75 Ω
1
+
VO
−
2
75 Ω
D Wide Range of Power Supplies
+
VS−
10 µF
0.1 µF
− VS = 3 V to 15 V
1.43 kΩ
1.43 kΩ
DESCRIPTION
FREQUENCY RESPONSE
6.3
6.1
6.0
5.9
5.8
5.6
5.4
DESCRIPTION
SN10501
Single
SN10502
Dual
SN10503
Triple
VO = 2 VPP
−0.1 dB at 51 MHz
5.7
5.5
DEVICE
VO = 0.1 VPP
−0.1 dB at 49 MHz
6.2
Signal Gain − dB
The SN1050x family is a set of rail-to-rail output single,
dual, and triple low-voltage, high-output swing, lowdistortion high-speed amplifiers ideal for driving data
converters, video switching, or low distortion applications.
This family of voltage feedback amplifiers can operate
from a single 15-V power supply down to a single 3-V
power supply while consuming only 14 mA of quiescent
current per channel. In addition, the family offers excellent
ac performance with 100-MHz bandwidth, 900-V/µs slew
rate and harmonic distortion (THD) at –78 dBc at 5 MHz.
5.3
Gain = 2
RL = 150 Ω to GND
VS = ±5 V
RF = 1.43 kΩ
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0 $#/*)'(
)#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'( ('&!/&$/ 3&$$&!'40
$#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+ '+('!5 #" &.. ,&$&%+'+$(0
Copyright  2003, Texas Instruments Incorporated
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
18 V
Supply voltage, VS
±VS
Input voltage, VI
Output current, IO (2)
150 mA
4V
Differential input voltage, VID
Continuous power dissipation
See Dissipation Rating Table
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE DISSIPATION RATINGS
POWER RATING(2)
Maximum junction temperature, TJ(3)
150°C
PACKAGE
Maximum junction temperature, continuous
operation, longterm reliability, TJ(4)
ΘJC
(°C/W)
ΘJA(1)
(°C/W)
125°C
DBV (5)
55
255.4
TA ≤ 25°C
391 mW
TA = 85°C
156 mW
Operating free-air temperature range, TA
Storage temperature range, Tstg
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
−40°C to 85°C
−65°C to 150°C
300°C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) The SN1050x may incorporate a PowerPAD on the underside of
the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical brief SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
(3)
(4)
The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the
device
D (8)
38.3
97.5
1.02 W
410 mW
D (14)
26.9
66.6
1.5 W
600 mW
DGK (8)
54.2
260
385 mW
154 mW
DGN (8)
4.7
58.4
1.71 W
685 mW
PWP (14)
2.07
37.5
2.67 W
1.07 W
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and
long term reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage,
(VS+ and VS−)
MIN
MAX
Dual supply
±1.35
±9
Single
supply
2.7
18
Input common-mode
voltage range
VS− + 1.1 VS+ − 1.1
UNIT
V
V
PACKAGE/ORDERING INFORMATION
TEMPERATURE
−40°C to 85°C
2
PACKAGED DEVICES
PACKAGE TYPE
TRANSPORT
MEDIA, QUANTITY
SINGLE
DUAL
TRIPLE
SN10501DBVT
−−−
−−−
SOT−23−5
Tape and Reel, 250
SN10501DBVR
−−−
−−−
SOT−23−5
Tape and Reel, 3000
SN10501DGK
SN10502DGK
−−−
MSOP−8
Rails, 75
SN10501DGKR
SN10502DGKR
−−−
MSOP−8
Tape and Reel, 2500
SN10501DGN
SN10502DGN
−−−
MSOP−8−PP
Rails, 75
SN10501DGNR
SN10502DGNR
−−−
MSOP−8−PP
Tape and Reel, 2500
SN10501D
SN10502D
SN10503D
SOIC
Rails, 75
SN10501DR
SN10502DR
SN10503DR
SOIC
Tape and Reel, 2500
−−−
−−−
SN10503PWP
TSSOP−14−PP
Rails, 75
−−−
−−−
SN10503PWPR
TSSOP−14−PP
Tape and Reel, 2000
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
VS = ±5 V, RL = 150 Ω, and G = 2 unless otherwise noted
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
25°C
0°C to
70°C
25°C
−40°C to
85°C
UNITS
MIN/
MAX
AC PERFORMANCE
G = 1, VO = 100 mVPP
170
MHz
Typ
G = 2, VO = 100 mVPP, Rf = 1 kΩ
100
MHz
Typ
G = 10, VO = 100 mVPP, Rf = 1 kΩ
12
MHz
Typ
0.1 dB flat bandwidth
G = 2, VO = 100 mVPP, Rf = 1.43 kΩ
50
MHz
Typ
Gain bandwidth product
Full-power bandwidth(1)
G > 10, f = 1 MHz, Rf = 1 kΩ
120
MHz
Typ
G = 2, VO = ±2.5 Vpp
57
MHz
Typ
Slew rate
G = 2, VO = ±2.5 Vpp
900
V/µs
Min
Settling time to 0.1%
G = −2, VO = ±2 Vpp
25
ns
Typ
Settling time to 0.01%
G = −2, VO = ±2 Vpp
52
ns
Typ
Harmonic distortion
G = 2, VO = 2 VPP, f = 5 MHz
Second harmonic distortion
RL = 150 Ω
RL = 150 Ω
−78
dBc
Typ
Third harmonic distortion
−85
dBc
Typ
Differential gain (NTSC, PAL)
G = 2, R = 150 Ω
0.007
%
Typ
Differential phase (NTSC, PAL)
G = 2, R = 150 Ω
0.007
°
Typ
Input voltage noise
f = 1 MHz
13
nV/√Hz
Typ
Input current noise
f = 1 MHz
0.8
pA/√Hz
Typ
Crosstalk (dual and triple only)
f = 5 MHz Ch-to-Ch
−90
dB
Typ
Small signal bandwidth
(1) Full-power bandwidth = SR / 2πVpp
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input offset voltage
Input bias current
Input offset current
VO = ±2 V
VCM = 0 V
VCM = 0 V
VCM = 0 V
100
80
75
75
dB
Min
12
25
30
30
mV
Max
0.9
3
5
5
µA
Max
100
500
700
700
nA
Max
−4 / 4
−3.9 / 3.9
V
Min
94
70
dB
Min
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
VCM = ±2 V
Input resistance
Input capacitance
Common-mode / differential
65
65
33
MΩ
Typ
1 / 0.5
pF
Max
OUTPUT CHARACTERISTICS
RL = 150 Ω
RL = 499 Ω
−4.5 / 4.5
V
Typ
−4.7 / 4.7
−4.5 / 4.5
−4.4 / 4.4
−4.4 / 4.4
V
Min
100
92
88
88
mA
Min
Output current (sinking)
RL = 10 Ω
RL = 10 Ω
−100
−92
−88
−88
mA
Min
Output impedance
f = 1 MHz
0.09
Ω
Typ
Output voltage swing
Output current (sourcing)
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Power supply rejection (±PSRR)
Per channel
±5
±9
±9
±9
V
Max
14
18
20
22
mA
Max
75
62
60
60
dB
Min
3
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
VS = 5 V, RL = 150 Ω, and G = 2 unless otherwise noted
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C to
85°C
UNITS
MIN/
MAX
AC PERFORMANCE
G = 1, VO = 100 mVPP
170
MHz
Typ
G = 2, VO = 100 mVPP, Rf = 1.5 kΩ
100
MHz
Typ
G = 10, VO = 100 mVPP, Rf = 1.5 kΩ
12
MHz
Typ
0.1 dB flat bandwidth
G = 2, VO = 100 mVPP, Rf = 1.24 kΩ
50
MHz
Typ
Gain bandwidth product
Full-power bandwidth(1)
G > 10, f = 1 MHz, Rf = 1.5 kΩ
120
MHz
Typ
G = 2, VO = 4 V step
60
MHz
Typ
Slew rate
G = 2, VO = 4 V step
750
V/µs
Min
Settling time to 0.1%
G = −2, VO = 2 V step
27
ns
Typ
Settling time to 0.01%
G = −2, VO = 2 Vpp
48
ns
Typ
Harmonic distortion
G = 2, VO = 2 VPP, f = 5 MHz
Second harmonic distortion
RL = 150 Ω
RL = 150 Ω
−82
dBc
Typ
Third harmonic distortion
−88
dBc
Typ
Differential gain (NTSC, PAL)
G = 2, R = 150 Ω
0.014
%
Typ
Differential phase (NTSC, PAL)
G = 2, R = 150 Ω
0.011
°
Typ
Input voltage noise
f = 1 MHz
13
nV/√Hz
Typ
Input current noise
f = 1 MHz
0.8
pA/√Hz
Typ
Crosstalk (dual and triple only)
f = 5 MHz Ch-to-Ch
−90
dB
Typ
Small signal bandwidth
(1) Full-power bandwidth = SR / 2πVpp
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input offset voltage
Input bias current
Input offset current
VO = 1.5 V to 3.5 V
VCM = 2.5 V
VCM = 2.5 V
VCM = 2.5 V
100
80
75
75
dB
Min
12
25
30
30
mV
Max
0.9
3
5
5
µA
Max
100
500
700
700
nA
Max
1/4
1.1 / 3.9
V
Min
96
70
dB
Min
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
VCM = 1.5 V to 3.5 V
Input resistance
Input capacitance
Common-mode / differential
65
65
33
MΩ
Typ
1 / 0.5
pF
Max
OUTPUT CHARACTERISTICS
RL = 150 Ω
RL = 499 Ω
0.5 / 4.5
V
Typ
0.2 / 4.8
0.3 / 4.7
0.4 / 4.6
0.4 / 4.6
V
Min
95
85
80
80
mA
Min
Output current (sinking)
RL = 10 Ω
RL = 10 Ω
−95
−85
−80
−80
mA
Min
Output impedance
f = 1 MHz
0.09
Ω
Typ
Output voltage swing
Output current (sourcing)
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Power supply rejection (±PSRR)
4
Per channel
5
18
18
18
V
Max
12
15
17
19
mA
Max
70
62
60
60
dB
Min
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
PIN ASSIGNMENTS
PACKAGE DEVICES
SN10501
DBV PACKAGE
(TOP VIEW)
VOUT
VS−
IN+
1
5
SN10501
D, DGK, DGN PACKAGE
(TOP VIEW)
VS+
2
3
4
IN −
NC
IN−
IN+
VS−
1
8
2
7
3
6
4
5
NC
VS+
VOUT
NC
SN10502
D, DGK, DGN PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
VS−
1
8
2
7
3
6
4
5
VS+
2OUT
2IN−
2IN+
NC − No internal connection
SN10503
D, PWP PACKAGE
(TOP VIEW)
NC
NC
NC
VS+
1IN+
1IN−
1OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
2OUT
2IN−
2IN+
VS−
3IN+
3IN−
3OUT
NC − No internal connection
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Frequency response
1−8
Small signal frequency response
9, 10
Large signal frequency response
11
Slew rate vs Output voltage step
12, 13
Harmonic distortion vs Frequency
14, 15
Voltage and current noise vs Frequency
16
Differential gain vs Number of loads
17, 18
Differential phase vs Number of loads
19, 20
Quiescent current vs Supply voltage
21
Output voltage vs Load resistance
22
Open-loop gain and phase vs Frequency
23
Rejection ratio vs Frequency
24
Rejection ratio vs Case temperature
25
Common-mode rejection ratio vs Input common-mode range
26, 27
Output impedance vs Frequency
28, 29
Crosstalk vs Frequency
Input bias and offset current vs Case temperature
30
31, 32
5
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
FREQUENCY RESPONSE
8
FREQUENCY RESPONSE
7
3
2
1M
5.7
5.5
5.4
10 M
100 M
5.3
1G
100 k
Figure 2
VO = 2 VPP
−0.1 dB at 14 MHz
5
Signal Gain − dB
Signal Gain − dB
6
VO = 0.1 VPP
−0.1 dB at 14 MHz
5.7
5.4
5.3
1M
−2
100 M
1G
5.6
5.5
5.4
5.3
100 M
VO = 0.1 VPP
−0.1 dB at 48 MHz
Gain = 2
RL = 150 Ω to VS/2
VS = 5 V
RF = 1.24 kΩ
100 k
1G
FREQUENCY RESPONSE
1M
10 M
100 M
6.2
3
2
Gain = 2
RL = 150 Ω to VS/2
VS = 5 V
RF = 301Ω
1M
10 M
VO = 2 VPP
−0.1 dB at 16 MHz
5.8
5.7
5.6
5.3
Gain = 2
RL = 150 Ω to VS/2
VS = 5 V
RF = 301 Ω
100 k
1M
10 M
Gain = 2
6
5.9
5.4
1G
7
6.0
5.5
100 M
FREQUENCY RESPONSE
VO = 0.1 VPP
−0.1 dB at 16 MHz
6.1
VO = 0.1 VPP
−3 dB at 84 MHz
1G
8
6.3
Signal Gain − dB
Signal Gain − dB
6
5.7
Figure 6
VO = 2 VPP
−3 dB at 89 MHz
100 k
5.8
Figure 5
5
−2
5.9
Figure 4
6
−1
6.0
f − Frequency − Hz
7
0
10 M
1G
VO = 2 VPP
−0.1 dB at 58 MHz
6.1
f − Frequency − Hz
FREQUENCY RESPONSE
4
6.2
f − Frequency − Hz
8
1
1M
100 M
FREQUENCY RESPONSE
Gain = 2
RL = 150 Ω to VS/2
VS = 5 V
RF = 1.24 kΩ
100 k
10 M
6.3
2
−1
1M
Figure 3
3
0
10 M
100 k
f − Frequency − Hz
VO = 0.1 VPP
−3 dB at 99 MHz
4
1
Gain = 2
RL = 150 Ω to GND
VS = ±5 V
RF = 301 Ω
100 k
1G
VO = 2 VPP
−3 dB at 99 MHz
7
6.0
5.5
Gain = 2
RL = 150 Ω to GND
VS = ±5 V
RF = 301 Ω
FREQUENCY RESPONSE
8
6.1
5.6
2
−2
100 M
Figure 1
6.2
VO = 0.1 VPP
−3 dB at 99 MHz
3
−1
f − Frequency − Hz
FREQUENCY RESPONSE
5.8
10 M
4
0
f − Frequency − Hz
6.3
5.9
1M
5
1
Gain = 2
RL = 150 Ω to GND
VS = ±5 V
RF = 1.43 kΩ
Signal Gain − dB
100 k
VO = 2 VPP
−0.1 dB at 51 MHz
Signal Gain − dB
−2
5.8
5.6
Gain = 2
RL = 150 Ω to GND
VS = ±5 V
RF = 1.43 kΩ
6
6.0
5.9
VO = 2 VPP
−3 dB at 99 MHz
7
Signal Gain − dB
Signal Gain − dB
Signal Gain − dB
VO = 0.1 VPP
−3 dB at 99 MHz
4
−1
VO = 0.1 VPP
−0.1 dB at 49 MHz
6.1
5
0
8
6.2
6
1
FREQUENCY RESPONSE
6.3
VO = 2 VPP
−3 dB at 99 MHz
5
RL = 150 Ω
RF = 1 kΩ
VO = 100 mVPP
VS = ±5 V
4
3
2
1
0
−1
100 M
f − Frequency − Hz
f − Frequency − Hz
Figure 7
Figure 8
1G
−2
Gain = 1
100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 9
1G
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
FREQUENCY RESPONSE
FREQUENCY RESPONSE
VS = 5 V
7
Gain = 2
6
Signal Gain − dB
6
5
RL = 499 Ω
RF = 1.5 kΩ
VO = 100 mVPP
VS = 5 V
4
3
2
1
VS = ±5 V
5
4
3
Gain = 2
RL = 150 Ω
RF = 1 kΩ
VO = 2 VPP
VS = ±5 V
2
0
Gain = 1
1
1M
10 M
100 M
f − Frequency − Hz
200
1M
100 M
1G
0
Harmonic Distortion − dBc
Rise
400
300
200
100
0
−10
−10
Gain = 2
RL = 150 Ω
VO = 2 VPP
VS = ±5 V
−30
−40
−50
HD2
−60
−70
HD3
−80
1.5
2
2.5
3
3.5
4
0.1
100
1
10
f − Frequency − MHz
VO − Output Voltage Step − V
Figure 13
−30
0.20
−60
−70
Hz
Hz
Vn − Voltage Noise − nV/
I n − Current Noise − pA/
Vn
10
1
In
Differential Gain − %
0.16
0.14
1
100 k
1M
f − Frequency − Hz
Figure 16
−100
0.1
1
10
f − Frequency − MHz
VS = 5 V
0.06
0.1
10 M
Gain = 2
Rf = 1.5 kΩ
40 IRE − NTSC
Worst Case ±100 IRE Ramp
0.35
0.10
0.08
100
0.4
VS = ±5 V
0.3
0.25
VS = 5 V
0.2
0.15
VS = ±5 V
0.1
0.05
0.02
10 k
HD3
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.12
0.04
1k
HD2
−80
Figure 15
Gain = 2
Rf = 1.5 kΩ
40 IRE − NTSC
Worst Case ±100
IRE Ramp
0.18
8
−50
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
10
100
7
−40
Figure 14
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
6
Gain = 2
RL = 150 Ω
VO = 2 VPP
VS = 5 V
−20
Differential Phase − °
1
5
−90
−100
0
4
HARMONIC DISTORTION
vs
FREQUENCY
0
−20
3
Figure 12
−90
0.5
2
VO − Output Voltage Step − V
HARMONIC DISTORTION
vs
FREQUENCY
Fall
500
0
1
Figure 11
800
Gain = 2
RL = 150 Ω
RF = 1 kΩ
VS = 5 V
10 M
f − Frequency − Hz
SLEW RATE
vs
OUTPUT VOLTAGE STEP
600
400
0
100 k
1G
Figure 10
700
Fall
600
0
−2
100 k
Rise
800
Harmonic Distortion − dBc
−1
Gain = 2
RL = 150 Ω
RF = 1 kΩ
VS = ±5 V
1000
SR − Slew Rate − V/ µ s
7
Signal Gain − dB
1200
8
8
SR − Slew Rate − V/ µ s
SLEW RATE
vs
OUTPUT VOLTAGE STEP
0
0
0
1
2
3
Number of Loads − 150 Ω
Figure 17
4
5
0
1
2
3
4
5
Number of Loads − 150 Ω
Figure 18
7
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
0.16
0.14
0.12
0.10
VS = 5 V
0.08
22
Gain = 2
Rf = 1.5 kΩ
40 IRE − PAL
Worst Case ±100 IRE Ramp
0.35
Differential Phase − °
0.18
0.06
0.3
0.25
VS = 5 V
0.2
0.15
VS = ±5 V
0.1
VS = ±5 V
0.04
12
10
TA = −40°C
8
6
4
3
4
0
5
1
2
3
4
Figure 19
Open-Loop Gain − dB
3
2
1
TA = −40 to 85°C
−1
−2
−3
−4
−5
100
1k
RL − Load Resistance − Ω
10 k
70
140
60
120
50
100
40
80
30
60
20
40
10
20
CMMR
90
80
PSRR
70
60
50
40
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
TC − Case Temperature − °C
Figure 25
CMRR − Common-Mode Rejection Ratio − dB
VS = ±5 V, 5 V, and 3.3 V
4
4.5
5
VS = ±5 V, 5 V, and 3.3 V
80
70
CMMR
60
50
PSRR
40
30
20
10
0
−20
1 k 10 k 100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Figure 22
REJECTION RATIO
vs
CASE TEMPERATURE
90
180
160
100
3.5
100
200
80
0
−10
3
REJECTION RATIO
vs
FREQUENCY
220
VS = ±5 V, 5 V,
and 3.3 V
90
2.5
Figure 21
110
100
4
2
VS − Supply Voltage − ±V
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
5
10
1.5
Figure 20
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
0
0
5
Number of Loads − 150 Ω
Rejection Ratios − dB
2
Phase − °
1
Number of Loads − 150 Ω
VO − Output Voltage − V
TA = 25°C
14
2
0
Rejection Ratio − dB
16
0
0
8
TA = 85°C
18
0.05
0.02
100
20
0
0.1
1
10
f − Frequency − MHz
100
Figure 23
Figure 24
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
CMRR − Common-Mode Rejection Ratio − dB
Differential Gain − %
0.4
Gain = 2
Rf = 1.5 kΩ
40 IRE − PAL
Worst Case ±100 IRE Ramp
Quiescent Current − mA/Ch
0.20
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
100
90
80
70
60
50
40
30
20
VS = ±5 V
TA = 25°C
10
0
−6
−4
−2
0
2
4
6
VICR − Input Common-Mode Voltage Range − V
Figure 26
100
90
80
70
60
50
40
30
20
10
VS = 5 V
TA = 25°C
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VICR − Input Common-Mode Voltage Range − V
Figure 27
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
OUTPUT IMPEDANCE
vs
FREQUENCY
0.1
1
Crosstalk all Channels
100
RF = 301 Ω
80
60
40
0.1
20
1M
10 M
100 M
1G
0.01
100 k
RF = 1.24 kΩ
1M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
Figure 28
Figure 29
0.84
IOS
10
0.9
5
0.88
0
IIB+
0.78
−5
IIB−
0.76
−10
−15
0.74
0.72
−20
−25
0.7
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 31
10 M
100 M
1G
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
5
VS = ±5 V
I IB − Input Bias Current − µ A
0.8
1M
f − Frequency − Hz
VS = 5 V
0.82
0
100 k
1G
Figure 30
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
I OS − Input Offset Current − nA
0.01
100 k
RF = 1.43 kΩ
VS = ±5 V, 5 V, and 3.3 V
Gain = 1
RL = 150 Ω
VIN= −1 dB
TA = 25°C
0
IOS
0.86
−5
IIB+
0.84
0.82
−10
−15
0.8
−20
IIB−
0.78
−25
I OS − Input Offset Current − nA
RF = 301 Ω
10
Gain = 2
RL = 150 Ω to VS/2
VO = 2 VPP
VS = 5 V
Crosstalk − dB
ZO − Output Impedance − Ω
1
120
100
Gain = 2
RL = 150 Ω to GND
VO = 2 VPP
VS = ±5 V
I IB − Input Bias Current − µ A
ZO − Output Impedance − Ω
100
10
CROSSTALK
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
−30
0.76
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 32
9
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
5V
+VS
+
HIGH-SPEED OPERATIONAL AMPLIFIERS
100 pF
50 Ω Source
The SN1050x operational amplifiers are a family of single,
dual, and triple rail-to-rail output voltage feedback
amplifiers. The SN1050x family combines both a high slew
rate and a rail-to-rail output stage.
+
VI
49.9 Ω
VO
_
D
D
D
D
D
D
Wideband, Noninverting Operation
Wideband, Inverting Gain Operation
Video Drive Circuits
Single Supply Operation
Power Supply Decoupling Techniques and
Recommendations
Active Filtering With the SN1050x
Driving Capacitive Loads
Board Layout
Thermal Analysis
Additional Reference Material
Mechanical Package Drawings
WIDEBAND, NONINVERTING OPERATION
499 Ω
Rf
1.3 kΩ
1.3 kΩ
Rg
0.1 µF 6.8 µF
Applications Section Contents
D
D
D
D
D
0.1 µF 6.8 µF
100 pF
−5 V
+
−VS
Figure 33. Wideband, Noninverting Gain
Configuration
WIDEBAND, INVERTING OPERATION
Since the SN1050x family are general-purpose, wideband
voltage-feedback amplifiers, several familiar operational
amplifier applications circuits are available to the designer.
Figure 34 shows a typical inverting configuration where
the input and output impedances and noise gain from
Figure 33 are retained in an inverting circuit configuration.
Inverting operation is one of the more common
requirements and offers several performance benefits.
The inverting configuration shows improved slew rates
and distortion due to the pseudo-static voltage maintained
on the inverting input.
5V
+VS
The SN1050x is a family of unity gain stable rail-to-rail
output voltage feedback operational amplifiers designed
to operate from a single 3-V to 15-V power supply.
+
100 pF
0.1 µF
6.8 µF
+
Figure 33 is the noninverting gain configuration of 2 V/V
used to demonstrate the typical performance curves.
Voltage feedback amplifiers, unlike current feedback
designs, can use a wide range of resistors values to set
their gain with minimal impact on their stability and
frequency response. Larger-valued resistors decrease the
loading effect of the feedback network on the output of the
amplifier, but this enhancement comes at the expense of
additional noise and potentially lower bandwidth.
Feedback resistor values between 1 kΩ and 2 kΩ are
recommended for most situations.
10
RT
649 Ω
CT
0.1 µF
50 Ω Source
VI
VO
_
499 Ω
Rg
Rf
1.3 kΩ
RM
52.3 Ω
1.3 kΩ
0.1 µF
100 pF
−5 V
6.8 µF
+
−VS
Figure 34. Wideband, Inverting Gain
Configuration
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
In the inverting configuration, some key design
considerations must be noted. One is that the gain resistor
(Rg) becomes part of the signal channel input impedance.
If the input impedance matching is desired (which is
beneficial whenever the signal is coupled through a cable,
twisted pair, long PC board trace, or other transmission
line conductors), Rg may be set equal to the required
termination value and Rf adjusted to give the desired gain.
However, care must be taken when dealing with low
inverting gains, as the resultant feedback resistor value
can present a significant load to the amplifier output. For
an inverting gain of 2, setting Rg to 49.9 Ω for input
matching eliminates the need for RM but requires a 100-Ω
feedback resistor. This has an advantage of the noise gain
becoming equal to 2 for a 50-Ω source impedance—the
same as the noninverting circuit in Figure 33. However, the
amplifier output now sees the 100-Ω feedback resistor in
parallel with the external load. To eliminate this excessive
loading, it is preferable to increase both Rg and Rf, values,
as shown in Figure 34, and then achieve the input
matching impedance with a third resistor (RM) to ground.
The total input impedance becomes the parallel
combination of Rg and RM.
The last major consideration to discuss in inverting
amplifier design is setting the bias current cancellation
resistor on the noninverting input. If the resistance is set
equal to the total dc resistance looking out of the inverting
terminal, the output dc error, due to the input bias currents,
is reduced to (input offset current) multiplied by Rf in
Figure 34, the dc source impedance looking out of the
inverting terminal is 1.3 kΩ || (1.3 kΩ + 25.6 Ω) = 649 Ω.
To reduce the additional high-frequency noise introduced
by the resistor at the noninverting input, and power-supply
feedback, RT is bypassed with a capacitor to ground.
+VS
50 Ω Source
+
VI
49.9 Ω
RT
499 Ω
+VS
2
Rf
1.3 kΩ
Rg
1.3 kΩ
+VS
2
50 Ω Source
VI
52.3 Ω
Rf
VS
Rg
1.3 kΩ
RT
+VS
2
1.3 kΩ
_
VO
+
499 Ω
+VS
2
Figure 35. DC-Coupled Single Supply Operation
VIDEO DRIVE CIRCUITS
Most video distribution systems are designed with 75-Ω
series resistors to drive a matched 75-Ω cable. In order to
deliver a net gain of 1 to the 75-Ω matched load, the
amplifier is typically set up for a voltage gain of +2,
compensating for the 6-dB attenuation of the voltage
divider formed by the series and shunt 75-Ω resistors at
either end of the cable. The circuit shown in Figure 36
applies to this requirement. Both the gain flatness and the
differential gain / phase performance of the SN1050x
provides exceptional results in video distribution
applications.
SINGLE SUPPLY OPERATION
The SN1050x family is designed to operate from a single
3-V to 15-V power supply. When operating from a single
power supply, care must be taken to ensure the input
signal and amplifier are biased appropriately to allow for
the maximum output voltage swing. The circuits shown in
Figure 35 demonstrate methods to configure an amplifier
in a manner conducive for single supply operation.
VO
_
VS+
+
10 µF
Video In
0.1 µF
5
3
75 Ω
4
+
75 Ω
1
−
VO
2
75 Ω
VS−
+
10 µF
0.1 µF
1.43 kΩ
1.43 kΩ
Figure 36. Cable Drive Application
11
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
Differential gain and phase measure the change in overall
small-signal gain and phase for the color subcarrier
frequency (3.58 MHz in NTSC systems) vs changes in the
large-signal output level (which represents luminance
information in a composite video signal). The SN1050x,
with the typical 150-Ω load of a single matched video
cable, shows less than 0.007% / 0.007° differential
gain/phase errors over the standard luminance range for
a positive video (negative sync) signal. Similar
performance is observed for negative video signals. In
practice, similar performance is achieved even with three
video loads as shown in Figure 37 due to the linear
high-frequency output impedance of the SN1050x.
VS+
0.1 µF
75 Ω
VO
+
10 µF
Video In
75 Ω
5
3
4
+
75 Ω
1
−
75 Ω
VO
2
75 Ω
1.43 kΩ
1.43 kΩ
0.1 µF
75 Ω
VO
VS−
+
10 µF
the output voltage range will be the limiting factor in the
total system and both specifications must be taken into
account when designing a system.
1.24 kΩ
1.24 kΩ
5V
Input Range
= 1 V to 2.25 V
75 Ω
−
VO Range
= 1 V to 2.25 V
+
75 Ω
RT
Figure 38. DC-Coupled Single-Supply Video
Amplifier
In most systems, this may be acceptable because most
receivers are ac-coupled and set the blank level to the
desired system value, typically 0 V (0-IRE). But, to ensure
full compatibility with any system, it is often desirable to
place an ac-coupling capacitor on the output as shown in
Figure 39. This eliminates the dc-bias voltage appearing
at the amplifier output. To minimize field tilt, the size of this
capacitor is typically 470 µF, although values as small as
220 µF have been utilized with acceptable results.
75 Ω
1.24 kΩ
1.24 kΩ
5V
Figure 37. Video Distribution
The above circuit is suitable for driving video cables,
provided that the length does not exceed a few feet. If
longer cables are driven, the gain of the SN1050x can be
increased to accommodate cable drops.
Configuring the SN1050x for single supply video
applications is easily done. But, attention must be made to
the bias voltages at the input and output to ensure the
system works as desired. Unlike some video amplifiers,
the input common-mode voltage range of the SN1050x
amplifiers do not include the negative power supply, but
rather it is about 1-V from each power supply. For split
supply configurations, this is very beneficial. But for
single-supply systems, there are some design constraints
that must be adhered to.
Figure 38 shows a single supply video configuration
illustrating the dc bias voltages acceptable for the
SN1050x. The lower end of the input common-mode range
is specified as 1 V. While the upper end is limited to 4 V with
the 5-V supply shown, the output range and gain of 2 limits
the highest acceptable input voltage to 4.5 V / 2 = 2.25 V.
The 4.5-V output is what is typically expected with a 150-Ω
load. It is easily seen that the input voltage range and/or
12
Output Range
= 2 V to 4.5 V
Input Range
= 1 V to 2.25 V
−
+
RT
Output Range
= 2 V to 4.5 V
75 Ω
VO Range
= 0 V to 1.25V
470 µF
75 Ω
Figure 39. AC-Coupled Output Single-Supply
Video Amplifier
In some systems, the physical size and sometimes cost of
a 470-µF capacitor can be prohibitive. One way to
circumvent this issue is to utilize two smaller capacitors in
a feedback configuration as shown in Figure 40. This is
commonly known as SAG correction. This circuit
increases the gain of the amplifier up to 3 V/V at low
frequencies to counteract the increased impedance of the
capacitor placed at the amplifier output. One issue that
must be resolved is the gain at low frequencies is typically
limited by the power-supply voltage and the output swing
of the amplifier. Therefore, it is possible to saturate the
amplifier at these low frequencies if full analysis is not done
on this system which includes both input and output
requirements.
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
1.24 kΩ
1.24 kΩ
5V
Input Range
= 1 V to 2.25 V
68 µF
22 µF
1.24 kΩ
5V
1.24
kΩ
75 Ω
−
+
1.24 kΩ
VO Range
= 0 V to 1.25V
5V
DAC Output
= 0 V to 2V
3.01 kΩ
RT
75 Ω
Output Range
= 2 V to 4.5 V
Many times the output of the video encoder or DAC does
not have the capability to output the 1-V to 2.25-V range,
but rather a 0-V to 1.25-V range. In this instance, the signal
must be ac-coupled to the amplifier input as shown in
Figure 41. Note that it does not matter what the voltage
output of the DAC is, but rather the voltage swing should
be kept less than 1.25 VPP.
470 µF
47 µF
75 Ω
3.01 kΩ
Figure 40. AC-Coupled SAG Corrected Output
Single-Supply Video Amplifier
VO Range
= 0 V to 2V
75 Ω
−
+
22 µF
Output Range
= 0.5 V to 4.5V
Input Range
= 1.5 V to 3.5V
Figure 42. AC-Coupled Wide Output Swing
Single-Supply Video Amplifier
1.24 kΩ
1.24 kΩ
2.5 V
5V
5V
DAC Output
= 0 V to 2V
3.01 kΩ
Output Range
= 0.5 V to 4.5V
75 Ω
−
+
VO Range
= 0 V to 2V
470 µF
47 µF
1.24 kΩ
1.24 kΩ
5V
5V
DAC Output
= 0 V to 1.25V
4.64 kΩ
−
+
47 µF
2.26 kΩ
75 Ω
3.01 kΩ
Output Range
= 2 V to 4.5 V
75 Ω
VO Range
= 0 V to 1.25V
470 µF
75 Ω
Input Range
= 1 V to 2.25V
Figure 43. AC-Coupled Wide Output Swing
Single-Supply Video Amplifier Utilizing Voltage
Reference
Another configuration that can be beneficial is to utilize the
amplifier in an inverting configuration is shown in
Figure 44.
68 µF
Figure 41. AC-Coupled Input and Output
Single-Supply Video Amplifier
To have even more dynamic range at the output, the
dc-bias at the output should be centered around 2.5 V for
the 5-V system shown. But, to have a wide output range
the input must also have a wide range and should be
centered around 2.5 V. The best ways to accomplish this
is to either ac-couple the gain resistor or bias it at 2.5 V
utilizing a reference supply as shown in Figure 42 and
Figure 43.
Input Range
= 1.5 V to 3.5V
1.24 kΩ
2.49 kΩ
DAC Output
= 0 V to 2V
5V
10 kΩ
5V
−
+
10 µF
10 kΩ
Output Range
= 0.5 V to 4.5V
75 Ω
VO Range
= 0 V to 2V
470 µF
75 Ω
Input = 2.5 V
Figure 44. Inverting AC-Coupled Wide Output
Swing Single-Supply Video Amplifier
13
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
Power Supply Decoupling Techniques and
Recommendations
APPLICATION CIRCUITS
Active Filtering With the SN1050x
High-frequency active filtering with the SN1050x is
achievable due to the amplifier’s high slew rate, wide
bandwidth, and voltage feedback architecture. Several
options are available for high-pass, low-pass, bandpass,
and bandstop filters of varying orders. A simple two-pole
low pass filter is presented here as an example, with two
poles at 25 MHz.
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
1.
Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
2.
Placement priority should put the smallest valued
capacitors closest to the device.
3.
Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths, with the exception of the
areas underneath the input and output pins.
4.
Recommended values for power supply decoupling
include a bulk decoupling capacitor (6.8 to 22 µF), a
mid-range decoupling capacitor (0.1 µF) and a high
frequency decoupling capacitor (1000 pF) for each
supply. A 100 pF capacitor can be used across the
supplies as well for extremely high frequency return
currents, but often is not required.
4.7 pF
50 Ω Source
1.3 kΩ
VI
1.3 kΩ
52.3 Ω
5V
_
49.9 Ω
VO
+
33 pF
−5 V
Figure 45. A Two-Pole Active Filter With Two
Poles Between 90 MHz and 100 MHz
Driving Capacitive Loads
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter, including
additional external capacitance, which may be
recommended to improve A/D linearity. A high-speed, high
open-loop gain amplifier like the SN1050x can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the amplifier’s open-loop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. When the primary considerations are
frequency response flatness, pulse response fidelity, or
distortion, the simplest and most effective solution is to
isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
14
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
BOARD LAYOUT
add a pole and/or a zero below 400 MHz that can
effect circuit operation. Keep resistor values as low as
possible, consistent with load driving considerations.
It has been suggested that a good starting point for
design is to set the Rf to 1.3 kΩ for low-gain,
noninverting applications. Doing this automatically
keeps the resistor noise terms low, and minimizes the
effect of their parasitic capacitance.
Achieving optimum performance with a high frequency
amplifier like the SN1050x requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
1.
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional band
limiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of
the ground and power planes around those pins.
Otherwise, ground and power planes should be
unbroken elsewhere on the board.
2.
Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF decoupling
capacitors. At the device pins, the ground and power
plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces
to minimize inductance between the pins and the
decoupling capacitors. The power supply connections
should always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board.
3.
Careful selection and placement of external
components preserves the high frequency
performance of the SN1050x. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep their leads and PC board trace length as
short as possible. Never use wire wound type
resistors in a high frequency application. Since the
output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place
the feedback resistor directly under the package on
the other side of the board between the output and
inverting input pins. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create significant
time constants that can degrade performance. Good
axial metal-film or surface-mount resistors have
approximately 0.2 pF in shunt with the resistor. For
resistor values > 2.0 kΩ, this parasitic capacitance can
4.
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50 mils to 100 mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RISO from the plot of recommended RISO vs
Capacitive Load. Low parasitic capacitive loads
(<4 pF) may not need an R(ISO), since the SN1050x is
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an R(ISO) are allowed as the signal gain
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6-dB signal loss
intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50-Ω
environment is normally not necessary onboard, and
in fact a higher impedance environment improves
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the output
of the SN1050x is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of R(ISO)
vs Capacitive Load. This setting does not preserve
signal integrity or a doubly-terminated line. If the input
impedance of the destination device is low, there is
some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
15
www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
Socketing a high speed part like the SN1050x is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create a troublesome parasitic network which can
make it almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the SN1050x onto the board.
THERMAL ANALYSIS
The SN1050x family of devices does not incorporate
automatic thermal shutoff protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 150_ C is exceeded.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
Tmax–T A
P Dmax +
q JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
16
1.5
PD − Maximum Power Dissipation − W
5.
1.25
8-Pin D Package
1
0.75
5-Pin DBV Package
0.5
0.25
0
−40
40
60
−20
0
20
TA − Ambient Temperature − °C
80
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 324.1°C/W for 5-Pin SOT−23 (DBV)
TJ = 150°C, No Airflow
Figure 46. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
consider not only quiescent power dissipation, but also
dynamic power dissipation. Often maximum power
dissipation is difficult to quantify because the signal pattern
is inconsistent, but an estimate of the RMS power
dissipation can provide visibility into a possible problem.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated