FlashFlex51 MCU SST89E52RC / SST89E54RC Programming Specification

FlashFlex51 MCU
SST89E52RC / SST89E54RC
A Microchip Technology Company
Programming Specification
Introduction
This document provides the instructions to help programming vendors qualify SST’s FlashFlex 51
Microcontroller.
Functional Blocks
8051
CPU Core
ALU,
ACC,
B-Register,
Instruction Register,
Program Counter,
Timing and Control
Interrupt
Control
Oscillator
8 Interrupts
Flash Control Unit
Watchdog Timer
SuperFlash
EEPROM
Primary Partition
RAM
512 x8
16 x8 for SST89E54RC
8 x8 for SST89E52RC
8
I/O
I/O Port 0
8
Secondary
Partition
1 x8
Security
Lock
I/O
I/O Port 1
8
I/O
I/O Port 2
8
Timer 0 (16-bit)
I/O Port 3
I/O
Timer 1 (16-bit)
8-bit
Enhanced
UART
Timer 2 (16-bit)
1259 B1.3
Figure 1: Functional Block Diagram
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DS25089A
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FlashFlex51 MCU
SST89E52RC / SST89E54RC
A Microchip Technology Company
Programming Specification
External Host Programming
External host programming mode allows the user to program the flash memory directly without using
the CPU.
External Host Programming Mode
External Host mode is entered by forcing PSEN# from a logic high to a logic low while RST input is
being held continuously high. The device will stay in External Host mode as long as RST = 1, PSEN# =
0, and EA# = 1.
A Read-ID operation is necessary to “arm” the device in External Host mode. No other External Host
mode commands can be enabled until a Read-ID is performed. In External Host mode, the internal
flash memory blocks are accessed through the re-assigned I/O port pins by an external host, such as
a MCU programmer, a PCB tester or a PC-controlled development board. See Figure 2 for details.
VSS VDD RST
0
Port 1
PSEN#
ALE/PROG#
EA#
6
Address Bus
A7-A0
7
PSEN#
ALE
EA#
0
Port 2
6
Address Bus
A15-A8
7
2
Flash
Control
Signals
4
Port 3
5
0
7
Port 0
6
7
Input/
Output
Data
Bus
1259 F04.1
Figure 2: I/O Pin Assignments for External Host Mode
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FlashFlex51 MCU
SST89E52RC / SST89E54RC
A Microchip Technology Company
Programming Specification
Table 1: External Host Mode Commands1
Operation
RST
PSEN#
PROG#/
ALE2
EA#
P3[7]
P3[5]
P3[4]
P3[2]
P0[7:0]
P2[7:0]
P1[7:0]
Read-ID
VIH
VIL
VIH
VIH
VIL
VIL
VIL
VIL
DO
AH
AL
Chip-Erase
VIH
VIL

VIH
VIL
VIL
VIL
VIH
X
X
X
Partition0-Erase
VIH
VIL

VIH
VIH
VIH
VIL
VIH
X
X
X
Sector-Erase
VIH
VIL

VIH
VIH
VIL
VIH
VIH
X
AH
AL
Byte-Program
VIH
VIL

VIH
VIH
VIH
VIH
VIL
DI
AH
AL
Byte-Verify (Read)
VIH
VIL
VIH
VIH
VIH
VIH
VIL
VIL
DO
AH
AL
Secure-Page0
VIH
VIL

VIH
VIL
VIL
VIH
VIH
X
90H
X
Secure-Page1
VIH
VIL

VIH
VIL
VIL
VIH
VIH
X
91H
X
Secure-Page2
VIH
VIL

VIH
VIL
VIL
VIH
VIH
X
92H
X
Secure-Page3
VIH
VIL

VIH
VIL
VIL
VIH
VIH
X
93H
X
Secure-Page4
VIH
VIL

VIH
VIL
VIL
VIH
VIH
X
94H
X
Disable-Extern-IAP
VIH
VIL

VIH
VIL
VIH
VIL
VIH
X
B0H
X
Disable-ExternBoot
VIH
VIL

VIH
VIL
VIH
VIL
VIH
X
B1H
X
Disable-ExternMOVC
VIH
VIL

VIH
VIL
VIH
VIL
VIH
X
B2H
X
Disable-ExternHost-Cmd
VIH
VIL

VIH
VIL
VIH
VIL
VIH
X
B3H
X
Enable-Clock-Double
VIH
VIL

VIH
VIH
VIL
VIL
VIL
X
E0H
X
Boot-From-UserVector
VIH
VIL

VIH
VIH
VIL
VIL
VIL
X
E1H
X
Boot-From-Zero
VIH
VIL

VIH
VIH
VIL
VIL
VIL
X
E2H
X
Set-User-Boot-Vector
VIH
VIL

VIH
VIH
VIL
VIL
VIH
DI
F0H
X
T0-0.0 25089
1. VIL = Input Low Voltage; VIH = Input High Voltage; X = Don’t care; AL = Address low order byte; AH = Address high
order byte; DI = Data Input; DO = Data Output.
2. Symbol  signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input.
All other combinations of the above input pins are invalid and may result in unexpected behaviors.
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FlashFlex51 MCU
SST89E52RC / SST89E54RC
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Programming Specification
Product Identification
The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as
SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms. The Read-ID command is selected by the command code of 0H on P3[7], P3[5], P3[4], and
P3[2]. See Figure 3 for timing waveforms.
Table 2: Product Identification
Address
Data
Manufacturer’s ID
30H
BFH
Device ID
31H
F7H
SST89E54RC
32H
43H
SST89E52RC
32H
42H
Device ID (extended)
T0-0.0 25089
Arming Command
An arming command sequence must take place before any External Host mode sequence command
is recognized by the device. This prevents accidental triggering of External Host mode commands due
to noise or programmer error. The arming command is as follows:
1.PSEN# goes low while RST is high. This will get the machine in External Host mode, re-configuring the pins, and turning on the on-chip oscillator.
2.A Read-ID command is issued, and after 1 ms the External Host mode commands can be
issued.
After the above sequence, all other External Host mode commands are enabled. Before the Read-ID
command is received, all other External Host mode commands received are ignored.
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FlashFlex51 MCU
SST89E52RC / SST89E54RC
A Microchip Technology Company
Programming Specification
External Host Mode Commands
The External Host mode commands are Read-ID, Chip-Erase, Partition0-Erase, Sector-Erase, ByteProgram, Byte-Verify, Secure-Page0, Secure-Page1, Secure-Page2, Secure-Page3, Secure-Page4,
Disable-Extern-IAP, Disable-Extern-Boot, Disable-Extern-MOVC, Disable-Extern-Host-Cmd, EnableClock-Double, Boot-From-User-Vector, Boot-From-Zero, and Set-User-Boot-Vector. See Table 1 for all
signal logic assignments, Figure 2 for I/O pin assignments, and Table 5 for the timing parameters.
The critical timing for all Erase and Program commands is generated by an on-chip flash memory controller. The high-to-low transition of the PROG# signal initiates the Erase or Program commands, which
are synchronized internally. The Read commands are asynchronous reads, independent of the
PROG# signal level.
The Chip-Erase, Partition0-Erase, and Sector-Erase commands are used for erasing all or part of the
memory array. Erased data bytes in the memory array will be erased to FFH. Memory locations that
are to be programmed must be in the erased state prior to programming.
The Chip-Erase command erases all bytes in both memory partitions. This command ignores the
Security setting status and will erase all settings on all pages and the different chip-level security
restrictions, returning the device to its Unlocked state. Chip-Erase will also erase the boot vector setting. Upon completion of Chip-Erase command, the chip will boot from the default setting. See Table 3
for the default boot vector setting and Figure 4 for timing waveforms.
Table 3: Default Boot Vector Settings
Device
Address
SST89E54RC
4000H
SST89E52RC
2000H
T0-0.0 25089
The Partition0-Erase command erases all bytes in memory partition 0. Secure-Page0-3 security settings will be reset to an unsecured state. See Figure 5 for the timing waveforms.
The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory is 128
Bytes. This command will not be executed if the Security lock is enabled. See Figure 6 for timing waveforms.
The Byte-Program command is used for programming new data into the memory array. Programming
will not take place if any security locks are enabled. See Figure 7 for timing waveforms.
The Byte-Verify command allows user verification that the device correctly performed an Erase or Program command. This command will be disabled if any security locks are enabled. See Figure 8 for timing waveforms.
The Secure-Page0, Secure-Page1, Secure-Page2, Secure-Page3, and Secure-Page4 commands program the security bit of each individual page. Once programmed, these bits can be erased using a
Chip-Erase command for Secure-Page0-4. Partition0-Erase will erase Secure-Page0-3. See Figure 9
for timing waveforms.
The Disable-Extern-IAP, Disable-Extern-Boot, Disable-Extern-MOVC, Disable-Extern-Host-Cmd,
Enable-Clock-Double, Boot-From-User-Vector, and Boot-From-Zero commands program the chip-level
security and boot vector options. The functions of these bits are described in the Security Lock and
Boot Options sections. Once programmed, these bits can only be erased through a Chip-Erase command. See Figure 4 for the Chip-Erase timing waveforms.
The Set-User-Boot-Vector command is used for programming new User Boot Vector.
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FlashFlex51 MCU
SST89E52RC / SST89E54RC
A Microchip Technology Company
Programming Specification
External Host Mode Clock Source
In External Host mode, an internal oscillator will provide clocking for the device, and the oscillator is
unaffected by the clock doubler logic. The on-chip oscillator will be turned on as the device enters
External Host mode; i.e. when PSEN# goes low while RST is high. During External Host mode, the
CPU core is held in reset. Upon exit from External Host mode, the internal oscillator is turned off.
Flash Operation Status Detection Via External Host Handshake
The device provides two methods for an external host to detect the completion of a flash memory operation to optimize the Program or Erase time. The end of a flash memory operation cycle can be
detected by:
1.Monitoring the Ready/Busy# bit at P3[3];
2.Monitoring the Data# Polling bit at P0[3].
Ready/Busy# (P3[3])
The progress of the flash memory programming can be monitored by the Ready/Busy# output signal.
P3[3] is driven low, some time after ALE/PROG# goes low during a flash memory operation to indicate
the Busy# status of the Flash Control Unit (FCU). P3[3] is driven high when the flash programming
operation is completed to indicate the ready status.
Data# Polling (P0[3])
During a Program operation, any attempts to read (Byte-Verify), while the device is busy, will receive
the complement of the data of the last byte loaded on P0[3] with the rest of the bits “0”. During a Program operation, the Byte-Verify command is reading the data of the last byte loaded, not the data at
the address specified.
Instructions to Perform External Host Mode Commands
To program data into the memory array, apply power supply voltage (VDD) to VDD and RST pins, and
perform the following steps:
1.
Maintain RST and EA# pin high and set PSEN# from logic high to low, in sequence
according to the appropriate timing diagram.
2.
Issue a Read-ID command to enable the External Host mode.
3.
Verify that the memory partitions or sectors for programming are in the erased state, FFH.
If not set to FFH, issue the appropriate Erase command.
4.
Select the memory location using the address lines (P2[7:0], P1[7:0]).
5.
Present the data in on P0[7:0].
6.
Set the command code on P3[7], P3[5], P3[4], and P3[2].
7.
Pulse ALE/PROG#, observing minimum pulse width.
8.
Wait for low to high transition on Ready/Busy# (P3[3]).
9.
Repeat steps 4 - 8 until programming is finished.
10. Verify the flash memory contents.
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FlashFlex51 MCU
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A Microchip Technology Company
Programming Specification
Additional Read Commands in External Host Mode
The procedure to issue additional read commands, shown in Table 4 below, is the same as the normal
Read ID command procedure, only the address is changed. Here is a short list of useful features:
•Read the user boot vector setting.
•Read the status of the page security bits (Page0_i, Page1_i, Page2_i, Page3_i, Page4_i).
•Read the chip-level security bits and boot-option setting bits (Boot-From-Zero_i, Boot-FromUser-Vector_i, Disable-Extern-Host-Cmd_i, Disable-Extern-MOVC_i, Disable-ExternBoot_i, Disable-Extern-IAP_i).
•Read the clock mode (Enable-Clock-Double_i) status.
Note:Commands shown in Table 4 are not ARMING commands.
Table 4: Additional Read Commands in External Host Mode
Address
Data
33H
Boot Vector
60H
X
X
X
Page4_i
Page3_i
Page2_i
Page1_i
Page0_i
61H
X
BootFrom –
Zero_i
BootFromUserVector_i
EnableClockDouble_i
DisableExternHostCmd_i
DisableExternMOVC_i
DisableExternBoot_i
DisableExternIAP_i
T0-0.0 25089
Note: X = Don’t care
Table 5: External Mode Flash Memory Programming/Verification Parameters1
Parameter2,3
Symbol
Min
Reset Setup Time
TSU
3
µs
Read-ID Command Width
TRD
1
µs
PSEN# Setup Time
TES
40
µs
Address, Command, Data Setup
Time
TADS
0
ns
Chip-Erase Time
TCE
350
ms
Partition 0 Erase Time
TPE
300
ms
30
ms
Sector-Erase Time
Program Setup Time
TSE
TPROG
1.2
0
Max
Units
µs
ns
Address, Command, Data Hold
TDH
Byte-Program Time4
TPB
100
µs
Re-map or Security bit Program
Time
TPS
100
µs
Verify Command Delay Time
TOA
100
ns
Verify High Order Address Delay
Time
TAHA
100
ns
Verify Low Order Address Delay
Time
TALA
100
ns
T0-0.0 25089
1.
2.
3.
4.
For IAP operations, the program execution overhead must be added to the above timing parameters.
Program and Erase times will scale inversely proportional to programming clock frequency.
All timing measurements are from the 50% of the input to 50% of the output.
Each byte must be erased before programming.
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Programming Specification
Flash Memory Programming Timing Diagrams with External Host Mode
TSU
RST
TES
PSEN#
ALE/PROG#
EA#
TRD
TRD
P3[7, 5, 4, 2]
0000b
0000b
P0
BFH
Device ID
P1
0030H
0031H
1259 F42.1
Note: For Device ID see Table 2 on page 4
Figure 3: Read-ID
Reads chip signature and identification registers at the addressed location.
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TDH
TPROG
EA#
TCE
P3[3]
P3[7, 5, 4, 2]
0001b
1259 F43.1
Figure 4: Chip-Erase
Erases both flash memory partitions. Security lock is ignored and the security bits are erased too.
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FlashFlex51 MCU
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Programming Specification
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TPROG
TDH
EA#
TPE
P3[3]
P3[7, 5, 4, 2]
1101b
1259 F44.1
Figure 5: Partition0-Erase
Erases the main flash memory partition. Security lock is ignored and the security bits are erased too.
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TPROG
TDH
EA#
P3[3]
TSE
P3[7, 5, 4, 2]
1011b
P1
AL
P2
AH
1259 F45.1
Figure 6: Sector-Erase
Erases the addressed sector if the security lock is not activated on that flash memory block.
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FlashFlex51 MCU
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Programming Specification
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TDH
TPROG
EA#
P3[3]
TPB
P3[7, 5, 4, 2]
1110b
P0
DI
P1
AL
P2
AH
1259 F46.1
Figure 7: Byte-Program
Programs the addressed code byte if the byte location has been successfully erased and not yet programmed.
Byte-Program operation is only allowed when the security lock is not activated on that flash memory block.
TSU
RST
TES
PSEN#
ALE/PROG#
EA#
TOA
1100b
P3[7, 5, 4, 2]
TAHA
DO
P0
TALA
AL
P1
AH
P2
1259 F47.1
Figure 8: Byte-Verify
Reads the code byte from the addressed flash memory location if the security lock is not activated on
that flash memory block.
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FlashFlex51 MCU
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A Microchip Technology Company
Programming Specification
TSU
RST
TES
PSEN#
TADS
ALE/PROG#
TDH
TPROG
EA#
P3[3]
TPS
P3[7, 5, 4, 2]
0011b
P2
90H / 91H / 92H / 93H / 94H
1259 F48.1
Figure 9: Secure-Page0, Secure-Page1, Secure-Page2, Secure-Page3, Secure-Page4
Programs the Security bits for Page0, Page1, Page2, Page3, Page4 respectively.
Only a Chip-Erase will erase a programmed security bit.
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FlashFlex51 MCU
SST89E52RC / SST89E54RC
A Microchip Technology Company
Programming Specification
Table 6: Revision History
Number
00
A
Description
•
•
•
•
Initial Release of Addendum
Applied new document format
Released document under letter revision system
Updated Spec number from S71259(02) to DS25089
Date
Dec 2006
Oct 2011
ISBN:978-1-61341-734-8
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office locations and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
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