Appendix

M
Section 34. Appendix
HIGHLIGHTS
This section of the manual contains the following major topics:
Appendix A:I2C Overview....................................................................................................34-2
Appendix B:List of LCD Glass Manufacturers ......................................................................34-11
Appendix C:Device Enhancement .......................................................................................34-13
Appendix D:Revision History................................................................................................34-19
34
Appendix
I2C is a trademark of Philips Corporation.
 1997 Microchip Technology Inc.
DS31034A page 34-1
PICmicro MID-RANGE MCU FAMILY
APPENDIX A: I 2C OVERVIEW
This section provides an overview of the Inter-Integrated Circuit (I 2C™) bus, with Subsection
A.2 “Addressing I2C Devices” discussing the operation of the SSP modules in I 2C mode.
The I 2C bus is a two-wire serial interface. The original specification, or standard mode, is for data
transfers of up to 100 Kbps. An enhanced specification, or fast mode (400 Kbps) is supported.
Standard and Fast mode devices will operate when attached to the same bus, if the bus operates
at the speed of the slower device.
The I 2C interface employs a comprehensive protocol to ensure reliable transmission and reception of data. When transmitting data, one device is the “master” which initiates transfer on the bus
and generates the clock signals to permit that transfer, while the other device(s) acts as the
“slave.” All portions of the slave protocol are implemented in the SSP module’s hardware, except
general call support, while portions of the master protocol need to be addressed in the
PIC16CXX software. The MSSP module supports the full implementation of the I 2C master protocol, the general call address, and data transfers upto 1 Mbps. The 1 Mbps data transfers are
supported by some of Microchips Serial EEPROMs. Table A-1 defines some of the I 2C bus terminology.
In the I 2C interface protocol each device has an address. When a master wishes to initiate a data
transfer, it first transmits the address of the device that it wishes to “talk” to. All devices “listen” to
see if this is their address. Within this address, a bit specifies if the master wishes to
read-from/write-to the slave device. The master and slave are always in opposite modes (transmitter/receiver) of operation during a data transfer. That is they can be thought of as operating in
either of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA) lines must have an open-drain or open-collector in order to perform the wired-AND function of the bus. External pull-up resistors are used
to ensure a high level when no device is pulling the line down. The number of devices that may
be attached to the I 2C bus is limited only by the maximum bus loading specification of 400 pF
and addressing capability.
DS31034A-page 34-2
 1997 Microchip Technology Inc.
Appendix A
A.1
Initiating and Terminating Data Transfer
During times of no data transfer (idle time), both the clock line (SCL) and the data line (SDA) are
pulled high through the external pull-up resistors. The START and STOP conditions determine
the start and stop of data transmission. The START condition is defined as a high to low transition
of the SDA when the SCL is high. The STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure A-1 shows the START and STOP conditions. The master
generates these conditions for starting and terminating data transfer. Due to the definition of the
START and STOP conditions, when data is being transmitted, the SDA line can only change state
when the SCL line is low.
Figure A-1:
Start and Stop Conditions
SDA
SCL
S
Start
Condition
Table A-1:
Term
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization
P
Change
of Data
Allowed
Change
of Data
Allowed
Stop
Condition
I2C Bus Terminology
Description
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock and terminates
the transfer.
The device addressed by a master.
More than one master device in a system. These masters can attempt to
control the bus at the same time without corrupting the message.
Procedure that ensures that only one of the master devices will control the
bus. This ensure that the transfer data does not get corrupted.
Procedure where the clock signals of two or more devices are synchronized.
34
Appenidx
 1997 Microchip Technology Inc.
DS31034A-page 34-3
PICmicro MID-RANGE MCU FAMILY
A.2
Addressing I 2C Devices
There are two address formats. The simplest is the 7-bit address format with a R/W bit
(Figure A-2). The more complex is the 10-bit address with a R/W bit (Figure A-3). For 10-bit
address format, two bytes must be transmitted. The first five bits specify this to be a 10-bit
address format. The 1st transmitted byte has 5-bits which specify a 10-bit address, the two MSbs
of the address, and the R/W bit. The second byte is the remaining 8-bits of the address.
Figure A-2:
7-bit Address Format
MSb
LSb
R/W
S
slave address
S
R/W
ACK
Figure A-3:
ACK
Sent by
Slave
Start Condition
Read/Write pulse
Acknowledge
I2C 10-bit Address Format
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0
ACK
sent by slave
= 0 for write
S
R/W
ACK
DS31034A-page 34-4
- Start Condition
- Read/Write Pulse
- Acknowledge
 1997 Microchip Technology Inc.
Appendix A
A.3
Transfer Acknowledge
All data must be transmitted per byte, with no limit to the number of bytes transmitted per data
transfer. After each byte, the slave-receiver generates an acknowledge bit (ACK) (Figure A-4).
When a slave-receiver doesn’t acknowledge the slave address or received data, the master must
abort the transfer. The slave must leave SDA high so that the master can generate the STOP condition (Figure A-1).
Figure A-4:
Slave-Receiver Acknowledge
Data
Output by
Transmitter
Data
Output by
Receiver
not acknowledge
acknowledge
SCL from
Master
1
8
2
S
Start
Condition
9
Clock Pulse for
Acknowledgment
If the master is receiving the data (master-receiver), it generates an acknowledge signal for each
received byte of data, except for the last byte. To signal the end of data to the slave-transmitter,
the master does not generate an acknowledge (not acknowledge). The slave then releases the
SDA line so the master can generate the STOP condition. The master can also generate the
STOP condition during the acknowledge pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next byte, holding the SCL line low will force
the master into a wait state. Data transfer continues when the slave releases the SCL line. This
allows the slave to move the received data or fetch the data it needs to transfer before allowing
the clock to start. This wait state technique can also be implemented at the bit level, Figure A-5.
Figure A-5:
Data Transfer Wait State
SDA
MSB
acknowledgment
signal from receiver
byte complete
interrupt with receiver
acknowledgment
signal from receiver
34
clock line held low while
interrupts are serviced
SCL
S
1
 1997 Microchip Technology Inc.
Address
7
8
R/W
9
ACK
1
Wait
State
2
Data
3•8
9
ACK
P
Stop
Condition
DS31034A-page 34-5
Appenidx
Start
Condition
2
PICmicro MID-RANGE MCU FAMILY
Figure A-6 and Figure A-7 show Master-transmitter and Master-receiver data transfer
sequences.
Figure A-6:
Master-Transmitter Sequence
For 7-bit address:
S Slave Address R/W A Data A Data A/A P
'0' (write)
data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
For 10-bit address:
S Slave Address R/W A1 Slave Address A2 Data A
(Code + A9:A8)
(A7:A0)
Data A/A P
(write)
A master transmitter addresses a slave receiver
with a 10-bit address.
From master to slave
From slave to master
Figure A-7:
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Master-Receiver Sequence
For 7-bit address:
S Slave Address
R/W A Data A Data
A
P
'1' (read)
data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
For 10-bit address:
S Slave Address R/W A1 Slave Address
(A7:A0)
(Code + A9:A8)
(write)
A2 Sr Slave Address R/W A3 Data A
(Code + A9:A8)
Data A P
(read)
A master transmitter addresses a slave receiver
with a 10-bit address.
From master to slave
From slave to master
DS31034A-page 34-6
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
 1997 Microchip Technology Inc.
Appendix A
When a master does not wish to relinquish the bus (which occurs by generating a STOP condition), a repeated START condition (Sr) must be generated. This condition is identical to the start
condition (SDA goes high-to-low while SCL is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to send “commands” to the slave and then
receive the requested information or to address a different slave device. This sequence is shown
in Figure A-8.
Figure A-8:
Combined Format
(read or write)
(n bytes + acknowledge)
S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P
(read)
Sr = repeated
Start Condition
(write)
Direction of transfer
may change at this point
Transfer direction of data and acknowledgment bits depends on R/W bits.
Combined format:
Sr Slave Address R/W A Slave Address A Data A
(Code + A9:A8)
(A7:A0)
Data A/A Sr Slave Address R/W A Data A
(Code + A9:A8)
Data A P
(read)
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
34
Appenidx
 1997 Microchip Technology Inc.
DS31034A-page 34-7
PICmicro MID-RANGE MCU FAMILY
A.4
Multi-master
The I2C protocol allows a system to have more than one master. This is called multi-master.
When two or more masters try to transfer data at the same time, arbitration and synchronization
occur.
A.4.1
Arbitration
Arbitration takes place on the SDA line, while the SCL line is high. The master which transmits a
high when the other master transmits a low loses arbitration (Figure A-9), and turns off its data
output stage. A master which lost arbitration can generate clock pulses until the end of the data
byte where it lost arbitration. When the master devices are addressing the same device, arbitration continues into the data.
Figure A-9:
Multi-Master Arbitration (Two Masters)
transmitter 1 loses arbitration
DATA 1 SDA
DATA 1
DATA 2
SDA
SCL
Masters that also incorporate the slave function, and have lost arbitration must immediately
switch over to slave-receiver mode. This is because the winning master-transmitter may be
addressing it.
Arbitration is not allowed between:
• A repeated START condition
• A STOP condition and a data bit
• A repeated START condition and a STOP condition
Care needs to be taken to ensure that these conditions do not occur.
DS31034A-page 34-8
 1997 Microchip Technology Inc.
Appendix A
A.4.2
Clock Synchronization
Clock synchronization occurs after the devices have started arbitration. This is performed using
a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the concerned devices to start counting off their low period. Once a device clock has gone low, it will hold
the SCL line low until its SCL high state is reached. The low to high transition of this clock may
not change the state of the SCL line, if another device clock is still within its low period. The SCL
line is held low by the device with the longest low period. Devices with shorter low periods enter
a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start
counting off their high periods. The first device to complete its high period will pull the SCL line
low. The SCL line high time is determined by the device with the shortest high period,
Figure A-10.
Figure A-10:
Clock Synchronization
wait
state
start counting
HIGH period
CLK
1
CLK
2
counter
reset
SCL
Figure A-11:
SCL
I2C Bus Start/Stop Bits Timing Specification
93
91
90
92
SDA
34
STOP
Condition
START
Condition
Microchip
Parameter
No.
Sym
I2C Bus Start/Stop Bits Timing Specification
Characteristic
Min
Typ
Max
Units
Conditions
Only relevant for
repeated START condition
After this period the first
clock pulse is generated
90
TSU:STA
START condition
Setup time
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
ns
91
THD:STA
TSU:STO
93
THD:STO
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4000
600
4700
600
4000
600
—
—
—
—
—
—
—
—
—
—
—
—
ns
92
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
 1997 Microchip Technology Inc.
ns
ns
DS31034A-page 34-9
Appenidx
Table A-2:
PICmicro MID-RANGE MCU FAMILY
I2C Bus Data Timing Specification
Figure A-12:
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Table A-3:
Microchip
Parameter
No.
I2C Bus Data Timing Specification
Sym
Characteristic
100
THIGH
Clock high time
101
TLOW
Clock low time
102
TR
SDA and SCL
rise time
103
TF
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
SDA and SCL fall 100 kHz mode
time
400 kHz mode
90
TSU:STA START condition
setup time
91
THD:STA START condition
hold time
106
THD:DAT Data input hold
time
107
TSU:DAT Data input setup
time
92
TSU:STO STOP condition
setup time
109
TAA
Output valid from
clock
110
TBUF
Bus free time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Min
Max
Units
4.0
0.6
4.7
1.3
—
20 +
0.1Cb
—
20 +
0.1Cb
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
1000
300
µs
µs
µs
µs
ns
ns
300
300
ns
ns
—
—
—
—
—
0.9
—
—
—
—
3500
1000
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Conditions
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first
clock pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can start
D102
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
DS31034A-page 34-10
 1997 Microchip Technology Inc.
Appendix B
APPENDIX B: LIST OF LCD GLASS MANUFACTURERS
AEG-MIS
3340 Peachtree Rd. NE Suite 500
Atlanta, GA 30326
TEL: 404-239-0277
FAX: 404-239-0383
Interstate Electronics Corp.
1001 E. Bull Rd.
Anaheim, CA 92805
TEL: 800-854-6979
FAX: 714-758-4111
All Shore INDS Inc.
1 Edgewater Plaza
Staten Island, NY 10305
TEL: 718-720-0018
FAX: 718-720-0225
Kent Display Systems
343 Portage Blvd.
Kent, OH 44240
TEL: 330-673-8784
Crystaloid
5282 Hudson Drive
Hudson, OH 44236-3769
TEL: 216-655-2429
FAX: 216-655-2176
LCD Planar Optics Corporation
2100-2 Artic Ave.
Bohemia, NY 11716
TEL: 516-567-4100
FAX: 516-567-8516
DCI Inc.
14812 W. 117th St.
Olathe, KS 66062-9304
TEL: 913-782-5672
FAX: 913-782-5766
LXD Inc.
7650 First Place
Oakwood Village, OH 44146
TEL: 216-786-8700
FAX: 216-786-8711
Excel Technology International Corporation
Unit 5, Bldg. 4, Stryker Lane
Belle Mead, NJ 08502
TEL: 908-874-4747
FAX: 908-874-3278
Nippon Sheet Glass
Tomen America Inc.
1285 Avenue of the Americas
New York, NY 10019
TEL: 212-397-4600
FAX: 212-397-3351
F-P Electronics/Mark IV Industries
6030 Ambler Drive
Mississauga, ON Canada L4W 2PI
TEL: 905-624-3020
FAX: 905-238-3141
OPTREX America
44160 Plymouth Oaks Blvd.
Plymouth, MI 48170
TEL: 313-416-8500
FAX: 313-416-8520
Hunter Components
24800 Chagrin Blvd, Suite 101
Cleveland, OH 44122
TEL: 216-831-1464
FAX: 216-831-1463
Phillips Components
LCD Business Unit
1273 Lyons Road, Bldg G
Dayton, OH 45459
TEL: 573-436-9500
FAX: 573-436-2230
34
Appenidx
 1997 Microchip Technology Inc.
DS31034A-page 34-11
PICmicro MID-RANGE MCU FAMILY
Satori Electric
23717 Hawthorne Blvd. 3rd Floor
Torrance, CA 90505
TEL: 310-214-1791
FAX: 310-214-1721
Varitronix Limited Inc.
3250 Wilshire Blvd. Suite 1901
Los Angeles, CA 90010
TEL: 213-738-8700
FAX: 213-738-5340
Seiko Instruments USA Inc.
Electronic Components Division
2990 West Lomita Blvd.
Torrance, CA 90505
TEL: 213-517-7770
213-517-8113
FAX: 213-517-7792
Varitronix Limited Inc.
4/F, Liven House
61-63 King Yip Street
Kwun Tong, Kowloon
Hong Kong
TEL: 852 2389 4317
FAX: 852 2343 9555
Standish International
European Technical Center
Am Baümstuck II
65520 Bad Camberg/Erbach
Germany
TEL: 011 49 6434 3324
FAX: 011 49 6434 377238
Varitronix (France) S.A.R.L.
13/15 Chemin De Chilly
91160 Champlain
France
TEL:(33) 1 69 09 7070
FAX:(33) 1 69 09 0535
Standish LCD
W7514 Highway V
Lake Mills, WI 53551
TEL: 414-648-1000
FAX: 414-648-1001
Varitronix Italia, S.R.L.
Via Bruno Buozzi 90
20099 Sesto San Giovanni
Milano, Italy
TEL:(39) 2 2622 2744
FAX:(39) 2 2622 2745
Truly Semiconductors Ltd. (USA)
2620 Concord Ave.
Suite 106
Alhambra, CA 91803
TEL: 818-284-3033
FAX: 818-284-6026
Varitronix (UK) Limited
Display House, 3 Milbanke Court
Milbanke Way, Bracknell
Berkshire RG12 1BR
United Kingdom
TEL:(44) 1344 30377
FAX(44) 1344 300099
Truly Semiconductor Ltd.
2/F, Chung Shun Knitting Center
1-3 Wing Yip Street,
Kwai Chung, N.T., Hong Kong
TEL: 852 2487 9803
FAX: 852 2480 0126
Varitronix (Canada) Limited
18 Crown Steel Drive, Suite 101
Markham, Ontario
Canada L3R 9X8
TEL:(905) 415-0023
FAX:(905) 415-0094
Vikay America Inc.
195 W. Main St.
Avon, CT 06001-3685
TEL: 860-678-7600
FAX: 860-678-7625
DS31034A-page 34-12
 1997 Microchip Technology Inc.
Appendix C
APPENDIX C: DEVICE ENHANCEMENT
As the Midrange architecture matured, certain modules and features have been enhanced. They
are:
1.
2.
3.
4.
5.
6.
7.
The data memory map
The SSP module
The A/D module
Brown-out Reset added to the core
MCLR Filter
USART
Device Oscillator
The following subsections discuss the implementations of these enhancements.
C.1
Data Memory Map
The Data Memory Map shows the location of the Special Function Registers (SFRs) and the
General Purpose Registers (GPRs). SFRs provide controls and give status on the operation of
the device, while the GPRs are the general purpose RAM.
Figure C-1 show the various memory maps that have been implemented in the midrange family.
Memory Map A was implemented on the first midrange devices. They were 18/20-pin devices
that had limited peripheral features. When the product roadmap dictated the requirement for
devices with increased I/O, and a richer peripheral set, memory map B was implemented. Memory map C is actually a subset of memory map B, but context saving (due to an interrupt) requires
additional software overhead. This is because there is no GPR in Bank1. To minimize the context
saving software, memory map D was defined. A common RAM memory map will be used for all
future devices. See the “Memory Organization” section for use and implementation of the
Midrange PICmicro’s memory.
Figure C-1:
Various Data Memory Maps
A
C
B
00h
0Bh
0Ch
80h
SFR
SFR
00h
8Bh
8Ch
1Fh
20h
(1)
GPR
7Fh
FFh
SFR
SFR
GPR
GPR
7Fh
Bank0 Bank1
80h
00h
9Fh
A0h
1Fh
20h
80h
SFR
GPR
FFh
SFR
9Fh
A0h
(2)
7Fh
FFh
Appenidx
D(3)
00h
1Fh
20h
80h
SFR
9Fh
A0h
F0h
FFh
Bank0
11Fh
120h
GPR
GPR
70h
7Fh
100h
SFR
(1)
Bank1
180h
SFR
19Fh
1A0h
(1)
Bank2
SFR
GPR
GPR
170h
17Fh
1F0h
1FFh
(1)
Bank3
Note 1: Mapped in Bank0.
2: Unimplemented, read as '0'.
3: Some devices have some GPR located in the SFR region.
 1997 Microchip Technology Inc.
34
Bank0 Bank1
Bank0 Bank1
DS31034A-page 34-13
PICmicro MID-RANGE MCU FAMILY
C.2
SSP (Synchronous Serial Port) Module
The SSP module has two modes of operation;
• SPI (Serial Peripheral Interface)
• I2C (Inter-Integrated Circuit).
There are now three different SSP modules that exist in Microchip’s design library. The first SSP
module (now called Basic SSP) implements two of the four SPI modes, and the I2C module in
slave mode. The second SSP module (called SSP) implements all four SPI modes, and the I2C
module in slave mode. The third SSP module (called Master SSP) implements all four SPI
modes, and the I2C module in master and slave modes. Table C-1 shows the devices that have
an SSP module and denotes which version is implemented. As new devices are introduced,
either the SSP module or Master SSP module will be implemented (that is, the Basic SSP module is being phased out). Only select devices will be introduced with the Master SSP module due
to the size (silicon area => cost) difference in relation to the SSP module. If your application
requires I2C Master mode, then you should also check into Microchip’s high-end family,
PIC17CXXX.
Table C-1:
Devices With an SSP module
Synchronous Serial Port Version
Device
SSP
Basic SSP
Master SSP (1)
PIC16C62
—
Yes
—
PIC16C62A
—
Yes
—
—
—
—
—
—
—
—
—
—
Yes
Yes
—
Yes
—
—
—
—
Yes
Yes
Yes
Yes
See Device
Data Sheet
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
Yes
—
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Device
Data Sheet
PIC16CR62
PIC16C63
PIC16CR63
PIC16C64
PIC16C64A
PIC16CR64
PIC16C65
PIC16C65A
PIC16CR65
PIC16C66
PIC16C67
PIC16C72
PIC16CR72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
PIC16C76
PIC16C77
PIC16C923
PIC16C924
Future Devices with SSP
module
—
Note 1: At present NO midrange devices are available with the Master SSP module. Please
refer to Microchip’s Web site or BBS for release of Product Briefs. You will be able to
find out the details of features for new devices.
This module is available on Microchip’s High End family (PIC17CXXX). Please
refer to Microchip’s Web site, BBS, Regional Sales Office, or Factory Representatives.
DS31034A-page 34-14
 1997 Microchip Technology Inc.
Appendix C
C.3
A/D (Analog-to-Digital) Module
There now exists several different versions of the A/D module in Microchip’s design library. The
first A/D module (now called Basic 8-bit A/D) is an 8-bit A/D with four input channels. The second
A/D module (called 8-bit A/D) is an 8-bit A/D with up to 8 input channels. The Third A/D module
(called 10-bit A/D) is a 10-bit A/D with up to16 input channels implemented. Table C-2 shows
which devices have an A/D module, and the version implemented. As new devices are introduced, either the 8-bit A/D module or 10-bit A/D module will be implemented (that is the Basic
8-bit A/D module is being phased out). If your application requires the 10-bit A/D, you should refer
to Microchip’s High End Family (PIC17CXXX). This family currently has some devices that have
this module implemented.
Table C-2:
Devices With A/D modules
Device
PIC16C710
PIC16C71
PIC16C711
PIC16C715
PIC16C72
PIC16CR72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
PIC16C76
PIC16C77
PIC16C924
PIC14C000
Future Devices
with A/D module
8-bit A/D
Basic 8-bit A/D
10-bit A/D (1)
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
See Device
Data Sheet
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
—
—
See Device
Data Sheet
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Device
Data Sheet
Slope A/D
—
Yes
See Device
Data Sheet
Note 1: At present NO midrange devices are available with the 10-bit A/D module. Please
refer to Microchip’s Web site or BBS for release of Product Briefs. You will be able to
find out the details of features for new devices.
This module is available on Microchip’s High End family (PIC17CXXX). Please
refer to Microchip’s Web site, BBS, Regional Sales Office, or Factory Representatives.
34
Appenidx
 1997 Microchip Technology Inc.
DS31034A-page 34-15
PICmicro MID-RANGE MCU FAMILY
C.4
Brown-out Reset
An internal Brown-out Reset (BOR) circuit was added as a special feature. This circuit will be
added to most new devices. The exception will be for devices whose target market will require
normal operation below the BOR trip point (handheld battery applications). Table C-3 shows the
devices that evolved into having the BOR circuitry.
Table C-3:
C.5
Devices That Were Revised to Include On-chip Brown-out Reset
Base Device
No
Brown-out Reset
Subsequent Device
with
Brown-out Reset
PIC16C62
PIC16C64
PIC16C65
PIC16C71
PIC16C73
PIC16C74
PIC16C62A
PIC16C64A
PIC16C65A
PIC16C711
PIC16C73A
PIC16C74A
Comparator
If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is
being executed (start of the Q2 cycle), then the CMIF interrupt flag bit may not get set.
DS31034A-page 34-16
 1997 Microchip Technology Inc.
Appendix C
C.6
MCLR Filter
The master clear (MCLR) logic has had a filter added. This filter ignores short duration (glitch)
low level pulses on the Master Clear pin. Table C-4 shows whether the device has the master
clear filter.
Table C-4:
Devices With Master Clear Filter
Master Clear
Device
 1997 Microchip Technology Inc.
Filter
Yes
Yes
—
—
—
—
Yes
—
—
Yes
—
—
—
—
—
—
—
—
Yes
—
—
—
—
Yes
—
Yes
—
—
—
Yes
Yes
Yes
Yes
—
—
—
—
—
Yes
Yes
Yes
Yes
—
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
—
Yes
—
Yes
Yes
Yes
—
—
—
—
Yes
Yes
Yes
DS31034A-page 34-17
34
Appenidx
PIC16C61
PIC16C62
PIC16C62A
PIC16CR62
PIC16C63
PIC16CR63
PIC16C64
PIC16C64A
PIC16CR64
PIC16C65
PIC16C65A
PIC16CR65
PIC16C66
PIC16C67
PIC16C620
PIC16C621
PIC16C622
PIC16C710
PIC16C71
PIC16C711
PIC16C715
PIC16C72
PIC16CR72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
PIC16C76
PIC16C77
PIC16C83
PIC16C84
PIC16F83
PIC16F84
PIC16C923
PIC16C924
All New Devices
No Filter
(Fast Reset)
PICmicro MID-RANGE MCU FAMILY
C.7
USART
The original USART/SCI module that was offered on Midrange devices specified a “high speed”
mode (when the BRGH control bit is set). Due to the design of the sampling circuitry, the operation of this mode was not as robust as desired. The sampling circuitry has been changed so that
operation now meets Microchip’s requirements. The difference in the sampling is described in the
“USART” section. Table C-5 shows which devices use the new and old sampling logic.
Table C-5:
USART/SCI Sampling Logic
Sampling Logic
Device
PIC16C63
PIC16CR63
PIC16C65
PIC16C65A
PIC16CR65
PIC16C66
PIC16C67
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
PIC16C76
PIC16C77
New Devices with
USART/SCI module
C.8
Old
New
Yes
Yes
Yes
Yes
Yes
—
—
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
Yes
Yes
—
—
—
—
Yes
Yes
—
Yes
Device Oscillator
A new mode has been added into the device oscillator which allows the device to operate from
an internal RC. This is specified at time of device programming (configuration word). This mode
will be included on many future devices. See the device data sheets configuration word to determine if the device supports this mode.
C.9
Parallel Slave Port
The control pins have changed from level sensitive to edge sensitive.
Table C-6:
Parallel Slave Port Change Sensitivity
Sensitivity
Device
PIC16C64
PIC16C64A
PIC16C65
PIC16C65A
PIC16C67
PIC16C74
PIC16C74A
PIC16C77
New Devices with
Parallel Slave Port
DS31034A-page 34-18
Level
Edge
Yes
—
Yes
—
—
Yes
—
—
—
Yes
—
Yes
Yes
—
Yes
Yes
—
Yes
 1997 Microchip Technology Inc.
Appendix D
APPENDIX D: REVISION HISTORY
Revision A
This is the initial released revision of the Reference Guide Appendix.
34
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 1997 Microchip Technology Inc.
DS31034A-page 34-19
PICmicro MID-RANGE MCU FAMILY
DS31034A-page 34-20
 1997 Microchip Technology Inc.