Call subroutine (Call)

Section 3. Instruction Descriptions
CALL
Call Subroutine
Syntax:
{label:}
Operands:
Operation:
lit23 ∈ [0 ... 8388606]
(PC)+4 → PC,
(PC<15:0>) → TOS,
(W15)+2 → W15
(PC<23:16>) → TOS,
(W15)+2 → W15
lit23 → PC, NOP → Instruction Register.
If S = 1, push the primary registers into the shadow registers.
None
Status Affected:
Encoding:
1st word
2nd word
Description:
CALL
CALL.S
lit23
0000
001S
nnnn
nnnn
nnnn
nnn0
0000
0000
0000
0000
0nnn
nnnn
Direct subroutine call over the entire 4M byte instruction program memory
range. Before the call is made, the 24-bit return address (PC+4) is pushed
onto the stack. After the return address is stacked, the 23-bit value ‘lit23’ is
loaded into the PC.
If the “.S” extension is specified, the primary registers are copied to the
shadow registers before the PC is modified. If the “.S” extension is not
specified, the shadow registers are not updated.
Example 1
Q3
Process
data
NOP
026000
026004
.
.
026844 _FIR:
026846
PC
W15
Data A268
Data A26A
SR
 2001 Microchip Technology Inc.
Before
Instruction
02 6000
A268
FFFF
FFFF
0000
Q4
Write to
PC
NOP
CALL
MOV
...
...
MOV
...
_FIR
W0, W1
#0x400, W2
PC
W15
Data A268
Data A26A
SR
Advanced Information
; Call _FIR subroutine
; (without shadowing)
; _FIR subroutine start
After
Instruction
02 6844
A26C
6000
0002
0000
DS70030A-page 3-87
Instruction
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
Read
lit23
NOP
NOP
Descriptions
The ‘S’ bit selects the shadowing option (1 for shadow, 0 for no shadow).
The ‘n’ bits form the target address.
3
dsPIC30F Programmer’s Reference Manual
Example 2
072000
072004
.
077A28 _G66:
077A2A
077A2C
PC
W15
Data 9004
Data 9006
SR
DS70030A-page 3-88
Before
Instruction
07 2000
9004
FFFF
FFFF
0000
CALL.S
MOV
...
INC
...
_G66
W0, W1
; Call _G66 subroutine
; (with shadowing)
W6, [W7]++
; _G66 subroutine start
PC
W15
Data 9004
Data 9006
SR
Advanced Information
After
Instruction
07 7A28
9008
2000
0007
0000
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CALL
Syntax:
Call Indirect Subroutine
{label:}
CALL
Wn
CALL.S
Operands:
Wn ∈ [W0, W15]
Operation:
(PC) +2 → PC,
(PC<15:0>) → TOS,
(W15)+2 → W15
(PC<23:16>) → TOS,
(W15)+2 → W15
0 → PC<22:17>, (Wn) → PC<16:1>, 0 → PC<0>;
NOP → Instruction Register.
If S = 1, push the primary registers into the shadow registers.
Status Affected:
None
Encoding:
Description:
0000
0001
S000
0000
0000
ssss
Indirect subroutine call over the first 64K instructions of program memory.
Before the call is made, the 24-bit return address (PC+2) is pushed onto the
stack. After the return address is stacked, the 16-bit value Wn is left-shifted
1 bit, zero-extended and loaded into the PC.
If the “.S” extension is specified, the primary registers are copied to the
shadow registers before the PC is modified. If the “.S” extension is not specified, the shadow registers are not updated.
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
NOP
 2001 Microchip Technology Inc.
Q2
Q3
Read Wn
Process
Data
NOP
NOP
Q4
Write to
PC
NOP
Advanced Information
DS70030A-page 3-89
Instruction
Words:
Descriptions
The ‘S’ bit selects the shadowing option (0 for no shadow, 1 for shadow).
The ‘s’ bits select the address of the source register.
3
dsPIC30F Programmer’s Reference Manual
Example 1
001002
001004
.
001600 _BOOT:
001602
.
PC
W0
W15
Data 6F00
Data 6F02
SR
Example 2
W0
; Call BOOT subroutine indirectly
; using W0 (no shadow)
#0x400, W2
#0x300, W6
; _BOOT starts here
Before
Instruction
00 1002
0B00
6F00
FFFF
FFFF
0000
004200
004202
.
005500 _TEST:
005502
.
PC
W7
W15
Data 6F00
Data 6F02
SR
DS70030A-page 3-90
CALL
...
...
MOV
MOV
...
Before
Instruction
00 4200
0980
6F00
FFFF
FFFF
0000
PC
W0
W15
Data 6F00
Data 6F02
SR
CALL.S
...
...
INC
DEC
...
After
Instruction
00 1600
0B00
6F04
1600
0000
0000
W7
; Call TEST subroutine indirectly
; using W7 (with shadow)
W1, W2
W1, W3
; _TEST starts here
;
PC
W7
W15
Data 6F00
Data 6F02
SR
Advanced Information
After
Instruction
00 5500
0980
6F04
4200
0000
0000
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CLR
Clear f or WREG
Syntax:
{label:}
CLR{.b}
f
WREG
Operands:
f ∈ [0 ... 8191]
Operation:
0 → destination designated by D
Status Affected:
Z
Encoding:
1110
Description:
1111
0BDf
ffff
ffff
ffff
Clear the contents of a file register or the default working register WREG. If
WREG is specified, the WREG is cleared. Otherwise, the specified file register f is cleared. This instruction sets the Zero flag bit.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘D’ bit selects the destination (0 for WREG, 1 for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Cycles:
1
3
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
CLR.B
Q3
Process
data
RAM200
Before
Instruction
RAM200
8009
SR
0000
Example 2
CLR
WREG
Before
Instruction
WREG
0600
SR
0000
 2001 Microchip Technology Inc.
Q4
Write to
destination
; Clear RAM200 (byte mode)
After
Instruction
RAM200
8000
SR
0004 (Z=1)
; Clear WREG (word mode)
After
Instruction
WREG
0000
SR
0004 (Z=1)
Advanced Information
DS70030A-page 3-91
Instruction
1
Descriptions
Words:
dsPIC30F Programmer’s Reference Manual
CLR
Clear Ws
Syntax:
{label:}
CLR{.b}
Ws
[Ws]
[Ws]++
[Ws]-[Ws++]
[Ws--]
Operands:
Ws ∈ [W0 ... W15]
Operation:
0 → Ws
Status Affected:
Z
Encoding:
1110
Description:
1011
0B00
0000
0ppp
ssss
Clear the contents of register Ws. Either register direct or indirect addressing may be used for Ws. This instruction sets the Zero flag bit.
The ‘B’ bits selects byte or word operation (0 for word, 1 for byte).
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the source/destination register.
Note:
Words:
1
Cycles:
1
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
CLR.B
Q3
Process
data
W2
Before
Instruction
W2
3333
SR
0000
Example 2
CLR
[W0]++
Before
Instruction
W0
2300
Data 2300
5607
SR
0000
DS70030A-page 3-92
Q4
Write to
destination
; Clear W2 (byte mode)
After
Instruction
W2
3300
SR
0004 (Z=1)
; Clear [W0]
; Post-increment W0
After
Instruction
W0
2302
Data 2300
0000
SR
0004 (Z=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CLR
Syntax:
Clear Accumulator, Prefetch Operands
{label:} CLR
A,
,Wxp,[Wx]
,Wyp,[Wy]
,AWB
B,
,Wxp,[Wx]+=kx
,Wyp,[Wy]+=ky
none
,Wxp,[Wx]-=kx
,Wyp,[Wy]-=ky
,Wxp,[W5+W8]
,Wyp,[W7+W8]
none
none
Operands:
Wxp ∈ {W0 ... W3}; Wx ∈ {W4, W5}; kx ∈ {-6, -4, -2, 2, 4, 6};
Wyp ∈ {W0 ... W3}; Wy ∈ {W6, W7}; ky ∈ {-6, -4, -2, 2, 4, 6};
AWB ∈ {W9, [W9]++}
Operation:
0 → ACC(A or B)
([Wx])→ Wxp; (Wx)+kx→Wx;
([Wy])→ Wyp; (Wy)+ky→Wy;
(ACC(B or A)) rounded → AWB
Status Affected:
OA, OB, SA, SB
Encoding:
Description:
1100
0011
A0xx
yyii
iijj
jjaa
Clear all 40 bits of the specified accumulator, optionally prefetch operands
in preparation for a MAC-type instruction and optionally store the non-specified accumulator results.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
 2001 Microchip Technology Inc.
Q2
Read
operands
Q3
Process
data
Q4
Write to
destination
Advanced Information
DS70030A-page 3-93
Instruction
The ‘A’ bit selects the other accumulator used for write back.
The ‘x’ bits select the pre-fetch Wxp destination.
The ‘y’ bits select the pre-fetch Wyp destination.
The ‘i’ bits select the Wx pre-fetch operation.
The ‘j’ bits select the Wy pre-fetch operation.
The ‘a’ bits select the accumulator write-back destination.
3
Descriptions
Operands Wx, Wxp, Wy and Wyp specify optional prefetch operations
which support indirect and register offset addressing as described in
Section 2.11.1. Operand AWB specifies the optional register direct or indirect store of the convergently rounded contents of the “other” accumulator
as described in Section 2.11.4.
dsPIC30F Programmer’s Reference Manual
Example 1
CLR
A, W0, [W4]++, W9
; Clear ACCA
; Load W0 with [W4], post-inc W4
; Store ACCB to W9
Before
Instruction
W0
F001
W4
2000
W9
C623
ACCA 00 0067 2345
ACCB 00 5420 ABDD
Data 2000
1221
SR
0000
Example 2
CLR
After
Instruction
W0
1221
W4
2002
W9
5421
ACCA 00 0000 0000
ACCB 00 5420 ABDD
Data 2000
1221
SR
0000
B, W2, [W4]++, W3, [W6]++, [W9]++
Before
Instruction
W2
W3
W4
W6
W9
ACCA
ACCB
Data 2000
Data 3000
Data 4000
SR
DS70030A-page 3-94
F001
C783
2000
3000
4000
00 0067 2345
00 5420 ABDD
1221
1221
FFC3
0000
; Clear ACCB
; Load W2 with [W4]
; Load W3 with [W6]
; Save ACCA to [W9]
; Post-inc W4, W6, W9
After
Instruction
W2
W3
W4
W6
W9
ACCA
ACCB
Data 2000
Data 3000
Data 4000
SR
Advanced Information
1221
FF80
2002
3002
4002
00 0067 2345
00 0000 0000
1221
FF80
0067
0000
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CLRWDT
Clear Watchdog Timer
Syntax:
{label:}
Operands:
none
Operation:
0 → WDT Reg
Status Affected:
TO, PD
Encoding:
CLRWDT
1111
1110
0110
0000
Description:
Clear the contents of the Watchdog Timer register.
Words:
1
Cycles:
1
0000
0000
Q Cycle Activity:
Q1
Decode
Q2
Q3
NOP
NOP
Q4
Write to
WDT Reg
3
Advanced Information
DS70030A-page 3-95
Instruction
Descriptions
 2001 Microchip Technology Inc.
dsPIC30F Programmer’s Reference Manual
COM
Complement f
Syntax:
{label:}
COM{.b}
f
{,WREG}
Operands:
f ∈ [0 ... 8191]
Operation:
(f) → destination designated by D
Status Affected:
SZ, N, Z
Encoding:
1110
Description:
1110
1BDf
ffff
ffff
ffff
Compute the 1’s complement of the contents of the file register and place the
result in the destination register. The optional WREG operand determines
the destination register. If WREG is specified, the result is stored in WREG.
If WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘D’ bit selects the destination (0 for WREG, 1 for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
COM.b
Q3
Process
data
RAM200
Before
Instruction
RAM200
80FF
SR
0000
Example 2
COM
; COM RAM200 (byte mode)
After
Instruction
RAM200
8000
SR
0024 (SZ, Z=1)
RAM400, WREG
Before
Instruction
WREG
1211
RAM400
0823
SR
0000
DS70030A-page 3-96
Q4
Write to
destination
; COM RAM400 and store to WREG
; (word mode)
After
Instruction
WREG
F7DC
RAM400
0823
SR
0010 (N=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
COM
Complement Ws
Syntax:
{label:}
COM{.b}
Ws,
Wd
[Ws],
[Wd]
[Ws]++,
[Wd]++
[Ws]--,
[Wd]--
[Ws++],
[Wd++]
[Ws--],
[Wd--]
Operands:
Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:
(Ws) → Wd
Status Affected:
SZ, N, Z
Encoding:
1110
Description:
1010
1Bqq
qddd
dppp
ssss
Compute the 1’s complement of the contents of the source register Ws and
place the result in the destination register Wd. Either register direct or indirect addressing may be used for both Ws and Wd.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘q’ bits select the destination address mode.
The ‘d’ bits select the address of the destination register.
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the source register.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
COM.b
[W0]++, [W1]++
Before
Instruction
W0
2301
W1
6000
Data 2300
5607
Data 6000
ABCD
SR
0000
 2001 Microchip Technology Inc.
Q3
Process
data
Q4
Write to
destination
; COM [W0] and store to [W1] (byte mode)
; Post-increment W0, W1
After
Instruction
W0
2302
W1
6001
Data 2300
5607
Data 6000
ABA9
SR
0010 (N=1)
Advanced Information
DS70030A-page 3-97
Instruction
Words:
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Descriptions
Note:
3
dsPIC30F Programmer’s Reference Manual
Example 2
COM
W0, [W1]++
Before
Instruction
W0
D004
W1
6000
Data 6000
ABA9
SR
0000
DS70030A-page 3-98
; COM W0 and store to [W1] (word mode)
; Post-increment W1
After
Instruction
W0
D004
W1
6002
Data 6000
200B
SR
0000
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CP
Compare f with WREG, Set status flags
Syntax:
{label:}
CP{.b}
f
Operands:
f ∈ [0 ...8191]
Operation:
(f) - (WREG)
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
0011
0B0f
ffff
ffff
ffff
Compute (f) - (WREG), and update the Status Register. This instruction is
equivalent to the SUBWF instruction, but the result of the subtraction is not
stored.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1
3
Q Cycle Activity:
CP.b
Q3
Process
data
RAM400
Before
Instruction
WREG
8823
RAM400
0823
SR
0000
Example 2
CP
0x1200
Before
Instruction
WREG
2377
Data 1200
2277
SR
0000
 2001 Microchip Technology Inc.
Q4
NOP
; Compare RAM400 with WREG (byte mode)
After
Instruction
WREG
8823
RAM400
0823
SR
0024 (SZ, Z=1)
; Compare (0x1200) with WREG (word mode)
After
Instruction
WREG
2377
Data 1200
2277
SR
0010 (N=1)
Advanced Information
DS70030A-page 3-99
Instruction
Example 1
Q2
Read
operands
Descriptions
Q1
Decode
dsPIC30F Programmer’s Reference Manual
CP
Compare Wb with lit5, Set status flags
Syntax:
{label:}
CP{.b}
Wb,
Operands:
Wb ∈ [W0 ... W15]; lit5 ∈ [0 ... 31]
Operation:
(Wb) - lit5
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
0001
#lit5
0www
wB00
011k
kkkk
Compute (Wb) - lit5, and update the Status Register. This instruction is
equivalent to the SUBLS instruction, but the result of the subtraction is not
stored. Register direct addressing must be used for Wb.
The ‘w’ bits select the address of the Wb base register.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘k’ bits provide the literal operand, a five bit integer number.
Note:
Words:
1
Cycles:
1
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
CP.b
Q3
Process
data
W4, #0x12
Before
Instruction
W4
7711
SR
0000
Example 2
CP
W4, #0x12
Before
Instruction
W4
7713
SR
0000
DS70030A-page 3-100
Q4
NOP
; Compare W4 with 0x12 (byte mode)
After
Instruction
W4
7711
SR
0010 (N=1)
; Compare W4 with 0x12 (word mode)
After
Instruction
W4
7713
SR
0000
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CP
Compare Ws with Wb, Set status flags
Syntax:
{label:}
CP{.b}
Wb,
Ws
[Ws]
[Ws]++
[Ws]-[Ws++]
[Ws--]
Operands:
Wb ∈ [W0 ... W15]; Ws ∈ [W0 ... W15]
Operation:
(Ws) - (Wb)
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
0001
0www
wB00
0ppp
ssss
Compute (Ws) - (Wb), and update the Status Register. This instruction is
equivalent to the SUBR instruction, but the result of the subtraction is not
stored. Register direct addressing must be used for Wb. Register direct or
indirect addressing may be used for Ws.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the Ws source register.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
CP.b
Q3
Process
data
W0, [W1]++
Before
Instruction
W0
D004
W1
6000
Data 6000
ABA9
SR
0000
 2001 Microchip Technology Inc.
Q4
NOP
; Compare [W1] with W0 (byte mode)
; Post-increment W1
After
Instruction
W0
D004
W1
6001
Data 6000
200B
SR
0010 (N=1)
Advanced Information
DS70030A-page 3-101
Instruction
Words:
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Descriptions
Note:
3
dsPIC30F Programmer’s Reference Manual
Example 2
CP
W5, W6
Before
Instruction
W5
8001
W6
2334
SR
0000
DS70030A-page 3-102
; Compare W6 with W5 (word mode)
After
Instruction
W5
8001
W6
2334
SR
0018 (N,OV=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CP0
Compare f with 0x0, Set status flags
Syntax:
{label:}
CP0{.b}
Operands:
f ∈ [0 ... 8191]
Operation:
(f) - 0x0
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
f
0010
0B0f
ffff
ffff
ffff
Compute (f) - 0x0 and update the Status Register. The result of the subtraction is not stored.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note:
Words:
1
Cycles:
1
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Q Cycle Activity:
Q1
Decode
CP0.b
RAM100
Before
Instruction
RAM100
44C3
SR
0000
Example 2
CP0
0x1FFE
Before
Instruction
Data 1FFE
0001
SR
0000
 2001 Microchip Technology Inc.
Q4
3
NOP
; Compare RAM100 with 0x0 (byte mode)
After
Instruction
RAM100
44C3
SR
0010 (N=1)
; Compare (0x1FFE) with 0x0 (word mode)
After
Instruction
Data 1FFE
0001
SR
0000
Advanced Information
DS70030A-page 3-103
Instruction
Q3
Process
data
Descriptions
Example 1
Q2
Read
operands
dsPIC30F Programmer’s Reference Manual
CP0
Compare Ws with 0x0, Set status flags
Syntax:
{label:}
CP0{.b}
Ws
[Ws]
[Ws]++
[Ws]-[Ws++]
[Ws--]
Operands:
Ws ∈ [W0 ... W15]
Operation:
(Ws) - 0x0000
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
0000
0B00
0000
0ppp
ssss
Compute (Ws) - 0x0 and update the Status Register. The result of the subtraction is not stored. Register direct or indirect addressing may be used for
Ws.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the Ws source register.
Note:
Words:
1
Cycles:
1
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operand
Q3
Process
data
CP0.b
[W4]--
Before
Instruction
W4
8001
Data 8000
0034
SR
0000
DS70030A-page 3-104
Q4
NOP
; Compare [W4] with 0 (byte mode)
; Post-decrement W4
After
Instruction
W4
8000
Data 8000
0034
SR
0024 (SZ, Z=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 2
CP0
[W5--]
Before
Instruction
W5
2400
Data 23FE
9000
SR
0000
; Compare [W5--] with 0 (word mode)
After
Instruction
W5
23FE
Data 23FE
9000
SR
0010 (N=1)
3
Advanced Information
DS70030A-page 3-105
Instruction
Descriptions
 2001 Microchip Technology Inc.
dsPIC30F Programmer’s Reference Manual
CP1
Compare f with 0xFFFF, Set status flags
Syntax:
{label:}
CP1{.b}
Operands:
f ∈ [0 ... 8191]
Operation:
(f) - 0xFFFF
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
f
0010
1B0f
ffff
ffff
ffff
Compute (f) - 0xFFFF and update the Status Register. The result of the subtraction is not stored.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note:
Words:
1
Cycles:
1
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
Q3
Process
data
CP1.b
RAM100
Before
Instruction
RAM100
44C3
SR
0000
Example 2
CP1
0x1FFE
Before
Instruction
Data 1FFE
0001
SR
0000
DS70030A-page 3-106
Q4
NOP
; Compare RAM100 with 0xFF (byte mode)
After
Instruction
RAM100
44C3
SR
0010 (N=1)
; Compare (0x1FFE) with 0xFFFF (word mode)
After
Instruction
Data 1FFE
0001
SR
0000
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CP1
Compare Ws with 0xFFFF, Set status flags
Syntax:
{label:}
CP1{.b}
Ws
[Ws]
[Ws]++
[Ws]-[Ws++]
[Ws--]
Operands:
Ws ∈ [W0 ... W15]
Operation:
(Ws) - 0xFFFF
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
0000
1B00
0000
0ppp
ssss
Compute (Ws) - 0xFFFF and update the Status Register. The result of the
subtraction is not stored. Register direct or indirect addressing may be used
for Ws.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the Ws source register.
Note:
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
CP1.b
Q3
Process
data
[W4]--
Before
Instruction
W4
8001
Data 8000
9934
SR
0000
 2001 Microchip Technology Inc.
Q4
NOP
; Compare [W4] with 0xFF (byte mode)
; Post-decrement W4
After
Instruction
W4
8000
Data 8000
9934
SR
0010 (N=1)
Advanced Information
DS70030A-page 3-107
Instruction
1
3
Descriptions
Words:
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
dsPIC30F Programmer’s Reference Manual
Example 2
CP1
[W6]++
Before
Instruction
W6
400E
Data 400E
FFFF
SR
0000
DS70030A-page 3-108
; Compare [W6] with 0xFFFF (word mode)
; Post-increment W6
After
Instruction
W6
4010
Data 400E
FFFF
SR
0025 (SZ, Z, C=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
CPB
Compare f with WREG using Borrow, Set status flags
Syntax:
{label:}
CPB{.b}
Operands:
f ∈ [0 ...8191]
Operation:
(f) - (WREG) - (C)
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
f
0011
1B0f
ffff
ffff
ffff
Compute (f) - (WREG) - (C), and update the Status Register. This instruction is equivalent to the SUBBWF instruction, but the result of the subtraction is not stored.
Description:
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1
3
Q Cycle Activity:
CPB.b
Q3
Process
data
RAM400
Before
Instruction
WREG
8823
RAM400
0823
SR
0000
Example 2
CPB
0x1200
Q4
NOP
; Compare RAM400 with WREG using C (byte mode)
After
Instruction
WREG
8823
RAM400
0823
SR
0010 (N=1)
; Compare (0x1200) with WREG using C (word mode)
Before
After
Instruction
Instruction
WREG
2377
WREG
2377
Data 1200
2377
Data 1200
2377
SR
0001 (C=1)
SR
0025 (SZ, Z, C=1)
 2001 Microchip Technology Inc.
Advanced Information
DS70030A-page 3-109
Instruction
Example 1
Q2
Read
operands
Descriptions
Q1
Decode
dsPIC30F Programmer’s Reference Manual
CPB
Compare Wb with lit5 using Borrow, Set status flags
Syntax:
{label:}
CPB{.b}
Wb,
Operands:
Wb ∈ [W0 ... W15]; lit5 ∈ [0 ... 31]
Operation:
(Wb) - lit5 - (C)
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
Description:
1110
0001
#lit5
1www
wB00
011k
kkkk
Compute (Wb) - lit5 - (C), and update the Status Register. This instruction is
equivalent to the SUBBLS instruction, but the result of the subtraction is not
stored. Register direct addressing must be used for Wb.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘k’ bits provide the literal operand, a five bit integer number.
Note:
Words:
1
Cycles:
1
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
CPB.b
Q3
Process
data
W4, #0x12
Before
Instruction
W4
7711
SR
0001 (C=1)
Example 2
CPB.b
W4, #0x12
Before
Instruction
W4
7711
SR
0000
DS70030A-page 3-110
Q4
NOP
; Compare W4 with 0x12 using C (byte mode)
After
Instruction
W4
7711
SR
0010 (N=1)
; Compare W4 with 0x12 using C (byte mode)
After
Instruction
W4
7711
SR
0010 (N=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 3
Example 4
CPB
W12, #0x1F
; Compare W12 with 0x1F using C (word mode)
Before
Instruction
W12
0020
SR
0000
After
Instruction
W12
0020
SR
0025 (SZ, Z, C=1)
CPB
; Compare W12 with 0x1F using C (word mode)
W12, #0x1F
Before
Instruction
W12
0020
SR
0001 (C=1)
After
Instruction
W12
0020
SR
0001 (C=1)
3
Advanced Information
DS70030A-page 3-111
Instruction
Descriptions
 2001 Microchip Technology Inc.
dsPIC30F Programmer’s Reference Manual
CPB
Compare Ws with Wb using Borrow, Set status flags
Syntax:
{label:}
CPB{.b}
Wb,
Ws
[Ws]
[Ws]++
[Ws]-[Ws++]
[Ws--]
Operands:
Wb ∈ [W0 ... W15]; Ws ∈ [W0 ... W15]
Operation:
(Ws) - (Wb) - (C)
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
0001
1www
wB00
0ppp
ssss
Compute (Ws) - (Wb) - (C), and update the Status Register. This instruction
is equivalent to the SUBBR instruction, but the result of the subtraction is
not stored. Register direct addressing must be used for Wb. Register direct
or indirect addressing may be used for Ws.
Description:
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the Ws source register.
Note:
Words:
1
Cycles:
1
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
CPB.b
Q3
Process
data
W0, [W1]++
Before
Instruction
W0
D0A9
W1
6000
Data 6000
ABA9
SR
0000
DS70030A-page 3-112
Q4
NOP
; Compare [W1] with W0 using C (byte mode)
; Post-increment W1
After
Instruction
W0
D0A9
W1
6001
Data 6000
ABA9
SR
0010 (N=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 2
CPB.b
W0, [W1]++
; Compare [W1] with W0 using C (byte mode)
; Post-increment W1
Before
After
Instruction
Instruction
W0
D0A9
W0
D0A9
W1
6000
W1
6001
Data 6000
ABA9
Data 6000
ABA9
SR
0001 (C=1)
SR
0025 (SZ, Z, C=1)
Example 3
CPB
W4, W5
Before
Instruction
W4
3000
W5
4000
SR
0001 (C=1)
; Compare W5 with W4 using C (word mode)
After
Instruction
W4
3000
W5
4000
SR
0001 (C=1)
3
Advanced Information
DS70030A-page 3-113
Instruction
Descriptions
 2001 Microchip Technology Inc.
dsPIC30F Programmer’s Reference Manual
CPFSEQ
Syntax:
Compare f with WREG, Skip if Equal
{label:}
CPFSEQ{.b}
Operands:
f ∈ [0 ... 8191]
Operation:
(f) - (WREG)
Skip if (f) = (WREG)
Status Affected:
None
Encoding:
Description:
1110
0111
f
1B0f
ffff
ffff
ffff
Compare the contents of the file register ‘f’ with the contents of WREG by
performing the subtraction (f) - (WREG), but do not store the result. If (f) =
(WREG) the next instruction (fetched during the current instruction execution)
is discarded and on the next cycle a NOP is executed instead. If (f) ≠ (WREG),
the next instruction is executed as normal.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1 (2 or 3 if skip taken)
Q Cycle Activity:
Q1
Decode
Q2
Read
register ‘f’
If skip (2nd cycle):
Q1
Q2
NOP
NOP
Q3
Process
data
Q4
Q3
Q4
NOP
NOP
NOP
If skip and followed by a two word instruction
(2nd, 3rd cycles):
Q1
Q2
Q3
Q4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DS70030A-page 3-114
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 1
002000 HERE:
002002
002004
002006
002008 BYPASS:
00200A
PC
WREG
Data 100
SR
Example 2
Before
Instruction
00 2000
1001
264F
0000
018000 HERE:
018002
018006
018008
PC
WREG
Data 100
SR
CPFSEQ
CALL
...
...
Before
Instruction
01 8000
3344
3344
0024 (SZ,Z=1)
0x1F00
_FIR
PC
WREG
Data 1F00
SR
Advanced Information
; If (0x100)=WREG (byte mode),
; skip the GOTO
After
Instruction
00 2002
1001
264F
0000
; If (0x1F00)=WREG (word mode),
; skip the subroutine call
After
Instruction
01 8006
3344
3344
0000 (SZ, Z=1)
DS70030A-page 3-115
3
Instruction
 2001 Microchip Technology Inc.
0x100
BYPASS
Descriptions
PC
WREG
Data 1F00
SR
CPFSEQ.b
GOTO
. . .
. . .
. . .
. . .
dsPIC30F Programmer’s Reference Manual
CPFSGT
Syntax:
Signed Compare f with WREG, Skip if Greater Than (f>WREG)
{label:}
CPFSGT{.b}
Operands:
f ∈ [0 ... 8191]
Operation:
(f) - (WREG)
Skip if (f) > (WREG)
Status Affected:
None
Encoding:
Description:
1110
0110
f
0B0f
ffff
ffff
ffff
Compare the contents of the file register ‘f’ with the contents of WREG by
performing the subtraction (f) - (WREG), but do not store the result. If (f) >
(WREG) the next instruction (fetched during the current instruction execution)
is discarded and on the next cycle a NOP is executed instead. Otherwise, the
next instruction is executed as normal.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1 (2 or 3 if skip taken)
Q Cycle Activity:
Q1
Decode
Q2
Read
operands
If skip (2nd cycle):
Q1
Q2
NOP
NOP
Q3
Process
data
Q4
Q3
Q4
NOP
NOP
NOP
If skip and followed by a two word instruction
(2nd, 3rd cycles):
Q1
Q2
Q3
Q4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DS70030A-page 3-116
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 1
002000 HERE:
002002
002006
002008
00200A BYPASS
00200C
PC
WREG
Data 100
SR
Example 2
Before
Instruction
00 2000
00FF
26FE
0011 (N,C=1)
018000 HERE:
018002
018006
018008
PC
WREG
Data 1F00
SR
CPFSGT.b
GOTO
. . .
. . .
. . .
. . .
CPFSGT
CALL
...
...
Before
Instruction
01 8000
2600
3000
0008 (OV=1)
0x100
BYPASS
PC
WREG
Data 100
SR
; If (0x100)>WREG (byte mode),
; skip the GOTO
After
Instruction
00 2002
00FF
26FE
0011 (N,C=1)
0x1F00
; If (0x1F00)>WREG (word mode),
_FIR
; skip the subroutine call
PC
WREG
Data 1F00
SR
After
Instruction
01 8006
2600
3000
0008 (OV=1)
3
Advanced Information
DS70030A-page 3-117
Instruction
Descriptions
 2001 Microchip Technology Inc.
dsPIC30F Programmer’s Reference Manual
CPFSLT
Syntax:
Signed Compare f with WREG, Skip if Less Than (f < WREG)
{label:}
CPFSLT{.b} f
Operands:
f ∈ [0 ... 8191]
Operation:
(f) - (WREG)
Skip if (f) < (WREG)
Status Affected:
None
Encoding:
Description:
1110
0110
1B0f
ffff
ffff
ffff
Compare the contents of the file register ‘f’ with the contents of WREG by
performing the subtraction (f) - (WREG), but do not store the result. If (f) <
(WREG) the next instruction (fetched during the current instruction execution) is discarded and on the next cycle a NOP is executed instead. Otherwise, the next instruction is executed as normal.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1 (2 or 3 if skip taken)
Q Cycle Activity:
Q1
Decode
Q2
Read
operands
If skip (2nd cycle):
Q1
Q2
NOP
NOP
Q3
Process
data
Q4
Q3
Q4
NOP
NOP
NOP
If skip and followed by a two word instruction
(2nd, 3rd cycles):
Q1
Q2
Q3
Q4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DS70030A-page 3-118
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 1
002000 HERE:
002002
002006
002008
00200A BYPASS:
00200C
PC
WREG
Data 100
SR
Example 2
Before
Instruction
00 2000
00FF
26FE
0010 (N=1)
018000 HERE:
018002
018006
018008
PC
WREG
Data 100
SR
; If (0x100)<WREG (byte mode),
; skip the GOTO
After
Instruction
00 2006
00FF
26FE
0010 (N=1)
0x1F00 ; If (0x1F00)<WREG (word mode),
_FIR
; skip the subroutine call
PC
WREG
Data 1F00
SR
Advanced Information
After
Instruction
01 8002
2600
3000
0000
3
DS70030A-page 3-119
Instruction
 2001 Microchip Technology Inc.
Before
Instruction
01 8000
2600
3000
0000
CPFSLT
CALL
. . .
. . .
0x100
BYPASS
Descriptions
PC
WREG
Data 1F00
SR
CPFSLT.b
GOTO
. . .
. . .
. . .
. . .
dsPIC30F Programmer’s Reference Manual
CPFSNE
Syntax:
Signed Compare f with WREG, Skip if not Equal (f ≠ WREG)
{label:}
CPFSNE{.b}
Operands:
f ∈ [0 ...8191]
Operation:
(f) - (WREG)
Skip if (f) ≠ (WREG)
Status Affected:
None
Encoding:
Description:
1110
0111
f
0B0f
ffff
ffff
ffff
Compare the contents of the file register ‘f’ with the contents of WREG by
performing the subtraction (f) - (WREG), but do not store the result. If (f) ≠
(WREG) the next instruction (fetched during the current instruction execution)
is discarded and on the next cycle a NOP is executed instead. Otherwise, the
next instruction is executed as normal.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1 (2 or 3 if skip taken)
Q Cycle Activity:
Q1
Decode
Q2
Read
operands
If skip (2nd cycle):
Q1
Q2
NOP
NOP
Q3
Process
data
Q4
Q3
Q4
NOP
NOP
NOP
If skip and followed by a two word instruction
(2nd, 3rd cycles):
Q1
Q2
Q3
Q4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DS70030A-page 3-120
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 1
002000 HERE:
002002
002006
002008
00200A BYPASS:
00200C
PC
WREG
Data 100
SR
Example 2
Before
Instruction
00 2000
00FF
26FE
0001 (C=1)
018000 HERE:
018002
018006
018008
PC
WREG
Data 100
SR
CPFSNE 0x1F00
CALL
_FIR
...
...
; If (0x1F00)!=WREG (word mode),
; skip the subroutine call
PC
WREG
Data 1F00
SR
Advanced Information
After
Instruction
00 2006
00FF
26FE
0001 (C=1)
After
Instruction
01 8002
3000
3000
0000
3
DS70030A-page 3-121
Instruction
 2001 Microchip Technology Inc.
Before
Instruction
01 8000
3000
3000
0000
; If (0x100)!=WREG (byte mode),
; skip the GOTO
Descriptions
PC
WREG
Data 1F00
SR
CPFSNE.b 0x100
GOTO
BYPASS
. . .
. . .
. . .
. . .
dsPIC30F Programmer’s Reference Manual
DAW
Syntax:
Decimal Adjust Wn
{label:}
DAW.b
Wn
Operands:
Wn ∈ [W0 ... W15]
Operation:
If [Wn<3:0> >9] or [DC = 1] then
(Wn<3:0>) + 6 → Wn<3:0>
else
(Wn<3:0>) → Wn<3:0>;
If [Wn<7:4> >9] or [C = 1] then
(Wn<7:4>) + 6 → Wn<7:4>
else
(Wn<7:4>) → Wn<7:4>;
Status Affected:
C
Encoding:
Description:
1111
1101
0100
0000
0000
ssss
Adjust the least-significant byte in Wn to produce a binary coded decimal
(BCD) result. The most-significant byte of Wn is not changed, and the Carry
flag bit is used to indicate any decimal rollover. Register direct addressing
must be used for Wn.
The ‘s’ bits select the address of the source / destination register.
Note 1: This instruction is used to correct the data format after two
packed BCD bytes have been added.
Note 2: This instruction operates in byte mode only and the .b extension
must be included with the opcode.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
DAW.b
Q3
Process
data
W0
Before
Instruction
W0
771A
SR
0002 (DC=1)
DS70030A-page 3-122
Q4
Write to
destination
; Decimal adjust W0 (byte mode)
After
Instruction
W0
7726
SR
0002 (DC=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
Example 2
DAW.b
W0
Before
Instruction
W0
7788
SR
0002 (DC=1)
Example 3
DAW
W13
Before
Instruction
W13
2710
SR
0000
Example 4
DAW
W13
Before
Instruction
W13
3383
SR
0002 (DC=1)
; Decimal adjust W0 (byte mode)
After
Instruction
W0
7736
SR
0003 (DC,C=1)
; Decimal adjust W13 (word mode)
After
Instruction
W13
0000
SR
0001 (C=1)
; Decimal adjust W13 (word mode)
After
Instruction
W13
3187
SR
0003 (DC,C=1)
3
Advanced Information
DS70030A-page 3-123
Instruction
Descriptions
 2001 Microchip Technology Inc.
dsPIC30F Programmer’s Reference Manual
DEC
Decrement f
Syntax:
{label:}
DEC{.b}
f
{,WREG}
Operands:
f ∈ [0 ... 8191]
Operation:
(f) - 1 → destination designated by D
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
1101
0BDf
ffff
ffff
ffff
Subtract one from the contents of the file register and place the result in the
destination register. The optional WREG operand determines the destination
register. If WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘D’ bit selects the destination (0 for WREG, 1 for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
DEC.b
Q3
Process
data
0x200
Before
Instruction
Data 200
80FF
SR
0000
Example 2
DEC
; Decrement (0x200) (byte mode)
After
Instruction
Data 200
80FE
SR
0010 (N=1)
RAM400, WREG
Before
Instruction
WREG
1211
RAM400
0823
SR
0000
DS70030A-page 3-124
Q4
Write to
destination
; Decrement RAM400 and store to WREG
; (word mode)
After
Instruction
WREG
0822
RAM400
0823
SR
0000
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
DEC
Decrement Ws
Syntax:
{label:}
DEC{.b}
Ws,
Wd
[Ws],
[Wd]
[Ws]++,
[Wd]++
[Ws]--,
[Wd]--
[Ws++],
[Wd++]
[Ws--],
[Wd--]
Operands:
Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:
(Ws) - 1 → Wd
Status Affected:
SZ, N, OV, Z, DC, Z
Encoding:
1110
Description:
1001
0Bqq
qddd
dppp
ssss
Subtract one from the contents of the source register Ws and place the
result in the destination register Wd. Either register direct or indirect
addressing may be used by Ws and Wd.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘q’ bits select the destination address mode.
The ‘d’ bits select the address of the destination register.
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the source register.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
DEC.b
Q3
Process
data
[W7]++, [W8]++
Before
Instruction
W7
2301
W8
6000
Data 2300
5607
Data 6000
ABCD
SR
0000
 2001 Microchip Technology Inc.
Q4
Write to
destination
; DEC [W7] and store to [W8] (byte mode)
; Post-increment W7, W8
After
Instruction
W7
2302
W8
6001
Data 2300
5607
Data 6000
AB55
SR
0000
Advanced Information
DS70030A-page 3-125
Instruction
Words:
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Descriptions
Note:
3
dsPIC30F Programmer’s Reference Manual
Example 2
DEC
W5, [W6]++
Before
Instruction
W5
D004
W6
6000
Data 6000
ABA9
SR
0000
DS70030A-page 3-126
; Decrement W5 and store to [W6] (word mode)
; Post-increment W6
After
Instruction
W5
D004
W6
6002
Data 6000
D003
SR
0010 (N=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
DEC2
Syntax:
Decrement Ws by 2
{label:}
DEC2{.b}
Ws,
Wd
[Ws],
[Wd]
[Ws]++,
[Wd]++
[Ws]--,
[Wd]--
[Ws++],
[Wd++]
[Ws--],
[Wd--]
Operands:
Ws ∈ [W0 ... W15]; Wd ∈ [W0 ... W15]
Operation:
(Ws) - 2 → Wd
Status Affected:
SZ, N, OV, Z, DC, C
Encoding:
1110
Description:
1001
1Bqq
qddd
dppp
ssss
Subtract two from the contents of the source register Ws and place the
result in the destination register Wd. Either register direct or indirect
addressing may be used by Ws and Wd.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘q’ bits select the destination address mode.
The ‘d’ bits select the address of the destination register.
The ‘p’ bits select the source address mode.
The ‘s’ bits select the address of the source register.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
DEC2.b
Q3
Process
data
[W7]--, [W8]-- ; DEC [W7] by 2, store to [W8] (byte mode)
; Post-decrement W7, W8
Before
Instruction
W7
2301
W8
6000
Data 2300
0107
Data 6000
ABCD
SR
0000
 2001 Microchip Technology Inc.
Q4
Write to
destination
After
Instruction
W7
2300
W8
5FFF
Data 2300
0107
Data 6000
ABFF
SR
0010 (N=1)
Advanced Information
DS70030A-page 3-127
Instruction
Words:
The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
Descriptions
Note:
3
dsPIC30F Programmer’s Reference Manual
Example 2
DEC2
W5, [W6]++
Before
Instruction
W5
D004
W6
6000
Data 6000
ABA9
SR
0000
DS70030A-page 3-128
; DEC W5 by 2, store to [W6] (word mode)
; Post-increment W6
After
Instruction
W5
D004
W6
6002
Data 6000
D002
SR
0010 (N=1)
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
DECSNZ
Decrement f, Skip if Not Zero
Syntax:
{label:}
DECSNZ{.b}
f
{,WREG}
Operands:
Operation:
Status Affected:
Encoding:
Description:
f ∈ [0 ... 8191]
(f) - 1 → destination designated by D; skip if result ≠ 0
None
1110
0101
1BDf
ffff
ffff
ffff
Subtract one from the contents of the file register and place the result in the
destination register. The optional WREG operand determines the destination
register. If WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
If the result of the subtraction is non-zero, the next instruction (fetched during
the current instruction execution) is discarded and on the next cycle a NOP is
executed instead. Otherwise, the next instruction is executed as normal
The ‘B’ bit selects byte or word operation (0 for word,1 for byte).
The ‘D’ bit selects the destination (0 for WREG, 1 for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation rather
than a word operation. You may use a .w extension to denote a
word operation, but it is not required.
3
Note 2: WREG is set by the WD bits, CORCON<11:8>.
1
1 (2 or 3 if skip taken)
Q2
Read
operands
If skip (2nd cycle):
Q1
Q2
NOP
NOP
Q3
Process
data
Q4
Write to
destination
Q3
Q4
NOP
NOP
If skip and followed by a two word instruction
(2nd, 3rd cycles):
Q1
Q2
Q3
Q4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
 2001 Microchip Technology Inc.
Advanced Information
DS70030A-page 3-129
Instruction
Descriptions
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
dsPIC30F Programmer’s Reference Manual
Example 1
002000 HERE:
002002
GOTO
002006
002008
00200A BYPASS:
00200C
DECSNZ.b
GOTO
.
.
.
.
.
.
.
.
Before
Instruction
PC
00 2000
Data 100
2627
SR
0000
Example 2
018000 HERE: DECSNZ
018002
CALL
018006
. . .
018008
. . .
PC
WREG
Data 1F0
SR
DS70030A-page 3-130
Before
Instruction
01 8000
2600
0001
0000
0x100
BYPASS
; Dec (0x100) (byte mode)
; If result!=0, skip the
.
.
.
.
After
Instruction
PC
00 2006
Data 100
2626
SR
0000
0x1F0, WREG ; Dec (0x1F0) (word mode)
_FIR
; If result!=0, skip the CALL
PC
WREG
Data 1F0
SR
Advanced Information
After
Instruction
01 8002
0000
0001
0000
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
DECSZ
Syntax:
Decrement f, Skip if Zero
{label:}
DECSZ{.b}
f
{,WREG}
Operands:
f ∈ [0 ... 8191]
Operation:
(f) - 1 → destination designated by D; skip if result = 0
Status Affected:
None
Encoding:
Description:
1110
0101
0BDf
ffff
ffff
ffff
Subtract one from the contents of the file register and place the result in the
destination register. The optional WREG operand determines the destination
register. If WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
If the result of the subtraction is zero, the next instruction (fetched during the
current instruction execution) is discarded and on the next cycle a NOP is
executed instead. Otherwise, the next instruction is executed as normal.
The ‘B’ bit selects byte or word operation (0 for word, 1 for byte).
The ‘D’ bit selects the destination (0 for WREG, 1 for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .b in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
3
Note 2: WREG is set by the WD bits, CORCON<11:8>.
Cycles:
1 (2 or 3 if skip taken)
Q Cycle Activity:
Q1
Decode
Q2
Read
operands
If skip (2nd cycle):
Q1
Q2
NOP
NOP
Q3
Process
data
Q4
Write to
destination
Q3
Q4
NOP
NOP
If skip and followed by a two word instruction
(2nd, 3rd cycles):
Q1
Q2
Q3
Q4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
 2001 Microchip Technology Inc.
Advanced Information
DS70030A-page 3-131
Instruction
1
Descriptions
Words:
dsPIC30F Programmer’s Reference Manual
Example 1
002000 HERE:
002002
002006
002008
00200A BYPASS:
00200C
DECSZ.b
GOTO
. . .
. . .
. . .
. . .
Before
Instruction
PC
00 2000
Data 100
2627
SR
0000
Example 2
018000 HERE: DECSZ
018002
CALL
018006
. . .
018008
. . .
PC
WREG
Data 1F0
SR
DS70030A-page 3-132
Before
Instruction
01 8000
2600
0001
0000
0x100
BYPASS
; Dec (0x100) (byte mode)
; If result=0, skip the GOTO
After
Instruction
PC
00 2002
Data 100
2626
SR
0000
0x1F0, WREG
_FIR
PC
WREG
Data 1F0
SR
Advanced Information
; Dec (0x1F0) (word mode)
; If result=0, skip the CALL
After
Instruction
01 8006
0000
0001
0000
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
DISI
Syntax:
Disable Interrupts
{label:}
DISI
#lit14
Operands:
lit14 ∈ [0 ... 16383]
Operation:
Disable interrupts for lit14 cycles
Status Affected:
None
Encoding:
Description:
1111
1100
00kk
kkkk
kkkk
kkkk
Disable ALL interrupts for lit14 instruction cycles after the instruction executes. Even Priority 7 interrupts are disabled and prevented from running.
However, traps are not prevented from running. This instruction can be
used before executing time-critical code to limit the effects of interrupts.
Note:
Words:
1
Cycles:
1
This instruction does not modify the GIE bit, INTCON<7>.
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
Q3
Process
data
DISI
#100
; Disable interrupts for 100 cycles
; now execute time-critical code
Before
Instruction
PC
00 2000
SR
0000
 2001 Microchip Technology Inc.
Advanced Information
After
Instruction
PC
00 2002
SR
0000
DS70030A-page 3-133
Instruction
. . .
3
Descriptions
002000 HERE:
002002
002004
Q4
Write to
destination
dsPIC30F Programmer’s Reference Manual
DIV
Syntax:
Divide TBD
{label:}
Operands:
TBD
Operation:
TBD
Status Affected:
TBD
Encoding:
Description:
1101
DIV
TBD
100x
xxxx
xxxx
xxxx
xxxx
TBD
Note:
Words:
1
Cycles:
TBD
Word operation is assumed.
Q Cycle Activity:
Q1
Decode
DS70030A-page 3-134
Q2
Read
operands
Q3
Process
data
Q4
TBD
Advanced Information
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
DO
Initialize Hardware Loop Literal
Syntax:
{label:}
Operands:
Slit16 ∈ [-32768 ... +32767];
lit14 ∈ [0 ... 16383]
Operation:
Push Shadows
(lit14) → DOCOUNT (Loop Count Register)
(PC)+4 → PC
(PC) → DOSTART (Loop Start Register)
(PC) + (2*Slit16) → DOEND (Loop End Register)
Enable Code Looping
Status Affected:
DA
Encoding:
Description:
DO
Slit16,
#lit14
0000
1000
00kk
kkkk
kkkk
kkkk
0000
0000
nnnn
nnnn
nnnn
nnnn
Initiate a no-overhead hardware DO loop which is executed ‘lit14’ times.
The DO loop begins at the address following the DO instruction (PC+4), and
ends at the address 2*Slit16 instruction words away. The 14-bit count value
(lit14) supports a maximum loop count value of 16383, and the 16-bit offset
value (Slit16) supports offsets of 32K instruction words in both directions.
Special Features, Restrictions:
The following features and restrictions apply to the DO instruction.
1. Using a loop count of 0 is invalid.
2. Using an offset of -1 is invalid.
3. Using an offset of 0 will generate a loop size of 1 word. This is like
a REPEAT instruction, where the instruction is fetched every iteration.
4. The very last instruction of the DO loop cannot be:
a. an instruction which changes program control flow (with the
exception of CALLW).
b. a DO, DOW or REPEAT instruction.
c. the instruction within a REPEAT loop.
d. a 2-word instruction.
Note:
The DO instruction is fully interruptible and supports 1 level of nesting.
Words:
2
Cycles:
2 + n*(# of cycles required to execute loop)
 2001 Microchip Technology Inc.
Advanced Information
DS70030A-page 3-135
Instruction
The ‘k’ bits specify the loop count.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+4), which is the last instruction executed in the loop.
3
Descriptions
When this instruction executes, DOCOUNT, DOSTART and DOEND are
first pushed into their respective shadow registers, and then updated with
the new DO loop parameters specified by the instruction. After the DO loop
completes execution, the pushed DOCOUNT, DOSTART and DOEND registers are restored.
dsPIC30F Programmer’s Reference Manual
DO
Initialize Hardware Loop Literal
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
002000 LOOP6:
002004
002006
002008
00200A END6:
00200C
PC
DOCOUNT
DOSTART
DOEND
SR
Example 2
Q4
Write to
destination
DO
END6, #5
; Initiate DO loop (5 reps)
ADD
W1, W2, W3 ; First instruction in loop
. . .
. . .
SUB
W2, W3, W4 ; Last instruction in loop
. . .
Before
Instruction
00 2000
0000
FF FFFF
FF FFFF
0001 (C=1)
PC
DOCOUNT
DOSTART
DOEND
SR
After
Instruction
00 2004
0005
00 2004
00 200A
0081 (DA, C=1)
01C000 LOOP12: DO
END12, #0x160 ; Initiate DO loop (352 reps)
01C004
DEC W1, W2
; First instruction in loop
01C006
. . .
01C008
. . .
01C00A
. . .
01C00C
. . .
01C00E
. . .
01C010
CALL _FIR88
; Call the FIR88 subroutine
01C014 END12: NOP
; Last instruction in loop
; (Required NOP filler)
PC
DOCOUNT
DOSTART
DOEND
SR
DS70030A-page 3-136
Q3
Process
data
Before
Instruction
01 C000
0000
FF FFFF
FF FFFF
0010 (N=1)
PC
DOCOUNT
DOSTART
DOEND
SR
Advanced Information
After
Instruction
01 C004
0160
01 C004
01 C014
0090 (DA, N=1)
 2001 Microchip Technology Inc.
Section 3. Instruction Descriptions
DO
Initialize Hardware Loop Wn
Syntax:
{label:}
Operands:
Slit16 ∈ [-32768 ... +32767];
Wn ∈ [W0 ... W15]
Operation:
Push Shadows
(Wn) → DOCOUNT (Loop Count Register)
(PC)+4 → PC
(PC) → DOSTART (Loop Start Register)
(PC) + (2*Slit16) → DOEND (Loop End Register)
Enable Code Looping
Status Affected:
None
Encoding:
Description:
DO
Slit16,
Wn
0000
1000
1000
0000
0000
ssss
0000
0000
nnnn
nnnn
nnnn
nnnn
Initiate a no-overhead hardware DO loop which is executed Wn times. The
DO loop begins at the address following the DO instruction (PC+4), and
ends at the address 2*Slit16 instruction words away. The lower 14 bits of
Wn support a maximum count value of 16383, and the 16-bit offset value
(Slit16) supports offsets of 32K instruction words in both directions.
Special Features, Restrictions:
The following features and restrictions apply to the DO instruction.
1. Using a loop count of 0 is invalid.
2. Using an offset of -1 is invalid.
3. Using an offset of 0 will generate a loop size of 1 word. This is like
a REPEAT instruction, where the instruction is fetched every iteration.
4. The very last instruction of the DO loop cannot be:
a. an instruction which changes program control flow (with the
exception of CALLW).
b. a DO, DOW or REPEAT instruction.
c. the instruction within a REPEAT loop.
d. a 2-word instruction.
Note:
The DO instruction is fully interruptible and supports 1 level of nesting.
Words:
2
Cycles:
2 + n*(# of cycles required to execute loop)
 2001 Microchip Technology Inc.
Advanced Information
DS70030A-page 3-137
Instruction
The ‘s’ bits specify the register Wn that contains the loop count (only the 14
LSBs of (Wn) are considered).
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+4), which is the last instruction executed in the loop.
3
Descriptions
When this instruction executes, DOCOUNT, DOSTART and DOEND are
first pushed into their respective shadow registers, and then updated with
the new DO loop parameters specified by the instruction. After the DO loop
completes execution, the pushed DOCOUNT, DOSTART and DOEND registers are restored.
dsPIC30F Programmer’s Reference Manual
DO
Initialize Hardware Loop Wn
Q Cycle Activity:
Q1
Decode
Example 1
Q2
Read
operands
002000 LOOP6:
002004
002006
002008
00200A
00200C
00200E
002010 END6:
PC
W0
DOCOUNT
DOSTART
DOEND
SR
Example 2
Q4
Write to
destination
DO
ADD
. . .
. . .
. . .
REPEAT
SUB
NOP
Before
Instruction
00 2000
0012
0000
FF FFFF
FF FFFF
0000
002000 LOOPA:
002004
002006
002008
00200A
002010 ENDA:
PC
W7
DOCOUNT
DOSTART
DOEND
SR
DS70030A-page 3-138
Q3
Process
data
Before
Instruction
00 2000
E00F
0000
FF FFFF
FF FFFF
0000
END6, W0
; Initiate DO loop (W0 reps)
W1, W2, W3 ; First instruction in loop
6
W2, W3, W4
; Last instruction in loop
; (Required NOP filler)
PC
W0
DOCOUNT
DOSTART
DOEND
SR
DO
DISI
. . .
. . .
. . .
MOV
ENDA, W7
#200
After
Instruction
00 2004
0012
0012
00 2004
00 2010
0080 (DA=1)
; Initiate DO loop (W7 reps)
; First instruction in loop
W1, [W2]++ ; Last instruction in loop
PC
W7
DOCOUNT
DOSTART
DOEND
SR
Advanced Information
After
Instruction
00 2004
E00F
200F
00 200
00 2010
0080 (DA=1)
 2001 Microchip Technology Inc.