ISL43L710, ISL43L711, ISL43L712 ® Data Sheet May 29, 2008 Ultra Low ON-Resistance, Single Supply, Differential SPST Analog Switches The Intersil ISL43L710, ISL43L711, ISL43L712 devices are low ON-resistance, low voltage, bidirectional, precision, differential single-pole/single-throw (SPST) analog switches designed to operate from a single +1.65V to +3.6V supply. Targeted applications include battery powered equipment that benefit from low RON (0.16Ω), low power consumption (0.12μW) and fast switching speeds (tON = 13ns, tOFF = 13ns). Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to switch in additional functionality while reducing ASIC design risk. The ISL43L71X are offered in small form factor packages, alleviating board space limitations. The ISL43L710, ISL43L711, ISL43L712 are differential single-pole/single-throw (SPST) devices. The ISL43L710 has two normally open (NO) switches; the ISL43L711 has two normally closed (NC) switches; the ISL43L712 has one normally open (NO) and one normally closed (NC) switch and can be used as an SPDT. The ISL43L712 is equipped with an inhibit pin to simultaneously open all signal paths. FN6092.3 Features • Pb-Free Available (RoHS Compliant) (See Ordering info) • Low ON Resistance (RON) - V+ = 3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.16Ω - V+ = 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26Ω • RON Matching Between Channels. . . . . . . . . . . . . . . 0.005Ω • RON Flatness Over Signal Range . . . . . . . . . . . . . . . 0.008Ω • Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.12μW • Fast Switching Action (V+ = 3.0V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns • ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV • 1.8V Logic Compatible (+3V Supply) • Available in 8 Ld TDFN and 8 Ld MSOP Packages Applications • Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Portable Test and Measurement • Medical Equipment • Audio and Video Switching Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANCE ISL43L710 ISL43L711 ISL43L712 NUMBER OF SWITCHES 2 2 2 SW 1/SW 2 NO/NO NC/NC NO/NC 1.8V RON 0.26Ω 0.26Ω 0.26Ω 1.8V tON/tOFF 30ns/25ns 30ns/25ns 3V RON 0.16Ω 3V tON/tOFF 13ns/13ns Truth Table ISL43L710 ISL43L711 LOGIC SW 1, 2 SW 1, 2 30ns/25ns 0 OFF ON 0.16Ω 0.16Ω 1 ON OFF 13ns/13ns 13ns/13ns ISL43L712 INH LOGIC SW 1 SW 2 1 X OFF OFF Related Literature 0 0 OFF ON Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”. 0 1 ON OFF PACKAGES 8 Ld 3x3 thin DFN, 8 Ld MSOP NOTE: 1. Logic “0” ≤ 0.5V. Logic “1” ≥ 1.4V with a 3V Supply. Application Note AN557 “Recommended Test Procedures for Analog Switches”. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL43L710, ISL43L711, ISL43L712 Pinouts (Note 2) ISL43L711 (8 LD MSOP, TDFN) TOP VIEW ISL43L710 (8 LD MSOP, TDFN) TOP VIEW V+ 8 COM1 1 NO1 2 IN 7 V+ 6 COM2 3 IN 5 GND NO2 4 8 COM1 1 NC1 2 N.C. 7 N.C. 6 COM2 3 NC2 4 5 GND ISL43L712 (8 LD MSOP, TDFN) TOP VIEW V+ 1 NO1 2 IN 3 NC2 4 8 COM1 7 INH 6 COM2 5 GND NOTE: 2. Switches Shown for Logic “0” Input. Ordering Information PART NUMBER (Note 3) PART MARKING TEMP. RANGE (°C) Pin Descriptions PIN PACKAGE PKG. DWG. # V+ FUNCTION System Power Supply Input (+1.65V to +3.6V) GND Ground Connection IN Digital Control Input ISL43L710IU L710 -40 to +85 8 Ld MSOP M8.118 ISL43L710IUZ (Note 4) L710Z -40 to +85 8 Ld MSOP (Pb-free) M8.118 ISL43L710IR L71 -40 to +85 8 Ld 3x3 TDFN L8.3x3A NO Analog Switch Normally Open Pin ISL43L711IU L711 -40 to +85 8 Ld MSOP NC Analog Switch Normally Closed Pin ISL43L711IR L71 -40 to +85 8 Ld 3x3 TDFN L8.3x3A INH Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. ISL43L712IU L712 -40 to +85 8 Ld MSOP N.C. No Connect ISL43L712IR L72 -40 to +85 8 Ld 3x3 TDFN L8.3x3A ISL43L712IUZ (Note 4) L712Z -40 to +85 8 Ld MSOP (Pb-free) ISL43L712IRZ (Note 4) L72Z -40 to +85 8 Ld 3x3 TDFN L8.3x3A (Pb-free) COM M8.118 M8.118 Analog Switch Common Pin M8.118 NOTES: 3. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages IN (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) NO, NC (Note 5) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 300mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . 500mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>8kV Thermal Resistance (Typical, Note 6) θJA (°C/W) 8 Ld 3x3 thin DFN Package . . . . . . . . . . . . . . . . . . . 110 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 190 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C (Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 5. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 7), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) MIN (Notes 8, 9) TYP MAX (Notes 8, 9) UNITS Full 0 - V+ V 25 - 0.17 0.25 Ω Full - - 0.3 Ω 25 - 0.005 0.02 Ω Full - - 0.04 Ω 25 - 0.008 0.06 Ω Full - - 0.07 Ω 25 -3 - 3 nA Full -60 - 60 nA 25 -3 - 3 nA Full -80 - 80 nA 25 - 15 25 ns Full - - 30 ns 25 - 15 25 ns Full - - 30 ns ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 4) RON Matching Between Channels, ΔRON V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at Max RON, (Note 11) RON Flatness, RFlat(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 12) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.3V, VCOM = 0.3, 3V, VNO or VNC = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF, VIN = 0 to 2.7V, (See Figure 1, Note 10) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF, VIN = 0 to 2.7V, (See Figure 1, Note 10) Turn-OFF Time, tOFF Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -125 - pC OFF Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1 VRMS, (See Figure 3) 25 - 62 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1 VRMS, (See Figure 5) 25 - -94 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 182 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 182 - pF COM ON Capacitance, CCOM(ON) 25 - 290 - pF 3 f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 7), Unless Otherwise Specified (Continued) TEMP (°C) MIN (Notes 8, 9) TYP Full 1.65 - 3.6 V 25 - - 30 nA Full - - 750 nA Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.4 - - V Full -0.5 - 0.5 μA PARAMETER TEST CONDITIONS MAX (Notes 8, 9) UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 1.65V to 3.6V, VIN = 0V or V+, all channels on or off DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ (Note 10) NOTES: 7. VIN = input voltage to perform proper function. 8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Limits established by characterization and are not production tested. 11. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value. 12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. Electrical Specifications - 1.8V Supply PARAMETER Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 7), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) MIN (Notes 8, 9) TYP MAX (Notes 8, 9) UNITS Full 0 - V+ V 25 - 0.26 0.35 Ω Full - - 0.4 Ω 25 - 0.005 - Ω Full - 0.005 - Ω 25 - 0.074 - Ω Full - 0.082 - Ω 25 -3 - 3 nA Full -60 - 60 nA 25 -3 - 3 nA Full -80 - 80 nA 25 - 30 40 ns Full - - 45 ns 25 - 25 35 ns Full - - 40 ns ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 4, Note 10) RON Matching Between Channels, ΔRON V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at Max RON, (Note 11) RON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 12) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 2.0V, VCOM = 0.3V, 1.8V, VNO or VNC = 1.8V, 0.3V COM ON Leakage Current, ICOM(ON) V+ = 2.0V, VCOM = 0.3V, 1.8V, or VNO or VNC = 0.3V, 1.8V DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF, VIN = 0 to 1.65V, (See Figure 1, Note 10) Turn-OFF Time, tOFF V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF, VIN = 0 to 1.65V, (See Figure 1, Note 10) Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -80 - pC OFF Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1 VRMS, (See Figure 3 and Figure 5) 25 - 62 - dB 25 - -94 - dB Crosstalk (Channel-to-Channel) 4 FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 7), Unless Otherwise Specified (Continued) TEMP (°C) MIN (Notes 8, 9) TYP NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 182 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 182 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 290 - pF 25 - - 30 nA Full - - 750 nA Input Voltage Low, VINL Full - - 0.4 V Input Voltage High, VINH Full 1.0 - - V Full -0.5 - 0.5 μA PARAMETER TEST CONDITIONS MAX (Notes 8, 9) UNITS POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 1.65V to 3.6V, VIN = 0V or V+, all channels on or off DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ (Note 10) Test Circuits and Waveforms V+ LOGIC INPUT V+ tr < 5ns tf < 5ns 50% C 0V tOFF SWITCH V INPUT NO SWITCH INPUT COM IN VOUT 90% SWITCH OUTPUT VOUT NO or NC 90% LOGIC INPUT CL 35pF RL 50Ω GND 0V tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VOUT RG ΔVOUT V+ LOGIC INPUT ON ON VG NO or NC GND C VOUT COM IN OFF CL 0V LOGIC INPUT Q = ΔVOUT x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION 5 FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Test Circuits and Waveforms (Continued) V+ V+ C C RON = V1/100mA SIGNAL GENERATOR NO or NC NO or NC VNX INX 1mA 0V or V+ 0V or V+ COM COM ANALYZER IN V1 GND GND RL FIGURE 3. OFF ISOLATION TEST CIRCUIT FIGURE 4. RON TEST CIRCUIT V+ C V+ C SIGNAL GENERATOR NO1 or NC1 COM1 50Ω NO or NC IN1 0V or V+ COM2 ANALYZER INX IN2 0V or V+ NO2 or NC2 GND 0V or V+ IMPEDANCE ANALYZER COM NC GND RL FIGURE 5. CROSSTALK TEST CIRCUIT FIGURE 6. CAPACITANCE TEST CIRCUIT Detailed Description The ISL43L71x family of devices are bidirectional, single pole/single throw (SPST) analog switches that offer precise switching capability from a single 1.65V to 3.6V supply with low on-resistance (0.16Ω) and high speed operation (tON = 13ns, tOFF = 13ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65V), low power consumption (2.7μW max), low leakage currents (80nA max), and the tiny TDFN and MSOP packaging. The ultra low on-resistance and RON flatness provide very low insertion loss and distortion to application that require signal reproduction. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (See Figure 7). To prevent forward biasing these diodes, V+ must 6 be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (See Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (See Figure 7). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 3.6V (See Figure 14). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM GND OPTIONAL PROTECTION DIODE FIGURE 7. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL43L71x construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L71x 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. 7 Logic-Level Thresholds High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 20MHz with a -3dB bandwidth of 175MHz (See Figure 15). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 62dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Typical Performance Curves TA = +25°C, Unless Otherwise Specified 0.26 0.19 V+ = 3V ICOM = 100mA ICOM = 100mA 0.18 0.24 V+ = 1.8V 0.17 0.22 +85°C RON (Ω) RON (Ω) 0.16 0.2 0.18 0.15 +25°C 0.14 0.16 V+ = 2.7V 0.13 V+ = 3V 0.14 0.12 -40°C V+ = 3.6V 0.11 0.12 0 1 2 3 0 4 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0 VCOM (V) FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE 50 0.30 V+ = 1.8V ICOM = 100mA 0 V+ = 3V +85°C 0.25 Q (pC) RON (Ω) -50 0.20 V+ = 1.8V -150 +25°C -40°C -100 0.15 -200 -250 0.10 0 0.5 1.0 1.5 0 2.0 0.5 1.0 1.5 2.0 2.5 3.0 VCOM (V) VCOM (V) FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE 50 80 70 40 60 +85°C 40 +85°C tOFF (ns) tON (ns) 50 +25°C 30 20 30 -40°C +25°C 20 -40°C 10 10 0 1.0 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 FIGURE 12. TURN-ON TIME vs SUPPLY VOLTAGE 8 4.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 V+ (V) FIGURE 13. TURN-OFF TIME vs SUPPLY VOLTAGE FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) NORMALIZED GAIN (dB) 1.8 1.6 V+ = 3V 0 GAIN -20 1.2 VINH 1.0 PHASE 0 20 VINL 40 0.8 60 0.6 80 0.4 0.2 1.0 RL = 50Ω VIN = 0.2VP-P to 2VP-P 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1 10 V+ (V) FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE -10 100 600 FIGURE 15. FREQUENCY RESPONSE 10 V+ = 3V -20 20 Die Characteristics -30 30 SUBSTRATE POTENTIAL (POWERED UP): -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 OFF ISOLATION (dB) CROSSTALK (dB) 100 FREQUENCY (MHz) PHASE (°) VINH AND VINL (V) 1.4 GND TRANSISTOR COUNT: 114 PROCESS: Submicron CMOS CROSSTALK -90 90 -100 100 -110 1k 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 16. CROSSTALK AND OFF ISOLATION 9 FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Thin Dual Flat No-Lead Plastic Package (TDFN) L8.3x3A 2X 0.15 C A A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.15 C B E SYMBOL MIN A 0.70 A1 - A3 6 INDEX AREA b TOP VIEW B 0.10 C // C SEATING PLANE SIDE VIEW D2 (DATUM B) 6 INDEX AREA 0.08 C A3 7 - 0.30 0.35 5, 8 2.40 7, 8, 9 1.60 7, 8, 9 - 2.30 - 1.50 - 0.65 BSC - k 0.25 - - - L 0.20 0.30 0.40 8 N 8 Nd 4 2 3 Rev. 3 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. NX k 4. All dimensions are in millimeters. Angles are in degrees. (DATUM A) E2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2/2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 NX b e 8 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 5 (Nd-1)Xe REF. 0.10 M C A B BOTTOM VIEW 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-WEEC-2 except for the “L” min dimension. CL NX (b) - 8 D2/2 1 0.80 0.05 3.00 BSC 1.40 e A 0.02 NOTES 3.00 BSC 2.20 E E2 0.75 MAX 0.20 REF 0.25 D D2 NOMINAL (A1) L1 5 10 L e SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE 10 FN6092.3 May 29, 2008 ISL43L710, ISL43L711, ISL43L712 Mini Small Outline Plastic Packages (MSOP) M8.118 (JEDEC MO-187AA) N 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 0.20 (0.008) 1 2 A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X θ A2 A1 b -H- 0.10 (0.004) L SEATING PLANE C MIN MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC 0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D - 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N -A- 0.65 BSC E L1 e D SYMBOL e L1 MILLIMETERS 0.95 REF 8 R 0.003 R1 0 α - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o -B- Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6092.3 May 29, 2008