OKDx-T/50-W12-C www.murata-ps.com 50A Digital PoL DC-DC Converter Series Typical units FEATURES Small package: SMD/TH: 30.85 x 20.0 x 8.2 mm (1.215 x 0.787 x 0.323 in); SIP: 33.0 x 7.6 x 18.1 mm (1.30 x 0.30 x 0.713 in) PRODUCT OVERVIEW Synchonization & phase spreading The OKDx-T/50-W12 series are high efficiency, digital point-of-Load (PoL) DC-DC power converters capable of delivering 50A/165W. Available in three different package formats, through-hole, single-in-line, and surface mount, these converters have a typical efficiency of 97.2%. PMBus™ compatibility allows monitoring and configuration of critical system-level performance require- ments. Apart from standard PoL performance and safety features like OVP, OCP, OTP, and UVLO, these digital converters have advanced features: digital current sharing (full power, no derating), non-linear transient response, optimized dead time control, synchronization, and phase spreading. These converters are ideal for use in telecommunications, networking, and distributed power applications. Current sharing, voltage tracking & voltage margining Power Management via PMBus™ Applications Voltage setting via pin-strap or PMBus™ Configurable soft-start/stop Distributed power architectures MTBF 14.2 Mh Configurable output voltage (Vout) and voltage margins (Margin low and Margin high) Intermediate bus voltage applications Configurable protection limits for OVP, input over voltage, input under voltage, over current, on/off, and temperature Network equipment 0.6 V - 3.3 V output voltage range High efficiency, typ. 97.2% at 5Vin, 3.3Vout half load Configuration and monitoring via PMBus™ Adaptive compensation of PWM control loop & fast loop transient response Non-Linear Response for reduction of decoupling capacitor Remote control & power good Output short-circuit, output over voltage, & over temperature protection Certified to UL/IEC 60950-1 Servers and storage applications Status monitor Vout, Iout, Vin, Temp, Power good, and On/Off PART NUMBER STRUCTURE OKD x - T / 50 - W12 E - xxx - C Digital Non-isolated PoL Y = Surface Mount H = Horizontal Mount Through-Hole X = SIP Trimmable Output Voltage Range 0.6 - 3.3Vdc RoHS Hazardous Substance Compliance C = RoHS-6 (does not claim EU RoHS exemption 7b – lead in solder) Software Configuration Digits (001 is positive turn-on logic) (002 is negative turn-on logic)* Long pin length (5.5mm) Maximum Rated Output Current in Amps Input Voltage Range 4.5-14Vdc *Special quantity order is required; contact Murata Power Solutions for MOQ and lead times. PM www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 1 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series ORDERING GUIDE Model Number OKDY-T/50-W12-001-C OKDH-T/50-W12-001-C OKDX-T/50-W12-001-C OKDX-T/50-W12E-001-C OKDH-T/50-W12-002-C OKDX-T/50-W12-002-C Output 0.6-3.3 V, 50 A/ 165 W Absolute Maximum Ratings Characteristics TP2 Operating temperature (see Thermal Consideration section) TS Storage temperature VI Input voltage (See Operating Information Section for input and output voltage relations) Logic I/O voltage CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC, GCB, PG Ground voltage differential -S, PREF, GND Analog pin voltage VO, +S, VTRK General and Safety Safety Calculated MTBF Min -40 -40 -0.3 -0.3 -0.3 -0.3 Conditions Designed for UL/IEC/EN 60950 1 Telcordia SR-332, Issue 2 Method 1 Min Typ Typ 14.2 Max 125 125 16 6.5 0.3 6.5 Max Unit °C °C V V V V Unit Mhrs Stress in excess of Absolute Maximum Ratings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits in the Electrical Specification. If exposed to stress above these limits, function and performance may degrade in an unspecified manner. default configuration file, unless otherwise specified. The default configuration file is designed to fit most application needs with focus on high efficiency. If different characteristics are required it is possible to change the configuration file to optimize certain performance characteristics. Note that current sharing operation requires changed configuration file. Configuration File This product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and performance of the product. The Electrical Specification table shows parameter values of functionality and performance with the In this Technical specification examples are included to show the possibilities with digital control. See Operating Information section for information about trade offs when optimizing certain key performance characteristics. C i=140 μF, C o =400 μF VIN VOUT VIN VOUT Ci Co GND GND +Sense -Sense PGOOD (SA1) SALERT CTRL VSET Controller and digital interface SYNC SCL SDA SA0 GCB VTRK PREF Fundamental Circuit Diagram www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 2 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Electrical Specifications, OKDY-T/50-W12-C and OKDH-T/50-W12-C TP1 = -30 to +95°C, VIN = 4.5 to 14 V, VIN > VOUT + 1.0 V Typical values given at: TP1 = +25 °C, VIN = 12.0 V, max IOUT, unless otherwise specified under Conditions. Default configuration file, 190 10-CDA 102 0206/001. External CIN = 470 μF/10 mΩ, COUT = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics VI Input voltage rise time Conditions monotonic Output voltage without pin strap Output voltage adjustment range Output voltage adjustment including margining Output voltage set-point resolution VO Load regulation; IO = 0 - 100% VOac Output ripple & noise CO = 470 μF (minimum external capacitance). See Note 11 IO Output current IS Static input current at max IO Ilim Current limit threshold Isc Short circuit current 50% of max IO See Note 17 V V V % FS -1 1 % -2 2 % ±0.025 47 2 2 2 3 2 2 2 2 20 25 30 35 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V See Note 18 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V Efficiency max IO Pd Power dissipation at max IO Pli Input idling power (no load) Default configuration: Continues Conduction Mode, CCM Unit V/ms 3.3 3.63 0.60 0.54 0.001 Ω mV mV mVp-p 50 3.10 4.80 8.19 14.53 52 RMS, hiccup mode, See Note 3 Max 2.4 Internal resistance +S/-S to VOUT/GND Line regulation Typ 1.2 Including line, load, temp. See Note 14 Current sharing operation See Note 15 Output voltage accuracy Min A 65 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V 11 9 7 6 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V 85.6 90.4 93.7 95.7 80.5 86.9 91.6 94.6 7.25 7.54 8.28 9.36 0.90 0.90 1.10 1.67 A A A % % W W www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 3 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Turned off with CTRL-pin PCTRL Input standby power Ci Co Internal input capacitance Internal output capacitance Total external output capacitance ESR range of capacitors (per single capacitor) COUT Vtr1 ttr1 fs Load transient peak voltage deviation (L to H/H to L) Load step 25-75-25% of max IO Load transient recovery time, Note 5 (L to H/H to L) Load step 25-75-25% of max IO Default configuration di/dt = 2 A/μs CO = 470 μF (minimum external capacitance) see Note 12 Default configuration di/dt = 2 A/μs CO = 470 μF (minimum external capacitance) see Note 12 Switching frequency Switching frequency range Switching frequency set-point accuracy Control Circuit PWM Duty Cycle Minimum Sync Pulse Width Input Clock Frequency Drift Tolerance Input Under Voltage Lockout, UVLO Input Over Voltage Protection, IOVP Power Good, PG, See Note 2 Output voltage Over/Under Voltage Protection, OVP/UVP Over Current Protection, OCP UVLO threshold UVLO threshold range Set point accuracy UVLO hysteresis UVLO hysteresis range Delay Fault response IOVP threshold IOVP threshold range Set point accuracy IOVP hysteresis IOVP hysteresis range Delay Fault response PG threshold PG hysteresis PG delay PG delay range UVP threshold UVP threshold range UVP hysteresis OVP threshold OVP threshold range UVP/OVP response time UVP/OVP response time range Fault response OCP threshold OCP threshold range Protection delay, Protection delay range Fault response Conditions Default configuration: Monitoring enabled, Precise timing enabled Min Typ Max Unit mW 170 140 400 See Note 9 470 30 000 μF μF μF See Note 9 5 30 mΩ VO = 0.6 V VO = 1.0 V VO = 1.8 V 79 / 256 127 / 298 144 / 324 VO = 3.3 V 210 / 327 VO = 0.6 V VO = 1.0 V VO = 1.8 V 60 / 100 100 / 100 100 / 100 VO = 3.3 V 100 / 100 PMBus configurable 320 200-640 External clock source -5 5 150 -13 5 95 13 -150 150 0.35 0-10.15 2.5 Automatic restart, 70 ms 16 4.2-16 PMBus configurable See Note 3 PMBus configurable -150 See Note 3 See Note 19 PMBus configurable PMBus configurable PMBus configurable PMBus configurable See Note 3 PMBus configurable See Note 4 PMBus configurable See Note 3 μs 3.85 3.85-14 PMBus configurable PMBus configurable mV 150 1 0-11.8 2.5 Automatic restart, 70 ms 90 5 Direct after DLC 0-500 85 0-100 5 115 100-115 25 5-60 Automatic restart, 70 ms 62 0-62 32 1-32 Automatic restart, 70 ms kHz kHz % % ns % V V mV V V μs V V mV V V μs % VO % VO s % VO % VO % VO % VO % VO μs μs A A Tsw Tsw www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 4 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Over Temperature Protection, OTP at P2 See Note 8 VIL VIH IIL VOL VOH IOL IOH tset thold tfree Cp Conditions OTP threshold OTP threshold range OTP hysteresis OTP hysteresis range Fault response Logic input low threshold Logic input high threshold Logic input low sink current Logic output low signal level Logic output high signal level Logic output low sink current Logic output high source current Setup time, SMBus Hold time, SMBus Bus free time, SMBus Internal capacitance on logic pins Initialization time Output Voltage Delay Time See Note 6 Output Voltage Ramp Time See Note 13 Delay duration Delay duration range Delay accuracy turn-on Delay accuracy turn-off Ramp duration Ramp duration range Ramp time accuracy VTRK Input Bias Current VTRK Tracking Ramp Accuracy (VO - VVTRK) VTRK Regulation Accuracy (VO - VVTRK) Current difference between products in a current sharing group Min PMBus configurable PMBus configurable See Note 3 SYNC, SA0, SA1, SCL, SDA, GCB, CTRL, VSET CTRL SYNC, SCL, SDA, SALERT, GCB, PG See Note 1 See Note 1 See Note 1 READ_IOUT vs IO 0.8 V V mA V V mA mA ns ns ms pF 2 0.6 0.4 2.25 4 2 10 See Note 10 See Note 16 PMBus configurable 40 10 5-500000 Current sharing operation VVTRK = 5.5 V 100% tracking, see Note 7 Current sharing operation 2 phases, 100% tracking VO = 1.0 V, 10 ms ramp 100% Tracking Current sharing operation 100% Tracking Steady state operation Ramp-up IO = 0-50 A, TP1 = 0 to +95 °C VI = 4.5-14 V, VO = 1.0 V IO = 0-50 A, TP1 = 0 to +95 °C VI = 4.5-14 V, VO = 0.6-3.3 V Note 1: See section I2C/SMBus Setup and Hold Times – Definitions. Note 2: Monitorable over PMBus Interface. Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart. See Operating Information for other fault response options. Note 4: Tsw is the switching period. Note 5: Within +/-3% of VO Note 6: See section Soft-start Power Up. Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth. Note 8: See section Over Temperature Protection (OTP). Note 9: See section External Capacitors. Note 10: See section Initialization Procedure. ms ms -0.25/+4 ms -0.25/+4 ms 10 0-200 100 20 PMBus configurable READ_VIN vs VI READ_VOUT vs VO READ_IOUT vs IO Unit °C °C °C °C 300 250 2 Number of products in a current sharing group Monitoring accuracy Typ Max 120 -40…+125 25 0-165 Automatic restart, 240 ms 110 -100 ms μs % 200 100 ±100 μA mV mV -1 1 % -2 2 % Max 2 x READ_IOUT monitoring accuracy 4 7 A 3 1 % % ±3.0 A ±5.0 A Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise. Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors. Note 13: Time for reaching 100% of nominal Vout. Note 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus. Note 15: Accuracy here means deviation from ideal output voltage level given by configured droop and actual load. Includes line, load and temperature variations. Note 16: For current sharing the Output Voltage Delay Time must be reconfigured to minimum 15 ms. Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative. Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled). Note 19: See sections Dynamic Loop Compensation and Power Good. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 5 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Efficiency and Power Dissipation Efficiency vs. Output Current, VI = 5 V Power Dissipation vs. Output Current, VI = 5 V [%] [W] 100 12 95 10 8 90 0.6 V 1.0 V 85 80 75 0 0 1 0 2 0 3 0 4 0.6 V 6 1.0 V 1.8 V 4 1.8 V 3.3 V 2 3.3 V 0 50 [A] 0 0 1 0 2 0 3 0 4 50 [A] Efficiency vs. load current and output voltage: TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m. Dissipated power vs. load current and output voltage: TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m. Efficiency vs. Output Current, VI = 12 V Power Dissipation vs. Output Current, VI = 12 V [%] [W] 100 12 10 95 8 90 0.6 V 1.0 V 85 80 0.6 V 6 1.0 V 1.8 V 4 1.8 V 3.3 V 2 3.3 V 75 0 0 0 1 0 2 0 3 0 4 50 [A] 0 0 1 0 2 0 3 0 4 50 [A] Efficiency vs. load current and output voltage at TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 μF/10 m. Dissipated power vs. load current and output voltage: TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 μF/10 m. Efficiency vs. Output Current and Switching Frequency Power Dissipation vs. Output Current and Switching frequency [%] [W] 95 12 10 90 200 kHz 85 200 kHz 8 320 kHz 6 320 kHz 80 480 kHz 4 480 kHz 75 640 kHz 2 640 kHz 70 0 0 10 0 2 0 3 0 4 Efficiency vs. load current and switch frequency at TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m. Default configuration except changed frequency 50 [A] 0 0 1 0 2 0 3 0 4 50 [A] Dissipated power vs. load current and switch frequency at TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m. Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 6 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Load Transient Load Transient vs. External Capacitance, VO = 1.0 V [mV] 500 Universal PID, No NLR Load Transient vs. External Capacitance, VO = 3.3 V [mV] 500 Universal PID, No NLR 400 DLC, No NLR 400 300 Universal PID, Default NLR 300 Universal PID, Default NLR 200 DLC, Default NLR 200 DLC, Default NLR 100 Universal PID, Opt. NLR 100 Universal PID, Opt. NLR DLC, Opt. NLR 0 0 1 2 3 4 DLC, Opt. NLR 0 0 5 [mF] DLC, No NLR 1 2 3 4 5 [mF] Load transient peak voltage deviation vs. external capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m, TP1 = +25 °C, VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/μs Load transient peak voltage deviation vs. external capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m, TP1 = +25 °C, VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/μs Load transient vs. Switch Frequency Output Load Transient Response, Default Configuration [mV] 600 Universal PID, No NLR 500 DLC, No NLR 400 Universal PID, Default NLR 300 DLC, Default NLR 200 Universal PID, Opt. NLR 100 DLC, Opt. NLR 0 200 300 400 500 600 [kHz] Load transient peak voltage deviation vs. frequency. Step-change (12.5-37.5-12.5 A). TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m Output voltage response to load current Step-change (12.5-37.5-12.5 A) at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V di/dt = 2 A/μs, fsw = 320 kHz CO = 470 μF/10 m Top trace: output voltage (200 mV/div.). Bottom trace: load current (10 A/div.). Time scale: (0.1 ms/div.). Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC). Note 2: In the load transient graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 7 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Current Characteristic Output Current Derating, VO = 0.6 V Output Current Derating, VO = 1.0 V [A] [A] 50 50 3.0 m/s 40 2.0 m/s 3.0 m/s 40 2.0 m/s 30 1.0 m/s 30 1.0 m/s 20 0.5 m/s 20 0.5 m/s Nat. Conv. 10 0 Nat. Conv. 10 0 20 40 60 80 100 120 [°C] 20 40 60 80 100 120 [°C] Available load current vs. ambient air temperature and airflow at VO = 0.6 V, VI = 12 V. See Thermal Consideration section. Available load current vs. ambient air temperature and airflow at VO = 1.0 V, VI = 12 V. See Thermal Consideration section. Output Current Derating, VO = 1.8 V Output Current Derating, VO = 3.3 V [A] [A] 50 50 3.0 m/s 3.0 m/s 40 40 2.0 m/s 2.0 m/s 30 1.0 m/s 30 1.0 m/s 20 0.5 m/s 20 0.5 m/s Nat. Conv. 10 10 Nat. Conv. 0 0 20 40 60 80 100 20 120 [°C] 40 60 80 100 120 [°C] Available load current vs. ambient air temperature and airflow at VO = 3.3 V, VI = 12 V. See Thermal Consideration section. Available load current vs. ambient air temperature and airflow at VO = 1.8 V, VI = 12 V. See Thermal Consideration section. Current Limit Characteristics, VO = 1.0 V Current Limit Characteristics, VO = 3.3 V [V] [V] 1.2 4.0 VI = 4.5, 5 .0V VI = 5.0, 12 V 0.9 3.0 4.5 V 4.5 V 5.0 V 0.6 5.0 V 2.0 12 V 12 V VI = 4.5,14 V 14 V 0.3 0.0 VI = 12, 14 V 14 V 1.0 0.0 50 55 60 65 [A] 50 55 60 65 [A] Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V. Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V. Note: Output enters hiccup mode at current limit. Note: Output enters hiccup mode at current limit. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 8 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Voltage Output Ripple & Noise, VO = 1.0 V Output Ripple & Noise, VO = 3.3 V Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.). Time scale: (2 μs/div.). VI = 12 V, CO = 470 μF/10 m IO = 50 A Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.). VI = 12 V, CO = 470 μF/10 m Time scale: (2 μs/div.). IO = 50 A Output Ripple vs. Input Voltage Output Ripple vs. Frequency [mVpk-pk] [mVpk-pk] 40 70 60 30 50 0.6 V 1.0 V 40 1.0 V 1.8 V 30 3.3 V 20 0.6 V 20 10 1.8 V 3.3 V 10 0 5 7 9 11 0 [V] 13 200 300 400 500 600 [kHz] Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 μF/10 m, IO = 50 A Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 μF/10 m, IO = 50 A. Default configuration except changed frequency. Output Ripple vs. External Capacitance Load regulation, VO = 1.0 V [mV] [V] 40 1.010 30 0.6 V 1.005 4.5 V 1.0 V 20 1.8 V 3.3 V 10 0 0 1 2 3 4 5 [mF] Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V. IO = 50 A. Parallel coupling of capacitors with 470 μF/10 m 5.0 V 1.000 12 V 14 V 0.995 0.990 0 5 10 15 20 25 [A] Load regulation at VO = 1.0 V, TP1 = +25 °C, CO = 470 μF/10 m www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 9 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Start-up and shut-down Start-up by input source Start-up enabled by connecting VI at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Shut-down by input source Top trace: output voltage (0.5 V/div.). Bottom trace: input voltage (5 V/div.). Time scale: (20 ms/div.). Start-up by CTRL signal Start-up by enabling CTRL signal at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Shut-down enabled by disconnecting VI at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Top trace: output voltage (0.5 V/div.). Bottom trace: input voltage (5 V/div.). Time scale: (2 ms/div.). Shut-down by CTRL signal Top trace: output voltage (0.5 V/div.). Bottom trace: CTRL signal (2 V/div.). Time scale: (20 ms/div.). Shut-down enabled by disconnecting VI at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Top trace: output voltage (0.5 V/div). Bottom trace: CTRL signal (2 V/div.). Time scale: (2 ms/div.). www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 10 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Electrical Specifications, OKDX-T/50-W12-C TP1 = -30 to +95 °C, VI = 4.5 to 14 V, VI > VO + 1.0 V Typical values given at: TP1 = +25 °C, VI = 12.0 V, max IO, unless otherwise specified under Conditions. Default configuration file, 190 10-CDA 102 0259/001. External CIN = 470 μF/10 mΩ, COUT = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics VI Input voltage rise time Conditions monotonic Output voltage without pin strap Output voltage adjustment range Output voltage adjustment including margining Output voltage set-point resolution VO Load regulation; IO = 0 - 100% VOac Output ripple & noise CO = 470 μF (minimum external capacitance). See Note 11 IO Output current IS Static input current at max IO Ilim Current limit threshold Isc Short circuit current RMS, hiccup mode, See Note 3 Efficiency max IO Pd Power dissipation at max IO Pli Input idling power (no load) Default configuration: Continues Conduction Mode, CCM PCTRL Input standby power Turned off with CTRL-pin Ci Internal input capacitance Max 2.4 Unit V/ms 3.3 3.63 V V V % FS 1 % 2 % ±0.025 -1 -2 47 2 2 2 3 2 2 2 2 20 25 30 40 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V See Note 18 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V 0.001 mV mV mVp-p 50 10 8 6 5 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V 85.2 90.2 93.3 95.3 80.2 86.6 91.2 94.2 7.40 7.73 8.68 10.15 0.95 0.95 1.22 1.88 170 140 A A 65 VO = 0.6 V VO = 1.0 V VO = 1.8 V VO = 3.3 V Default configuration: Monitoring enabled, Precise timing enabled Ω 3.12 4.81 8.22 14.59 52 50% of max IO See Note 17 0.60 0.54 Internal resistance +S/-S to VOUT/GND Line regulation Typ 1.2 Including line, load, temp. See Note 14 Current sharing operation See Note 15 Output voltage accuracy Min A A % % W W mW μF www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 11 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Co Internal output capacitance Total external output capacitance COUT ESR range of capacitors (per single capacitor) Vtr1 ttr1 fs Load transient peak voltage deviation (L to H/H to L) Load step 25-75-25% of max IO Default configuration di/dt = 2 A/μs CO = 470 μF (minimum external capacitance) see Note 12 Load transient recovery time, Note 5 (L to H/H to L) Load step 25-75-25% of max IO Default configuration di/dt = 2 A/μs CO = 470 μF (minimum external capacitance) see Note 12 Switching frequency Switching frequency range Switching frequency set-point accuracy Control Circuit PWM Duty Cycle Minimum Sync Pulse Width Input Clock Frequency Drift Tolerance Input Under Voltage Lockout, UVLO Input Over Voltage Protection, IOVP Power Good, PG, See Note 2 Output voltage Over/Under Voltage Protection, OVP/UVP Over Current Protection, OCP UVLO threshold UVLO threshold range Set point accuracy UVLO hysteresis UVLO hysteresis range Delay Fault response IOVP threshold IOVP threshold range Set point accuracy IOVP hysteresis IOVP hysteresis range Delay Fault response PG threshold PG hysteresis PG delay PG delay range UVP threshold UVP threshold range UVP hysteresis OVP threshold OVP threshold range UVP/OVP response time UVP/OVP response time range Fault response OCP threshold OCP threshold range Protection delay, Protection delay range Fault response Conditions Min Typ 400 See Note 9 470 30 000 Unit μF μF See Note 9 5 30 mΩ VO = 0.6 V 90 / 300 VO = 1.0 V 120 / 300 VO = 1.8 V 160 / 305 VO = 3.3 V 230 / 315 VO = 0.6 V 70 / 100 VO = 1.0 V 100 / 100 VO = 1.8 V 100 / 100 VO = 3.3 V 100 / 100 PMBus configurable 320 200-640 External clock source mV μs -5 5 150 -13 5 95 13 3.85 3.85-14 PMBus configurable -150 150 0.35 0-10.15 2.5 Automatic restart, 70 ms 16 4.2-16 PMBus configurable See Note 3 PMBus configurable -150 PMBus configurable See Note 3 See Note 19 PMBus configurable PMBus configurable PMBus configurable PMBus configurable See Note 3 PMBus configurable See Note 4 PMBus configurable See Note 3 Max 150 kHz kHz % % ns % V V mV V V μs V V mV V V μs 1 0-11.8 2.5 Automatic restart, 70 ms 90 5 Direct after DLC 0-500 85 0-100 5 115 100-115 25 % VO % VO ms s % VO % VO % VO % VO % VO μs 5-60 μs Automatic restart, 70 ms 60 0-60 32 1-32 Automatic restart, 70 ms A A Tsw Tsw www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 12 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Over Temperature Protection, OTP at P2 See Note 8 VIL VIH IIL VOL VOH IOL IOH tset thold tfree Cp Conditions OTP threshold OTP threshold range OTP hysteresis OTP hysteresis range Fault response Logic input low threshold Logic input high threshold Logic input low sink current Logic output low signal level Logic output high signal level Logic output low sink current Logic output high source current Setup time, SMBus Hold time, SMBus Bus free time, SMBus Internal capacitance on logic pins Initialization time Output Voltage Delay Time See Note 6 Output Voltage Ramp Time See Note 13 Delay duration Delay duration range Delay accuracy turn-on Delay accuracy turn-off Ramp duration Ramp duration range Ramp time accuracy VTRK Input Bias Current VTRK Tracking Ramp Accuracy (VO - VVTRK) VTRK Regulation Accuracy (VO - VVTRK) Current difference between products in a current sharing group Min PMBus configurable PMBus configurable See Note 3 SYNC, SA0, SA1, SCL, SDA, GCB, CTRL, VSET CTRL SYNC, SCL, SDA, SALERT, GCB, PG See Note 1 See Note 1 See Note 1 READ_IOUT vs IO 0.8 V V mA V V mA mA ns ns ms pF 2 0.6 0.4 2.25 4 2 10 See Note 10 See Note 16 PMBus configurable 40 10 5-500000 Current sharing operation VVTRK = 5.5 V 100% tracking, see Note 7 Current sharing operation 2 phases, 100% tracking VO = 1.0 V, 10 ms ramp 100% Tracking Current sharing operation 100% Tracking Steady state operation Ramp-up IO = 0-50 A, TP1 = 0 to +95 °C VI = 4.5-14 V, VO = 1.0 V IO = 0-50 A, TP1 = 0 to +95 °C VI = 4.5-14 V, VO = 0.6-3.3 V Note 1: See section I2C/SMBus Setup and Hold Times – Definitions. Note 2: Monitorable over PMBus Interface. Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart. See Operating Information for other fault response options. Note 4: Tsw is the switching period. Note 5: Within +/-3% of VO Note 6: See section Soft-start Power Up. Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth. Note 8: See section Over Temperature Protection (OTP). Note 9: See section External Capacitors. Note 10: See section Initialization Procedure. ms ms -0.25/+4 ms -0.25/+4 ms 10 0-200 100 20 PMBus configurable READ_VIN vs VI READ_VOUT vs VO READ_IOUT vs IO Unit °C °C °C °C 300 250 2 Number of products in a current sharing group Monitoring accuracy Typ Max 120 -40…+125 25 0-165 Automatic restart, 240 ms 110 -100 ms μs % 200 100 ±100 μA mV mV -1 1 % -2 2 % Max 2 x READ_IOUT monitoring accuracy 4 7 A 3 1 % % ±3.0 A ±5.0 A Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise. Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors. Note 13: Time for reaching 100% of nominal Vout. Note 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus. Note 15: Accuracy here means deviation from ideal output voltage level given by configured droop and actual load. Includes line, load and temperature variations. Note 16: For current sharing the Output Voltage Delay Time must be reconfigured to minimum 15 ms. Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative. Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled). Note 19: See sections Dynamic Loop Compensation and Power Good. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 13 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Efficiency and Power Dissipation Efficiency vs. Output Current, VI = 5 V Power Dissipation vs. Output Current, VI = 5 V [%] [W] 100 12 10 95 8 90 0.6 V 1.0 V 85 80 75 0 10 20 30 40 0.6 V 6 1.0 V 1.8 V 4 1.8 V 3.3 V 2 3.3 V 0 50 [A] 0 10 20 30 40 50 [A] Efficiency vs. load current and output voltage: TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m. Dissipated power vs. load current and output voltage: TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m. Efficiency vs. Output Current, VI = 12 V Power Dissipation vs. Output Current, VI = 12 V [%] [W] 100 12 10 95 8 90 0.6 V 1.0 V 85 80 0.6 V 6 1.0 V 1.8 V 4 1.8 V 3.3 V 2 3.3 V 75 0 0 10 20 30 40 50 [A] 0 10 20 30 40 50 [A] Efficiency vs. load current and output voltage at TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 μF/10 m. Dissipated power vs. load current and output voltage: TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 μF/10 m. Efficiency vs. Output Current and Switching Frequency Power Dissipation vs. Output Current and Switching frequency [%] [W] 95 12 10 90 200 kHz 85 200 kHz 8 320 kHz 6 320 kHz 80 480 kHz 4 480 kHz 75 640 kHz 2 640 kHz 70 0 0 10 20 30 40 Efficiency vs. load current and switch frequency at TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m. Default configuration except changed frequency 50 [A] 0 10 20 30 40 50 [A] Dissipated power vs. load current and switch frequency at TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m. Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 14 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Load Transient Load Transient vs. External Capacitance, VO = 1.0 V [mV] 500 400 Universal PID, No NLR Load Transient vs. External Capacitance, VO = 3.3 V [mV] 500 Universal PID, No NLR DLC, No NLR 400 DLC, No NLR 300 Universal PID, Default NLR 300 Universal PID, Default NLR 200 DLC, Default NLR 200 DLC, Default NLR 100 Universal PID, Opt. NLR 100 Universal PID, Opt. NLR DLC, Opt. NLR 0 0 1 2 3 4 5 [mF] DLC, Opt. NLR 0 0 1 2 3 4 5 [mF] Load transient peak voltage deviation vs. external capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m, TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/μs Load transient peak voltage deviation vs. external capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m, TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/μs Load transient vs. Switch Frequency Output Load Transient Response, Default Configuration [mV] 600 Universal PID, No NLR 500 DLC, No NLR 400 Universal PID, Default NLR 300 DLC, Default NLR 200 Universal PID, Opt. NLR 100 DLC, Opt. NLR 0 200 300 400 500 600 [kHz] Load transient peak voltage deviation vs. frequency. Step-change (12.5-37.5-12.5 A). TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m Output voltage response to load Step-change (12.5-37.5-12.5 A) at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V di/dt = 2 A/μs, fsw = 320 kHz CO = 470 μF/10 m Top trace: output voltage (200 mV/div.). Bottom trace: load current (10 A/div.). Time scale: (0.1 ms/div.). Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC). Note 2: In these graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 15 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Current Characteristic Output Current Derating, VO = 0.6 V Output Current Derating, VO = 1.0 V [A] [A] 50 50 3.0 m/s 3.0 m/s 40 2.0 m/s 40 2.0 m/s 30 1.0 m/s 30 1.0 m/s 20 0.5 m/s 20 0.5 m/s Nat. Conv. 10 0 Nat. Conv. 10 0 20 40 60 80 100 120 [°C] 20 40 60 80 100 120 [°C] Available load current vs. ambient air temperature and airflow at VO = 0.6 V, VI = 12 V. See Thermal Consideration section. Available load current vs. ambient air temperature and airflow at VO = 1.0 V, VI = 12 V. See Thermal Consideration section. Output Current Derating, VO = 1.8 V Output Current Derating, VO = 3.3 V [A] [A] 50 50 3.0 m/s 3.0 m/s 40 2.0 m/s 40 2.0 m/s 30 1.0 m/s 30 1.0 m/s 20 0.5 m/s 20 0.5 m/s Nat. Conv. 10 0 Nat. Conv. 10 0 20 40 60 80 100 120 [°C] 20 Available load current vs. ambient air temperature and airflow at VO = 1.8 V, VI = 12 V. See Thermal Consideration section. 40 60 80 100 120 [°C] Available load current vs. ambient air temperature and airflow at VO = 3.3 V, VI = 12 V. See Thermal Consideration section. Current Limit Characteristics, VO = 1.0 V Current Limit Characteristics, VO = 3.3 V [V] [V] 1,2 4,0 0,9 3,0 4.5 V 4.5 V 5.0 V 0,6 VI = 4.5, 5.0 V VI = 12, 14 V 5.0 V 2,0 12 V 12 V 14 V 0,3 0,0 VI = 4.5, 14 V VI = 5.0, 12 V 14 V 1,0 0,0 50 55 60 65 [A] Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V. Note: Output enters hiccup mode at current limit. 50 55 60 65 [A] Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V. Note: Output enters hiccup mode at current limit. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 16 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Voltage Output Ripple & Noise, VO = 1.0 V Output Ripple & Noise, VO = 3.3 V Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.). Time scale: (2 μs/div.). VI = 12 V, CO = 470 μF/10 m IO = 50 A Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.). Time scale: (2 μs/div.). VI = 12 V, CO = 470 μF/10 m IO = 50 A Output Ripple vs. Input Voltage Output Ripple vs. Frequency [mVpk-pk] [mVpk-pk] 50 60 50 40 0.6 V 30 1.0 V 0.6 V 40 1.0 V 30 1.8 V 1.8 V 20 3.3 V 10 3.3 V 20 10 0 5 7 9 11 0 [V] 13 200 300 400 500 600 [kHz] Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 μF/10 m, IO = 50 A. Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 μF/10 m, IO = 50 A. Default configuration except changed frequency. Output Ripple vs. External Capacitance Load regulation, VO = 1.0 V [mV] [V] 50 1,010 40 0.6 V 30 1,005 4.5 V 1.0 V 1.8 V 20 3.3 V 10 0 0 1 2 3 4 5 [mF] Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, IO = 50 A. Parallel coupling of capacitors with 470 μF/10 m 5.0 V 1,000 12 V 14 V 0,995 0,990 0 5 10 15 20 25 [A] Load regulation at VO = 1.0 V, TP1 = +25 °C, CO = 470 μF/10 m www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 17 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Start-up and shut-down Start-up by input source Start-up enabled by connecting VI at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Shut-down by input source Top trace: output voltage (0.5 V/div.). Bottom trace: input voltage (5 V/div.). Time scale: (20 ms/div.). Start-up by CTRL signal Start-up by enabling CTRL signal at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Shut-down enabled by disconnecting VI at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Top trace: output voltage (0.5 V/div). Bottom trace: input voltage (5 V/div.). Time scale: (2 ms/div.). Shut-down by CTRL signal Top trace: output voltage (0.5 V/div.). Bottom trace: CTRL signal (2 V/div.). Time scale: (20 ms/div.). Shut-down enabled by disconnecting VI at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V CO = 470 μF/10 m, IO = 50 A Top trace: output voltage (0.5 V/div). Bottom trace: CTRL signal (2 V/div.). Time scale: (2 ms/div.). www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 18 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Conducted EMI Input terminal value (typical for default configuration) Output Ripple and Noise Output ripple and noise is measured according to figure below. A 50 mm conductor works as a small inductor forming together with the two capacitors as a damped filter. 50 mm conductor Vout Tantalum Capacitor Output 10 μ F Capacitor 470 μ F/10 m Ω +S –S GND Ceramic Capacitor 0.1 μ F Load EMC Specification Conducted EMI measured according to test set-up below. The fundamental switching frequency is 320 kHz at VI = 12 V, max IO. 50 mm conductor BNC-contact to oscilloscope Output ripple and noise test set-up. Operating information EMI without filter To spectrum analyzer RF Current probe 1kHz – 50MHz Battery supply Resistive load C1 POL 50mm C1 = 10uF / 600VDC Feed- Thru RF capacitor 800mm 200mm Conducted EMI test set-up Layout Recommendations The radiated EMI performance of the product will depend on the PWB layout and ground layer design. It is also important to consider the standoff of the product. If a ground layer is used, it should be connected to the output of the product and the equipment ground or chassis. Power Management Overview This product is equipped with a PMBus interface. The product incorporates a wide range of readable and configurable power management features that are simple to implement with a minimum of external components. Additionally, the product includes protection features that continuously safeguard the load from damage due to unexpected system faults. A fault is also shown as an alert on the SALERT pin. The following product parameters can continuously be monitored by a host: Input voltage, output voltage/current, and internal temperature. If the monitoring is not needed it can be disabled and the product enters a low power mode reducing the power consumption. The protection features are not affected. The product is delivered with a default configuration suitable for a wide range operation in terms of input voltage, output voltage, and load. The configuration is stored in an internal Non-Volatile Memory (NVM). All power management functions can be reconfigured using the PMBus interface. Please contact your local Murata Power Solutions representative for design support of custom configurations or appropriate SW tools for design and download of your own configurations. Input Voltage The input voltage range, 4.5 - 14 V, makes the product easy to use in intermediate bus applications when powered by a non-regulated bus converter or a regulated bus converter. See Ordering Information for input voltage range. A ground layer will increase the stray capacitance in the PWB and improve the high frequency EMC performance. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 19 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Input Under Voltage Lockout, UVLO The product monitors the input voltage and will turn-on and turn-off at configured levels. The default turn-on input voltage level setting is 4.20 V, whereas the corresponding turn-off input voltage level is 3.85 V. Hence, the default hysteresis between turn-on and turn-off input voltage is 0.35 V. Once an input turn-off condition occurs, the device can respond in a number of ways as follows: 1. Continue operating without interruption. The unit will continue to operate as long as the input voltage can be supported. If the input voltage continues to fall, there will come a point where the unit will cease to operate. 2. Continue operating for a given delay period, followed by shutdown if the fault still exists. The device will remain in shutdown until instructed to restart. I inputRMS = I load D (1–D), where I load is the output load current and D is the duty cycle. The maximum load ripple current becomes I load 2 . The ripple current is divided into three parts, i.e., currents in the input source, external input capacitor, and internal input capacitor. How the current is divided depends on the impedance of the input source, ESR and capacitance values in the capacitors. A minimum capacitance of 300 μF with low ESR is recommended. The ripple current rating of the capacitors must follow Eq. 1. For high-performance/transient applications or wherever the input source performance is degraded, additional low ESR ceramic type capacitors at the input is recommended. The additional input low ESR capacitance above the minimum level insures an optimized performance. Output capacitors: When powering loads with significant dynamic current requirements, the voltage regulation at the point of load can be improved by addition of decoupling capacitors at the load. The default response from a turn-off is an immediate shutdown of the The most effective technique is to locate low ESR ceramic and electrolytic device. The device will continuously check for the presence of the fault capacitors as close to the load as possible, using several capacitors in condition. If the fault condition is no longer present, the product will be reenabled. The turn-on and turn-off levels and response can be reconfigured parallel to lower the effective ESR. The ceramic capacitors will handle highfrequency dynamic load changes while the electrolytic capacitors are used using the PMBus interface. to handle low frequency dynamic load changes. Ceramic capacitors will also reduce high frequency noise at the load. Remote Control It is equally important to use low resistance and low inductance PWB The product is equipped with a remote layouts and cabling. control function, i.e., the CTRL pin. The External decoupling capacitors are a part of the control loop of the product Vext remote control can be connected to and may affect the stability margins. either the primary negative input Stable operation is guaranteed for the following total capacitance CO in connection (GND) or an external CTRL the output decoupling capacitor bank where voltage (Vext), which is a 3 - 5 V positive supply voltage in accordance Eq. 2. CO >C min , C max @ >470, 30000@ μF. GND to the SMBus Specification version The decoupling capacitor bank should consist of capacitors which has a 2.0. capacitance value larger than C t C min and has an ESR range of The CTRL function allows the product to be turned on/off by an external device like a semiconductor or mechanical switch. By default the product Eq. 3. ESR >ESRmin , ESRmax @ >5, 30@ mΩ will turn on when the CTRL pin is left open and turn off when the CTRL pin is applied to GND. The CTRL pin has an internal pull-up resistor. When the The control loop stability margins are limited by the minimum time constant CTRL pin is left open, the voltage generated on the CTRL pin is max 5.5 V. W min of the capacitors. Hence, the time constant of the capacitors should If the device is to be synchronized to an external clock source, the clock follow Eq. 4. frequency must be stable prior to asserting the CTRL pin. Eq. 4. W t W min C min ESRmin 2.35 P s The product can also be configured using the PMBus interface to be “Always on” or turn on/off can be performed with PMBus commands. This relation can be used if your preferred capacitors have parameters outside the above stated ranges in Eq. 2 and Eq.3. Input and Output Impedance The impedance of both the input source and the load will interact with the impedance of the product. It is important that the input source has low characteristic impedance. The performance in some applications can be enhanced by addition of external capacitance as described under External x If the capacitors capacitance value is C C min one must use at least Decoupling Capacitors. If the input voltage source contains significant N capacitors where inductance, the addition a capacitor with low ESR at the input of the C product will ensure stable operation. ªC º N t « min » and ESR t ESRmin min . C C » « External Capacitors x If the ESR value is ESR ! ESRmax one must use at least N capacitors Input capacitors: of that type where The input ripple RMS current in a buck converter is equal to 3. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 20 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series ª ESR º C min N t« . » and C t ESR N max » « x If the ESR value is ESR ESR min the capacitance value should be ESRmin . ESR For a total capacitance outside the above stated range or capacitors that do not follow the stated above requirements above a re-design of the control loop parameters will be necessary for robust dynamic operation and stability. C t C min Control Loop The product uses a voltage-mode synchronous buck controller with a fixed frequency PWM scheme. Although the product uses a digital control loop, it operates much like a traditional analog PWM controller. As in the analog controller case, the control loop compares the output voltage to the desired voltage reference and compensation is added to keep the loop stable and fast. The resulting error signal is used to drive the PWM logic. Instead of using external resistors and capacitors required with traditional analog control loops, the product uses a digital Proportional-Integral-Derivative (PID) compensator in the control loop. The characteristics of the control loop is configured by setting PID compensation parameters. These PID settings can be reconfigured using the PMBus interface. Dynamic Loop Compensation (DLC) The DLC feature might in some documents be referred to as “Auto Compensation” or “Auto Tuning” feature. The DLC feature measures the characteristics of the power train and calculates the proper compensator PID coefficients. The default configuration is that once the output voltage ramp up has completed, the DLC algorithm will begin and a new optimized compensator solution (PID setting) will be found and implemented. The DLC algorithm typically takes between 50 ms and 200 ms to complete. By the PMBus command AUTO_COMP_CONFIG the user may select between several different modes of operation: x x x x Disable Autocomp once, will run DLC algorithm each time the output is enabled (default configuration) Autocomp every second will initiate a new DLC algorithm each 1 second Autocomp every minute will initiate a new DLC algorithm every minute. The DLC can also be configured to run once only after the first ramp up (after input power have been applied) and to use that temporary stored PID settings in all subsequent ramps. If input power is cycled a new DLC algorithm will be performed after the first ramp up. The default setting is however to run the DLC algorithm after every ramp up. The DLC algorithm can also be initiated manually by sending the AUTO_COMP_CONTROL command. The DLC can also be configured with Auto Comp Gain Control. This scales the DLC results to allow a trade-off between transient response and steady-state duty cycle jitter. A setting of 100% will provide the fastest transient response while a setting of 10% will produce the lowest jitter. The default is 50%. Changing DLC and PID Setting Some caution must be considered while DLC is enabled and when it is changed from enabled or disabled. When operating, the controller IC uses the settings loaded in its (volatile) RAM memory. When the input power is applied the RAM settings are retrieved from the pin-strap resistors and the two non-volatile memories (DEFAULT and USER). The sequence is described in the “Initialization Procedure” section. When DLC is enabled: When DLC is enabled, the normal sequence (after input power has been applied) that a value stored in the user non-volatile memory overwrites any previously loaded value does not apply for the PID setting (stored in the PID_TAPS register). The PID setting in the user non-volatile memory is ignored and a non-configurable default PID setting is loaded to RAM to act as a safe starting value for the DLC. Once the output has been enabled and the DLC algorithm has found a new optimized PID setting, it will be loaded in RAM and used by the control loop. When saving changes to the user non-volatile memory, all changes made to the content of RAM will be saved. This also includes the default PID setting (loaded to RAM to act as a safe starting value) or the PID setting changed by the DLC algorithm after enabling output. The result is that as long as DLC is enabled the PID setting in the user non-volatile memory is ignored, but it might accidentally get overwritten. When changing DLC from disabled to enabled: A non-configurable default PID setting is loaded to RAM to act as a safe starting value for the DLC (same as above). When changing DLC from enabled to disabled: When changing DLC from enabled to disabled, the PID setting in the user non-volatile memory will be loaded to RAM. Any new optimized PID setting in RAM will be lost, if not first stored to the user non-volatile memory. When DLC is disabled: When DLC is disabled and input power has been applied, the PID setting in the user non-volatile memory will be loaded to RAM and used in the control loop. The original PID setting in the user non-volatile memory is quite slow and not recommended for optimal performance. If DLC is disabled it is recommended to either: 1. Use the DLC to find optimized PID setting. 2. Use Ericsson Power Designer to find appropriate PID setting. 3. Use Universal PID as defined below. The Universal PID setting (taps) is: www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 21 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series A = 3289.56, B = -6248.12, C = 2964.06 Write 0x7CB941FDC3417CCD99 to PID_TAPS register and write command STORE_USER_ALL Note that if DLC is enabled, for best results VI must be stable before DLC algorithm begins. Load Transient Response Optimization The product incorporates a Non-Linear transient Response, NLR, loop that decreases the response time and the output voltage deviation during a load transient. The NLR results in a higher equivalent loop bandwidth than is possible using a traditional linear control loop. The product is pre-configured with appropriate NLR settings for robust and stable operation for a wide range of input voltage and a capacitive load range as defined in the section External Decoupling Capacitors. For an application with a specific input voltage, output voltage, and capacitive load, the NLR configuration can be optimized for a robust and stable operation and with an improved load transient response. This will also reduce the amount of output decoupling capacitors and yield a reduced cost. However, the NLR slightly reduces the efficiency. In order to obtain maximal energy efficiency the load transient requirement has to be met by the standard control loop compensation and the decoupling capacitors. The NLR settings can be reconfigured using the PMBus interface. Remote Sense The product has remote sense that can be used to compensate for voltage drops between the output and the point of load. The sense traces should be located close to the PWB ground layer to reduce noise susceptibility. Due to derating of internal output capacitance the voltage drop should be kept below VDROPMAX = (5.5–VO)/2. A large voltage drop will impact the electrical performance of the regulator. If the remote sense is not needed, +S should be connected to VOUT and −S should be connected to GND. Output Voltage Adjust using Pin-strap Resistor Using an external Pin-strap resistor, RSET, the output voltage can be set in the range 0.6 V to 3.3 VSET V at 28 different levels shown R SET in the table below. The resistor PREF should be applied between the VSET pin and the PREF pin. RSET also sets the maximum output voltage, see section “Output Voltage Range Limitation.” The resistor is sensed only during product start-up. Changing the resistor value during normal operation will not change the output voltage. The input voltage must be at least 1 V larger than the output voltage in order to deliver the correct output voltage. See Ordering Information for output voltage range. VO [V] 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 RSET[kΩ] 10 11 12.1 13.3 14.7 16.2 17.8 19.6 21.5 23.7 26.1 28.7 31.6 1.25 1.30 1.40 34.8 38.3 42.2 VO [V] 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.50 3.00 3.30 RSET[kΩ] 46.4 51.1 56.2 61.9 68.1 75 82.5 90.9 100 110 121 133 The output voltage and the maximum output voltage can be pin strapped to three fixed values by connecting the VSET pin according to the table below. VO [V] 0.60 1.2 2.5 VSET Shorted to PREF Open “high impedance” Logic High, GND as reference Output Voltage Adjust using PMBus The output voltage set by pin-strap can be overridden by configuration file or by using a PMBus command. See Electrical Specification for adjustment range. When setting the output voltage by configuration file or by a PMBus command, the specified output voltage accuracy is valid only when the set output voltage level falls within the same bin range as the voltage level defined by the pin-strap resistor RSET. The applicable bin ranges are defined in the table below. Valid accuracy for voltage levels outside the applicable bin range is two times the specified. Example: Nominal VO is set to 1.10 V by RSET = 26.1 kΩ. 1.10 V falls within the bin range 0.988-1.383 V, thus specified accuracy is valid when adjusting VO within 0.988-1.383V. VO bin ranges [V] 0.600 – 0.988 0.988 – 1.383 1.383 – 1.975 1.975 – 2.398 2.398 – 2.963 2.963 – 3.753 Output Voltage Range Limitation The output voltage range that is possible to set by configuration or by the PMBus interface is limited by the pin-strap resistor RSET. The maximum output voltage is set to 110% of the nominal output value defined by RSET, VO,MAX = 1.1 x VO,RSET. This protects the load from an over voltage due to an accidental wrong PMBus command. The following table shows recommended resistor values for RSET. Maximum 1% tolerance resistors are required. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 22 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Output Voltage Adjust Limitation using PMBus In addition to the maximum output voltage limitation by the pin-strap resistor RSET, there is also a limitation in how much the output voltage can be increased while the output is enabled. If output is disabled then RSET resistor is the only limitation. falls below 85% of the nominal voltage. These limits may be changed via the PMBus interface. A PG delay period is defined as the time from when all conditions within the product for asserting PG are met to when the PG signal is actually asserted. The default PG delay is set to 10 ms. This value can be reconfigured using the PMBus interface. Example: If the output is enabled with output voltage set to 1.0 V, then it is only possible to adjust/change the output voltage up to 1.7- V as long as the output is enabled. For products with DLC the PG signal is by default asserted directly after the DLC operation have been completed. If DLC is disabled the configured PG delay will be used. This can be reconfigured using the PMBus interface. VO setting when enabled [V] 0.000 – 0.988 0.988 – 1.383 1.383 – 1.975 1.975 – 2.398 2.398 – 2.963 2.963 – 3.753 VO set range while enabled [V] ~0.2 to >1.2 ~0.2 to >1.7 ~0.2 to >2.5 ~0.2 to >2.97 ~0.2 to >3.68 ~0.2 to >4.65 Over Voltage Protection (OVP) The product includes over voltage limiting circuitry for protection of the load. The default OVP limit is 15% above the nominal output voltage. If the output voltage exceeds the OVP limit, the product can respond in different ways: 1. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts. 2. Turn off the high-side MOSFET and turn on the low-side MOSFET. The low-side MOSFET remains ON until the device attempts a restart, i.e. the output voltage is pulled to ground level (crowbar function). The default response from an overvoltage fault is to immediately shut down as in 2. The device will continuously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. For continuous OVP when operating from an external clock for synchronization, the only allowed response is an immediate shutdown. The OVP limit and fault response can be reconfigured using the PMBus interface. Under Voltage Protection (UVP) The product includes output under voltage limiting circuitry for protection of the load. The default UVP limit is 15% below the nominal output voltage. The UVP limit can be reconfigured using the PMBus interface. Power Good The product provides a Power Good (PG) flag in the Status Word register that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. If specified in section Connections, the product also provides a PG signal output. The PG pin is active high and by default open-drain but may also be configured as push-pull via the PMBus interface. By default, the PG signal will be asserted when the output reaches above 90% of the nominal voltage, and de-asserted when the output Switching Frequency The fundamental switching frequency is 320 kHz, which yields optimal power efficiency. The switching frequency can be set to any value between 200 kHz and 640 kHz using the PMBus interface. The switching frequency will change the efficiency/power dissipation, load transient response and output ripple. For optimal control loop performance in a product without DLC, the control loop must be reoptimized when changing the switching frequency. Synchronization Synchronization is a feature that allows multiple products to be synchronized to a common frequency. Synchronized products powered from the same bus eliminate beat frequencies reflected back to the input supply, and also reduces EMI filtering requirements. Eliminating the slow beat frequencies (usually <10 kHz) allows the EMI filter to be designed to attenuate only the synchronization frequency. Synchronization can also be utilized for phase spreading, described in section Phase Spreading. The products can be synchronized with an external oscillator or one product can be configured with the SYNC pin as a SYNC Output working as a master driving the synchronization. All others on the same synchronization bus must be configured with SYNC Input. Default configuration is using the internal clock, independently of signal at the SYNC pin. Phase Spreading When multiple products share a common DC input supply, spreading of the switching clock phase between the products can be utilized. This dramatically reduces input capacitance requirements and efficiency losses, since the peak current drawn from the input supply is effectively spread out over the whole switch period. This requires that the products are synchronized. Up to 16 different phases can be used. The phase spreading of the product can be configured using the PMBus interface. Parallel Operation (Current Sharing) Paralleling multiple products can be used to increase the output current capability of a single power rail. By connecting the GCB pins of each device and configuring the devices as a current sharing rail, the units will share the current equally, enabling up to 100% utilization of the current capability for each device in the current sharing rail. The product uses a low-bandwidth, first-order digital current sharing by www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 23 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series aligning the output voltage of the slave devices to deliver the same current as the master device. Artificial droop resistance is added to the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and PWB layout. Up to 7 devices can be configured in a given current sharing group. shutdown of the device. The device will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be re-enabled. The load distribution should be designed for the maximum output short circuit current specified. The OCP limit and response of the product can be reconfigured using the PMBus interface. In order to avoid interference with other algorithms executing during parallel operation, the dead-time algorithm should be turned off and fixed dead-times be used. Initialization Procedure The product follows a specific internal initialization procedure after power is applied to the VIN pin: Phase Adding and Shedding for Parallel Operation During periods of light loading, it may be beneficial to disable one or more phases (modules) in order to eliminate the current drain and switching losses associated with those phases, resulting in higher efficiency. The product offers the ability to add and drop phases (modules) using a PMBus command in response to an observed load current change. All phases (modules) in a current share rail are considered active prior to the current sharing rail ramp to power-good. Phases can be dropped after power-good is reached. Any member of the current sharing rail can be dropped. If the reference module is dropped, the remaining active module with the lowest member position will become the new reference. Additionally, any change to the number of members of a current sharing rail will precipitate autonomous phase distribution within the rail where all active phases realign their phase position based on their order within the number of active members. If the members of a current sharing rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared. 1. Status of the address and output voltage pin-strap pins are checked and values associated with the pin settings are loaded to RAM. Efficiency Optimized Dead Time Control The product utilizes a closed loop algorithm to optimize the deadtime applied between the gate drive signals for the switch and synch FETs. The algorithm constantly adjusts the deadtime non-overlap to minimize the duty cycle, thus maximizing efficiency. This algorithm will null out deadtime differences due to component variation, temperature and loading effects. The algorithm can be configured via the PMBus interface. Over Current Protection (OCP) The product includes current limiting circuitry for protection at continuous overload. The following OCP response options are available: 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. Values stored in the Murata default non-volatile memory are loaded to RAM. This overwrites any previously loaded values. 3. Values stored in the user non-volatile memory are loaded to RAM. This overwrites any previously loaded values. Once the initialization process is completed, the product is ready to be enabled using the CTRL pin. The product is also ready to accept commands via the PMBus interface, which will overwrite any values loaded during the initialization procedure. Soft-start Power Up The soft-start control introduces a time-delay before allowing the output voltage to rise. Once the initialization time has passed the device will wait for the configured delay period prior to starting to ramp its output. After the delay period has expired, the output will begin to ramp towards its target voltage according to the configured soft-start ramp time. The default settings for the soft-start delay period and the softstart ramp time is 10 ms. Hence, power-up is completed within 20 ms in default configuration using remote control. When the soft-start delay time is set to 0 ms, the module will begin its ramp-up after the internal circuitry has initialized (approximately 2 ms). It is generally recommended to set the soft-start ramp-up time to a value greater than 500 μs to prevent inadvertent fault conditions due to excessive inrush current. The acctual minimum ramp-up time will however normally be limited by the control loop settings and ramp-up times of internal interface voltages in the controller circuit to approximately 2 ms. The soft-start power up of the product can be reconfigured using the PMBus interface. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. VIN 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. CTRL 4. Continue operating through the fault (this could result in permanent damage to the power supply). VOUT 5. Initiate an immediate shutdown. The default response from an over current fault is an immediate Initialization time Delay time Ramp time Illustration of Power Up Procedure www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 24 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series VOUT VOUT V1 MASTER V2 SLAVE t t Illustration of Ratiometric Voltage Tracking Illustration of Output Voltage Sequencing. Output Voltage Sequencing A group of products may be configured to power up in a predetermined sequence. This feature is especially useful when powering advanced processors, FPGAs, and ASICs that require one supply to reach its operating voltage prior to another. Multi-product sequencing can be achieved by configuring the start delay and rise time of each device through the PMBus interface and by using the CTRL start signal. Voltage Tracking The product integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the VTRK pin with no external components required. During ramp-up, the output voltage follows the VTRK voltage until the preset output voltage level is met. The product offers two modes of tracking as follows: 1. Coincident. This mode configures the product to ramp its output voltage at the same rate as the voltage applied to the VTRK pin. VOUT MASTER SLAVE t Illustration of Coincident Voltage Tracking. 2. Ratiometric. This mode configures the product to ramp its output voltage at a rate that is a percentage of the voltage applied to the VTRK pin. The default setting is 50%, but a different tracking ratio may be set by an external resistive voltage divider or through the PMBus interface. The master device in a tracking group is defined as the device that has the highest target output voltage within the group. This master device will control the ramp rate of all tracking devices and is not configured for tracking mode. All of the CTRL pins in the tracking group must be connected and driven by a single logic source. It should be noted that current sharing groups that are also configured to track another voltage do not offer pre-bias protection; a minimum load should therefore be enforced to avoid the output voltage from being held up by an outside force. Voltage Margining Up/Down The product can adjust its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. This provides a convenient method for dynamically testing the operation of the load circuit over its supply margin or range. It can also be used to verify the function of supply voltage supervisors. Margin limits of the nominal output voltage ±5% are default, but the margin limits can be reconfigured using the PMBus interface. Pre-Bias Startup Capability Pre-bias startup often occurs in complex digital systems when current from another power source is fed back through a dual-supply logic component, such as FPGAs or ASICs. The product family incorporates synchronous rectifiers, but will not sink current during startup, or turn off, or whenever a fault shuts down the product in a pre-bias condition. Pre-bias protection is not offered for current sharing groups that also have voltage tracking enabled. Group Communication Bus The Group Communication Bus, GCB, is used to communicate between products. This dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. The GCB solves the PMBus data rate limitation. The GCB pin on all devices in an application should be connected together. A pull-up resistor is required on the common GCB in order to guarantee the rise time as follows: www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 25 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Eq. 5. = RGCB CGCB ≤ 1μs, where RGCB is the pull up resistor value and CGCB is the bus loading. The pull-up resistor should be tied to an external supply voltage in range from 3.3 to 5 V, which should be present priorμ to or during power-up. Products with P2 as reference OTP: When TP2 as defined in thermal consideration section exceeds 120°C the product will shut down. For products with P2 as a reference for OTP the configured default value in the controller circuit in position P2 is 120°C. If exploring untested compensation or deadtime configurations, it is recommended that 27 Ω series resistors are placed between the GCB pin of each product and the common GCB connection. This will avoid propagation of faults between products potentially caused by hazardous configuration settings. When the configurations of the products are settled the series resistors can be removed. The OTP threshold, hysteresis, and fault response of the product can be reconfigured using the PMBus interface. The fault response can be configured as follows: The GCB is an internal bus, such that it is only connected across the modules and not the PMBus system host. GCB addresses are assigned on a rail level, i.e. modules within the same current sharing group share the same GCB address. Addressing rails across the GCB is done with a 5 bit GCB ID, yielding a theoretical total of 32 rails that can be shared with a single GCB bus. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. Fault spreading The product can be configured to broadcast a fault event over the GCB bus to the other devices in the group. When a non-destructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the GCB bus. The other devices on the GCB bus will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so. 5. Initiate an immediate shutdown. Over Temperature Protection (OTP) The products are protected from thermal overload by an internal over temperature shutdown function in the controller circuit N1, located at position P2 (see section Thermal Consideration). Some of the products that this specification covers use the temperature at position P2 (TP2) as a reference for specified OTP threshold and some use position P1 (TP1) as a reference for specified OTP threshold. See the Over Temperature Protection section in the electrical specification for each product. Products with P1 as reference for OTP: When TP1 as defined in thermal consideration section exceeds approximately 120 °C the product will shut down. The specified OTP threshold and hysteresis are valid for worst case operation regarding cooling conditions, input voltage and output voltage. The actually configured default value in the controller circuit in position P2 is 110 °C, but at worst case operation the temperature is approximately 10 °C higher at position P1. At light load the temperature is approximately the same in position P1 and P2. This means the OTP threshold and hysteresis will be lower at light load conditions when P1 is used as a reference for OTP. 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts (default configuration). 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. 4. Continue operating through the fault (this could result in permanent damage to the power supply). Optimization examples This product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and performance of the product. It is possible to change the configuration file to optimize certain performance characteristics. In the table below is a schematic view on how to change different configuration parameters in order to achieve an optimization towards a wanted performance. Config. parameters Optimized performance Maximize efficiency Increase No change Decrease Control Diode Switching NLR Min. loop emulation pulse frequency threshold bandwidth (DCM) Enable Disable Enable or disable Minimize ripple ampl. Enable or disable Improve load transient response Minimize idle power loss Disable Disable Enable Enable Note 1: The following table, graphs, and waveforms are only examples and valid for OKDX-T/50-W12-001-C. Note 2: In the following table and graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered for load transient. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 26 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Default configuration: Continues Conduction Mode, CCM Pli DCM, DiscontinInput idling power ues Conduction (no load) Mode (diode emulation) DCM with Minimum Pulse Enabled PCTRL Input standby power Load transient peak voltage deviation Vtr1 Load step 25-75-25% of max IO Load transient recovery time ttr1 Load step 25-75-25% of max IO Turned off with CTRL-pin Default configuration di/dt = 2 A/μs CO = 470 μF DLC and Optimized NLR configuration di/dt = 2 A/μs CO = 470 μF Default configuration di/dt = 2 A/μs CO=470 μF DLC and Optimized NLR configuration di/dt = 2 A/μs CO = 470 μF VO = 0.6 V 0.95 VO = 1.0 V 0.95 VO = 1.8 V 1.22 VO = 3.3 V 1.88 VO = 0.6 V 0.21 VO = 1.0 V 0.21 VO = 1.8 V 0.21 VO = 3.3 V 0.21 VO = 0.6 V 0.43 VO = 1.0 V 0.46 VO = 1.8 V 0.54 VO = 3.3 V Default configuration: Monitoring enabled Pulse monitor mode: Monitoring disabled 0.67 Efficiency vs. Output Current and Switching frequency W [%] 95 90 W W 200 kHz 85 320 kHz 80 480 kHz 75 640 kHz 70 0 170 mW 109 mW Low power mode: Monitoring disabled 85 mW VO = 0.6 V 300 VO = 1.0 V 300 VO = 1.8 V 305 VO = 3.3 V 315 0 1 0 2 0 3 50 [A] 40 Efficiency vs. load current and switching frequency at TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 mΩ Default configuration except changed frequency Load transient vs. Switching frequency [mV] 600 Universal PID, No NLR 500 VO = 0.6 V 100 VO = 1.0 V 100 VO = 1.8 V 100 VO = 3.3 V 100 VO = 0.6 V 100 VO = 1.0 V 100 VO = 1.8 V 100 VO = 3.3 V 100 VO = 0.6 V 50 VO = 1.0 V 50 VO = 1.8 V 50 VO = 3.3 V 50 DLC, No NLR 400 mV Universal PID, Default NLR 300 DLC, Default NLR 200 Universal PID, Opt. NLR 100 DLC, Opt. NLR mV 0 200 300 400 500 600 [kHz] Load transient peak voltage deviation vs. frequency. Step-change (12.5-37.5-12.5 A). TP1 = +25 °C, VI = 12 V, VO =1.0 V, CO = 470 μF/10 mΩ μs Power Dissipation vs. Output Current and Switching frequency [W] 12 10 200 kHz 8 6 320 kHz 4 480 kHz 2 640 kHz 0 0 10 0 2 0 3 0 4 50 [A] Dissipated power vs. load current and switching frequency at TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 mΩ Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 27 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Output Load Transient Response, Default Configuration Output Ripple vs. Switching frequency [mVpk-pk] 60 50 0.6 V 40 1.0 V 30 1.8 V 3.3 V 20 10 0 200 300 400 500 600 [kHz] Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 μF/10 mΩ, IO = 50 A resistive load. Default configuration except changed frequency. Output voltage response to load current step-change (12.5-37.5-12.5 A) at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V di/dt=2 A/μs, fsw = 320 kHz, CO = 470 μF/10 mΩ Default configuration (DLC and default NLR) Load Transient vs. Decoupling Capacitance, VO = 1.0 V Output Load Transient Response, DLC and No NLR [mV] 500 Top trace: output voltage (200 mV/div.). Bottom trace: load current (10 A/div.). Time scale: (0.1 ms/div.). Universal PID, No NLR 400 DLC, No NLR 300 Universal PID, Default NLR 200 DLC, Default NLR 100 Universal PID, Opt. NLR DLC, Opt. NLR 0 0 1 2 3 4 5 [mF] Output voltage response to load current step-change (12.5-37.5-12.5 A) at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V di/dt=2 A/μs, fsw = 320 kHz, CO = 470 μF/10 mΩ DLC and no NLR Load transient peak voltage deviation vs. decoupling capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mΩ, TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/μs Load Transient vs. Decoupling Capacitance, VO = 3.3 V [mV] 500 Top trace: output voltage (200 mV/div.). Bottom trace: load current (10 A/div.). Time scale: (0.1 ms/div.). Output Load Transient Response, DLC and Optimized NLR Universal PID, No NLR 400 DLC, No NLR 300 Universal PID, Default NLR 200 DLC, Default NLR 100 Universal PID, Opt. NLR DLC, Opt. NLR 0 0 1 2 3 4 5 [mF] Load transient peak voltage deviation vs. decoupling capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mΩ, TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/μs Output voltage response to load current step-change (12.5-37.5-12.5 A) at: TP1 = +25 °C, VI = 12 V, VO = 1.0 V di/dt=2 A/μs, fsw = 320 kHz, CO = 470 μF/10 mΩ DLC and optimized NLR Top trace: output voltage (200 mV/div.). Bottom trace: load current (10 A/div.). Time scale: (0.1 ms/div.). www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 28 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Thermal Consideration AIR FLOW General The product is designed to operate in different thermal environments and sufficient cooling must be provided to ensure reliable operation. P1 Cooling is achieved mainly by conduction, from the pins to the host board, and convection, which is dependent on the airflow across the product. Increased airflow enhances the cooling of the product. The Output Current Derating graph found in the Output section for each model provides the available output current vs. ambient air temperature and air velocity at specified VI. The product is tested on a 254 x 254 mm, 35 μm (1 oz), test board mounted vertically in a wind tunnel with a cross-section of 608 x 203 mm. The test board has 8 layers. Proper cooling of the product can be verified by measuring the temperature at positions P1 and P2. The temperature at these positions should not exceed the max values provided in the table below. P2 SIP Version:Temperature positions and air flow direction. Definition of reference temperature TP1 The reference temperature is used to monitor the temperature limits of the product. Temperature above maximum TP1, measured at the reference point P1 is not allowed and may cause degradation or permanent damage to the product. TP1 is also used to define the temperature range for normal operating conditions. TP1 is defined by the design and used to guarantee safety margins, proper operation and high reliability of the product. Note that the max value is the absolute maximum rating (non destruction) and that the electrical Output data is guaranteed up to TP1 +95°C. Definition of product operating temperature The product operating temperatures are used to monitor the temperature of the product, and proper thermal conditions can be verified by measuring the temperature at positions P1 and P2. The temperature at these positions (TP1, TP2) should not exceed the maximum temperatures in the table below. The number of measurement points may vary with different thermal design and topology. Temperatures above maximum TP1, measured at the reference point P1 are not allowed and may cause permanent damage. It should also be noted that depending on setting of the over temperature protection (OTP) and operating conditions, the product may shut down before the maximum allowed temperature at TP1 is reached. Position Description Max Temp. P1 Reference point, L1, inductor 125°C* P2 N1, control circuit 125°C* * A guard band of 5 °C is applied to the maximum recorded component temperatures when calculating output current derating curves. AIR FLOW Top view P1 Bottom view P2 Pin layout, top view (component placement for illustration only). Pin 1A, 1B 2A, 2B 3A, 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B 9A 9B 10A 10B Designation VIN GND VOUT VTRK PREF +S −S SA0 GCB SCL SDA VSET SYNC SALERT CTRL PG SA1 Function Input Voltage Power Ground Output Voltage Voltage Tracking input Pin-strap reference Positive sense Negative sense PMBus address pinstrap 0 Group Communication Bus PMBus Clock PMBus Data Output voltage pinstrap Synchronization I/O PMBus Alert Remote Control Power Good PMBus address pinstrap 1 Temperature positions and air flow direction. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 29 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Unused input pins Unused SDA, SCL and GCB pins should still have pull-up resistors as specified. Unused VTRK or SYNC pins should be left open or connected to the PREF pin. SIP Version: Pin layout, top view (component placement for illustration only). Pin 1A, 1B 2A, 2B 3A, 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B 9A 9B 10A 10B Designation VIN GND VOUT +S −S VSET VTRK SALERT SDA SCL SA1 SA0 SYNC PG CTRL GCB PREF Function Input Voltage Power Ground Output Voltage Positive sense Negative sense Output voltage pinstrap Voltage Tracking input PMBus Alert PMBus Data PMBus Clock PMBus address pinstrap 1 PMBus address pinstrap 0 Synchronization I/O Power Good Remote Control Group Communication Bus Pin-strap reference Unused CTRL pin can be left open due to internal pull-up. VSET and SA0/SA1 pins must be used. These pins must have pinstrap resistors or strapping settings as specified. PWB layout considerations The pin-strap resistors, RSET, and RSA0/RSA1 should be placed as close to the product as possible to minimize loops that may pick up noise. Avoid current carrying planes under the pin-strap resistors and the PMBus signals. The capacitor CI (or capacitors implementing it) should be placed as close to the input pins as possible. Capacitor CO (or capacitors implementing it) should be placed close to the load. Care should be taken in the routing of the connections from the sensed output voltage to the S+ and S– terminals. These sensing connections should be routed as a differential pair, preferably between ground planes which are not carrying high currents. The routing should avoid areas of high electric or magnetic fields. Typical Application Circuit Standalone operation with PMBus communication. Top view of product footprint. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 30 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Application Circuit (SIP version) Standalone operation with PMBus communication. Top view of product footprint. Typical Application Circuit (Parallel Operation) www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 31 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series PMBus interface This product provides a PMBus digital interface that enables the user to configure many aspects of the device operation as well as to monitor the input and output voltages, output current and device temperature. The product can be used with any standard two-wire I2C or SMBus host device. In addition, the product is compatible with PMBus version 1.1 and includes an SALERT line to help mitigate bandwidth limitations related to continuous fault monitoring. The product supports 100 kHz bus clock frequency only. The PMBus signals, SCL, SDA and SALERT require passive pull-up resistors as stated in the SMBus Specification. Pull-up resistors are required to guarantee the rise time as follows: Eq. 6. = Rp Cp ≤ 1μs, where Rp is the pull-up resistor value and Cp is the bus loading, the maximum allowed bus load is 400 pF. The pull-up resistor should be tied to an external supply voltage in range from 2.7 to 5.5 V, which should be present prior to or during power-up. If the proper power supply is not available, voltage dividers may be applied. Note that in this case, the resistance in the equation above corresponds to parallel connection of the resistors forming the voltage divider. Monitoring via PMBus It is possible to monitor a wide variety of parameters through the PMBus interface. Fault conditions can be monitored using the SALERT pin, which will be asserted when any number of pre-configured fault or warning conditions occurs. It is also possible to continuously monitor one or more of the power conversion parameters including but not limited to the following: Input voltage (READ_VIN) The Snapshot feature enables the user to read the parameters via the PMBus interface during normal operation, although it should be noted that reading the 22 bytes will occupy the bus for some time. The Snapshot enables the user to store the snapshot parameters to Flash memory in response to a pending fault as well as to read the stored data from Flash memory after a fault has occurred. Automatic store to Flash memory following a fault is triggered when any fault threshold level is exceeded, provided that the specific fault response is to shut down. Writing to Flash memory is not allowed if the device is configured to restart following the specific fault condition. It should also be noted that the device supply voltage must be maintained during the time the device is writing data to Flash memory; a process that requires between 700-1400 μs depending on whether the data is set up for a block write. Undesirable results may be observed if the input voltage of the product drops below 3.0 V during this process. Non-Volatile Memory (NVM) The product incorporates two Non-Volatile Memory areas for storage of the supported PMBus commands; the Default NVM and the User NVM. The Default NVM is pre-loaded with Murata factory default values. The Default NVM is write-protected and can be used to restore the Murata factory default values through the command RESTORE_DEFAULT_ALL. The User NVM is pre-loaded with Murata factory default values. The User NVM is writable and open for customization. The values in NVM are loaded into operational RAM during initialization according to section “Initialization Procedure”, where after commands can be changed through the PMBus Interface. The STORE_USER_ALL command will store the changed parameters to the User NVM. Output voltage (READ_VOUT) Output current (READ_IOUT) Internal junction temperature (READ_TEMPERATURE_1) INITIALIZATION User NVM Factory default Customizable Switching frequency (READ_FREQUENCY) STORE_USER_ALL RESTORE USER ALL Duty cycle (READ_DUTY_CYCLE) In the default configuration monitoring is enabled also when the output voltage is disabled. This can be changed in order to reduce standby power consumption. Snap shot parameter capture This product offers a special feature that enables the user to capture parametric data during normal operation or following a fault. The following parameters are stored: Input voltage Output voltage Output current Internal junction temperature Switching frequency Duty cycle Status registers Default NVM Factory default Write-protected INITIALIZATION RAM RESTORE_DEFAULT_ALL WRITE PMBus interface READ Software tools for design and production Murata provides software tools for configuration and monitoring of this product via the PMBus interface. For more information please contact your local Murata sales representative. PMBus addressing The PMBus address should be configured with resistors connected between the SA0/SA1 pins and the PREF pin, as shown in the www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 32 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series figure below. Recommended resistor values for hard-wiring PMBus addresses are shown in the table. 1% tolerance resistors are required. Addresses listed in the table below are reserved or assigned according to the SMBus specification and may not be usable. Refer to the SMBus specification for further information. SA0 SA1 R SA1 R SA0 PREF Schematic of connection of address resistor. Index 0 1 2 3 4 5 6 7 8 9 10 11 12 Reserved Addresses Address 4Bh is allocated for production needs and cannot be used. RSA [kΩ] 10 11 12.1 13.3 14.7 16.2 17.8 19.6 21.5 23.7 26.1 28.7 31.6 Index 13 14 15 16 17 18 19 20 21 22 23 24 RSA [kΩ] 34.8 38.3 42.2 46.4 51.1 56.2 61.9 68.1 75 82.5 90.9 100 Address (decimal) 0 1 2 3-7 8 9-11 12 40 44-45 55 64-68 72-75 97 120-123 124-127 Comment General Call Address / START byte CBUS address Address reserved for different bus format Reserved for future use SMBus Host Assigned for Smart Battery SMBus Alert Response Address Reserved for ACCESS.bus host Reserved by previous versions of the SMBus specification Reserved for ACCESS.bus default address Reserved by previous versions of the SMBus specification Unrestricted addresses SMBus Device Default Address 10-bit slave addressing Reserved for future use I2C/SMBus – Timing The PMBus address follows the equation below: Eq. 7. PMBus Address (decimal) = 25 x (SA1 index) + (SA0 index) The user can theoretically configure up to 625 unique PMBus addresses, however the PMBus address range is inherently limited to 128. Therefore, the user should use index values 0 - 4 on the SA1 pin and the full range of index values on the SA0 pin, which will provide 125 device address combinations. The user shall also be aware of further limitations of the address space as stated in the SMBus Specification. Note that address 0x4B is allocated for production needs and cannot be used. Optional PMBus Addressing Alternatively the PMBus address can be defined by connecting the SA0/SA1 pins according to the table below. SA1 = open for products with no SA1 pin. SA1 low open high low 20h 23h 26h Low = Shorted to PREF Open = High impedance High = Logic high, GND as reference, Logic High definitions see Electrical Specification SA0 open 21h 24h 27h high 22h 25h Reserved Setup and hold times timing diagram The setup time, tset, is the time data, SDA, must be stable before the rising edge of the clock signal, SCL. The hold time thold, is the time data, SDA, must be stable after the rising edge of the clock signal, SCL. If these times are violated incorrect data may be captured or meta-stability may occur and the bus communication may fail. When configuring the product, all standard SMBus protocols must be followed, including clock stretching. Refer to the SMBus specification, for SMBus electrical and timing requirements. This product does not support the BUSY flag in the status commands to indicate product being too busy for SMBus response. Instead a busfree time delay according to this specification must occur between every SMBus transmission (between every stop & start condition). In case of storing the RAM content into the internal non-volatile memory (commands STORE_USER_ALL and STORE_DEFAULT_ALL) an additional delay of 100 ms has to be inserted. A 100 ms delay should be inserted after a restore from internal non-volatile memory (commands RESTORE_DEFAULT_ALL and RESTORE_USER_ALL). www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 33 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series PMBus Commands The products are PMBus compliant. The following table lists the implemented PMBus read commands. For more detailed information see PMBus Power System Management Protocol Specification; Part I – General Requirements, Transport and Electrical Interface and PMBus Power System Management Protocol; Part II – Command Language. Designation Standard PMBus Commands Control Commands PAGE OPERATION ON_OFF_CONFIG WRITE_PROTECT Output Commands VOUT_MODE (Read Only) VOUT_COMMAND VOUT_TRIM VOUT_CAL_OFFSET VOUT_MAX VOUT_MARGIN_HIGH VOUT_MARGIN_LOW VOUT_TRANSITION_RATE VOUT_DROOP MAX_DUTY FREQUENCY_SWITCH VIN_ON VIN_OFF IOUT_CAL_GAIN IOUT_CAL_OFFSET VOUT_SCALE_LOOP VOUT_SCALE_MONITOR COEFFICIENTS Fault Limit Commands POWER_GOOD_ON POWER_GOOD_OFF VOUT_OV_FAULT_LIMIT VOUT_OV_WARN_LIMIT VOUT_UV_WARN_LIMIT VOUT_UV_FAULT_LIMIT IOUT_OC_FAULT_LIMIT IOUT_OC_WARN_LIMIT IOUT_UC_FAULT_LIMIT OT_FAULT_LIMIT OT_WARN_LIMIT UT_WARN_LIMIT UT_FAULT_LIMIT VIN_OV_FAULT_LIMIT VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT Fault Response Commands VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_RESPONSE OT_FAULT_RESPONSE UT_FAULT_RESPONSE VIN_OV_FAULT_RESPONSE VIN_UV_FAULT_RESPONSE IOUT_OC_FAULT_RESPONSE IOUT_UC_FAULT_RESPONSE Time setting Commands TON_DELAY Cmd Impl 00h 01h 02h 10h No Yes Yes No 20h 21h 22h 23h 24h 25h 26h 27h 28h 32h 33h 35h 36h 38h 39h 29h 2Ah 30h Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No No No 5Eh 5Fh 40h 42h 43h 44h 46h 4Ah 4Bh 4Fh 51h 52h 53h 55h 57h 58h 59h Yes No Yes No No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes 41h 45h 50h 54h 56h 5Ah 47h 4Ch Yes Yes Yes Yes Yes Yes No No 60h Yes Designation TON_RISE TOFF_DELAY TOFF_FALL TON_MAX_FAULT_LIMIT Status Commands (Read Only) CLEAR_FAULTS STATUS_BYTE STATUS_WORD STATUS_VOUT STATUS_IOUT STATUS_INPUT STATUS_TEMPERATURE STATUS_CML STATUS_MFR_SPECIFIC Monitor Commands (Read Only READ_VIN READ_VOUT READ_IOUT READ_TEMPERATURE_1 READ_TEMPERATURE_2 READ_FAN_SPEED_1 READ_DUTY_CYCLE READ_FREQUENCY Group Commands INTERLEAVE PHASE_CONTROL Identification Commands PMBUS_REVISION MFR_ID MFR_MODEL MFR_REVISION MFR_LOCATION MFR_DATE MFR_SERIAL Supervisory Commands STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL STORE_USER_ALL RESTORE_USER_ALL Product Specific Commands Output Commands XTEMP_SCALE XTEMP_OFFSET Time Setting Commands POWER_GOOD_DELAY Fault limit Commands IOUT_AVG_OC_FAULT_LIMIT IOUT_AVG_UC_FAULT_LIMIT Fault Response Commands MFR_IOUT_OC_FAULT_RESPONSE MFR_IOUT_UC_FAULT_RESPONSE OVUV_CONFIG Configuration and Control Commands MFR_CONFIG USER_CONFIG MISC_CONFIG TRACK_CONFIG PID_TAPS PID_TAPS_CALC* INDUCTOR NLR_CONFIG Cmd 61h 64h 65h 62h Impl Yes Yes Yes No 03h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 80h Yes Yes Yes Yes Yes Yes Yes Yes Yes 88h 8Bh 8Ch 8Dh 8Eh 90h 94h 95h Yes Yes Yes Yes No No Yes Yes 37h F0h Yes Yes 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh Yes Yes Yes Yes Yes Yes Yes 11h 12h 15h 16h Yes Yes Yes Yes D9h DAh No No D4h Yes E7h E8h Yes Yes E5h E6h D8h Yes Yes Yes D0h D1h E9h E1h D5h F2h D6h D7h Yes Yes Yes Yes Yes Yes Yes Yes www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 34 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Designation TEMPCO_CONFIG IOUT_OMEGA_OFFSET* AUTO_COMP_CONTROL** AUTO_COMP_CONFIG** DEADTIME DEADTIME_CONFIG DEADTIME_MAX SNAPSHOT SNAPSHOT_CONTROL DEVICE_ID USER_DATA_00 Group Commands SEQUENCE GCB_CONFIG GCB_GROUP ISHARE_CONFIG PHASE_CONTROL Supervisory Commands PRIVATE_PASSWORD PUBLIC_PASSWORD UNPROTECT SECURITY_LEVEL Cmd DCh BEh BDh BCh DDh DEh BFh EAh F3h E4h B0h Impl Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes E0h D3h E2h D2h F0h Yes Yes Yes Yes Yes FBh FCh FDh FAh Yes Yes Yes Yes Notes: Cmd is short for Command. Impl is short for Implemented. * These commands are available in products without DLC. ** These commands are available in products with DLC. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 35 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-THROUGH-HOLE MOUNT All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 36 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-SURFACE MOUNT All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 37 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-SIP VERSION All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 38 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Soldering Information - Surface Mounting and Hole Mount through Pin in Paste Assembly The product is intended for forced convection or vapor phase reflow soldering in SnPb or Pb-free processes. The reflow profile should be optimised to avoid excessive heating of the product. It is recommended to have a sufficiently extended preheat time to ensure an even temperature across the host PWB and it is also recommended to minimize the time in reflow. A no-clean flux is recommended to avoid entrapment of cleaning fluids in cavities inside the product or between the product and the host board, since cleaning residues may affect long time reliability and isolation voltage. General reflow process specifications Average ramp-up (TPRODUCT) Typical solder melting (liquidus) temperature Minimum reflow time above TL Minimum pin temperature Peak product temperature TL TPIN TPRODUCT Average ramp-down (TPRODUCT) Maximum time 25°C to peak SnPb eutectic 3°C/s max 3°C/s max 183°C 221°C 60 s 210°C 225°C 6°C/s max 6 minutes 60 s 235°C 260°C 6°C/s max Pb-free Lead-free (Pb-free) solder processes For Pb-free solder processes, a pin temperature (TPIN) in excess of the solder melting temperature (TL, 217 to 221°C for SnAgCu solder alloys) for more than 60 seconds and a peak temperature of 245°C on all solder joints is recommended to ensure a reliable solder joint. Maximum Product Temperature Requirements Top of the product PWB near pin 10B is chosen as reference location for the maximum (peak) allowed product temperature (TPRODUCT) since this will likely be the warmest part of the product during the reflow process. SnPb solder processes For SnPb solder processes, the product is qualified for MSL 1 according to IPC/JEDEC standard J STD 020C. During reflow TPRODUCT must not exceed 225 °C at any time. Pb-free solder processes For Pb-free solder processes, the product is qualified for MSL 3 according to IPC/JEDEC standard J-STD-020C. 8 minutes During reflow TPRODUCT must not exceed 260 °C at any time. Temperature TPRODUCT maximum TPIN minimum Pin profile TL Product profile Time in reflow Time in preheat / soak zone Time 25°C to peak Dry Pack Information Products intended for Pb-free reflow soldering processes are delivered in standard moisture barrier bags according to IPC/JEDEC standard J STD 033 (Handling, packing, shipping and use of moisture/ reflow sensitivity surface mount devices). Using products in high temperature Pb-free soldering processes requires dry pack storage and handling. In case the products have been stored in an uncontrolled environment and no longer can be considered dry, the modules must be baked according to J STD 033. Time Thermocoupler Attachment Minimum Pin Temperature Recommendations Pin number 2B is chosen as reference location for the minimum pin temperature recommendation since this will likely be the coolest solder joint during the reflow process. Pin 10B for measurement of maximum Product temperature TPRODUCT SnPb solder processes For SnPb solder processes, a pin temperature (TPIN) in excess of the solder melting temperature, (TL, 183°C for Sn63Pb37) for more than 60 seconds and a peak temperature of 220°C is recommended to ensure a reliable solder joint. For dry packed products only: depending on the type of solder paste and flux system used on the host board, up to a recommended maximum temperature of 245°C could be used, if the products are kept in a controlled environment (dry pack handling and storage) prior to assembly. Pin 2B for measurement of minimum Pin (solder joint) temperature TPIN www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 39 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Soldering Information - Hole Mounting The hole mounted product is intended for plated through hole mounting by wave or manual soldering. The pin temperature is specified to maximum to 270°C for maximum 10 seconds. A maximum preheat rate of 4°C/s and maximum preheat temperature of 150°C is suggested. When soldering by hand, care should be taken to avoid direct contact between the hot soldering iron tip and the pins for more than a few seconds in order to prevent overheating. A no-clean flux is recommended to avoid entrapment of cleaning fluids in cavities inside the product or between the product and the host board. The cleaning residues may affect long time reliability and isolation voltage. Delivery Package Information The products are delivered in antistatic carrier tape (EIA 481 standard). Carrier Tape Specifications Material Surface resistance Bakeability Tape width, W Pocket pitch, P1 Pocket depth, K0 Reel diameter Reel capacity Reel weight Antistatic PS <107Ohm/square The tape is not bakable 56 mm [2.20 inch] 32 mm [1.26 inch] 13 mm [0.51 inch] 381 mm [15 inch] 130 products /reel 1.8 kg/full reel www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 40 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Soldering Information - Hole Mounting (SIP version) The product is intended for plated through hole mounting by wave or manual soldering. The pin temperature is specified to maximum to 270°C for maximum 10 seconds. A maximum preheat rate of 4°C/s and maximum preheat temperature of 150°C is suggested. When soldering by hand, care should be taken to avoid direct contact between the hot soldering iron tip and the pins for more than a few seconds in order to prevent overheating. A no-clean flux is recommended to avoid entrapment of cleaning fluids in cavities inside the product or between the product and the host board. The cleaning residues may affect long time reliability and isolation voltage. Delivery Package Information (SIP version) The products are delivered in antistatic trays. Tray Specifications Material Surface resistance Bakability Tray thickness Box capacity Tray weight Antistatic Polyethylene foam 105< Ohms/square <1011 The trays are not bakeable 15 mm [0.709 inch] 100 products, 2 full trays/box) 35 g empty tray, 549 g full tray Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. ISO 9001 and 14001 REGISTERED This product is subject to the following operating requirements and the Life and Safety Critical Application Sales Policy: Refer to: http://www.murata-ps.com/requirements/ Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. © 2016 Murata Power Solutions, Inc. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A04 Page 41 of 41