IBM Research Reliability of advanced CMOS devices and circuits James H. Stathis IBM Thomas J. Watson Research Center Yorktown Heights, NY © 2009 IBM Corporation 1 IBM Research CMOS Scaling Rules Voltage, V / α WIRING tox/α W/α GATE n+ source n+ drain L/α p substrate, doping α*NA SCALING: Voltage: V/α Oxide: tox /α Wire width: W/α Gate width: L/α Diffusion: xd /α Substrate: α NA 2 xd/α R. H. Dennard et al., IEEE J. Solid State Circuits, (1974). RESULTS: Higher Density: ~α2 Higher Speed: ~α Power/ckt: ~1/α2 tox scaling required for short channel control Power Density: ~Constant © 2009 IBM Corporation IBM Research CMOS Scaling Rules Voltage, V / α WIRING tox/α W/α GATE n+ source n+ drain L/α p substrate, doping α*NA SCALING: Voltage: V/α Oxide: tox /α Wire width: W/α Gate width: L/α Diffusion: xd /α Substrate: α NA 3 11Å xd/α R. H. Dennard et al., IEEE J. Solid State Circuits, (1974). RESULTS: Higher Density: ~α2 Higher Speed: ~α Power/ckt: ~1/α2 tox scaling required for short channel control Power Density: ~Constant © 2009 IBM Corporation IBM Research CMOS Scaling Rules Voltage, V / α WIRING tox/α W/α GATE n+ source n+ drain L/α p substrate, doping α*NA SCALING: Voltage: V/α Oxide: tox /α Wire width: W/α Gate width: L/α Diffusion: xd /α Substrate: α NA 4 11Å xd/α R. H. Dennard et al., IEEE J. Solid State Circuits, (1974). RESULTS: Higher Density: ~α2 Higher Speed: ~α Power/ckt: ~1/α2 tox scaling required for short channel control Power Density: ~Constant ¾ Approaching atomistic and quantum-mechanical boundaries ¾ Atoms are not scalable! © 2009 IBM Corporation IBM Research NiSi Device Scaling Conventional bulk device or partially-depleted SOI (PDSOI) – Aggressive gate dielectric scaling for improved short channel control – Increased random doping fluctuations due to width and length scaling – Spacer thickness decreasing • Becoming comparable to old gate dielectric thickness (~10nm) 5 BandPoly edge Gate gate Gate Oxide NiSi Extension Extension SOI Extension Embedded Halo Stressor tSi BOX Si substrate Node Device Pitch (nm) 45 170-180 32 120-130 22 80-100 15 65-80 11 50-65 © 2009 IBM Corporation IBM Research CMOS Scaling: Oxide electric field increasing 10 Field driven wearout increasing 9 7 6 45 nm 5 100 - ΔVmax (mV) Field (MV/cm) 8 4 3 2 1 0 1980 350 nm 4 1985 1990 1995 2000 year published source: IEDM and VLSI 6 65 nm 2005 6 8 10 Eoxide (MV/cm) estimated NBTI at 10 years Eox = (Vgate / telectrical) = (CV/ε) © 2009 IBM Corporation IBM Research Major MOSFET oxide failure mechanisms Bias/Temperature Instability – NBTI – PBTI Dielectric Breakdown 7 © 2009 IBM Corporation IBM Research Negative-bias-temperature instability 8 © 2009 IBM Corporation IBM Research Negative-bias-temperature instability pFET on-state VDD 0v 9 VDD Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate. © 2009 IBM Corporation IBM Research Negative-bias-temperature instability pFET on-state Thermal activation (~0.2eV) VDD 0v 10 VDD Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate. © 2009 IBM Corporation IBM Research Negative-bias-temperature instability pFET on-state Thermal activation (~0.2eV) VDD 0v 11 VDD Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate. Believed to be caused by an electrochemical reaction with a hydrogen related species in the oxide, reacting with holes in the pfet channel. First described by Miura and Matukura. Jpn. J. Appl. Phys., vol. 5, p. 180, 1966. 1966 © 2009 IBM Corporation IBM Research Negative-bias-temperature instability (NBTI) 0.02 – PFET threshold voltage shift -ΔVt (V) Basic features: (a) nitrided oxide SiO2 0.01 • negative threshold voltage (Vt) shift • interface states and positive oxide charge Æ drive current reduction Æ circuit speed reduction 0.00 0 4x10 4 4 8x10 time (sec) – Power law time dependence 10 -1 – Nitrided oxide has larger shift and shallower slope • Nitridation of gate oxide makes it worse “The Negative Bias Temperature Instability in MOS Devices: A Review”, J.H. Stathis and S. Zafar, Microelectronics Reliability, 46, 270-286 (2006). 12 -ΔVt (V) (b) 10 -2 10 -3 10 nitrided oxide SiO2 -4 10 1 2 3 10 10 10 time (sec) 4 10 5 © 2009 IBM Corporation IBM Research NBTI “PBTI” is a Vt shift observed under positive bias (i.e., in n-FET) – Not seen in SiO2/poly under normal use conditions abs(ΔVt) at 100 s (V) “PBTI” in high-k NFET 10 PBTI -1 SiO2/HfO2/TiN (tHfO2= 2.2 nm) 10 -2 SiON/poly-Si (tSiON= 1.3 nm) SiON/poly-Si (tSiON= 1.3 nm) 2.2nm 10 -3 -3 -2 -1 0 1 2 3 Vg-VT (V) 3 2 ΔVt @ Qinj = 10 C/cm (V) – Charge trapping in high-k layer 0.16 Vg = 2.2 V 0.14 0.12 0.10 0.08 0.06 0.04 Vg = 1.8 V 0.02 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 HfO2 Thickness, tHfO2 (nm) S. Pae et al., IRPS 2008. 13 A. Kerber et al., to be published, IEEE Trans. Dev. and Mater. Reliab. © 2009 IBM Corporation IBM Research NBTI and PBTI in SRAM NBTI VDD BR BL PL ‘1’ ‘1’ PR AXL ‘0’ VL WL Static noise margin analysis (butterfly curve) NL ‘1’ VR ‘1’ AXR NR PBTI 14 © 2009 IBM Corporation IBM Research Effect of PBTI on SRAM Initial SNM Vt increase in one nfet – Worst case degradation, SNM decreases Vt increase in both nfets – SNM better than asymmetric case – Not worst-case 15 J.C. Lin, et al., IRPS 2007. © 2009 IBM Corporation IBM Research Effect of combined NBTI & PBTI Relative sensitivity: – SRAM cell is ~2x more sensitive to PBTI compared to NBTI Symmetric degradation of cells leads to little increase in failure probability – Worst case is asymmetric PBTI degradation 1,000 Typical design corner 2 1.8 1.6 1.4 1.2 1 0.8 0 0.5 1 WW 1.5 ::W W PR PL,PR 2 2.5 # of faulty cells in 100MB memory ) δVt,PR δSNM/δV/t,NL (ΔSNM(δ/SNM/ ΔVt,PBTI ) :):((ΔSNM ΔV t,NBTI) 2.2 T=85oC and Vdd=0.9V ΔVt,PR=50mV 100 ΔVt,PR=100mV Worst case 10 Sym. effect 1 NL NL,NR 0.1 0 A. Bansal et al., IRPS 2009. 16 ΔVt,PR=0 20 40 60 ΔVt,NL [mV] 80 100 © 2009 IBM Corporation IBM Research Oxide breakdown Defect generation leading to breakdown Critical defect density (NBD) R. Degraeve et al., TED 45, 904 (1998). 17 © 2009 IBM Corporation IBM Research Statistical Distribution of Breakdown Time-to-Breakdown (TBD), or Charge-to-Breakdown (QBD), is a statistically distributed quantity – Random defect generation The Weibull Distribution is an ‘extreme value’ distribution in ln(x) and is appropriate for a ‘‘weakest-link’’ type of problem. – The weakest link in a chain controls the failure of the whole chain – If any one spot on a dielectric breaks, the entire device is broken – If any transistor fails, the whole circuit or chip fails 18 © 2009 IBM Corporation IBM Research E.Y. Wu et al. Semic. Sci. Technol 15, 425 (2000). Weibull Distribution FBD (t ) = 1 − e ⎛ t ⎞ ⎟⎟ −⎜⎜ ⎝ T63 ⎠ β F is the cumulative failure probability, i.e., the population fraction failed by age x, where x can be either charge or time. The characteristic life T63 corresponds to the charge or time where 63.2% of samples fail, and β is called the slope parameter, or Weibull slope. Plotting W≡ln[-ln(1-F)] against ln(x) gives a straight line with slope β. 19 © 2009 IBM Corporation IBM Research Thickness-dependent Weibull slope a0/2 “Percolation” model tox Defects generated randomly in oxide until a conducting (“percolating”) path is formed – Widely accepted, common to all physical models of defect generation Explains thickness-dependent NBD and Weibull slope Random defect generation Connection from one electrode toward the other R. Degraeve et al., IEDM 1995, p. 866. 20 J. H. Stathis, J. Appl. Phys. 86, 5757 (1999). © 2009 IBM Corporation IBM Research “Progressive” (gradual) breakdown Defect Current (A) Gate breakdown is not a sudden, catastrophic process. It occurs gradually, over a measurable time scale. 100.0µ PFET, -2.1 V, 1.5 nm 80.0µ F. Monsieur et al., 60.0µ 40.0µ 20.0µ 0.0 3.6x106 3.8x106 4.0x106 4.2x106 Microelectron. Reliab. 41, 1035 (2001). B.P. Linder et al., Electron Dev. Lett. vol 23, p. 661 (2002). T. Hosoi et al., IEDM 2002, pp. 155-158 F. Monsieur et al., IRPS2002 and IRPS2003. B.P. Linder et al., IRPS 2003, p. 402. Stress Time (s) 21 © 2009 IBM Corporation IBM Research Weibull distribution plus progressive breakdown ∞ f (t ) = ∫f BD ( t − Δt PBD ) f PBD ( Δt PBD )dΔt PBD 0 Convolution of breakdown time distribution and post-breakdown growth time distribution ¾ Curvature on Weibull plot S. Tous et al., Elec. Dev. Lett. 2008, p. 949. 22 © 2009 IBM Corporation IBM Research Post-breakdown growth time distribution E. Wu et al., IEDM 2007, p. 493. 23 © 2009 IBM Corporation IBM Research Progressive breakdown implications ¾When does a circuit fail? BD BD after T. Hosoi et al., SSDM 2002 pp. 155-158 24 © 2009 IBM Corporation IBM Research Transfer curves of inverters after oxide BD (experiment and model) positive stress 1.2 negative stress -5 5 fresh ~10 ×V A Vout (V) 0.8 -4 2 ~10 ×V A fresh -4 -4 5 ~10 ×V A increasing -V stress 3 ~10 ×V A 0.4 -4 4 ~10 ×V A increasing +V stress -5 measured model 5 ~10 ×V A 0.0 0.0 0.4 0.8 1.2 0.0 0.4 Vin (V) 0.8 1.2 Vin (V) R. Rodríguez et al.: IRPS 2003 p. 11; EDL 24, 114 (2003); ESREF ’03. See further: B. Cheek et al.: IRPS 2004 p. 110. and: H-M. Huang et al., IRPS 2004 p. 593. 25 © 2009 IBM Corporation IBM Research Effect of oxide breakdown on SRAM (model) 1.0 0.9 SNM / SNMfresh 0.8 VL VR 0.7 50% reduction in SNM for BD current > 50 μA 0.6 BD model: 5 I=K×V 0.5 worst case: n-source BD 0.4 0.13μm SRAM (1.2V) drain p-source n-source 0.3 0.2 0.1 0.0 -7 10 -6 10 -5 10 – pulls down voltage at opposite node – loads weaker p-FET -4 10 -3 10 -2 10 -1 10 IBD (A) (current through BD spot for V=Vdd) R. Rodríguez et al., Electron Dev. Lett. 23, 559 (2002). 26 © 2009 IBM Corporation IBM Research Summary: effects of oxide wearout in circuits Negative Bias Temperature Instability (NBTI) Positive Bias Temperature Instability (PBTI) Hot Carrier Injection (HCI) Oxide Breakdown (Progressive Breakdown) – Generally, only one broken gate in a circuit • Breakdown is a statistically rare event – All transistors in circuit may be degraded simultaneously, or particular individuals may be more vulnerable • 27 Depending on circuit history © 2009 IBM Corporation IBM Research Acknowledgements Barry Linder Ernest Wu Aditya Bansal Sufi Zafar Andreas Kerber Ed Cartier – This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. 28 © 2009 IBM Corporation