DG411, DG412, DG413 Data Sheet June 1999 Monolithic Quad SPST, CMOS Analog Switches The DG411 series monolithic CMOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole throw (SPST) analog switches, and TTL and CMOS compatible digital inputs. File Number Features • ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 35Ω • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . <35µW • Fast Switching Action - tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175ns - tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145ns These switches feature lower analog ON resistance (<35Ω) and faster switch time (tON < 175ns) compared to the DG211 or DG212. Charge injection has been reduced, simplifying sample and hold applications. • Low Charge Injection The improvements in the DG411 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40VP-P signals. Power supplies may be single-ended from +5V to +34V, or split from ±5V to ±20V. • Single or Split Supply Operation The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±15V analog input range. The switches in the DG411 and DG412 are identical, differing only in the polarity of the selection logic. Two of the switches in the DG413 (#1 and #4) use the logic of the DG211 and DG411 (i.e., a logic “0” turns the switch ON) and the other two switches use DG212 and DG412 positive logic. This permits independent control of turn-on and turn-off times for SPDT configurations, permitting “break-beforemake” or “make-before-break” operation with a minimum of external logic. • Upgrade from DG211/DG212 • TTL, CMOS Compatible Applications • Audio Switching • Battery Operated Systems • Data Acquisition • Hi-Rel Systems • Sample and Hold Circuits • Communication Systems • Automatic Test Equipment Pinout DG411, DG412, DG413 (PDIP, SOIC) TOP VIEW TRUTH TABLE DG411 LOGIC DG412 DG413 SWITCH SWITCH SWITCH 1, 4 SWITCH 2, 3 0 ON OFF OFF ON 1 OFF ON ON OFF NOTE: 3282.5 Logic “0” ≤0.8V. Logic “1” ≥2.4V. IN1 1 16 IN2 D1 2 15 D2 S1 3 14 S2 V- 4 13 V+ GND 5 12 VL S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 Ordering Information PART NUMBER 1 TEMP. RANGE (oC) PACKAGE PKG. NO. DG411DJ -40 to 85 16 Ld PDIP E16.3 DG411DY -40 to 85 16 Ld SOIC M16.15 DG412DJ -40 to 85 16 Ld PDIP E16.3 DG412DY -40 to 85 16 Ld SOIC M16.15 DG413DJ -40 to 85 16 Ld PDIP E16.3 DG413DY -40 to 85 16 Ld SOIC M16.15 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 DG411, DG412, DG413 Functional Diagrams Four SPST Switches per Package Switches Shown for Logic “1” Input DG411 DG412 S1 IN1 IN1 D1 S2 IN2 IN1 D2 S3 D2 S3 IN3 IN3 D3 S4 IN4 D1 S2 IN2 IN2 IN3 S1 D1 S2 D2 S3 D3 S4 D3 S4 IN4 IN4 D4 Schematic Diagram DG413 S1 D4 D4 (1 Channel) V+ S VVL V+ INX D GND V- Pin Descriptions PIN SYMBOL 1 IN1 Logic Control for Switch 1. DESCRIPTION 2 D1 Drain (Output) Terminal for Switch 1. 3 S1 Source (Input) Terminal for Switch 1. 4 V- 5 GND Negative Power Supply Terminal. Ground Terminal (Logic Common). 6 S4 Source (Input) Terminal for Switch 4. 7 D4 Drain (Output) Terminal for Switch 4. 8 IN4 Logic Control for Switch 4. 9 IN3 Logic Control for Switch 3. 10 D3 Drain (Output) Terminal for Switch 3. 11 S3 Source (Input) Terminal for Switch 3. 12 VL Logic Reference Voltage. 13 V+ Positive Power Supply Terminal (Substrate). 14 S2 Source (Input) Terminal for Switch 2. 15 D2 Drain (Output) Terminal for Switch 2. 16 IN2 Logic Control for Switch 2. 2 DG411, DG412, DG413 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) to (V+) +0.3V Digital Inputs, VS , VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature (Plastic Packages) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max) Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min) Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX , DX , or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (oC) (NOTE 4) (NOTE 5) (NOTE 4) MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS RL = 300Ω, CL = 35pF, VS = ±10V (Figure 1) Turn-ON Time, tON Turn-OFF Time, tOFF 25 - 110 175 ns 85 - - 220 ns 25 - 100 145 ns 85 - - 160 ns Break-Before-Make Time Delay DG413 Only, RL = 300Ω, CL = 35pF (Figure 2) 25 - 25 - ns Charge Injection, Q (Figure 3) CL = 10nF, VG = 0V, RG = 0Ω 25 - 5 - pC OFF Isolation (Figure 5) RL = 50Ω, CL = 5pF, f = 1MHz 25 - 68 - dB 25 - -85 - dB 25 - 9 - pF Drain OFF Capacitance, CD(OFF) 25 - 9 - pF Channel ON Capacitance, CD(ON) + CS(ON) 25 - 35 - pF Crosstalk (Channel-to-Channel), (Figure 4) Source OFF Capacitance, CS(OFF) f = 1MHz (Figure 6) DIGITAL INPUT CHARACTERISTICS Input Current VIN Low, IIL VIN Under Test = 0.8V, All Others = 2.4V Full -0.5 0.005 0.5 µA Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -0.5 0.005 0.5 µA ± 10mA Full -15 - 15 V ± 10mA, VD = ±8.5V, V+ = 13.5V, V- = -13.5V 25 - 25 35 Ω Full - - 45 Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG IS = Drain-Source ON Resistance, rDS(ON) IS = 3 DG411, DG412, DG413 Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified (Continued) TEMP (oC) TEST CONDITIONS V+ = 16.5V, V- = -16.5V, VD = ±15.5V, VS = Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) ± PARAMETER 15.5V V+ = 16.5V, V- = -16.5V, VS = VD = ±15.5V Channel ON Leakage Current, ID(ON) + IS(ON) (NOTE 4) (NOTE 5) (NOTE 4) MIN TYP MAX UNITS 25 -0.25 ±0.1 0.25 nA Full -5 - +5 nA 25 -0.25 ±0.1 0.25 nA Full -5 - +5 nA 25 -0.4 ±0.1 0.4 nA Full -10 - +10 nA 25 - 0.0001 1 µA - 5 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V 85 Negative Supply Current, I- Logic Supply Current, IL Ground Current, IGND Electrical Specifications 25 -1 -0.0001 - µA 85 -5 - - µA 25 - 0.0001 1 µA 85 - - 5 µA 25 -1 -0.0001 - µA 85 -5 - - µA (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (oC) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS 25 - 175 250 ns 85 - - 315 ns 25 - 95 125 ns 85 - - 140 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON RL = 300Ω, CL = 35pF, VS = 8V, (Figure 1) Turn-OFF Time, tOFF Break-Before-Make Time Delay DG413 Only, RL = 300Ω, CL = 35pF, VS = 8V 25 - 25 - ns Charge Injection, Q CL = 10nF, VG = 6.0V, RG = 0Ω 25 - 25 - pC Full 0 - 12 V 25 - 40 80 Ω Full - - 100 Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) IS = -10mA, VD = 3V, 8V V+ = 10.8V 4 DG411, DG412, DG413 Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (oC) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS 25 - 0.0001 1 µA - 5 µA -0.0001 - µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13.2V, V- = 0V VIN = 0V or 5V Negative Supply Current, I- Logic Supply Current, IL Ground Current, IGND 85 25 -1 85 -5 - - µA 25 - 0.0001 1 µA 85 - - 5 µA 25 -1 -0.0001 - µA 85 -5 - - µA NOTES: 3. VIN = input voltage to perform proper function. 4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Test Circuits and Waveforms VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. 50% 0V V+ SWITCH OUTPUT D1 S1 VO IN1 SWITCH INPUT VS SWITCH OUTPUT +15V VL SWITCH INPUT tOFF VO +5V tr < 20ns tf < 20ns 3V LOGIC INPUT 90% 90% RL LOGIC INPUT CL V- GND -15V 0V tON NOTE: Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all IN and S. For load conditions, see Specifications. CL includes fixture and stray RL capacitance. V O = V S -----------------------------------R L + r DS ( ON ) FIGURE 1A. MEASUREMENTS POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES 3V LOGIC INPUT SWITCH OUTPUT (V01) VL 0V VS1 V+ 90% D1 S2 D2 VS2 = 10V 0V VS2 RL2 300Ω IN1 , IN2 LOGIC INPUT GND 0V tD tD FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME 5 +15V S1 VS1 = 10V 90% SWITCH OUTPUT VO2 +5V V-15V VO1 VO2 RL1 300Ω CL1 35pF CL2 35pF CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUITS DG411, DG412, DG413 Test Circuits and Waveforms (Continued) SWITCH OUTPUT V+ RG D1 ∆VO VO INX VG OFF ON OFF OFF ON Q = ∆VO x CL OFF CL VVIN = 3V INX GND NOTE: INX dependent on switch configuration, input polarity determined by sense of switch. FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. CHARGE INJECTION C SIGNAL GENERATOR V+ +15V C SIGNAL GENERATOR 0dBm VS VD 50Ω 0V, 2.4V IN1 IN2 0V, 2.4V VD ANALYZER RL V- GND 0V, 2.4V V- C -15V -15V FIGURE 4. CROSSTALK TEST CIRCUIT FIGURE 5. OFF ISOLATION TEST CIRCUIT +15V C V+ VS INX 0V, 2.4V IMPEDANCE ANALYZER VD f = 1MHz GND V- C -15V FIGURE 6. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT 6 VS VD ANALYZER C GND +15V INX NC RL 0dBm V+ DG411, DG412, DG413 Application Information Summing Amplifier When driving a high impedance, high capacitance load such as shown in Figure 7, where the inputs to the summing amplifier have some noise filtering, it is necessary to have shunt switches for rapid discharge of the filter capacitor, thus preventing offsets from occurring at the output. Single Supply Operation The DG411, DG412, DG413 can be operated with unipolar supplies from 5V to 44V. These devices are characterized and tested for single supply operation at 12V to facilitate the majority of applications. To function properly, 12V is tied to Pins 13 and 0V is tied to Pin 4. Pin 12 still requires 5V for TTL compatible switching. R1 R2 VIN1 C1 R5 R3 R4 VIN2 + R6 C2 DG413 FIGURE 7. SUMMING AMPLIFIER 7 VOUT DG411, DG412, DG413 Typical Performance Curves 45 40 rDS(ON) (Ω) 35 A: B: C: D: E: F: 240 ±5V ±8V ±10V ±12V ±15V ±20V V+ = 15V, V- = -15V VL = 5V, VS = 10V 210 A 180 tON , tOFF (ns) 50 B 30 C 25 D E 20 F 15 150 tON 120 tOFF 90 60 10 30 5 TA = 25oC 0 -20 -15 -10 -5 0 5 10 15 0 -55 20 -35 -15 FIGURE 8. ON RESISTANCE vs VD AND POWER SUPPLY VOLTAGE 25 45 65 85 105 125 FIGURE 9. SWITCHING TIME vs TEMPERATURE 40 30 5 TEMPERATURE (oC) DRAIN VOLTAGE (V) 100mA V+ = 15V, V- = -15V VL = 5V, TA = 25oC 10mA V+ = 15V, V- = -15V VL = 5V 20 ID(OFF) 0 1mA ISUPPLY IS , ID (pA) 10 IS(OFF) -10 ID(ON) + IS(ON) -20 I+, I- 100µA 4SW 10µA IL -30 1µA 4SW -40 100nA -50 -10 -5 0 VS, VD (V) 5 10 10nA 10 15 100 1K 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 10. LEAKAGE CURRENTS vs ANALOG VOLTAGE FIGURE 11. SUPPLY CURRENT vs INPUT SWITCHING FREQUENCY 100 80 1SW 1SW -60 -15 140 V+ = 15V, V- = -15V VL = 5V 120 V+ = 15V, V- = -15V VL = 5V CL = 10nF 100 60 80 CL = 10nF Q (pC) Q (pC) 40 20 CL = 1nF 60 40 20 0 0 -20 CL = 1nF -20 -40 -60 -15 -40 -10 -5 0 5 10 15 VS (V) FIGURE 12. CHARGE INJECTION vs SOURCE VOLTAGE 8 -60 -15 -10 -5 0 5 10 VD (V) FIGURE 13. CHARGE INJECTION vs DRAIN VOLTAGE 15 DG411, DG412, DG413 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2760µm x 1780µm x 485µm Type: Nitride Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: SiAl Thickness: 12kÅ ±1kÅ 1.5 x 105 A/cm2 Metallization Mask Layout DG411, DG412, DG413 D1 (2) IN1 (1) IN2 (16) (15) D2 (14) S2 S1 (3) (13) V+ SUBSTRATE V- (4) (12) VL GND (5) (11) S3 S4 (6) (7) D4 9 (8) IN4 (9) IN3 (10) D3 DG411, DG412, DG413 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 18.66 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 10 MILLIMETERS 0.204 0.355 - 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 16 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 16 6 7 4 9 Rev. 0 12/93 DG411, DG412, DG413 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- α e B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MAX MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e A1 MIN 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 16 0o 16 8o 0o 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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