ISL84521, ISL84522, ISL84523 ® Data Sheet September 2002 Low-Voltage, Single and Dual Supply, Quad SPST, Analog Switches FN6031 Features • Drop-in Replacements for MAX4521 - MAX4523 The Intersil ISL84521–ISL84523 devices are CMOS, precision, quad analog switches designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. Targeted applications include battery powered equipment that benefit from the devices’ low power consumption (<1µW), low leakage currents (1nA max), and fast switching speeds (tON = 45ns, tOFF = 15ns). A12Ω maximum RON flatness ensures signal fidelity, while channel-to-channel mismatch is guaranteed to be less than 4Ω. The 3mm x 3mm Quad NoLead Flatpack (QFN) package alleviates board space limitations, making this newest line of low-voltage switches an ideal solution. The ISL84521/ISL84522/ISL84523 are quad single-pole/ single-throw (SPST) devices. The ISL84521 has four normally closed (NC) switches; the ISL84522 has four normally open (NO) switches; the ISL84523 has two NO and two NC switches and can be used as a dual SPDT, or a dual 2:1 multiplexer. Table 1 summarizes the performance of this family. For higher performance, pin compatible versions, see the ISL43140-42 data sheet. TABLE 1. FEATURES AT A GLANCE ISL84521 ISL84522 ISL84523 Number of Switches 4 4 4 Configuration All NC All NO 2 NC / 2 NO ±5V RON 65Ω 65Ω 65Ω ±5V tON / tOFF 45ns / 15ns 45ns / 15ns 45ns / 15ns 5V RON 125Ω 125Ω 125Ω 5V tON / tOFF 60ns / 20ns 60ns / 20ns 60ns / 20ns 3V RON 260Ω 260Ω 260Ω 3V tON / tOFF 120ns / 40ns 120ns / 40ns 120ns / 40ns Packages 16 Ld SOIC (N), 16 Ld 3x3 QFN, 16 Ld TSSOP • Four Separately Controlled SPST Switches • Pin Compatible with DG411/DG412/DG413 • ON Resistance (RON Max.) . . . . . . . . . . . . . . . . . . . 100Ω • RON Matching Between Channels. . . . . . . . . . . . . . . . . . <1Ω • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<1µW • Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA • Fast Switching Action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns • Minimum 2000V ESD Protection per Method 3015.7 • TTL, CMOS Compatible Applications • Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Communications Systems - Military Radios - RF “Tee” Switches • Test Equipment - Ultrasound - Electrocardiograph • Heads-Up Displays • Audio and Video Switching • General Purpose Circuits - +3V/+5V DACs and ADCs - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved ISL84521, ISL84522, ISL84523 (Note 1) IN1 IN2 COM2 15 COM2 16 15 14 13 GND 5 12 N.C. NC4 6 11 NC3 10 COM3 1 12 NC2 V- 2 11 V+ GND 3 10 N.C. NC4 4 9 9 IN3 COM2 15 COM2 16 15 14 13 13 V+ V- 4 GND 5 12 N.C. NO4 6 11 NO3 10 COM3 COM4 7 ISL84522 (QFN) TOP VIEW 16 IN2 14 NO2 NO1 3 NO1 1 12 NO2 V- 2 11 V+ GND 3 10 N.C. NO4 4 9 9 IN3 5 COM4 IN4 8 8 IN2 COM1 2 7 IN1 IN1 1 6 COM1 ISL84522 (SOIC, TSSOP) TOP VIEW 5 IN2 COM2 ISL84523 (QFN) TOP VIEW 15 COM2 16 15 14 13 13 V+ V- 4 NO3 8 16 IN2 14 NC2 NO1 3 7 IN1 IN1 1 6 COM1 ISL84523 (SOIC, TSSOP) TOP VIEW COM1 2 NC3 COM3 IN4 8 IN3 COM4 7 NC1 COM3 13 V+ V- 4 IN3 14 NC2 NC1 3 IN4 COM1 2 16 IN2 IN4 IN1 1 ISL84521 (QFN) TOP VIEW COM1 ISL84521 (SOIC, TSSOP) TOP VIEW COM4 Pinouts NO1 1 12 NC2 V- 2 11 V+ GND 3 10 N.C. 10 COM3 NO4 4 9 COM4 7 9 IN3 IN4 8 NOTE: 1. Switches Shown for Logic “0” Input. 2 5 6 7 8 COM3 11 NC3 IN3 NO4 6 IN4 12 N.C. COM4 GND 5 NC3 ISL84521, ISL84522, ISL84523 Truth Table ISL84521 LOGIC ISL84522 ISL84523 SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3 0 ON OFF OFF ON 1 OFF ON ON OFF NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V. Pin Descriptions PIN FUNCTION V+ Positive Power Supply Input V- Negative Power Supply Input. Connect to GND for Single Supply Configurations. GND Ground Connection IN Digital Control Input COM Analog Switch Common Pin NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin N.C. No Internal Connection Ordering Information PART NO. (BRAND) (NOTE 2) TEMP. RANGE (oC) PACKAGE PKG. NO. ISL84521IB -40 to 85 16 Ld SOIC (N) M16.15 ISL84521IR* (521I) -40 to 85 16 Ld QFN L16.3x3 ISL84521IV -40 to 85 16 Ld TSSOP M16.173 ISL84522IB -40 to 85 16 Ld SOIC (N) M16.15 ISL84522IR* (522I) -40 to 85 16 Ld QFN L16.3x3 ISL84522IV -40 to 85 16 Ld TSSOP M16.173 ISL84523IB -40 to 85 16 Ld SOIC (N) M16.15 ISL84523IR* (523I) -40 to 85 16 Ld QFN L16.3x3 ISL84523IV -40 to 85 16 Ld TSSOP M16.173 NOTES: 2. Most surface mount devices are available on tape and reel; add “-T” to suffix. * In Development. 3 ISL84521, ISL84522, ISL84523 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V All Other Pins (Note 3) . . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV Thermal Resistance (Typical, Note 4) Operating Conditions Temperature Range ISL8452XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC θJA (oC/W) 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 75 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Moisture Sensitivity (See Technical Brief TB363) All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Storage Temperature Range. . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC and TSSOP - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications: ±5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 6) MIN Full V- - V+ V 25 - 65 100 Ω TYP (NOTE 6) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON VS = ±5V, ICOM = 1.0mA, VCOM = ±3V, See Figure 5 Full - - 125 Ω RON Matching Between Channels, ∆RON VS = ±5V, ICOM = 1.0mA, VCOM = ±3V 25 - 1 4 Ω Full - - 6 Ω RON Flatness, RFLAT(ON) VS = ±5V, ICOM = 1.0mA, VCOM = ±3V, Note 8 25 - 7 12 Ω Full - - 15 Ω nA NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, Note 7 COM OFF Leakage Current, ICOM(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, Note 7 COM ON Leakage Current, ICOM(ON) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, Note 7 25 -1 0.01 1 Full -10 - 10 nA 25 -1 0.01 1 nA Full -10 - 10 nA 25 -2 0.01 2 nA Full -20 - 20 nA Full - 1.6 2.4 V DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH, IINL Full 0.8 1.6 - V VS = ±5.5V, VIN = 0V or V+ Full -1 0.03 1 µA VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 45 80 ns Full - - 100 ns VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 15 30 ns Full - - 40 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay (ISL84523), tD VS = ±5.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 25 5 20 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 5 pC NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 2 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 2 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 5 - pF 4 ISL84521, ISL84522, ISL84523 Electrical Specifications: ±5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, See Figures 4 and 6 Crosstalk, Note 9 TEMP (oC) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS 25 - >90 - dB 25 - <-90 - dB Full ±2 - ±6 V 25 -1 0.05 1 µA Full -1 - 1 µA 25 -1 0.05 1 µA Full -1 - 1 µA POWER SUPPLY CHARACTERISTICS Power Supply Range VS = ±5.5V, VIN = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, INOTES: 5. VIN = Input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 8. Flatness is defined as the delta between the maximum and minimum RON values over the specified voltage range. 9. Between any two switches. Electrical Specifications: 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 6) TYP Full 0 - V+ V MAX (NOTE 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, See Figure 5 25 - 125 200 Ω Full - - 250 Ω RON Matching Between Channels, ∆RON V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V 25 - 2 8 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, Note 7 COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, Note 7 COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, Note 7 ON Resistance, RON Full - - 10 Ω 25 -1 0.01 1 nA Full -10 - 10 nA 25 -1 0.01 1 nA Full -10 - 10 nA 25 -2 - 2 nA Full -20 - 20 nA DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Full - 1.6 2.4 V Input Voltage Low, VINL Full 0.8 1.6 - V V+ = 5.5V, VIN = 0V or V+ Full -1 0.03 1 µA Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 60 100 ns Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Full - - 150 ns 25 - 20 50 ns Full - - 75 ns Break-Before-Make Time Delay (ISL84523), tD V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 25 10 30 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 5 pC 25 -1 0.05 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- 5 Full -1 - 1 µA 25 -1 0.05 1 µA Full -1 - 1 µA ISL84521, ISL84522, ISL84523 Electrical Specifications: 3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 6) Full 0 - V+ V 25 - 260 500 Ω Full - - 600 Ω Full - 1.6 2.4 V TYP MAX (NOTE 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 2.7V, ICOM = 0.1mA, VNO or VNC = 1V DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH, IINL Full 0.8 1.6 - V V+ = 3.6V, VIN = 0V or V+ Full -1 0.03 1 µA V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to V+, See Figure 1 25 - 120 250 ns Full - - 300 ns V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to V+, See Figure 1 25 - 40 80 ns Full - - 100 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay (ISL84523), tD V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 25 15 50 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 0.5 5 pC POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- 25 -1 0.05 1 µA Full -1 - 1 µA 25 -1 0.05 1 µA Full -1 - 1 µA Test Circuits and Waveforms 3V LOGIC INPUT V+ tr < 20ns tf < 20ns 50% 0V C tOFF VNX SWITCH VNX INPUT VOUT 90% SWITCH OUTPUT C SWITCH INPUT VOUT NO or NC COM IN 90% RL 300Ω GND 0V LOGIC INPUT tON V- Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES 6 C CL 35pF ISL84521, ISL84522, ISL84523 Test Circuits and Waveforms (Continued) V+ SWITCH OUTPUT VOUT ∆VOUT RG C VOUT COM NO or NC 3V ON ON LOGIC INPUT OFF 0V VG GND C Q = ∆VOUT x CL Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 2A. MEASUREMENT POINTS IN CL LOGIC INPUT V- Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ C C 3V LOGIC INPUT 0V VOUT1 NO1 VNX COM1 VOUT2 RL1 300Ω NC2 COM2 IN1 90% 90% SWITCH OUTPUT VOUT1 0V RL2 300Ω IN2 90% SWITCH OUTPUT VOUT2 0V 90% LOGIC INPUT CL2 35pF GND tD tD CL1 35pF C V- CL includes fixture and stray capacitance. Reconfigure accordingly to test SW3 and SW4. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY) V+ V+ C C RON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX IN 0V or 2.4V 1mA COM ANALYZER COM GND GND RL V- C Repeat test for all switches. V- Repeat test for all switches. FIGURE 4. OFF ISOLATION TEST CIRCUIT 7 0.8V or 2.4V IN V1 FIGURE 5. RON TEST CIRCUIT C ISL84521, ISL84522, ISL84523 Test Circuits and Waveforms (Continued) V+ V+ C SIGNAL GENERATOR NO1 or NC1 50Ω COM1 NO or NC IN2 IN 0V or 2.4V IN2 0V or 2.4V COM2 ANALYZER NO CONNECTION NO2 or NC2 0V or 2.4V IMPEDANCE ANALYZER COM GND GND RL V- C FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Description The ISL84521–ISL84523 quad analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (65Ω) and high speed switching (tON = 45ns, tOFF = 15ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (1µW), low leakage currents (1nA max), and the tiny QFN packaging. High frequency applications also benefit from the wide bandwidth, and the very high OFF isolation and crosstalk rejection. V- FIGURE 7. CAPACITANCE TEST CIRCUIT unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM Supply Sequencing And Overvoltage Protection As with any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (see Figure 8). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is 8 VOPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL8452X construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL8452X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies, and bipolar supplies need not be symmetrical. The minimum recommended ISL84521, ISL84522, ISL84523 supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance Curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals, so switch parameters especially RON - are strong functions of both supplies. Logic-Level Thresholds V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.5V to 10V. At 12V the VIH level is about 2.7V, so for best results use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 300MHz (see Figure 15), with a small signal -3dB bandwidth in excess of 400MHz, and a large signal bandwidth exceeding 300MHz. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. OFF Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high OFF Isolation and Crosstalk rejection provided by this family. At 10MHz, OFF isolation is about 50dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease OFF Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. Typical Performance Curves TA = 25oC, Unless Otherwise Specified 90 70 60 40 250 85oC 200 25oC 150 -40oC 100 V- = 0V 200 85oC 150 25oC 85oC 25oC -40oC -40oC 85oC 175 125 85oC 110 3 4 5 6 7 8 V+ (V) 9 10 11 FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE 9 12 50 V+ = 5V 25oC V+ = 3.3V -40oC V- = 0V V- = 0V 25oC 80 0 V+ = 2.7V V- = 0V 50 225 75 140 100 50 ICOM = 1mA 250 RON (Ω) RON (Ω) 50 300 VCOM = (V+) - 1V ICOM = 1mA V- = -5V 80 -40oC 0 1 2 3 VCOM (V) 4 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE 5 ISL84521, ISL84522, ISL84523 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) 180 140 85oC 25oC 100 2.5 -40oC V+ = 3.3V VS = ±3V 100 85oC 80 25oC 60 -40oC 40 90 VS = ±5V -5 25oC 50 -40oC -4 -3 -2 -1 0 1 VCOM (V) 2 3 4 -7.5 -5 5 -2.5 0 VCOM (V) 5 FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE 250 125 25oC VCOM = (V+) - 1V V- = -5V 100 25 tOFF (ns) -40oC 0 300 V- = 0V 250 200 85oC 150 0 2 3 0 50 V- = 0V 40 85oC 25oC 20 -40oC 4 5 6 7 8 9 10 11 10 12 85oC -40oC 30 25oC 100 50 25oC 50 85oC -40oC 2 3 4 5 6 V+ (V) 7 8 9 10 11 FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE -10 VS = ±5V VIN = 0.2VP-P GAIN 0 -30 VIN = 0.2VP-P 45 90 VIN = 5VP-P 135 180 RL = 50Ω 10 100 FREQUENCY (MHz) FIGURE 15. FREQUENCY RESPONSE 10 600 CROSSTALK (dB) 0 PHASE (DEGREES) VIN = 5VP-P PHASE 10 V+ = 3V to 12V or -20 VS = ±2V to ±5V 3 -3 12 V+ (V) FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE 1 VCOM = (V+) - 1V V- = -5V -40oC 75 25oC 50 25oC 100 -40oC 150 NORMALIZED GAIN (dB) 2.5 20 RL = 50Ω 30 -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 CROSSTALK -90 90 -100 -110 1k OFF ISOLATION (dB) -5 200 tON (ns) V+ = 5V 2.5 VS = ±5V 85oC 70 0 Q (pC) RON (Ω) 60 120 30 5 VS = ±2V ICOM = 1mA 100 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 16. CROSSTALK AND OFF ISOLATION 110 500M ISL84521, ISL84522, ISL84523 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: ISL84521: 188 ISL84522: 188 ISL84523: 188 PROCESS: Si Gate CMOS 11 ISL84521, ISL84522, ISL84523 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA 0.25(0.010) M H 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M 0.10(0.004) C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 12 MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS MAX A1 e C MIN α 16 0° 16 8° 0° 7 8° Rev. 0 12/93 ISL84521, ISL84522, ISL84523 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N INDEX AREA E 0.25(0.010) M E1 2 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M SEATING PLANE L A D -C- α e A1 b 0.10(0.004) M 0.25 0.010 A2 c 0.10(0.004) C A M B S SYMBOL MIN MAX MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.193 0.201 4.90 5.10 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC E 0.246 L 0.0177 N NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 13 MILLIMETERS α 0.65 BSC 0.256 6.25 0.0295 0.45 16 0° - 0.75 6 16 8° 0° - 6.50 7 8° Rev. 0 6/98 ISL84521, ISL84522, ISL84523 Quad No-Lead Flatpack (QFN) 2X L16.3x3 0.15 C A D A 16 LEAD QUAD NO-LEAD FLAT PACKAGE (COMPLIANT TO JEDEC MO-220-VEEC ISSUE C) D/2 MILLIMETERS D1 D1/2 2X N 6 0.50 DIA. 0.15 C B 1 2 3 E1/2 E/2 E1 0.15 C A NOTES 0.90 - A1 - - 0.05 - A2 - - 0.70 - 0.35 5,8 0.20 REF 0.23 3.00 BSC - 2.75 BSC - E2 0 NX C 0.95 A3 SIDE VIEW A1 1.25 - 2.75 BSC 0.95 1.10 1.25 0.65 BSC k 0.25 L 0.50 - 0.60 - - 0.75 8 2 0.10 M C A B Nd 4 3 8 Ne 4 3 7 NX k D2 2 N P - - 0.60 - θ - - 12 - 4X P Rev. 0 6/01 1 NOTES: 2 3 (Ne-1)Xe REF. E2 E2/2 NX L 1. Dimensioning and tolerancing per ASME Y14.5-1994. 7 2. N is the number of terminals. 8 3. Nd is the number of terminals in the X direction, and Ne is the number of terminals in the Y direction. 4. Controlling dimension: Millimeters. Converted dimensions to inches are not necessarily exact. Angles are in degrees. e (Nd-1)Xe REF. C BOTTOM VIEW C L 7,8 16 D2 8 7,8 N 5 4X P 1.10 3.00 BSC e 0.05 C - D E1 A 0.28 D1 E A2 NX b MAX - D2 2X SEATING PLANE NOMINAL - b B TOP VIEW MIN A A3 E 0.15 C B 2X SYMBOL 5. Dimension b applies to the plated terminal and is measured between 0.20mm and 0.25mm from the terminal tip. C A1 NX b C L 5 6. The Pin #1 identifier exists on the top surface as an indentation mark in the molded body. SECTION "C-C" e e TERMINAL TIP FOR ODD TERMINAL/SIDE 7. Dimensions D2 and E2 are the maximum exposed pad dimensions for improved grounding and thermal performance. 8. Nominal dimensions provided to assist with PCB Land Pattern Design efforts, see Technical Brief TB389. FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14