Ultrafast, Low Noise, Low Dropout Linear Regulators Running in Parallel Produce Clean, Efficient, High Current Point-of-Load Power for FPGA and Server Backplanes Kelly Consoer The latest FPGAs and processors have migrated to deep submicron geometries with gigahertz+ data rates and integrated telemetry channels that operate from 0.9V to 1.8V supply rails. The transient power demand for these processors can reach more than 10A peak current in nanoseconds. At these processor speeds and high currents even the local PCB backplane impedances around the processor can contribute to supply droop, where millivolts of supply droop or supply noise can degrade data integrity. To manage the system power distribution, switching regulators may be used locally to downconvert from a higher voltage rail. These regulators are traditionally bypassed with a large quantity of bulk caps to reduce ripple and buffer the load transients. Unfortunately, bulk tantalum and electrolytic caps have parasitic ESL and ESR that limits their ability to bypass fast high current load transients. To a lesser extent, even large ceramic caps are bandwidth limited by their inherent ESL. The LT3070 and LT3071 family of UltraFast™ transient response, low noise, low dropout linear regulators addresses this challenge. The high bandwidths of the LT3070 and LT3071 reduce the supply impedance at the point-of-load using Figure 1. Paralleled LT3070s with VIOC control of upstream LTC3415 switcher implementation VBIAS 3.3V CIN1 100µF 6.3V ×2 0.1µF 49.9k 1Ω CBIAS1 4.7µF SVIN PGOOD RUN PVIN L1 0.2µH SVIN TRACK SW PHMODE EN 1.3V/7A IN CIN2 22µF VO0 LT3070 OUT COUT1 2.2µF* COUT2 4.7µF* VOUT 1V 3.5A COUT3 10µF* RTRACE 3mΩ CONTROLLED *X5R OR X7R CAPACITORS MARGTOL CLKIN LTC3415 MGN MARGSEL BSEL VIOC VFB SGND MODE ITHM ITH SGND 17.4k 1% 15k 1% 1nF CBULK 100µF 6.3V ×2 EN BIAS IN NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 AND LT3070 ×2 ON SAME PCB POWER PLANE CBULK: TDK C3225X5ROJ107M CIN1: TDK C3225X5ROJ107M CIN2’ CIN3: TDK C2012X5R1A226K COUT1’ COUT4: TDK C2012X5R1A225K COUT2’ COUT5: TDK C2012X5R1A475K COUT3’ COUT6: TDK C2012X5R1A106K CBIAS1’ CBIAS2: TDK C2012X5R1A475K L1: IHLP-2525CZ-01 RREF/BYP: GRM155R71E103K ALL RESISTORS ARE 1%, 0402 CASE SIZE, UNLESS OTHERWISE NOTED P.O.L. 1 REF/BYP GND RREF/BYP1 0.01µF CIN3 22µF 20k P.O.L. 2 VO0 RTRACE 3mΩ CONTROLLED PWRGD SENSE LT3070 OUT VO1 VO2 COUT4 2.2µF* MARGSEL VIOC 2k 4.7nF 1nF COUT5 4.7µF* *X5R OR X7R CAPACITORS MARGTOL 10k POWER PLANE 1V/7A CBIAS2 4.7µF PGND 28 | July 2010 : LT Journal of Analog Innovation PWRGD SENSE VO1 VO2 PLLLPF CLKOUT BIAS PWRGD REF/BYP GND RREF/BYP1 0.01µF COUT6 10µF* VOUT 1V 3.5A design ideas Figure 2. Two paralleled LT3070s clean up the power produced by an LTC3415 switching regulator with minimal impact on efficiency and board real estate only a few small, low ESR, ceramic capacitors, saving bulk capacitance and cost. These linear regulators supply up to 5A of output current with a typical dropout voltage of 85mV. A 0.01µF reference bypass capacitor decreases output voltage noise to 25µVRMS, yielding an output that is not only responsive but also very quiet. The LT3070 and LT3071 incorporate a unique VIOC tracking function to control the switching regulator powering the input. The LT3070 has digital controls that allow the user to margin the system output voltage in increments of ±1%, ±3% or ±5%. The LT3071 has an analog margining pin that allows the user to margin the system output voltage ±10%. The LT3071 also has a IMON output current monitor to support system load current diagnostics. The features included in the LT3070 and LT3071 make them ideal for high performance FPGAs, microprocessors or sensitive communication supply applications. A TIME FOR SHARING Multiple LT3070/71s can be paralleled to increase available output current with minimal ballasting. In fact, eight LT3070s have successfully been paralleled to share a common 30A load. Simply tie the REF/BYP pins of the paralleled regulators together. This effectively gives an averaged value of multiple 600mV reference voltage sources. Tie the OUT pins of the paralleled regulators to the common load plane through a small piece of PC trace ballast or an actual surface mount sense resistor beyond the primary output capacitors of each regulator. The required ballast is dependent on the application output voltage and peak load current. The recommended ballast is the value that contributes 1% to load regulation. For example, two LT3070/71 regulators configured to output 1V, sharing a 10A load require 2mΩ of ballast at each output. The Kelvin SENSE pins connect to the regulator side of the ballast resistors to keep the individual control loops from conflicting with each other, as shown in Figure 1. Keep this ballast trace area free of solder to maintain a controlled resistance. SIMPLIFIED INTEGRATION WITH SWITCHING REGULATORS YIELDS HIGH EFFICIENCY Figure 1 illustrates the use of the LT3070’s VIOC function. This feature transfers control of the switcher output (LDO input) to one of the LDOs such that the digital output control of the LDO sets the output of the LTC3415 to maintain 300mV headroom VIN to VOUT, across the LDOs , optimizing power dissipation on the fly. The demo board in Figure 2 demonstrates a single LTC3415 switching regulator supplying two LT3070 LDOs with cojoined outputs ballasted by sense resistors. Close examination of this board layout reveals a pair of small routes from the switcher PGND to the LDO SGND. Likewise, similar routes are incorporated in a buried layer between the switcher output and the LDO inputs, terminated by the LDO input decoupling capacitors. These serve as π-filters to help isolate the LDO reference from the switching noise. Figure 3 illustrates the quiet performance the two LT3070s sharing a pulsed 0.1A to 7A load while exhibiting less than 10mV of excursion on the output load. This is in sharp contrast to the relatively noisy load regulation waveform of the of the adjoining switching regulator. In conclusion, the LT3070 and LT3071 provide power efficient, area efficient, UltraFast transient response, low noise, point-of-load regulation for the most demanding server applications. n LT3070 VOUT 10mV/DIV ILOAD = 7A ILOAD = 0.1A SWITCHING REGULATOR VOUT 10mV/DIV 200µs/DIV Figure 3. Waveform of paralleled LT3070s contrasted to the LT3415 switcher output July 2010 : LT Journal of Analog Innovation | 29