TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 D D D D D D D Single-Chip EtherLoop Transceiver Programmable Transmit (TX) and Receive (RX) Gain Via Digital Interface Low Overall Power Consumption Power-Down Mode Minimizes Server Modem Power Consumption in Multiplexed Applications Low Noise Low Distortion All Terminals Protected to Survive, Without Damage, a Simulated Static Discharge of 1 kV From a 100-pF Capacitor Applied Through a 1.5-kΩ Resistor With Respect to Chip Ground (VEE) Single-Rail 5-V Power Supply Operating Temperature –40°C to 85°C Ambient – Allows Operation in Central Office and Distributed-Server Modem Applications 48-Pin Thin Plastic Quad Flatpack D D D 19 43 18 44 17 45 16 46 15 47 14 48 13 1 2 3 VEE 11 12 20 42 10 21 41 9 22 40 7 8 39 6 23 5 24 38 4 PRODUCT PREVIEW 26 25 27 28 RXOUT RX_TERM RXGAIN2 RXGAIN0 RXGAIN1 TX_EN VEE 30 29 31 32 33 34 VEE VEE VCC NU NU 35 37 CBIAS1 REMREF IP_INT OP_INT IN_INT ON_INT NU TXINP TXINN NU VEE VEE NU RXIP RXIN NU VEE VCC REMN TXOP TXON REMP VEE 36 PT PACKAGE (TOP VIEW) VEE TXGAIN3 TXGAIN2 TXGAIN1 TXGAIN0 ANG REFP RXBIAS TXBIAS VCC VEE VEE NU – Not used description The TNETEL1400 is an Etherloop transceiver. EtherLoop technology enables simultaneous voice and Ethernet communication over local-loop plain old telephone service (POTS) wiring. The TNETEL1400 supports data rates of up to 6 Mbit/s and POTS wire lengths of up to 21,000 feet. Figure 1 shows a typical system with an EtherLoop modem located at each end of the POTS line. Each EtherLoop modem has a 10Base-T Ethernet interface and is responsible for buffering Ethernet data before sending it over the POTS wire. The server-end (SE) EtherLoop modem is located in a central switching office and can communicate with several client-end (CE) EtherLoop modems, based on a round-robin arbitration scheme. The CE EtherLoop modem typically is located at a remote site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EtherLoop is a trademark of Elastic Networks. Copyright 1999, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 description (continued) POTS Phone ☎ CE Modem POTS Line Ethernet Network Ethernet Network Remote Location See Note A SE Modem Central Office POTS Line POTS Phone CE Modem ☎ Ethernet Network Remote Location NOTE A: Flexible multiplexing scheme allows one SE modem to interface with many CE modems. Figure 1. Typical EtherLoop System Ethernet Network Ethernet Interface SDRAM FLASH ROM PRODUCT PREVIEW Figure 2 shows a block diagram of a typical CE EtherLoop modem. Ethernet data destined for the POTS wire is received via 10Base-T interface and presented to the EtherLoop processor. The EtherLoop processor performs Ethernet frame processing and buffer management. The EtherLoop processor sends buffered Ethernet frames to the TNETEL1200 EtherLoop modem. The TNETEL1200 performs data modulation before passing the modulated digital data to a digital-to-analog (DAC) converter. The resulting analog signal passes to the TNETEL1400 transceiver, which acts as the line interface. The modem uses a half-duplex communication protocol over the POTS wire, and data received from the POTS wire follows the reverse path back to the Ethernet framer. EtherLoop Processor ☎ SRAM TNETEL1200 EtherLoop Modem DAC ADC TNETEL1400 EtherLoop Transceiver Voice Band Filter POTS Phone POTS Line Figure 2. Typical CE EtherLoop Modem Figure 3 shows a block diagram of a typical SE EtherLoop modem. Data flow follows the same path as in the CE EtherLoop modem. In the SE application, the EtherLoop processor also performs round-robin arbitration between each of the attached TNETEL1400 devices. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETEL1400 EtherLoop TRANSCEIVER Ethernet Interface SRAM DAC TNETEL1200 EtherLoop Modem EtherLoop Processor MUX Ethernet Network SDRAM FLASH ROM SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 ADC TNETEL1400 EtherLoop Transceiver POTS Line TNETEL1400 EtherLoop Transceiver POTS Line TNETEL1400 EtherLoop Transceiver POTS Line Figure 3. Typical SE EtherLoop Modem D D PRODUCT PREVIEW summary of TNETEL1400 EtherLoop transceiver Drives POTS line with signal generated by DAC Interfaces signal received from POTS line to ADC RXIN RX_TERM RXIP TXON TXOP functional block diagram IP_INT OP_INT IN_INT ON_INT TXINN TX TXINP RX RXOUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RXGAIN2–RXGAIN0 RXBIAS ANG REFP TXBIAS CBIAS1 REMN REMP REMREF TX_EN TXGAIN3–TXGAIN0 Bias 3 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 APPLICATION INFORMATION† 5V RX_MODE 2.2 µF OP_INT IN_INT ON_INT TX_IN 0.22 µF 0.22 µF TXINN RX_OUT TXINP 5Ω TX_EN 4 5Ω 13 Ω 1% 4.99 kΩ ANG RXBIAS TXBIAS CBIAS1 REMN REMP 10 K RFEP Bias 0.22 µF REMREF PRODUCT PREVIEW 0.1 µF RXIN RXTERM RXIP IP_INT TXON 0.1 µF TXOP 2.2 µF 4.99 kΩ 100 nF 100 nF 3 100 nF RXGAIN TXGAIN Figure 4. EtherLoop Front-End Application (CE) † All bias resistors should be 1% tolerance. The resistors on REMP, REMN, and REMREF also should be 1% and placed as close as possible to their respective pins. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 Terminal Functions transmit (TX) TERMINAL NAME NO. I/O† DESCRIPTION CBIAS1 2 I/O IN_INT 6 I Transmit voltage bias decoupling Transmit interstage ac coupling pin 1 (negative side) IP_INT 4 I Transmit interstage ac coupling pin 2 (positive side) ON_INT 7 O Transmit interstage ac coupling pin 2 (negative side) OP_INT 5 O Transmit interstage ac coupling pin 1 (positive side) REMREF 3 O Transmit temperature-compensating bias reference TX_EN 26 I TXBIAS 16 I Transmit enable 1 = Transmitter enabled 0 = Transmitter disabled Transmit current bias Transmit preattenuation select (0 to –30 dB in –3-dB steps) 23 (MSB) 22 21 20 (LSB) I TXINN 10 I Transmit input negative. TXINN can be coupled to ground for SE input). TXINP 9 I Transmit input positive. TXINP can be coupled to ground for SE input). TXON 46 O Transmitter output negative TXOP 45 O Transmitter output positive PRODUCT PREVIEW TXGAIN3 TXGAIN2 TXGAIN1 TXGAIN0 0000 = 0 dB 0001 = – 3 dB • • • 1010 = –30 dB 1011 = TX OFF • • • 1110 = TX OFF 1111 = TX OFF † I = input, O = output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 Terminal Functions (Continued) receive (RX) TERMINAL I/O† NAME NO. RX_TERM 30 I RXBIAS 17 I DESCRIPTION Receive passive termination RX_TERM = 1: 110 Ω switched IN RX_TERM = 0: 110 Ω switched OUT Receive current bias Receive gain select PRODUCT PREVIEW RXGAIN2 RXGAIN1 RXGAIN0 000 = RX OFF • • • 011 = RX OFF 100 = 0 dB 101 = 12 dB 110 = 24 dB 111 = 30 dB 29 (MSB) 27 28 (LSB) I RXIN 40 I Receiver input negative/TX feedback RXIP 39 I Receiver input positive/TX feedback RXOUT 31 † I = input, O = output O Receiver output (single ended) miscellaneous TERMINAL NAME I/O† NO. DESCRIPTION ANG 19 O Analog ground (2.5 V) reference REFP 18 O 4-V bandgap reference REMN 44 I/O Negative external emitter resistor REMP 47 I/O Positive external emitter resistor † I = input, O = output power supply TERMINAL NAME NU VCC VEE 6 DESCRIPTION NO. 8, 11, 32, 33, 38, 41 Not used 15, 34, 43 5-V power 1, 12, 13, 14, 24, 25, 35, 36, 37, 42, 48 Ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply-voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 V to VCC to 0.7 V Input-voltage range: Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to VCC to 0.7 V Output-voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 25°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN MAX UNIT 4.75 5.25 V VCC VIH Supply voltage VIL IOH Low-level input voltage High-level input current mA IOL TA Low-level input current mA High-level input voltage 2.1 V 1 –40 85 °C PRODUCT PREVIEW Operating free-air temperature range V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 electrical characteristics over recommended operating conditions PARAMETER ICC Supply current VREF VANG 4-V reference voltage IREFP IANG 4-V reference current TEST CONDITIONS MIN TYP† MAX Normal operation 25 50 Power-down mode 1.5 3 2.5-V reference voltage 3.88 4 4.12 2.38 2.5 2.62 Source 2.5-V reference current Source/sink † All typical values are at VCC = 5 V, TA = 25°C (unless otherwise noted). UNIT µA V V 1 mA 100 mA transmitter (see Figure 5) PARAMETER PRODUCT PREVIEW TX maximum output level TX attentuator accuracy ((relative to maximum output)) TX attentuator accuracy (relative output) ( l ti tto maximum i t t) MIN TYP† MAX UNIT TXGAIN = 0000, RXGAIN = 0XX 21 22 23 dBm TXGAIN = 0001 –3.3 –3 –2.7 TXGAIN = 0010 –6.3 –6 –5.7 TEST CONDITIONS VCC = 5 V, RL = 110 Ω, RX_TERM = 0, TX_EN = 1, V(TXINP) = 1.2 VPP sinusoid at f = 500 kHz (see Note 1) VCC = 5 V, RL = 110 Ω, RX_TERM = 0, TX_EN = 1, RXGAIN = 0XX, V(TXINP) = 1.2 1 2 VPP sinusoid at f = 500 kHz [output [out ut is measured at IN_INT and IP_INT (ac coupled)] TXGAIN = 0011 –9.3 –9 –8.7 TXGAIN = 0100 –12.3 –12 –11.7 TXGAIN = 0101 –15.3 –15 –14.7 TXGAIN = 0110 –18.3 –18 –17.7 TXGAIN = 0111 –21.3 –21 –20.7 TXGAIN = 1000 –24.3 –24 –23.7 TXGAIN = 1001 –27.3 –27 –26.7 TXGAIN = 1010 –30.3 –30 –29.7 TX output level variation over frequency 30 kHz < f < 2.5 MHz monotonically decreasing for f > 3 MHz, RL = 110 Ω, RX_TERM = 0, TX_EN = 1, V(TXINP) = 1.2 VPP sinusoid at f = 500 kHz with transformer connected as in Figure 1 (see Note 1) TXGAIN = 0000, RXGAIN = 0XX TX output distortion (all gain settings) VCC = 5 V, RL = 110 Ω, RX_TERM = 0,, TX_EN = 1,, _ _ V(TXINP) = 1.2 VPP sinusoid at f = 500 kHz (see Note 1) TXGAIN = 0000,, RXGAIN = 0XX TX output signal-to-noise ratio (SNR) (all gain settings) VCC = 5 V, RL = 110 Ω, RX_TERM = 0, TX_EN = 1, V(TXINP) = 1.2 VPP sinusoid at f = 500 kHz (see Note 1) TXGAIN = 0000, RXGAIN = 0XX TX maximum output-level variation with VCC VCC = 5 V ± 0.25 V, RL = 110 Ω, RX_TERM = 0, TX_EN = 1, V(TXINP) = 1.2 VPP sinusoid at f = 500 kHz (see Note 1) TXGAIN = 0000, RXGAIN = 0XX Zin(TXIN) Odd harmonics Even harmonics TX input impedance TX input impedance variation as percent of Zin(TXIN) 1 dB –35 dBc –50 50 dB 1 TXGAIN = 0000, RXGAIN = 0XX (see Note 1) TXGAIN = 0000, RXGAIN = 0XX dB 1400 –30% TYP+ 30% dB/V Ω 30% † All typical values are at VCC = 5 V, TA = 25°C (unless otherwise noted). NOTE 1: While the RX circuit is disabled during transmission, it is still connected and, therefore, must withstand the signal levels placed at its input terminals. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 transmitter (see Figure 5) (continued) TEST CONDITIONS MIN VCC = 5 V, RL = 110 Ω, RX_TERM = 0, TX_EN = 1, V(TXINP) = 1.2 VPP sinusoid at f = 500 kHz (see Note 1) TXGAIN = 0000, RXGAIN = 0XX TX output stability Source impedance ≤ 50 Ω, Supply impedance ≤ 10 Ω, Zloads: voltage standing-wave ratio (VSWR) 4:1 and open circuit TXGAIN = 0000, RXGAIN = 0XX TX supply current VOUT = 0, VOUT = MAX, TX output return loss TXGAIN = 0000, RXGAIN = 0XX Irms(TXOP)– Irms(TXON) TX output current balance TYP† –5 TXGAIN = 0000 MAX 5 35 TXGAIN = 0000 45 120 18 UNIT mA mA dB µs † All typical values are at VCC = 5 V, TA = 25°C (unless otherwise noted). NOTES: 1. While the RX circuit is disabled during transmission, it is still connected and, therefore, must withstand the signal levels placed at its input terminals. 2. The power-up/power-down time is the time it takes for the signal path to completely settle and meet all the transmission specifications after TXGAIN and RXGAIN are set to power-up condition or switched from one gain setting to another. This time consists of slewing and exponential settling of bias and AC coupling capacitors and, therefore, the values of these components must be as shown in the application diagram, Figure 4. TX power-up time TXGAIN = 0000, RXGAIN = 0XX (see Note 2) 100 receiver (see Figures 6 and 7) PARAMETER RX idle channel noise TEST CONDITIONS RL = 2 kΩ, kΩ CL = 20 pF F, 30 kHz < f < 2.75 2 75 MHz, MHz RX_TERM = 1,, TX_EN = 0,, _ _ V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz (see Note ( N t 3) MIN TYP† MAX RXGAIN = 11 691 RXGAIN = 10 478 RXGAIN = 01 266 RXGAIN = 00 160 RXGAIN = 11 24 30 31 RXGAIN = 10 23 24 25 RXGAIN = 01 11 12 13 0 1 UNIT µV µ RMS RX gain accuracy VCC = 5 V, RL = 2 kΩ, CL = 20 pF, 30 kHz < f < 2.75 2 75 MHz, MHz RX_TERM RX TERM = 1, 1 TX_EN TX EN = 0, 0 V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz RXGAIN = 00 –1 RX gain over frequency (WRT gain at 500 kHz) RL = 2 kΩ, CL = 20 pF, 30 kHz < f < 2.75 MHz, 30 kHz < f < 2.5 MHz monotically decreasing for f > 3 MHz, TX_EN = 0, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz RX_TERM = 1, RXGAIN = 111 –1 RL = 2 kΩ, CL = 20 pF, dc < f < 3 MHz, TX_EN = 0, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz RX_TERM = 1, RXGAIN = 111 RL = 2 kΩ, CL = 20 pF, TX_EN = 0, V(RXIN) = 1.5 VPP, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz RX_TERM = 1, RXGAIN = 111 30 dB RL = 2 kΩ, CL = 20 pF, TX_EN = 0, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz (see Note 4) RX_TERM = 1, RXGAIN = 111 17 dBm RX power-supply rejection (WRT VCC only) RX common-mode rejection RX IIP3 intercept dB 1 dB 0.03 V/V † All typical values are at VCC = 5 V, TA = 25°C (unless otherwise noted). NOTES: 3. Idle channel noise is the noise (Vrms) measured at RXOUT with no signal at RXIN. This voltage is integrated over the 30-KHz to 2.75-MHz band. This specification is in place of the original noise-figure specification, and is correlated to NF with laboratory measurements. 4. The two tones used for this test are at 1.39 MHz and 1.58 MHz, and the in-band IIP3 products are at 1.2 MHz and 1.77 MHz. The IIP3 intercept point is the output power level, where the power of the harmonics equals that of the signal frequencies. This point is an intersection of two straight lines extrapolated from two low-power measurements. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PRODUCT PREVIEW PARAMETER TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 receiver (see Figures 6 and 7) (continued) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT –40 dBc RX output total harmonic distortion RL = 2 kΩ, CL = 20 pF, TX_EN = 0, V(RXOUT) = 2 VPP, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz RX_TERM = 1, RXGAIN = 111 RX ZIN _ RL = 2 kΩ,, CL = 20 pF,, RXGAIN = 111,, TX_EN = 0,, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz RX_TERM = 1 77 RX_TERM = 0 10 RX maximum supply current RL = 2 kΩ, CL = 20 pF, TX_EN = 0, V(RXOUT) = 4 VPP, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz RX_TERM = 1, RXGAIN = 111 20 mA RX power-up time RL = 2 kΩ, CL = 20 pF, TX_EN = 0, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz (see Note 2) RX_TERM = 1, RXGAIN = 111 30 µs Power-down supply current RL = 2 kΩ, CL = 20 pF, RX_TERM = 1, TX_EN = 0, V(RXIP – RXIN) = 0.04 VPP sinusoid at f = 500 kHz (see Note 2) TXGAIN = 1111, RXGAIN = 000 3 mA 110 143 Ω kΩ PRODUCT PREVIEW † All typical values are at VCC = 5 V, TA = 25°C (unless otherwise noted). NOTE 2. The power-up/power-down time is the time it takes for the signal path to completely settle and meet all the transmission specifications after TXGAIN and RXGAIN are set to power-up condition or switched from one gain setting to another. This time consists of slewing and exponential settling of bias and AC coupling capacitors and, therefore, the values of these components must be as shown in the application diagram, Figure 4. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 110 V 5V RX_TERM 1 µF 1 µF 33 nF 33 nF PRODUCT PREVIEW 33 nF + 33 nF VI Bias – 4.99 kΩ 5Ω 5Ω 4 80.6 kΩ 3 100 nF 7.5 Ω 100 nF 100 nF [000] RXGAIN TXGAIN Figure 5. TX Test Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 0.04 VPP + – 1 µF 1 µF 33 nF 33 nF 100 nF 2 kΩ PRODUCT PREVIEW Bias 5Ω 4.99 kΩ 80.6 kΩ 100 nF 100 nF 5Ω 4 7.5 Ω [1111] RXGAIN Figure 6. RX Test Circuit 12 3 100 nF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 110 Ω 1 µF 1 µF 33 nF 33 nF 5Ω 4.99 kΩ 80.6 kΩ 100 nF 100 nF PRODUCT PREVIEW Bias 5Ω 4 7.5 Ω 3 100 nF [1111] RXGAIN Figure 7. RX Noise Test Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TNETEL1400 EtherLoop TRANSCEIVER SPHS004A – FEBRUARY 1999 – REVISED MARCH 1999 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 PRODUCT PREVIEW 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads conected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated