3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) IDT71V428S IDT71V428L Features Description ◆ The IDT71V428 is a 4,194,304-bit high-speed Static RAM organized as 1M x 4. It is fabricated using IDT’s high-perfomance, highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a costeffective solution for high-speed memory needs. The IDT71V428 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V428 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V428 is packaged in a 32-pin, 400 mil Plastic SOJ. ◆ ◆ ◆ ◆ ◆ ◆ ◆ 1M x 4 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times — Commercial and Industrial: 10/12/15ns Single 3.3V power supply One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Available in 32-pin, 400 mil plastic SOJ package. Functional Block Diagram A0 • • • • • • ADDRESS DECODER 4,194,304-BIT MEMORY ARRAY A19 I/O0 – I/O3 4 4 • I/O CONTROL 4 WE OE CS CONTROL LOGIC 3623 drw 01 SEPTEMBER 2004 1 ©2004 Integrated Device Technology, Inc. DSC-3623/06 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges Pin Configuration A0 A1 A2 A3 A4 CS I/O 0 VDD VSS I/O 1 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Description SO32-3 SOJ Top View A19 A18 A17 A16 A15 OE I/O 3 VSS VDD I/O 2 A14 A13 A12 A11 A10 NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 – A19 Address Inputs Input CS Chip Select Input WE Write Enable Input OE Output Enable Input I/O 0 - I/O 3 Data Input/Output VDD 3.3V Power VSS Ground I/O Power Gnd 3623 tbl 02 Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) Symbol 3623 drw 02 Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 8 pF 3623 tbl 03 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. Truth Table(1,2) CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected - Standby (ISB) VHC(3) X X High-Z Deselected - Standby (ISB1) Function 3623 tbl 01 NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = V CC -0.2V. 3. Other inputs ≥VHC or ≤VLC. 6.42 2 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Absolute Maximum Ratings(1) Symbol Rating Value Unit VDD Supply Voltage Relative to VSS -0.5 to +4.6 V VIN, VOUT Terminal Voltage Relative to VSS -0.5 to VDD+0.5 V TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o PT Power Dissipation 1 W IOUT DC Output Current 50 mA Grade Temperature VSS VDD Commercial 0°C to +70°C 0V See Below Industrial –40°C to +85°C 0V See Below 3623 tbl 05 C C Recommended DC Operating Conditions Symbol 3623 tbl 04 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter VDD Supply Voltage VSS Ground VIH Input High Voltage Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 2.0 ____ (2) Input Low Voltage VIL Min. VDD+0.3 ____ -0.3 V (1) V 0.8 V 3623 tbl 06 NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) IDT71V428 Symbol |ILI| |ILO| VOL VOH Parameter Test Condition Min. Max. Unit Input Leakage Current VDD = Max., VIN = VSS to VDD ___ 5 µA Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD ___ 5 µA IOL = 8mA, V DD = Min. ___ 0.4 V 2.4 ___ V Output Low Voltage Output High Voltage IOH = -4mA, V DD = Min. 3623 tbl 07 DC Electrical Characteristics(1,2,3) (VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V) 71V428S/L10 Symbol ICC ISB ISB1 Parameter 71V428S/L12 71V428S/L15 Com'l. Ind.(5) Com'l. Ind. Com'l. Ind. Unit Dynam ic Operating Current CS ≤ VLC, Outputs Open, V DD = Max., f = f MAX(4) S 150 150 140 140 130 130 mA L 140 — 130 130 120 120 mA Dynamic Standby Power Supply Current CS ≥ VHC, Outputs Open, V DD = Max., f = f MAX(4) S 60 60 50 50 40 40 mA L 40 — 35 35 30 30 mA Full Standby Power Supply Current (static) CS ≥ VHC, Outputs Open, V DD = Max., f = 0(4) S 20 20 20 20 20 20 mA L 10 — 10 10 10 10 NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High). 3. Power specifications are preliminary. 4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 5. Standard power 10ns (S10) speed grade only. 6.42 3 mA 3623 tbl 08 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges AC Test Conditions GND to 3.0V Input Pulse Levels Input Rise/Fall Times 1.5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V See Figure 1, 2 and 3 AC Test Load 3623 tbl 09 AC Test Loads 3.3V +1.5V 320Ω DATAOUT 50Ω I/O Z0 = 50Ω 5pF* 350Ω 30pF 3623 drw 03 3623 drw 04 Figure 1. AC Test Load * Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, t CHZ, tOHZ, tOW, and tWHZ) 7 • 6 ∆tAA, tACS (Typical, ns) 5 4 • 3 • 2 • 1 • • • 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) Figure 3. Output Capacitive Derating 6.42 4 3623 drw 05 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) AC Electrical Characteristics Commercial and Industrial Temperature Ranges (VDD = 3.3V ± 10%, Commercial and Industrial Temperature Ranges) 71V428S/L10(2) 71V428S/L12 71V428S/L15 Min. Max. Min. Max. Min. Max. Unit Read Cycle Time 10 ____ 12 ____ 15 ____ ns Address Access Time ____ 10 ____ 12 ____ 15 ns Chip Select Access Time ____ 10 ____ 12 ____ 15 ns 4 ____ 4 ____ 4 ____ ns Symbol Parameter READ CYCLE tRC tAA tACS tCLZ (1) Chip Select to Output in Low-Z tCHZ(1) Chip Deselect to Output in High-Z ____ 5 ____ 6 ____ 7 ns tOE Output Enable to Output Valid ____ 5 ____ 6 ____ 7 ns tOLZ (1) Output Enable to Output in Low-Z 0 ____ 0 ____ 0 ____ ns tOHZ (1) Output Disable to Output in High-Z ____ 5 ____ 6 ____ 7 ns tOH Output Hold from Address Change 4 ____ 4 ____ 4 ____ ns tPU(1) Chip Select to Power Up Time 0 ____ 0 ____ 0 ____ ns Chip Deselect to Power Down Time ____ 10 ____ 12 ____ 15 ns tWC Write Cycle Time 10 ____ 12 ____ 15 ____ ns tAW Address Valid to End of Write 8 ____ 8 ____ 10 ____ ns tCW Chip Select to End of Write 8 ____ 8 ____ 10 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 8 ____ 8 ____ 10 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End of Write 6 ____ 6 ____ 7 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tOW(1) Output Active from End of Write 3 ____ 3 ____ 3 ____ ns Write Enable to Output in High-Z ____ 6 ____ 7 ____ 7 ns tPD(1) WRITE CYCLE tWHZ (1) 3623 tbl 10 NOTES: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 2. 0°C to +70°C temperature range only for low power 10ns (L10) speed grade. 6.42 5 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1 (1) tRC ADDRESS tAA OE tOE tOLZ CS tCLZ DATAOUT VDD SUPPLY ICC CURRENT ISB (5) (5) tACS (3) tCHZ HIGH IMPEDANCE (5) tOHZ (5) DATAOUT VALID tPD tPU 3623 drw 06 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID 3623 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 6 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No.1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tWP (2) tAS tWR WE tWHZ DATAOUT (5) tOW (5) HIGH IMPEDANCE (3) (5) (3) tDH tDW DATAIN tCHZ DATAIN VALID 3623 drw 08 Timing Waveform of Write Cycle No.2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID 3623 drw 09 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 7 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 71V428 Device Type X X Die Power Revision XX Speed XXX Package X X Process/ Temperature Range Blank Commercial (0°C to +70°C) I Industrial (–40°C to +85°C) G Restricted hazardous substance device Y 32-pin 400-mil SOJ (S0323) 10* 12 15 Speed in nanoseconds S L Standard Power Low Power Blank First Generation or current stepping being shipped Y Second Generation die step * Commercial only for low power (L10) speed grade. 3623 drw 10 6.42 8 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges Datasheet Document History 8/31/99 9/29/99 11/26/02 07/31/03 09/30/04 Pg. 2 Pg. 4 Pg. 7 Pg. 9 Pg. 1–9 Pg. 8 Pg. 8 Pg. 8 Updated to new format Added footnote for VHC in Truth Table Added footnote on jig and scope capacitance in Figure 2 Revised footnote on Write Cycle No. 1 diagram Added Datasheet Document History Added Industrial temperature range offerings Updated ordering information for die revision Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y. Added "Restricted hazardous substance device" to ordering information. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 9 for Tech Support: [email protected] 800-544-7726