MB39C502 DS405-00020-E

The following document contains information on Cypress products.
MB39C502/C503/C504
High Efficiency
Single Output Step Down DC/DC Controller
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Publication Number MB39C502_DS405-00020-1v0-E
CONFIDENTIAL
Revision 1.0
Issue Date September 9, 2014
v1.1
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion
data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this
proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing
process that require maintaining efficiency and quality, this document may be revised by subsequent
versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
2
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MB39C502/C503/C504
High Efficiency
Single Output Step Down DC/DC Controller
Data Sheet (Full Production)
1.
Description
MB39C502 is a single output step down DC/DC controller using external FETs. It achieves the high
efficiency with “Enhanced Low Power Mode (LPM) Operation” in light load. In Enhanced LPM, this controller
operates that the quiescent current is reduced only 30μA and the switching frequency is fallen by extending
on time. These operations enable to improve the efficiency in light load. Internal compensation circuit with
current mode architecture and internal boost switch allow reducing the BOM parts and the component area.
2.
Features


















3.
High Efficiency with Enhanced LPM Operation
Automatic Transition for PFM/PWM
Enhanced LPM Operation Transferred by SLP_N Assertion
Over Current Alerting
Reference Voltage Accuracy: ±1%
Output Voltage Range : 0.7V to 2.0V (MB39C502)
: 2.4V to 3.5V (MB39C503)
: fixed 5V
(MB39C504)
VIN Input Voltage Range : 4.0V to 25V (MB39C502/C503)
: 5.4V to 25V (MB39C504)
VDD Input Voltage Range: 4.5V to 5.5V (MB39C502/C503)
Internal 5V LDO with Switchover (MB39C504)
Fixed Frequency Emulated On-Time Control: 800kHz
Current Mode Architecture with Internal Compensation Circuit
Internal Boost Switch
Fixed 700μs Soft Start Time without Load Dependence
Internal Discharge FET
Power Good Monitor
Enhanced Protection Functions: OVP, UVP, ILIM
Thermal Shutdown
Small 3mm × 3mm × 0.75mm QFN16 Package
Applications
 Point of Load VR for Note PC
 General Purpose Step Down Regulator
Publication Number MB39C502_DS405-00020-1v0-E
Revision 1.0
Issue Date September 9, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
v1.2
D a t a S h e e t
Contents
1. Description ............................................................................................................................................... 3
2. Features .................................................................................................................................................... 3
3. Applications ............................................................................................................................................. 3
4. Typical Application .................................................................................................................................. 5
5. Pin Configuration..................................................................................................................................... 6
6. Pin Configuration..................................................................................................................................... 7
7. Block Diagram.......................................................................................................................................... 9
8. Absolute Maximum Rating .................................................................................................................... 11
9. Recommended Operating Conditions ................................................................................................. 12
10. Electrical Characteristics ...................................................................................................................... 14
11. Protections and Power Good function ................................................................................................ 23
11.1 Description ................................................................................................................................... 23
11.2 Timing Chart ................................................................................................................................. 24
12. Enhanced LPM Description .................................................................................................................. 27
12.1 Ultra Low Quiescent Current ........................................................................................................ 27
12.2 Extended On Time........................................................................................................................ 27
12.3 Timing Chart of Enhanced LPM.................................................................................................... 28
13. Over Current Alerting Description ....................................................................................................... 29
14. Application Note .................................................................................................................................... 30
14.1 Setting Operating Conditions ........................................................................................................ 30
14.1.1 Setting Output Voltage ...................................................................................................... 30
14.1.2 Setting Over Current Limitation and Over Current Alerting ............................................... 30
14.2 Selection Parts ............................................................................................................................. 32
14.2.1 Selection of Smoothing Inductor ....................................................................................... 32
14.2.2 Selection of Switching FET ............................................................................................... 33
14.2.3 Selection of Fly Back Diode .............................................................................................. 35
14.2.4 Selection of Boost Diode ................................................................................................... 35
14.2.5 Selection of Input Capacitor .............................................................................................. 36
14.2.6 Selection of Output Capacitor ........................................................................................... 37
14.2.7 Selection of Boost Capacitor ............................................................................................. 38
14.2.8 Selection of VDD Capacitor............................................................................................... 39
14.2.9 Selection of VCC Capacitor and Resistor.......................................................................... 39
14.3 Layout........................................................................................................................................... 40
15. Ordering Information ............................................................................................................................. 44
16. Package Dimensions ............................................................................................................................. 45
17. Major Changes ....................................................................................................................................... 46
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4.
Typical Application
(MB39C502/C503)
(MB39C504)
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5.
Pin Configuration
(MB39C502/C503)
(MB39C504)
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6.
Pin Configuration
(MB39C502/C503)
Pin Number
Pin Name
I/O
Description
1
ILIM(*1)
I
Connect to VCC terminal.
2
ALERT_N
O
Open drain output terminal with over current alerting.
3
VDD
I
Power supply voltage input terminal of switching FET gate driver.
4
DRVL
O
Low side switching FET gate driver output terminal.
5
PGND
-
Power ground.
6
LX
-
Inductor and high side switching FET source connection terminal.
7
VIN
I
Power supply of switching regulator input terminal.
8
DRVH
O
High side switching FET gate driver output terminal.
9
BST
I
Boost capacitor connection terminal.
10
EN
I
11
CSP
I
Current sensing positive input terminal.
12
CSN
I
Current sensing negative input terminal.
13
FB
I
Feedback voltage input of switching regulator.
14
SLP_N
I
15
PWRGD
O
Open drain output terminal with power good.
16
VCC
I
Power supply voltage input terminal of PWM controller.
AGND
-
Analog ground.
Enable input of PWM controller.
When turning on, apply greater than 0.65V and less than 5.5V. When turning off, apply less
than 0.25V.
EP
Low power mode signal input terminal.
Transferred to low power mode by connecting to “L” level
*1: ILIM terminal should be fixed to connect to VCC terminal.
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(MB39C504)
Pin Number
Pin Name
I/O
Description
1
ILIM(*1)
I
Connect to VCC terminal whenever.
2
VOUT
I
DCDC output voltage input for switchover.
3
LDO5
O
5V LDO output terminal.
4
DRVL
O
Low side switching FET gate driver output terminal.
5
PGND
-
Power ground.
6
LX
-
Inductor and high side switching FET source connection terminal.
7
VIN
I
Power supply of switching regulator input terminal.
8
DRVH
O
High side switching FET gate driver output terminal.
9
BST
I
Boost capacitor connection terminal.
10
EN
I
11
CSP
I
Current sensing positive input terminal.
12
CSN
I
Current sensing negative input terminal.
13
VOUTS
I
DCDC output voltage input terminal.
14
SLP_N
I
15
PWRGD
O
Open drain output terminal with power good.
16
VCC
I
Power supply voltage input terminal of PWM controller.
EP
AGND
-
Analog ground.
Enable input of PWM controller.
When turning on, apply greater than 2.5V and less than 25V. When turning off, apply less than
0.6V.
Low power mode signal input terminal.
Transferred to low power mode by connecting to “L” level
*1: ILIM terminal should be fixed to connect to VCC terminal.
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7.
Block Diagram
(MB39C502/C503)
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(MB39C504)
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8.
Absolute Maximum Rating
(MB39C502/C503/C504)
Parameter
Symbol
Power supply voltage
Terminal voltage
Unit
+28
V
VVCC
VCC input voltage
–0.3
+6.5
V
VVDD
VDD input voltage (MB39C502/C503)
–0.3
+6.5
V
VVOUT
VOUT input voltage (MB39C504)
–0.3
+6.5
V
VBST
BST bias voltage
–0.3
+34.5
V
VLX
LX switching voltage
–2
+28
V
VFB
FB input voltage (MB39C502/C503)
–0.3
VVCC +0.3
V
VVOUTS
VOUTS input voltage
–0.3
+6.5
V
VINPUT
ILIM input voltage
–0.3
VVCC +0.3
V
CSP, CSN input voltage
–0.3
+6.5
V
EN input voltage (MB39C502/C503)
–0.3
+6.5
V
EN input voltage (MB39C504)
–0.3
+28
V
VSLP
SLP_N input voltage
–0.3
+6.5
V
VNOD
PWRGD, ALERT_N bias voltage
–0.3
+6.5
V
BST–LX difference voltage
–0.3
+6.5
V
-
+28
V
-
+28
V
AGND–PGND difference voltage
–0.3
+0.3
V
CSP–CSN difference voltage
–0.3
+0.3
V
VBST-VDD
VBST-LDO5
VGND
VCSP-CSN
BST–VDD difference voltage
(MB39C502/C503)
BST–VOUT, LDO5 difference voltage
(MB39C504)
IDRV
DRVH, DRVL DC current
–60
+60
mA
INOD
PWRGD
-
+2
mA
IALERT
ALERT_N sink current (MB39C502/C503)
-
+2
mA
Ta ≤ ±25°C
-
2100(*1)
mW
–55
+125
°C
PD
Storage temperature
Max
–0.3
VBST-LX
Power dissipation
Min
VIN input voltage
VEN
Output current
Rating
VVIN
VCS
Difference voltage
Condition
TSTG
-
*1: When the IC is mounted on 10cm × 10cm four-layer square epoxy board. IC is mounted on a four-layer
epoxy board, which terminal bias, and the IC’s thermal pad is connected to the epoxy board.
WARNING
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
MB39C502_DS405-00020-1v0-E, September 9, 2014
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9.
Recommended Operating Conditions
(MB39C502/C503/C504)
Parameter
Symbol
Power supply voltage
Unit
Typ
Max
25
V
VIN input voltage (MB39C502/C503)
4.0
-
VVIN
VIN input voltage (MB39C504)
5.4
-
25
V
VVCC
VCC input voltage
4.5
-
5.5
V
VVDD
VDD input voltage (MB39C502)
4.5(*1)
-
5.5
V
VVDD
VDD input voltage (MB39C503)
4.5
-
5.5
V
VLDO5
VOUT input voltage (MB39C504)
4.5
-
5.5
V
VBST
BST bias voltage
0
-
30.5
V
VLX
LX switching voltage
–1
-
25
V
0
-
VVCC
V
VINPUT
FB, ILIM input voltage
(MB39C502/C503)
ILIM input voltage (MB39C504)
0
-
VVCC
V
VCS
CSP, CSN input voltage (MB39C502)
0
-
2.0
V
VCS
CSP, CSN input voltage (MB39C503)
0
-
3.5
V
0
-
5.5
V
0
-
5.5
V
VCS
VEN
CSP, CSN, VOUTS input voltage
(MB39C504)
EN, SLP_N input voltage
(MB39C502/C503)
VEN
EN input voltage (MB39C504)
0
-
25
V
VSLP
SLP_N input voltage (MB39C504)
0
-
5.5
V
0
-
5.5
V
PWRGD bias voltage (MB39C504)
0
-
5.5
V
BST–LX difference voltage
0
-
5.5
V
-
-
25
V
-
-
25
V
–0.05
-
0.05
V
0
-
35
mV
VNOD
VNOD
VBST-LX
VBST-VDD
Difference voltage
Value
Min
VVIN
VINPUT
Terminal voltage
Condition
VBST-LDO5
VGND
VCSP-CSN
PWRGD, ALERT_N bias voltage
(MB39C502/C503)
BST–VDD difference voltage
(MB39C502/C503)
BST–VOUT, LDO5 difference voltage
(MB39C504)
AGND–PGND difference voltage
CSP–CSN difference voltage
IDRV
DRVH, DRVL DC current
–45
-
45
mA
INOD
PWRGD, ALERT_N sink current
-
-
1
mA
BST capacitor
CBST
Connect BST to LX capacitor
-
0.47
-
μF
VCC capacitor
CVCC
Connect VCC to AGND capacitor
-
1.0
-
μF
-
4.7
-
μF
-
4.7
-
μF
–30
-
85
°C
Output current
VDD capacitor
CVDD
LDO5 capacitor
CLDO5
Operating ambient
temperature
TA
Connect VDD to PGND capacitor
(MB39C502/C503)
Connect LDO5 to PGND
capacitor(MB39C504)
Ambient temperature
*1: This VDD minimum input voltage indicates dynamic input range below 1ms. Refer to figure (next page)
about the static VDD minimum input voltage.
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VDD Static Input Voltage / V
VDD Static Input Voltage vs. Ambient Temprature
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
(BAT54XV2T1G boost diode connected)
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
100
Ambient Temprature / degC
WARNING
−
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
−
Always use semiconductor devices within their recommended operating condition ranges.
−
Operation outside these ranges may adversely affect reliability and could result in device failure.
−
No warranty is made with respect to use, conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
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10. Electrical Characteristics
(MB39C502)
VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
Parameter
Symbol
Value
Condition
Unit
Min
Typ
Max
0.693
0.700
0.707
Ta = –10°C to 85°C
0.686
-
0.714
V
VFB = 1.0V
–0.1
-
0.1
μA
REFERENCE VOLTAGE
This voltage is compared to feedback
Internal reference voltage
FB input current
VREF
IFB
voltage. Ta = 25°C
V
ENABLE, SLP_N
Enable condition
EN input current
SLP_N enable condition
SLP_N input current
VEN
Enable voltage range
0.65
-
5.5
V
VDSB
Disable voltage range
0
-
0.25
V
-
0
0.1
μA
VSLPDSB
IEN
VEN = 5.0V
LPM disable voltage range
0.65
-
5.5
V
VSLPEN
LPM enable voltage range
0
-
0.35
V
ISLP_N
VSLP_N = 5.0V
-
0
0.1
μA
-
380
760
μA
-
180
360
μA
-
30
60
μA
VDD, VCC input current at VEN = 0V
-
0.1
1.0
μA
VVIN = 25V
-
10
15
μA
VIN input current at VEN = 0V
-
0.1
1.0
μA
SUPPLY CURRENT
IVDDPWM
VDD, VCC input current at PWM
operating. TA = 25°C
VDD, VCC input current at idle state in
VDD supply current
IVDDPFM
PFM operation. Static 0A inductor
current. TA = 25°C
VDD, VCC input current at idle state in
IVDDLPM
LPM operation. Static 0A inductor
current. TA = 25°C
VDD shutdown current
VIN supply current
VIN shutdown current
IVDDSDN
IVIN
IVINSDN
UNDER VOLTAGE LOCKOUT
VCC UVLO threshold
VUVLO
UVLO release voltage
3.99
4.14
4.29
V
VHYS
Hysteresis
0.005
0.070
0.200
V
200
-
1000
μs
598
665
732
μs
SOFT START, DISCHARGE
Period of power on reset
tPOR
Ramp up time
tSS
From enable ON to the switching
initiating.
From the switching initiating after enable
ON to the output voltage reaches 95%.
Discharge resistance
RDISCHG
VOUT = 0.2V, discharge enable.
Discharge ends voltage
VDISCHG
VCSN voltage.
14
CONFIDENTIAL
50
100
200
Ω
0.07
0.10
0.13
V
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VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C502)
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
ON TIMER
On time
tON
VVIN = 7.4V, VCSN = 1.2V
193
210
227
ns
Minimum on time
tMINON
VVIN = 7.4V, VCSN = 0.2V
80
120
-
ns
Minimum off time
tMINOFF
-
200
400
ns
19.0
24.0
29.0
mV
CURRENTLIMITATION
Current limitation threshold
VILIMIT
CSP–CSN difference voltage at ILIM
connects to VCC.
ILIM input current
IILIM
VILIM = 5.0V
-
0
0.1
μA
CSP, CSN input current
ICS
VCS = 1.2V
–5.0
–2.0
-
μA
110
115
125
%
4
10
25
μs
65
70
75
%
40
100
200
μs
86
92
98
%
3
5
7
%
μs
OVER AND UNDER VOLTAGE PROTECTION
Over voltage threshold ratio
Propagation delay of OV
Under voltage threshold ratio
Propagation delay of UV
RTOV
For target output voltage. At output
voltage increasing.
tOV
RTUV
For target output voltage. At output
voltage decreasing.
tUV
POWER GOOD MONITOR
Power good threshold ratio
RTPG
Hysteresis Ratio
RTHYS
Propagation delay
PWRGD leak current
PWRGD output voltage “L”
level
For target output voltage. At output
voltage increasing.
-
tPG
Power good
20
50
200
tPB
Power bad
4
10
25
μs
ILKPG
VPWRGD = 5.5V
-
0
1
μA
VOLPG
IPWRGD = 1mA sink
-
0.05
0.10
V
-
150(*1)
-
°C
-
125(*1)
-
°C
78
85
92
%
μs
THERMAL SHUT DOWN
TTSDH
Shut down temperature
TTSDL
Shut down temperature.
Exited temperature from thermal shut
down state.
OVER CURRENT ALERTING
Over current alerting
threshold ratio
Propagation delay
ALERT_N leak current
ALERT_N output voltage “L”
level
RTALT
For target current limitation. At output
current increasing.
tALTON
On alerting assertion
20
50
200
tALTOFF
On alerting de-assertion
3
10
25
μs
ILKALT
VALERT_N = 5.5V
-
0
1
μA
VOLALT
IALERT_N = 1mA sink
-
0.05
0.10
V
*1: No production tested, ensure by design.
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VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C502)
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
DRIVER
RHOH
At 100mA current sourcing
-
3(*1)
-
Ω
RHOL
At 100mA current sinking
-
1(*1)
-
Ω
RLOH
At 100mA current sourcing
-
4(*1)
-
Ω
RLOL
At 100mA current sinking
-
0.75(*1)
-
Ω
High side source current
ISRCH
VDRVH = 2.5V
-
0.7(*1)
-
A
High side sink current
ISINKH
VDRVH = 2.5V
-
1.1(*1)
-
A
Low side source current
ISRCL
VDRVL = 2.5V
-
0.5(*1)
-
A
Low side sink current
ISINKL
VDRVL = 2.5V
-
1.7(*1)
-
A
10
20
-
ns
High side on resistance
Low side on resistance
From DRVH turn off to DRVL turn on.
Dead time
tDEAD
Boost switch on resistance
RBST
IBST = 10mA
-
30
50
Ω
BST leak current
ILKBST
VBST = 30V
-
0.1
1.0
μA
And reverse it.
BOOST SWITCH
*1: No production tested, ensure by design.
16
CONFIDENTIAL
MB39C502_DS405-00020-1v0-E, September 9, 2014
v1.1
D a t a S h e e t
VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C503)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
0.99
1.00
1.01
Ta = –10°C to 85°C
0.98
-
1.02
V
VFB = 1.0V
–0.1
-
0.1
μA
V
REFERENCE VOLTAGE
This voltage is compared to feedback
Internal reference voltage
FB input current
VREF
IFB
voltage. Ta = 25°C
V
ENABLE, SLP_N
Enable condition
EN input current
SLP_N enable condition
SLP_N input current
VEN
Enable voltage range
0.65
-
5.5
VDSB
Disable voltage range
0
-
0.25
V
VEN = 5.0V
-
0
0.1
μA
IEN
VSLPDSB
LPM disable voltage range
0.65
-
5.5
V
VSLPEN
LPM enable voltage range
0
-
0.35
V
ISLP_N
VSLP_N = 5.0V
-
0
0.1
μA
-
380
760
μA
-
180
360
μA
-
30
60
μA
VDD, VCC input current at VEN = 0V
-
0.1
1.0
μA
VVIN = 25V
-
10
15
μA
IVINSDN
VIN input current at VEN = 0V
-
0.1
1.0
μA
VUVLO
UVLO release voltage
3.99
4.14
4.29
V
VHYS
Hysteresis
0.005
0.070
0.200
V
200
-
1000
μs
598
665
732
μs
SUPPLY CURRENT
IVDDPWM
VDD, VCC input current at PWM
operating. TA = 25°C
VDD, VCC input current at idle state in
VDD supply current
IVDDPFM
PFM operation. Static 0A inductor
current. TA = 25°C
VDD, VCC input current at idle state in
IVDDLPM
LPM operation. Static 0A inductor
current. TA = 25°C
VDD shutdown current
VIN supply current
VIN shutdown current
IVDDSDN
IVIN
UNDER VOLTAGE LOCKOUT
VCC UVLO threshold
SOFT START, DISCHARGE
Period of power on reset
tPOR
Ramp up time
tSS
From enable ON to the switching
initiating.
From the switching initiating after enable
ON to the output voltage reaches 95%.
Discharge resistance
RDISCHG
VOUT = 0.2V, discharge enable.
Discharge ends voltage
VDISCHG
VCSN voltage.
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
50
100
200
Ω
0.07
0.10
0.13
V
17
v1.1
D a t a S h e e t
VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C503)
Parameter
Symbol
Value
Condition
Min
Typ
Max
621
Unit
ON TIMER
On time
tON
VVIN = 7.4V, VCSN = 3.3V
529
575
Minimum on time
tMINON
VVIN = 7.4V, VCSN = 0.2V
100
200
Minimum off time
tMINOFF
-
ns
ns
90
180
ns
26.0
31.0
mV
CURRENTLIMITATION
Current limitation threshold
VILIMIT
CSP–CSN difference voltage at ILIM
21.0
connects to VCC.
ILIM input current
IILIM
VILIM = 5.0V
-
0
0.1
μA
CSP input current
ICSP
VCSP = 3.3V
-
2.0
5.0
μA
CSN input current
ICSN
VCSP = 3.3V
-
8.0
20.0
μA
110
115
125
%
4
10
25
μs
65
70
75
%
40
100
200
μs
86
92
98
%
OVER AND UNDER VOLTAGE PROTECTION
Over voltage threshold ratio
Propagation delay of OV
Under voltage threshold ratio
Propagation delay of UV
RTOV
For target output voltage. At output
voltage increasing.
tOV
RTUV
For target output voltage. At output
voltage decreasing.
tUV
POWER GOOD MONITOR
Power good threshold ratio
RTPG
Hysteresis Ratio
RTHYS
Propagation delay
PWRGD leak current
PWRGD output voltage “L”
level
For target output voltage. At output
voltage increasing.
3
5
7
%
tPG
Power good
-
20
50
200
μs
tPB
Power bad
4
10
25
μs
ILKPG
VPWRGD = 5.5V
-
0
1
μA
VOLPG
IPWRGD = 1mA sink
-
0.05
0.10
V
TTSDH
Shut down temperature.
-
150(*1)
-
°C
-
125(*1)
-
°C
78
85
92
%
THERMAL SHUT DOWN
Shut down temperature
TTSDL
Exited temperature from thermal shut
down state.
OVER CURRENT ALERTING
Over current alerting
threshold ratio
Propagation delay
ALERT_N leak current
ALERT_N output voltage “L”
level
RTALT
For target current limitation. At output
current increasing.
tALTON
On alerting assertion
20
50
200
μs
tALTOFF
On alerting de-assertion
3
10
25
μs
ILKALT
VALERT_N = 5.5V
-
0
1
μA
VOLALT
IALERT_N = 1mA sink
-
0.05
0.10
V
*1: No production tested, ensure by design.
18
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MB39C502_DS405-00020-1v0-E, September 9, 2014
v1.1
D a t a S h e e t
VIN = 7.4V, VDD, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C503)
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
DRIVER
RHOH
At 100mA current sourcing
-
3(*1)
-
Ω
RHOL
At 100mA current sinking
-
1(*1)
-
Ω
RLOH
At 100mA current sourcing
-
4(*1)
-
Ω
RLOL
At 100mA current sinking
-
0.75(*1)
-
Ω
High side source current
ISRCH
VDRVH = 2.5V
-
0.7(*1)
-
A
High side sink current
ISINKH
VDRVH = 2.5V
-
1.1(*1)
-
A
Low side source current
ISRCL
VDRVL = 2.5V
-
0.5(*1)
-
A
Low side sink current
ISINKL
VDRVL = 2.5V
-
1.7(*1)
-
A
10
20
-
ns
High side on resistance
Low side on resistance
From DRVH turn off to DRVL turn on.
Dead time
tDEAD
Boost switch on resistance
RBST
IBST = 10mA
-
30
50
Ω
BST leak current
ILKBST
VBST = 30V
-
0.1
1.0
μA
And reverse it.
BOOST SWITCH
*1: No production tested, ensure by design.
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
19
v1.1
D a t a S h e e t
VIN = 7.4V, VOUT, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C504)
Parameter
Symbol
Value
Condition
Min
Typ
Max
4.95
5.00
5.05
Unit
REFERENCE VOLTAGE
This voltage is compared to feedback
Internal reference voltage
VREF
VOUTS input current
IVOUTS
voltage. Ta = 25°C
V
Ta = –10°C to 85°C
4.90
-
5.10
V
VVOUTS = 5.0V
2.5
5.0
12.5
μA
V
ENABLE, SLP_N
Enable condition
EN input current
SLP_N enable condition
SLP_N input current
VEN
Enable voltage range
2.5
-
25
VDSB
Disable voltage range
0
-
0.6
V
VEN = 5.0V
-
0.5
1.2
μA
IEN
VSLPDSB
LPM disable voltage range
0.65
-
5.5
V
VSLPEN
LPM enable voltage range
0
-
0.35
V
ISLP_N
VSLP_N = 5.0V
-
0
0.1
μA
-
400
800
μA
-
200
400
μA
-
50
100
μA
VOUT, VCC input current at VEN = 0V
-
0.1
1.0
μA
VVIN = 25V
-
20
30
μA
IVINSDN
VIN input current at VEN = 0V
-
0.1
1.0
μA
VUVLO
UVLO release voltage
3.99
4.14
4.29
V
VHYS
Hysteresis
0.005
0.070
0.200
V
300
-
1400
μs
598
665
732
μs
SUPPLY CURRENT
IVOUTPWM
VOUT, VCC input current at PWM
operating. TA = 25°C
VOUT, VCC input current at idle state in
VOUT supply current
IVOUTPFM
PFM operation. Static 0A inductor
current. TA = 25°C
VOUT, VCC input current at idle state in
IVOUTLPM
LPM operation. Static 0A inductor
current. TA = 25°C
VOUT shutdown current
VIN supply current
VIN shutdown current
IVOUTSDN
IVIN
UNDER VOLTAGE LOCKOUT
VCC UVLO threshold
SOFT START, DISCHARGE
Period of power on reset
tPOR
Ramp up time
tSS
From enable ON to the switching
initiating.
From the switching initiating after enable
ON to the output voltage reaches 95%.
Discharge resistance
RDISCHG
VOUT = 0.2V, discharge enable.
Discharge ends voltage
VDISCHG
VCSN voltage.
20
CONFIDENTIAL
50
100
200
Ω
0.07
0.10
0.13
V
MB39C502_DS405-00020-1v0-E, September 9, 2014
v1.1
D a t a S h e e t
VIN = 7.4V, VOUT, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C504)
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
ON TIMER
On time
tON
VVIN = 7.4V, VVOUT = 5.0V
802
872
942
ns
Minimum on time
tMINON
VVIN = 7.4V, VVOUT = 0.2V
100
200
-
ns
Minimum off time
tMINOFF
-
120
240
ns
21.0
26.0
31.0
mV
CURRENTLIMITATION
Current limitation threshold
VILIMIT
CSP–CSN difference voltage at ILIM
connects to VCC.
ILIM input current
IILIM
VILIM = 5.0V
-
0
0.1
μA
CSP input current
ICSP
VCSP = 5.0V
-
2.0
5.0
μA
CSN input current
ICSN
VCSN = 5.0V
-
8.0
20.0
μA
110
115
125
%
4
10
25
μs
65
70
75
%
40
100
200
μs
86
92
98
%
OVER AND UNDER VOLTAGE PROTECTION
Over voltage threshold ratio
Propagation delay of OV
Under voltage threshold ratio
Propagation delay of UV
RTOV
For target output voltage. At output
voltage increasing.
tOV
RTUV
For target output voltage. At output
voltage decreasing.
tUV
POWER GOOD MONITOR
Power good threshold ratio
RTPG
Hysteresis Ratio
RTHYS
Propagation delay
PWRGD leak current
PWRGD output voltage “L”
level
For target output voltage. At output
voltage increasing.
3
5
7
%
tPG
Power good
-
20
50
200
μs
tPB
Power bad
4
10
25
μs
ILKPG
VPWRGD = 5.5V
-
0
1
μA
VOLPG
IPWRGD = 1mA sink
-
0.05
0.10
V
TTSDH
Shut down temperature.
-
150(*1)
-
°C
-
125(*1)
-
°C
THERMAL SHUT DOWN
Shut down temperature
TTSDL
Exited temperature from thermal shut
down state.
*1: No production tested, ensure by design.
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
21
v1.1
D a t a S h e e t
VIN = 7.4V, VOUT, BST and EN connect to 5V power supply, PGND, LX = 0V. TA = –30°C to +85°C, unless
otherwise noted.
(MB39C504)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
4.75
5.00
5.25
V
25
-
-
mA
-
80
125
mA
VOUT voltage rising.
4.35
4.50
4.60
V
Hysteresis voltage.
0.08
0.10
0.12
V
100
150
400
μs
5V LDO
Output voltage
VLDO5
Output current
ILDO5
Output short current
ILDO5S
VSWOVR
Switchover voltage
VHYS
Startup time
tSLDO5
No switchover.
VOUT input voltage < 4.4V
No switchover.
VVIN = 5.4V
No switchover.
VLDO5 = 0V
LDO5 voltage reaches to 4.2V.
CLDO5, CVCC = 1.0μF
DRIVER
High side on resistance
Low side on resistance
RHOH
At 100mA current sourcing
-
3(*1)
-
Ω
RHOL
At 100mA current sinking
-
1(*1)
-
Ω
RLOH
At 100mA current sourcing
-
4(*1)
-
Ω
RLOL
At 100mA current sinking
-
0.75(*1)
-
Ω
High side source current
ISRCH
VDRVH = 2.5V
-
0.7(*1)
-
A
High side sink current
ISINKH
VDRVH = 2.5V
-
1.1(*1)
-
A
Low side source current
ISRCL
VDRVL = 2.5V
-
0.5(*1)
-
A
Low side sink current
ISINKL
VDRVL = 2.5V
-
1.7(*1)
-
A
Dead time
tDEAD
10
20
-
ns
From DRVH turn off to DRVL turn on.
And reverse it.
BOOST SWITCH
Boost switch on resistance
RBST
IBST = 10mA
-
30
50
Ω
BST leak current
ILKBST
VBST = 30V
-
0.1
1.0
μA
*1: No production tested, ensure by design.
22
CONFIDENTIAL
MB39C502_DS405-00020-1v0-E, September 9, 2014
v1.1
D a t a S h e e t
11. Protections and Power Good function
11.1 Description
(MB39C502/C503/C504)
This PWM Control IC has some protection functions UVLO, OVP, UVP, ILIM, and TSD for the assumed
various power system failures. Details of these protections are written as follows.
Under Voltage Lockout (UVLO)
The under voltage lockout (UVLO) protects ICs from malfunction and protects the system from
destruction/deterioration, according to the reasons mentioned below.
− Transitional state when the voltage inputs to VCC (5V power supply) terminal.
− Momentary decrease
To prevent such a malfunction, this function detects a voltage drop of the 5V power supply, and stops IC
operations. When the voltage of 5V power supply exceeds the threshold voltage of the under voltage lockout
protection circuit, the system is restored.
Over Voltage Protection (OVP)
This function stops the output voltage when the output voltage has increased, and protects devices
connected to the output. When the over voltage is detected, the controller is fixed that the high side
switching FET is turned off and the low side switching FET is turned on with 10μs propagation delay. When
the enable is reentered, this fixed state is released and beginning soft start.
Under Voltage Protection (UVP)
This function stops the output voltage when the output voltage has lowered, and protects devices connected
to the output. When the under voltage is detected, the controller is fixed that the high side switching FET is
turned off and the low side switching FET is turned off with 100μs propagation delay. When the enable is
reentered, this fixed state is released and beginning soft start.
Over Current Limitation (ILIM)
This function limits the output current when it has increased, and protects devices connected to the output.
This function detects the inductor valley current with current sense resister RSENSE. The differential voltage
of the CSP-CSN terminals is amplified to x20 by internal current sense amplifier, and compared to the limit
voltage of 480mV fixed at internal preset condition. Until the amplified voltage fall the limit voltage, the high
side switching FET is held in the off state. After the voltage has fallen below the limit voltage, the high side
switching FET is placed into the ON state. This limits the lower bound of the inductor current and also
restricts the over current. As a result, it becomes operation that the output voltage droops.
Thermal Shutdown (TSD)
This function prevents the PWM Control IC from a thermal destruction. If the junction temperature reaches
+150°C, the high side and low side switching FET are turned off. Then the discharge operation is carried out
to discharge the output capacitor (The discharge operation continues until the state of the thermal shutdown
released). If the junction temperature drops to +125°C, the soft start is automatically reactivated.
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
23
v1.1
D a t a S h e e t
Power Good (PWRGD)
Power good flag is hoisted at PWRGD terminal (Open Drain) to “Hi-Z” level with 50μs propagation delay,
when the output voltage becomes larger than 92% of the output setting voltage. It is related by the OVP
protection written above. When the output voltage becomes lower than power good threshold level, the
PWRGD terminal is changed to “L” level with 10μs propagation delay.
State Table of Protection Function
(MB39C502/C503/C504)
High Side
Low Side
Output
FET
FET
state
Under Voltage Lockout (UVLO)
OFF
OFF
OFF
Over Voltage Protection (OVP)
OFF
ON
Under Voltage Protection (UVP)
OFF
OFF
Switching
Switching
−
OFF
OFF
OFF
Protection Function
Over Current Limitation (ILIM)
Thermal Shutdown (TSD)
Remarks
After releasing UVLO, the System is an automatic
restoration with soft start.
Latch
Latch stall.
OFF
It returns the System by enable reentry.
Latch
Latch stall.
OFF
It returns the System by enable reentry.
The output voltage is drooped with current limitation.
After releasing TSD, the System is an automatic
restoration with soft start.
11.2 Timing Chart
(MB39C502/C503/C504)
Under Voltage Lockout Protection (UVLO)
24
CONFIDENTIAL
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v1.1
D a t a S h e e t
Over Voltage Protection (OVP)
Under Voltage Protection (UVP)
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
25
v1.1
D a t a S h e e t
Over Current Limitation (ILIM)
Thermal Shutdown (TSD)
26
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v1.1
D a t a S h e e t
12. Enhanced LPM Description
(MB39C502/C503/C504)
This PWM controller has some features for high efficiency technology with “Ultra low quiescent current” and
“Extended on time” on asserting SLP_L signal from the system.
Notes
−
−
Perform transferring to Enhanced LPM in the static switching state after 2ms from EN turn on. The
soft starting on the enabling Enhanced LPM does not allow this controller.
In Enhanced LPM, maximum loading current is less than critical current of “Discontinuous
Conductive Mode”, in other words “pulse skip mode”.
12.1 Ultra Low Quiescent Current
(MB39C502/C503/C504)
This controller has the feature of “Ultra low quiescent current” 30uA in enhanced LPM. So that the IC power
loss is effectively improved efficiency in DCDC light load.
12.2 Extended On Time
(MB39C502/C503/C504)
This controller uses feed forward on-time architecture with the information of input and output voltage. And
this controller is transferred “Extended on-time” keeping the input and output voltage information in
enhanced LPM. BY the on time is extended, gate drive loss is reduced by decreasing the switching
frequency.
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
27
v1.1
D a t a S h e e t
12.3 Timing Chart of Enhanced LPM
(MB39C502/C503/C504)
This controller is transferred to enhanced LPM synchronized the zero crossing of inductor current, and
transferred to normal operation with 100ns propagation delay avoid the switching period.
ILOAD
ILOAD
SLP_N
SLP_N
< 100ns
VR mode
Inductor
current
normal
0A
low power
synchronized with zero cross
flag of Inductor Current
VR mode
Inductor
current
Idle state
Idle state
ILOAD
ILOAD
SLP_N
SLP_N
low power
normal
anytime for idle period
0A
Idle state
Idle state
< 1.25us (< fSW_CCM-1)
VR mode
Inductor
current
Idle state
28
CONFIDENTIAL
normal
0A
keep the normal mode
VR mode
Inductor
current
Idle state
low power
0A
Idle state
normal
Wait the timing
becomes to an idle
mode
Idle state
MB39C502_DS405-00020-1v0-E, September 9, 2014
v1.1
D a t a S h e e t
13. Over Current Alerting Description
(MB39C502/C503)
This controller has “Over Current Alerting” function. In near over current limitation range, the ALERT_N with
Nch open drain terminal is change to “L” level. Over current alerting level is set 85% for over current
limitation level.
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
29
v1.1
D a t a S h e e t
14. Application Note
14.1 Setting Operating Conditions
14.1.1 Setting Output Voltage
The output voltage can be set by adjusting the setting output voltage resister ratio. Setting output voltage is
calculated by the following formula.
(MB39C502)
VOUT 
R1  R2
 0.7
R2
(MB39C503/C504)
VOUT 
R1  R 2
 1.0
R2
VOUT
R1, R2
: output setting voltage (V)
: Feedback resistor (Ω)
The total resistor value (R1+R2) of the setting output resistor should be selected up to 300kΩ.
When the output voltage setting value is higher than 1.2V, select resistance that the current of 300μA or
more flows into feedback resistor.
14.1.2
Setting Over Current Limitation and Over Current Alerting
The over current limitation value can be set by adjusting the current sense resistor. Calculate the resister
value by the following formula.
(MB39C502)




1

I V  300  109 

RSENSE  0.025   I LIMIT  L  OUT
2
L


1

V
 300 10 9
ΔI
R SENSE  0.024   I LIMIT  L  OUT
2
L

(MB39C503/C504)
RSENSE
ILIMIT
ΔIL
VOUT
L
: Over current limitation value setting resister (Ω)
: Over current limitation value (A)
: Inductor ripple current peak to peak value (A)
: Output Voltage (V)
: Inductance (H)
The over current limitation value needs to set a sufficient margin against the maximum load current.
The over current alerting value is set with over current limitation value as following formula.
30
CONFIDENTIAL
MB39C502_DS405-00020-1v0-E, September 9, 2014
v1.1
D a t a S h e e t
(MB39C503/C504)
 0.024 VOUT  300 10 9
I ALERT  

2 L
 R SENSE
RSENSE
IALERT
ΔIL
VOUT
L
: Over current limitation value setting resister (Ω)
: Over current Alerting value (A)
: Inductor ripple current peak to peak value (A)
: Output Voltage (V)
: Inductance (H)
MB39C502_DS405-00020-1v0-E, September 9, 2014
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
ΔI
  0.85  L

2

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14.2 Selection Parts
14.2.1 Selection of Smoothing Inductor
(MB39C502/C503/C504)
As a rough guide, inductance of an inductor should keep the peak to peak value of inductor ripple current
below 50% of the maximum output current. The inductance fulfilling the above condition can be found by the
following formula.
L
VIN  VOUT
VOUT

LOR  I OUT _ MAX VIN  f SW
L
: Inductance (H)
IOUT_MAX
: Maximum load current
LOR
: Inductor ripple current peak to peak value – Maximum output current ratio (less than
0.5)
VIN : Power supply voltage (V)
VOUT
: Output Voltage (V)
fSW
: Switching frequency (Hz)
The minimum output current (critical current) in the condition that inductor current does not flow in reverse
can be found by the following formula.
I OC 
VOUT VIN  VOUT

2  L VIN  f SW
IOC
L
VIN
VOUT
fSW
: Critical current (A)
: Inductance (H)
: Power supply voltage (V)
: Output voltage (V)
: Switching frequency (Hz)
The maximum value of the current flowing through the inductor needs to be found in order to determine
whether the current flowing through the inductor is within the rated value. The maximum current flowing
through the inductor can be found by the following formula.
I L _ MAX  I OUT _ MAX 
IL_MAX
IOUT_MAX
ΔIL
32
CONFIDENTIAL
ΔI L
2
: Maximum inductor current (A)
: Maximum load current (A)
: Inductor ripple current peak to peak value (A)
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14.2.2
Selection of Switching FET
(MB39C502/C503/C504)
In general, MOSFET should be used with a 30V absolute maximum rating. Obtain the maximum value of the
current flowing through the switching FET in order to determine whether the current flowing through the
switching FET is within the rated value. The maximum current flowing through the switching FET can be
found by the following formula.
I D _ MAX  I OUT _ MAX 
ID_MAX
IOUT_MAX
ΔIL
ΔI L
2
: Maximum switching FET drain current (A)
: Maximum load current (A)
: Inductor ripple current peak to peak value (A)
In addition, find the loss of the switching FET in order to determine whether the allowable loss of the
switching is within the rated value. The allowable loss of the high side FET can be found by the following
formula.
PFET _ HS  PRON _ HS  RSW _ HS
PFET_HS
PRON_HS
PSW_HS
: Overall Loss of high side FET (W)
: Conduction loss of high side FET (W)
: Switching loss of high side FET (W)
The conduction loss of high side is followed as.
PRON _ HS  I OUT _ MAX 
2
PRON_HS
IOUT_MAX
VIN
VOUT
RON_HS
VOUT
 RON _ HS
VIN
: Conduction loss of high side FET (W)
: Maximum load current (A)
: Power supply voltage (V)
: Output voltage (V)
: On resistance of high side FET (Ω)
The switching loss of high side is followed as.
PSW _ HS  1.56  VIN  f SW  I OUT _ MAX  QSW
PSW_HS
VIN
fSW
IOUT_MAX
QSW
: Switching loss of high side FET (W)
: Power supply voltage (V)
: Switching frequency (Hz)
: Maximum load current (A)
: Amount of high side FET gate switch electric charge (C)
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MOSFET has a tendency where the gate drive loss increases because lower voltage product has the bigger
amount of gate electric charge (QG). Normally, we recommend a 4V drive product, however, the idle period
at light load (both the high side FET and the low side FET is off period) get longer and the gate drive voltage
of the high side FET may decrease, in the automatic PFM/PWM transition. The voltage drops most at no
load mode. At the time, confirm that the boost voltage (voltage between BST-LX pins) is a big enough value
for the gate threshold value voltage of the high side FET.
If it is not enough, consider adding the boost diode, increasing the capacitor value of the capacitor or using a
2.5V (or 1.8V) drive product to the high side FET.
The allowable loss of the low side FET can be found by the following formula.
 V
2
PFET _ LS  PRON _ LS  I OUT _ MAX  1  OUT
VIN

PFET_LS
PRON_LS
IOUT_MAX
VIN
VOUT
RON_LS

  RON _ LS

: Overall loss of low side FET (W)
: Conduction loss of low side FET (W)
: Maximum output current (A)
: Switching power supply voltage (V)
: Output voltage (V)
: On resistance of low side FET (Ω)
In switching of low side FET, the transiting voltage between drain to source is generally small. The switching
FET loss is omitted in this document as it is negligible.
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14.2.3
Selection of Fly Back Diode
(MB39C502/C503/C504)
This device is improved by adding the fly back diode when the conversion efficiency improvement or the
suppression of the low side FET fever is desired, although those are unnecessary to execute normally. The
effect is achieved in the condition where the switching frequency is high or output voltage is lower. Select
period for the electric current flow into fly back diode is limited to dead time period because the synchronous
rectification system is adopted (as for the dead time, see “Electrical Characteristics”). Each rating for the fly
back diode can be calculated by the following formula.
I D  I OUT _ MAX  f SW  t D1  t D 2 
ID
IOUT_MAX
fSW
tD1, tD2
: Forward current rating of SBD (A)
: Maximum load current (A)
: Switching frequency (Hz)
: Dead times (s)
I FSM  I OUT _ MAX 
IFSM
IOUT_MAX
ΔIL
I L
2
: Rated value of fly back diode (V)
: Maximum output current (A)
: Inductor ripple current peak to peak value (A)
VR _ FLY  VIN
VR_FLY
VIN
14.2.4
: DC reversing voltage of fly back diode (V)
: Switching power supply voltage (V)
Selection of Boost Diode
(MB39C502)
Select a schottky barrier diode (SBD) that has a small forward voltage drop. The current to drive the gate of
High-side FET flows to the SBD of the boost circuit. The average current can be found by the following
formula. Select a boost diode that keep the average current below the current rating.
I D  QG _ HS  f SW
ID
QG_HS
fSW
: Forward current (A)
: Total gate electric charge of high-side FET (C)
: Switching Frequency (Hz)
The rating of the boost diode can be found by the following formula.
VR _ BOOST  VIN
VR_BOOST
VIN
: Boost Diode DC reverse voltage (V)
: Switching power supply voltage (V)
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14.2.5
Selection of Input Capacitor
(MB39C502/C503/C504)
Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the
tantalum capacitor and the polymer capacitor of low ESR when a mass capacitor is needed as the ceramic
capacitor cannot support.
The ripple voltage is generated in the power supply voltage by the switching operation. Calculate the lower
bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of the power
supply from the following formula.
ΔVIN 
I OUT _ MAX
ΔVIN
IOUT_MAX
CIN
VIN
VOUT
fSW
ESR
ΔIL
C IN

VOUT
ΔI 

 ESR   I OUT _ MAX  L 
VIN  f SW
2 

: Power supply ripple voltage peak to peak value (V)
: Maximum load current (A)
: Input capacitance (F)
: Power supply voltage (V)
: Output voltage (V)
: Switching frequency (Hz)
: Series resistance component of input capacitor (Ω)
: Ripple current peak to peak value of inductor (A)
Capacitor has frequency characteristics, the temperature characteristics, and the voltage characteristics, etc.
The effective capacitance might become extremely small depending on the use conditions. Note the
effective capacitance in the use conditions.
Calculate ratings of the input capacitor by following formula.
VCIN  VIN
VCIN
VIN
: Withstand voltage of the input capacitor (V)
: Power supply voltage (V)
Irms  I OUT _ MAX 
Irms
IOUT_MAX
VIN
VOUT
36
CONFIDENTIAL
VOUT  VIN  VOUT

VIN
: Allowable ripple current of input capacitor (effective value) (A)
: Maximum load current (A)
: Power supply voltage (V)
: Output voltage (V)
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14.2.6
Selection of Output Capacitor
Since a high ESR causes the output ripple voltage to increase, a low ESR capacitor is needs to be used in
order to reduce the output ripple voltage. Generally, the ceramic capacitor is used as the output capacitor.
With the switching ripple voltage taken consideration, the minimum capacitance required can be found by
the following formula.
(MB39C502/C503/C504)
COUT 
COUT
ESR
ΔVOUT
ΔIL
1
2π  f SW  ΔVOUT ΔI L  ESR 
: Output capacitance (F)
: Series resistance element of output capacitor (Ω)
: Output ripple voltage (V)
: Inductor ripple current peak to peak value (A)
Also, it is necessary to unite a pole by the output capacitor and the output load with a zero by the internal
compensation circuit, and to limit the crossover frequency. The minimum capacitance required can be found
by the following formula.
(MB39C502)
C OUT  42.5  10 6 
I OUT _ MAX
VOUT
(MB39C503)
COUT  49.0  10 6 
IOUT_ MAX
VOUT
(MB39C504)
C OUT  21.7  106  I OUT _ MAX
(MB39C502)
C OUT  0.59  10 6 
1
R SENSE  VOUT
(MB39C503)
COUT  0.67  10 6 
1
R SENSE  VOUT
(MB39C504)
C OUT  0.27  10 6 
1
R SENSE
IOUT_MAX
: Maximum output load current (A)
VOUT
: Output voltage (V)
RSENSE
: Over current limitation value setting resister (Ω)
MB39C502_DS405-00020-1v0-E, September 9, 2014
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37
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Moreover, the output capacitance is also derived from the allowable amount of overshoot and under shoot.
Adjust the capacitance so that the overshoot/undershoot voltage should not exceed the target voltage
range.
14.2.7
Selection of Boost Capacitor
To drive the gate of high side FET, the boost capacitor must have enough stored charge. 0.47μF is assumed
to be standard; however, it is necessary to adjust it when the high side FET Q G is big. Consider the
capacitance calculated by the following formula as the lowest value for the boost capacitance and select a
thing anymore.
(MB39C502/C503/C504)
C BST  10  QG _ HS
CBST
QG_HS
: Boost capacitance (F)
: Amount of high side FET gate charge (C)
Calculate ratings of the boost capacitor by the following formula.
(MB39C502/C503)
VCBST  VVDD
(MB39C504)
VCBST  VLDO5
VCBST
VVDD
VLDO5
38
CONFIDENTIAL
: Withstand voltage of the boost capacitor (V)
: Input voltage of VDD terminal (V)
: Input voltage of LDO5 terminal (V)
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14.2.8
Selection of VDD Capacitor
4.7μF is assumed to be a standard, and when QG of switching FET used large, it is necessary to adjust it. To
suppress the ripple voltage by the switching FET gate drive, consider the capacitance calculated by the
following formula as the lowest value for VDD Capacitor and select a thing any more.
Calculate ratings of the VDD terminal capacitor by the following formula.
(MB39C502/C503)
CVDD  50  QG
(MB39C504)
C LDO5  50  QG
CVDD
CLDO5
QG
: VDD pin capacitance (F)
: LDO5 pin capacitance (F)
: Total amount of high and low side FETs gate charge (C)
Calculate ratings of the VDD terminal capacitor by the following formula.
(MB39C502/C503)
VCVDD  VVDD
(MB39C504)
VCLDO5  VLDO5
VCVDD
VVDD
VCLDO5
VLDO5
14.2.9
: Withstand voltage of the VDD terminal capacitor (V)
: Input voltage of VDD terminal (V)
: Withstand voltage of the LDO5 terminal capacitor (V)
: Input voltage of LDO5 terminal (V)
Selection of VCC Capacitor and Resistor
(MB39C502/C503)
Connect 1.0μF between VCC to AGND terminal. Connect 10Ω between VCC to VDD terminal.
(MB39C504)
Connect 1.0μF between VCC to AGND terminal. Connect 10Ω between VCC to LDO5 terminal.
MB39C502_DS405-00020-1v0-E, September 9, 2014
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39
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14.3 Layout
(MB39C502/C503)
Consider the points listed below and do the layout design.
 Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor








40
CONFIDENTIAL
connected with the VCC and VDD pins, and AGND pin of the switching system parts with switching system
GND (PGND). Connect other GND connection pins with control system GND (AGND), and separate each
GND, and try not to pass the heavy current path through the control system GND (AGND) as much as
possible. In that case, connect control system GND (AGND) and switching system GND (PGND) at the
single point of GND (PGND) directly below IC. Switching system parts are Input capacitor (CIN), Switching
FET, fly back diode (SBD), inductor (L) and Output capacitor (COUT).
Connect the switching system parts as much as possible on the surface. Avoid the connection through the
through hole as much as possible.
As for AGND pins of the switching system parts, provide the through hole at the proximal place, and
connect it with GND of internal layer.
Pay the most attention to the loop composed of input capacitor (C IN), switching FET, and fly back diode
(SBD). Consider parts are disposed mutually to be near for making the current loop as small as possible.
Place the bootstrap capacitor (CBST) proximal to BST and LX pins of IC as much as possible.
Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current flows
momentary in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.
Large electric current flows momentary in the net of DRVH and DRVL pins connected with the gate of
switching FET. Wire the line width of about 0.8 mm to be a standard, as short as possible. Take special
care about the line of the DRVL pin, and wire the line as short as possible.
By-pass capacitor (CVCC, CVDD) connected with VCC, and VDD should be placed close to the pin as much
as possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal
through-hole.
Pull the feedback line to be connected to the FB pin of the IC separately from near the output capacitor pin,
whenever possible. Consider the line connected with FB pins to keep away from a switching system parts
as much as possible because it is sensitive to the noise.
Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to
the FB pin. In addition, for the internal layer right under the component mounting place, provide the control
system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the power supply
as much as possible.
Consider that the discharge current momentary flows into the CSN pin (about 10mA at 1.0V output
voltage) when the DC/DC operation stops, and then sustain the width for the feedback line.
There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and
parts sensitive to noise should be considered to be placed away from the inductor (or backside of place
equipped with inductor).
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GND routing example
Layout example of switching components
High Side
Switching FET
Surface Layer
CBST
VIN
To LX
CVIN
PGND
Low Side
Switching FET
CVCC
(Top View)
CVIN
EP :AGND
SBD
(Optional)
Sense
Resistor
PGND
Inductor
Inner Layer :
AGND
CVDD
Inner Layer :
PGND
Connect the PGND to the AGND at single
point directly under the IC
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
Output
Capacitor
VOUT
To CSP
VOUT Sense
To CSN
41
v1.1
D a t a S h e e t
(MB39C504)
Consider the points listed below and do the layout design.
 Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor








42
CONFIDENTIAL
connected with the VCC and LDO5 pins, and AGND pin of the switching system parts with switching
system GND (PGND). Connect other GND connection pins with control system GND (AGND), and
separate each GND, and try not to pass the heavy current path through the control system GND (AGND)
as much as possible. In that case, connect control system GND (AGND) and switching system GND
(PGND) at the single point of GND (PGND) directly below IC. Switching system parts are Input capacitor
(CIN), Switching FET, fly back diode (SBD), inductor (L) and Output capacitor (C OUT).
Connect the switching system parts as much as possible on the surface. Avoid the connection through the
through hole as much as possible.
As for AGND pins of the switching system parts, provide the through hole at the proximal place, and
connect it with GND of internal layer.
Pay the most attention to the loop composed of input capacitor (C IN), switching FET, and fly back diode
(SBD). Consider parts are disposed mutually to be near for making the current loop as small as possible.
Place the bootstrap capacitor (CBST) proximal to BST and LX pins of IC as much as possible.
Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current flows
momentary in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.
Large electric current flows momentary in the net of DRVH and DRVL pins connected with the gate of
switching FET. Wire the line width of about 0.8 mm to be a standard, as short as possible. Take special
care about the line of the DRVL pin, and wire the line as short as possible.
By-pass capacitor (CVCC, CLDO5) connected with VCC, and LDO5 should be placed close to the pin as
much as possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the
proximal through-hole.
Pull the feedback line to be connected to the FB pin of the IC separately from near the output capacitor pin,
whenever possible. Consider the line connected with FB pins to keep away from a switching system parts
as much as possible because it is sensitive to the noise.
Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to
the FB pin. In addition, for the internal layer right under the component mounting place, provide the control
system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the power supply
as much as possible.
Consider that the discharge current momentary flows into the CSN pin (about 10mA at 1.0V output
voltage) when the DC/DC operation stops, and then sustain the width for the feedback line.
There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and
parts sensitive to noise should be considered to be placed away from the inductor (or backside of place
equipped with inductor).
MB39C502_DS405-00020-1v0-E, September 9, 2014
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D a t a S h e e t
GND routing example
Layout example of switching components
High Side
Switching FET
Surface Layer
CBST
VIN
To LX
CVIN
PGND
Low Side
Switching FET
CVCC
(Top View)
CVIN
EP :AGND
SBD
(Optional)
Sense
Resistor
PGND
Inductor
Inner Layer :
AGND
CLDO5
Inner Layer :
PGND
Connect the PGND to the AGND at single
point directly under the IC
MB39C502_DS405-00020-1v0-E, September 9, 2014
CONFIDENTIAL
Output
Capacitor
VOUT
To CSP
VOUT Sense
To CSN
43
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15. Ordering Information
Table 15-1 Ordering information
Part number
MB39C502WQN-G-AMERE1
MB39C503WQN-G-AMERE1
MB39C504WQN-G-AMERE1
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CONFIDENTIAL
Package
Remarks
16-pin plastic QFN
(WNT016)
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16. Package Dimensions
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17. Major Changes
Page
Section
Change Results
Revision 1.0
-
46
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-
Initial release
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
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chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions. If any products described in this document
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respective government entity will be required for export of those products.
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®
®
®
TM
Copyright © 2014 Spansion
All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse ,
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LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks
of their respective owners.
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