Easy, ±5V Split-Voltage Power Supply for Analog Circuits Draws Only 720nA at No Load Jim Drew Analog circuits often need a split-voltage power supply to achieve a virtual ground at the output of an amplifier. These split-voltage power supplies are generally low power supplies supporting tens of milliamps of differential current loads. Figure 1 shows such a power supply using two LTC3388-3 20V high efficiency step-down regulators powered from a 6V–12V power source. The positive voltage rail is created by configuring one LTC3388-3 in its standard buck topology while the negative voltage rail is created with a second LTC3388-3 by grounding the VOUT connection and using the GND pin as the negative voltage rail. The negative voltage rail is connected to the exposed pad of this LTC3388-3 and must be isolated from the system ground plane and have sufficient surface area to provide adequate cooling of the LTC3388-3. while maintaining output regulation. They are capable of supplying up to 50m A of load current and contain an accurate undervoltage lockout (UVLO) feature to maintain a low quiescent current when the input is below 2.3V. The output voltage is digitally programmable to four output regulated voltages along with a PGOOD status pin that indicates that the outputs are above 92% (typ) of the output setting. The LTC3388-1 can be digitally set to 1.2V, 1.5V, 1.8V or 2.5V while the LTC3388-3 can be set to 2.8V, 3.0V, 3.3V or 5.0V. Both devices are available in a 10-lead MSE or a 3mm × 3mm DFN package. The LTC3388-1 and LTC3388-3 are high efficiency step-down regulators that draw only 720n A (typ) of DC current at no load Figure 1. Easy split-voltage power supply 1µF 6.3V 2.2µF 25V 4.7µF 6.3V 2.2µF 25V 4.7µF 6.3V VIN LTC3388-3 CAP SW VIN2 VOUT 100µH IND-LPS5030 PGOOD EN D0, D1 STBY VOUT 5V 100µF 50mA 6.3V VIN2 VIN LTC3388-3 CAP SW VIN2 VOUT EN PGOOD STBY D0, D1 100µH IND-LPS5030 100µF 6.3V 100 1 0.01 0.0001 0.0001 VIN2 GND VOUT –5V 50mA 40 | July 2011 : LT Journal of Analog Innovation As the output voltage decays due to an external load, the buck regulator remains Figure 2. Input current versus output current for the split voltage power supply of Figure 1 (–5V curve also applies to –5V supply shown in Figure 3) GND 1µF 6.3V Configuring the LTC3388 as a buck regulator creates a positive voltage by ramping the inductor current up to IPEAK (150m A typ) through an internal PMOS switch and then ramping the current down to 0m A through an internal NMOS switch. This action charges the output capacitor to slightly above the regulation voltage at which time the buck regulator enters sleep mode. INPUT CURRENT (mA) 6V TO 12V OPERATION OF THE SPLIT-VOLTAGE SUPPLY VOUT = ±5V VOUT = –5V VIN = 12V 1 0.01 OUTPUT CURRENT (mA) 100 design ideas The LTC3388-1 and LTC3388-3 are high efficiency step-down regulators that draw only 720nA (typ) of DC current at no load while maintaining output regulation. They are capable of supplying up to 50mA of load current and contain an accurate undervoltage lockout (UVLO) feature to maintain a low quiescent current when the input is below 2.3V. in sleep mode and an internal sleep comparator monitors the output voltage. When the output voltage drops below the regulation voltage, the buck regulator wakes up and the cycle repeats. This hysteretic method of providing a regulated output reduces losses associated with MOSFET switching and maintains an output voltage at light loads. The buck regulator is able to support 50m A of average load current when it is switching. A negative output voltage rail is created by grounding the VOUT node of the buck regulator. This sets the ground reference connection of the LTC3388 as a negative voltage rail. The voltage from the VIN pin to the negative voltage rail is the sum of the input voltage plus the magnitude of negative voltage rail. This limits the source voltage to 20V (the LTC3388’s VIN(MAX)) minus the magnitude of the negative rail voltage. The inductor current is ramped up to IPEAK through the internal PMOS switch as in the buck regulator configuration and then down to zero through the NMOS switch, charging the output capacitor to a negative voltage. This switching action is that of an inverting critical NEGATIVE VOLTAGE SUPPLY conduction synchronous buck-boost converter. The maximum output current of this configuration is limited by the peak current of the inductor, the input voltage and the magnitude of the output voltage. The expression below estimates the maximum output current available. IOUT = Figure 3 shows the buck-boost configuration creating a negative output voltage rail. In this configuration the input voltage needs only be above the UVLO voltage of 2.5V (typ) to start the regulator. The –5V curve in Figure 2 applies here with a 12V input, as in the previous circuit. IPEAK VIN • – 2 VIN + V OUT CONCLUSION An easy-to-implement split-voltage power supply using the LTC3388 yields a low quiescent current, high efficiency solution for powering low current analog circuits that need a virtual ground output. The output voltage of each device is digitally programmable to four output voltages from 1.2V to 5.0V and will support a load current up to 50m A. Each regulator requires only four external capacitors and one inductor, covering minimal board real estate. A PGOOD status pin is provided to indicate when the output is within regulation. The LTC3388-1 and the LTC3388-3 are available in a 10-lead MSE or a 3mm × 3mm DFN package. n In a split voltage power supply application, the analog circuit is connected between the positive voltage rail and the negative voltage rail. This results in the load current of both regulators to be equal in magnitude. Figure 2 is a plot of the input current versus the output current for the circuit in Figure 1. At very low load currents, <10µ A, the effect of the input quiescent current can be seen as a positive offset in the input current. For higher load currents, >100µ A, this effect is minimal and the input current is approximately equal to the output current. The expression for the input current may be approximated as: + IIN = – IOUT V OUT + V OUT • + 2 • IQ η VIN h = EFFICIENCY 3V TO 15V 1µF 6.3V Figure 3. Negative voltage power supply 2.2µF 25V VIN LTC3388-3 CAP SW VIN2 VOUT 100µF 6.3V PGOOD EN 4.7µF 6.3V 100µH IND-LPS5030 D0, D1 STBY VIN2 GND VOUT –5V 50mA July 2011 : LT Journal of Analog Innovation | 41