LTC3335 - Nanopower Buck-Boost DC/DC with Integrated Coulomb Counter

LTC3335
Nanopower Buck-Boost
DC/DC with Integrated
Coulomb Counter
Description
Features
680nA Input Quiescent Current (Output in
Regulation at No Load)
n1.8V to 5.5V Input Operating Range
n Selectable Output Voltages of 1.8V, 2.5V, 2.8V,
3V, 3.3V, 3.6V, 4.5V, 5V
n Integrated Coulomb Counter Measures
Accumulated Battery Discharge
n±5% Battery Discharge Measurement Accuracy
n Programmable Peak Input Current of 5mA, 10mA,
15mA, 25mA, 50mA, 100mA, 150mA, 250mA
n Up to 50mA of Output Current
n Up to 90% Efficiency
n Programmable Coulomb Counter Prescaler for Wide
Range of Battery Sizes
n Programmable Discharge Alarm Threshold
n I2C Interface
n Low Profile (0.75mm) 20-Lead (3mm × 4mm) QFN
Package
The LTC®3335 is a high efficiency, low quiescent current
(680nA) buck-boost DC/DC converter with an integrated
precision coulomb counter which monitors accumulated
battery discharge in long life battery powered applications.
The buck-boost can operate down to 1.8V on its input and
provides eight pin-selectable output voltages with up to
50mA of output current.
n
The coulomb counter stores the accumulated battery discharge in an internal register accessible via an I2C interface.
The LTC3335 features a programmable discharge alarm
threshold. When the threshold is reached, an interrupt is
generated at the IRQ pin.
To accommodate a wide range of battery types and sizes,
the peak input current can be selected from as low as 5mA
to as high as 250mA and the full-scale coulomb counter
has a programmable range of 32,768:1.
The LTC3335 is available in a 3mm × 4mm QFN-20 package.
Applications
n
n
n
n
L, LT, LTC, LTM, Linear Technology, the Linear logo, SmartMesh and Dust Networks are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Long Lifetime Primary Cell Battery Applications
Wireless Sensors
Remote Monitors
Dust Networks® SmartMesh® Applications
Typical Application
Efficiency vs Load for 100mA
IPEAK Setting
2.2mH TO 47µH
100
PRIMARY CELL
SW1
SW2
BAT
+
10µF
90
1.8V TO 5V
VOUT
PVOUT
PBAT
EN
DVCC
10k
10k
LTC3335
SCL
I2C
3
3
SDA
IRQ
PGOOD
IPK[2:0]
OUT[2:0]
80
47µF
GND
3335 TA01
EFFICIENCY (%)
IPEAK = 5mA TO 250mA
70
60
50
40
30
20 BAT = 3.6V
L = 150µH
10
DCR = 0.3Ω
0
0.001
0.01
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
1
0.1
ILOAD (mA)
10
100
3335 TA01a
3335f
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1
LTC3335
Absolute Maximum Ratings
Pin Configuration
(Note 1)
GNDA
PGOOD
SCL
IRQ
TOP VIEW
BAT, PBAT, VOUT, PVOUT Voltage................... –0.3V to 6V
EN, OUT[2:0],
IPK[2:0] Voltage ......–0.3V to [Lesser of (BAT + 0.3V) or 6V]
DVCC, SDA, SCL Voltage............................... –0.3V to 6V
PGOOD,
IRQ Voltage......–0.3V to [Lesser of (DVCC + 0.3V) or 6V]
SW1, SW2 Current............................................... 350mA
Operating Junction Temperature Range
(Notes 2, 3)............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
20 19 18 17
SDA
1
16 EN
DVCC
2
15 IPK2
OUT2
3
OUT1
4
OUT0
5
12 VOUT
GNDD
6
11 PVOUT
14 IPK1
BAT
13 IPK0
9 10
SW2
8
SW1
7
PBAT
21
PGND
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 52°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3335EUDC#PBF
LTC3335EUDC#TRPBF
LGTR
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
LTC3335IUDC#PBF
LTC3335IUDC#TRPBF
LGTR
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
3335f
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LTC3335
Electrical
Characteristics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2). BAT = PBAT = DVCC = 3.6V, GNDA = GNDD = PGND = 0V, VOUT = PVOUT.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Buck-Boost DC/DC
Input Voltage Range
l
1.8
5.5
V
440
680
360
700
1000
540
nA
nA
µA
Input Quiescent Current
Shutdown
Sleeping (In Regulation)
Not Sleeping
BAT and PBAT Combined
EN = 0
EN = 1
EN = 1, ISW1 = ISW2 = 0 (Note 4)
Regulated Output Voltage
1.8V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
1.737
1.806
1.794
1.863
V
V
2.5V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
2.425
2.508
2.492
2.575
V
V
2.8V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
2.716
2.809
2.791
2.884
V
V
3V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
2.910
3.010
2.990
3.090
V
V
3.3V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
3.200
3.311
3.289
3.400
V
V
3.6V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
3.492
3.612
3.588
3.708
V
V
4.5V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
4.365
4.515
4.485
4.635
V
V
5V Output Setting
Sleep Threshold
Wake-Up Threshold
l
l
4.850
5.017
4.983
5.150
V
V
(Note 5)
l
89
92
95
%
100
150
nA
l
225
200
250
250
275
275
mA
mA
l
135
125
150
150
165
165
mA
mA
l
90
85
100
100
110
110
mA
mA
l
45
42.5
50
50
55
55
mA
mA
l
21.5
20
25
25
27.5
27.5
mA
mA
l
12.5
12
15
15
16.5
16.5
mA
mA
l
8.25
8
10
10
11
11
mA
mA
l
4
3.75
5
5
5.5
5.5
mA
mA
PGOOD Falling Threshold
VOUT Leakage Current
All Output Settings, VOUT in Regulation
Input Peak Switch Current
250mA IPEAK Setting (Note 6)
150mA IPEAK Setting (Note 6)
100mA IPEAK Setting (Note 6)
50mA IPEAK Setting (Note 6)
25mA IPEAK Setting (Note 6)
15mA IPEAK Setting (Note 6)
10mA IPEAK Setting (Note 6)
5mA IPEAK Setting (Note 6)
IZERO Current Threshold (Note 7)
All IPEAK Settings
Available Output Current
100mA IPEAK Setting, VOUT = 3.3V
0
20
mA
mA
3335f
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3
LTC3335
Electrical
Characteristics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2). BAT = PBAT = DVCC = 3.6V, GNDA = GNDD = PGND = 0V, VOUT = PVOUT.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PMOS Switch A On-Resistance
(From PBAT to SW1)
250mA IPEAK Setting
150mA IPEAK Setting
100mA IPEAK Setting
50mA IPEAK Setting
25mA IPEAK Setting
15mA IPEAK Setting
10mA IPEAK Setting
5mA IPEAK Setting
0.38
0.55
0.76
1.40
2.67
4.36
6.48
12.82
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
NMOS Switch B On-Resistance
(From SW1 to PGND)
250mA IPEAK Setting
150mA IPEAK Setting
100mA IPEAK Setting
50mA IPEAK Setting
25mA IPEAK Setting
15mA IPEAK Setting
10mA IPEAK Setting
5mA IPEAK Setting
0.57
0.85
1.20
2.26
4.37
7.18
10.69
21.20
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
NMOS Switch C On-Resistance
(From SW2 to PGND)
IPK[2:0] = 1xx
IPK[2:0] = 0xx
0.37
2.05
Ω
Ω
PMOS Switch D On-Resistance
(From PVOUT to SW2)
PVOUT = VOUT = 3.3V
250mA IPEAK Setting
150mA IPEAK Setting
100mA IPEAK Setting
50mA IPEAK Setting
25mA IPEAK Setting
15mA IPEAK Setting
10mA IPEAK Setting
5mA IPEAK Setting
0.60
0.86
1.18
2.14
4.06
6.61
9.81
19.40
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
PMOS Switch Leakage
Switches A, D
SW1 = SW2 = 0V, BAT = 5.5V, VOUT = 5.5V
0
10
nA
NMOS Switch Leakage
Switches B, C
SW1 = BAT = 5.5V, SW2 = VOUT = 5.5V
0
10
nA
Coulomb Counter
qLSB (for Prescaler setting M=0)
250mA IPEAK Setting
(Notes 8,9)
150mA IPEAK Setting
100mA IPEAK Setting (Note 10)
Full-Scale Coulomb Count
(Battery Capacity)
7.031
4.218
l
2.728
2.812
A • hr
2.896
A • hr
50mA IPEAK Setting
1.406
A • hr
25mA IPEAK Setting
703.1
mA • hr
15mA IPEAK Setting
421.8
mA • hr
10mA IPEAK Setting
281.2
mA • hr
5mA IPEAK Setting
140.6
mA • hr
5mA IPEAK Setting, M=15, L = 2.2mH; (Smallest Battery)
1.094
mA • hr
100mA IPEAK Setting, M = 8, L = 100μH
l
2.717
250mA IPEAK Setting, M = 0, L = 47μH; (Largest Battery)
Total Unadjusted Coulomb Counter
Error (Note 10)
A • hr
2.801
2.885
1793
Buck-Boost Switching, 100mA IPEAK Setting, VOUT = 3.3V, BAT = 3.6V l
A • hr
A • hr
–5
5
l
1.8
5.5
l
BAT – 0.5
70
%
Digital Inputs and Output
DVCC Voltage
Digital Input High Voltage
4
For Pins EN, IPK[2:0], OUT[2:0]
For Pins SDA, SCL
V
V
%DVCC
3335f
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LTC3335
Electrical
Characteristics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2). BAT = PBAT = DVCC = 3.6V, GNDA = GNDD = PGND = 0V, VOUT = PVOUT.
PARAMETER
CONDITIONS
MIN
Digital Input Low Voltage
For Pins EN, IPK[2:0], OUT[2:0]
For Pins SDA, SCL
l
Digital Output High Voltage
For Pins PGOOD, IRQ; 1µA Out of Pin
l DVCC – 0.5
Digital Output Low Voltage
For Pins PGOOD, IRQ; 1µA Into Pin
For Pin SDA; 3mA Into Pin
l
Input High Current
For Pins EN, IPK[2:0], OUT[2:0], SDA, SCL
Input Low Current
For Pins EN, IPK[2:0], OUT[2:0], SDA, SCL
TYP
MAX
UNITS
0.5
30
V
%DVCC
V
0.5
0.4
V
V
0
10
nA
0
10
nA
400
kHz
I2C Timing Characteristics (See Figure 1)
I2C Read Address
I2C Write Address
11001001
11001000
Clock Operating Frequency
fSCL
Bus Free Time Between
STOP/START
tBUF
1.3
µs
Repeated START Set-Up Time
tSU,STA
600
ns
Hold Time (Repeated) START
Condition
tHD,STA
600
ns
Set-Up Time for STOP Condition
tSU,STO
600
ns
Data Set-Up Time (Input)
tSU,DAT
100
ns
Data Hold Time (Input)
tHD,DATI
0
Data Hold Time (Output)
tHD,DATO
0
0.9
µs
µs
Clock/Data Fall Time
tf
20
300
ns
Clock/Data Rise Time
tr
20
300
ns
Clock LOW Period
tLOW
1.3
µs
Clock HIGH Period
tHIGH
0.6
µs
Spike Suppression Time
tSP
50
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3335 is tested under pulsed load conditions such that TJ ≈
TA. The LTC3335E is guaranteed to meet specifications from 0°C to 85°C.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization, and correlation with statistical
process controls. The LTC3335I is guaranteed over the –40°C to 125°C
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal impedance, and other environmental factors.
Note 3: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD • θJA).
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The PGOOD Falling Threshold is specified as a percentage of the
average of the measured sleep and wake-up thresholds for each selected
output. The PGOOD rising threshold is equal to the sleep threshold. See
Regulated Output Voltage specification.
ns
Note 6: For the 100mA IPEAK setting, the value given in the table is
measured in a closed-loop set-up with a 100µH inductor, a 3.6V BAT
voltage, and the LTC3335 switching. For the other seven IPEAK settings,
the values given in the table are calculated from an open-loop DC
measurement of IPEAK (LTC3335 not switching), the propagation delay of
the IPEAK comparator, and the recommended inductor value for each IPEAK
setting.
Note 7: IZERO measurements are performed when the LTC3335 is not
switching. The values seen in operation will be slightly lower due to the
propagation delay of the comparators
Note 8: The equivalent charge of an LSB in the accumulated charge
register depends on the IPEAK setting and the internal pre-scaling factor M.
See Choosing Coulomb Counter Prescaler M section for more information.
1mA • hr = 3.6A • s = 3.6C.
Note 9: The values given in the table are for applications using the
recommended inductor value for each IPEAK setting.
Note 10: The specified accuracy of qLSB in percent is better than that of
the corresponding IPEAK because the full-scale ON time of the AC(ON)
time measurement is internally adjusted to compensate for errors in the
actual IPEAK value. The Total Unadjusted Coulomb Counter Error specified
includes any inaccuracy in qLSB.
3335f
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5
LTC3335
Timing Diagram
SDA
tLOW
tf
tSU,DAT
tr
tHD,STA
tf
tBUF
tr
tSP
SCL
S
tHD,STA
tHD,DAT
tHIGH
tSU,STA
Sr
tSU,STO
P
S
3335 TD
S = START, Sr = REPEATED START, P = STOP
Figure 1. Definition of Timing on I2C Bus
6
3335f
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LTC3335
Typical
Performance Characteristics
TA = 25°C, BAT = PBAT = 3.6V, GNDA = GNDD =
PGND = 0V, VOUT = PVOUT = 3.3V, 100mA IPEAK setting, unless otherwise noted.
3.0
3.6
4.2
BAT (V)
4.8
5.4
2.4
3.0
3.6
4.2
4.8
3335 G01
2.88
2.50
2.84
2.80
2.46
VOUT (V)
VOUT (V)
2.8V Output vs Temperature
2.5V Output vs Temperature
2.42
2.38
2.76
SLEEP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
2.34
2.72
2.68
2.60
2.26
2.56
2.22
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2.52
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G05
3335 G06
3.3V Output vs Temperature
3.10
3.35
3.05
3.30
3.00
3.6V Output vs Temperature
3.70
3.65
3.60
2.85
VOUT (V)
3.25
SLEEP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
3.20
3.15
3.55
SLEEP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
3.45
3.40
SLEEP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
3.30
2.75
3.05
2.70
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3.00
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G07
3.50
3.35
3.10
2.80
SLEEP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
2.64
2.30
3V Output vs Temperature
VOUT (V)
3335 G03
2.54
3335 G04
2.90
371
369
367
365
363
361
359
357
355
353
351
349
BAT = 5.5V
347
BAT = 3.6V
345
BAT = 1.8V
343
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G02
1.8V Output vs Temperature
1.86
1.84
1.82
1.80
1.78
1.76
SLEEP THRESHOLD
1.74
WAKE-UP THRESHOLD
1.72
PGOOD FALLING
1.70
1.68
1.66
1.64
1.62
1.60
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2.95
5.4
BAT (V)
VOUT (V)
2.4
125°C
85°C
25°C
–45°C
IBAT + IPBAT (µA)
125°C
85°C
25°C
–45°C
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1.8
Input Quiescent Current (Active)
vs Temperature
VOUT (V)
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1.8
Input Quiescent Current in Sleep
vs BAT
IBAT (nA)
IBAT (nA)
Input Quiescent Current in
Shutdown vs BAT
3.25
3335 G08
3.20
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G09
3335f
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7
LTC3335
Typical Performance Characteristics
PGND = 0V, VOUT = PVOUT = 3.3V, 100mA IPEAK setting, unless otherwise noted.
5V Output vs Temperature
IVOUT vs Temperature
4.60
5.10
200
4.55
5.05
180
4.50
5.00
4.45
4.95
4.40
4.90
4.35
4.85
140
SLEEP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
4.80
4.75
4.20
4.70
4.15
4.65
4.10
4.60
4.05
4.55
4.00
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
4.50
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
20
0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G12
IPEAK vs Temperature,
5mA Setting
IPEAK vs Temperature,
100mA Setting
254
252
250
248
246
101.6
100.8
100.0
99.2
98.4
97.6
96.8
96.0
95.2
94.4
93.6
92.8
92.0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
IPEAK (mA)
IPEAK (mA)
80
3335 G11
IPEAK vs Temperature,
250mA Setting
244
242
240
238
236
234
232
230
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G13
5.08
5.04
5.00
4.96
4.92
4.88
4.84
4.80
4.76
4.72
4.68
4.64
4.60
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G15
3335 G14
IPEAK vs BAT, 250mA Setting
105
262
IPEAK vs BAT, 100mA Setting
5.25
104
5.20
258
103
5.15
256
102
5.10
101
5.05
254
252
250
248
246
IPEAK (mA)
260
IPEAK (mA)
IPEAK (mA)
100
40
3335 G10
100
99
4.95
4.90
97
4.85
240
96
4.80
238
1.8
95
1.8
242
2.4
3.0
3.6
4.2
BAT (V)
4.8
5.4
3335 G16
2.4
3.0
4.2
3.6
BAT (V)
4.8
5.4
3335 G17
IPEAK vs BAT, 5mA Setting
5.00
98
244
8
120
60
IPEAK (mA)
4.25
VOUT = 5V
160
IVOUT (nA)
SLEEP THRESHOLD
WAKE-UP THRESHOLD
PGOOD FALLING
4.30
VOUT (V)
VOUT (V)
4.5V Output vs Temperature
TA = 25°C, BAT = PBAT = 3.6V, GNDA = GNDD =
4.75
1.8
2.4
3.0
4.2
3.6
BAT (V)
4.8
5.4
3335 G18
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LTC3335
Typical Performance Characteristics
PGND = 0V, VOUT = PVOUT = 3.3V, 100mA IPEAK setting, unless otherwise noted.
RDS(ON) vs Temperature,
250mA Setting
2.00
1.75
PMOS D, VOUT = 1.8V
PMOS D, VOUT = 5V
NMOS C, BAT = 1.8V
NMOS C, BAT = 5.5V
2.25
2.00
1.75
1.50
RDS(ON) (Ω)
RDS(ON) (Ω)
2.50
PMOS A, BAT = 1.8V
PMOS A, BAT = 5.5V
NMOS B, BAT = 1.8V
NMOS B, BAT = 5.5V
2.25
RDS(ON) vs Temperature,
5mA Setting
RDS(ON) vs Temperature,
250mA Setting
1.25
1.00
1.50
RDS(ON) (Ω)
2.50
1.25
1.00
0.75
0.75
0.50
0.50
0.25
0.25
0.00
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
0.00
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G19
100
Efficiency vs Load Current
for 250mA IPEAK Setting
90
80
80
70
70
60
50
40
30
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
20
10
0
0.001
–10 10 30 50 70 90 110 130
TEMPERATURE (°C)
100
90
0.01
BAT = 3.6V
L = 47µH
DCR = 0.33Ω
10
0.1
1.0
ILOAD (mA)
3335 G22
100
PMOS A, BAT = 1.8V
PMOS A, BAT = 5.5V
NMOS B, BAT = 1.8V
NMOS B, BAT = 5.5V
–10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3335 G21
EFFICIENCY (%)
PMOS D, VOUT = 1.8V
PMOS D, VOUT = 5V
NMOS C, BAT = 1.8V
NMOS C, BAT = 5.5V
EFFICIENCY (%)
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–50 –30
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–50 –30
3335 G20
RDS(ON) vs Temperature,
5mA Setting
RDS(ON) (Ω)
TA = 25°C, BAT = PBAT = 3.6V, GNDA = GNDD =
Efficiency vs Load Current
for 100mA IPEAK Setting
60
50
40
30
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
20
10
0
0.001
100
0.01
BAT = 3.6V
L = 100µH
DCR = 0.6Ω
10
0.1
1.0
ILOAD (mA)
3335 G23
Efficiency vs Load Current
for 5mA IPEAK Setting
100
100
3335 G24
Efficiency vs BAT for 250mA
IPEAK Setting
100
Efficiency vs BAT for 100mA
IPEAK Setting
90
60
50
40
30
20
10
0
0.001
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
BAT = 3.6V
L = 2.2mH
DCR = 11Ω
0.1
0.01
90
90
80
80
EFFICIENCY (%)
70
EFFICIENCY (%)
EFFICIENCY (%)
80
70
60
ILOAD = 25mA VOUT = 3.3V
ILOAD = 250µA L = 47µH
ILOAD = 25µA DCR = 0.33Ω
ILOAD = 5µA
50
1.0
ILOAD (mA)
3335 G25
40
1.8
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
5.3
3335 G26
70
60
ILOAD = 10mA VOUT = 3.3V
ILOAD = 100µA L = 100µH
ILOAD = 10µA DCR = 0.6Ω
ILOAD = 5µA
50
40
1.8
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
5.3
3335 G27
3335f
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9
LTC3335
Typical Performance Characteristics
PGND = 0V, VOUT = PVOUT = 3.3V, 100mA IPEAK setting, unless otherwise noted.
90
MAX ILOAD (mA)
80
EFFICIENCY (%)
100
ILOAD = 500µA VOUT = 3.3V
ILOAD = 50µA L = 2.2mH
ILOAD = 5µA
DCR = 11Ω
ILOAD = 1µA
70
60
50
40
Buck-Boost Maximum Load
vs BAT for 250mA IPEAK Setting
90
36
80
32
70
28
60
50
40
30
20
30
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
0
1.8
5.3
2.4
3.0
4.2
3.6
BAT (V)
4.8
3335 G28
3.35
1.8
3.34
ILOAD = 1mA
ILOAD = 10mA
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
0.2
0
1.8
2.4
3.0
4.2
3.6
BAT (V)
4.8
5.4
3.31
3.27
1.8
2.4
3.0
3.6
4.2
BAT (V)
4.8
5.4
BAT = 1.8V
BAT = 3.6V
BAT = 5.5V
3.31
3.30
0.01
0.1
1
LOAD CURRENT (mA)
10
3335 G33
3335 G32
Input Quiescent Current Into PBAT
Due to Gate Charge, VOUT = 3.3V,
Running Continuous
Buck-Boost Switching Waveforms
IPEAK = 5mA
IPEAK = 10mA
IPEAK = 15mA
IPEAK = 25mA
IPEAK = 50mA
IPEAK = 100mA
IPEAK = 150mA
IPEAK = 250mA
215
IPBAT (µA)
165
INDUCTOR
CURRENT
50mA/DIV
3335 G34
4.8
Buck-Boost Load Regulation,
VOUT = 3.3V, 100mA IPEAK Setting
3.27
0.001
5.4
OUTPUT
VOLTAGE
50mV/DIV
SW1
VOLTAGE
5V/DIV
SW2
VOLTAGE
5V/DIV
2ms/DIV
BAT = 3.6V, VOUT = 3.3V
COUT = 47µF, L = 100µH
100mA IPEAK SETTING
LOAD STEP FROM 1mA TO 20mA
4.2
3.6
BAT (V)
3.28
3.28
Buck-Boost Load Step Transient
LOAD
CURRENT
10mA/DIV
3.0
3.29
3335 G31
OUTPUT
VOLTAGE
20mV/DIV
2.4
3.32
3.32
3.29
0.4
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
3.33
3.30
0.6
12
3335 G30
3.33
1.4
VOUT (V)
MAX ILOAD (mA)
1.6
0.8
16
0
1.8
5.4
Buck-Boost Line Regulation,
VOUT = 3.3V, 100mA IPEAK Setting
3.34
1.0
20
3335 G29
Buck-Boost Maximum Load
vs BAT for 5mA IPEAK Setting
1.2
24
4
VOUT (V)
2.0
Buck-Boost Maximum Load
vs BAT for 100mA IPEAK Setting
8
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
10
20
1.8
40
MAX ILOAD (mA)
100
Efficiency vs BAT for 5mA
IPEAK Setting
TA = 25°C, BAT = PBAT = 3.6V, GNDA = GNDD =
115
65
20µs/DIV
BAT = 3.6V, VOUT = 3.3V
COUT = 100µF, L = 100µH
100mA IPEAK SETTING
ILOAD = 10mA
3335 G35
15
1.8
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
5.3
3335 G36
10
3335f
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LTC3335
Typical Performance Characteristics
PGND = 0V, VOUT = PVOUT = 3.3V, 100mA IPEAK setting, unless otherwise noted.
5
Total Unadjusted Coulomb
Counter Error During Continuous
Switching (250mA IPEAK Setting)
4
3
Total Unadjusted Coulomb
Counter Error During Continuous
Switching (150mA IPEAK Setting)
3
1
1
ERROR (%)
2
1
0
0
–1
0
–1
–2
–2
–2
–3
–3
–3
–4
–4
–4
–5
1.8
–5
1.8
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
5.3
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
1.8
2
ERROR (%)
1
0
–1
–2
–3
–4
–5
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
5.3
3.3 3.8
BAT (V)
4.8
Total Unadjusted Coulomb
Counter Error During Continuous
Switching (15mA IPEAK Setting)
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
3
1
–5
–7
–9
–13
–15
–17
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
–19
1.8
5.3
2.3
2.8
3.3 3.8
BAT (V)
3335 G41
4.3
4.8
5.3
5.3
–11
4.3
4.8
5.3
3335 G42
Total Unadjusted Coulomb
Counter Error During Continuous
Switching(5mA IPEAK Setting)
ERROR (%)
2.8
4.3
–3
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
2.3
3.3 3.8
BAT (V)
–1
Total Unadjusted Coulomb
Counter Error During Continuous
Switching (10mA IPEAK Setting)
5
3
1
–1
–3
–5
–7
–9
–11
–13
–15
–17
–19
–21
–23
–25
1.8
5
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
3335 G40
ERROR (%)
–6
1.8
2.8
3335 G39
Total Unadjusted Coulomb
Counter Error During Continuous
Switching (25mA IPEAK Setting)
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
3
2.3
3335 G38
Total Unadjusted Coulomb
Counter Error During Continuous
Switching (50mA IPEAK Setting)
4
–5
1.8
5.3
ERROR (%)
5
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
3
2
–1
Total Unadjusted Coulomb
Counter Error During Continuous
Switching (100mA IPEAK Setting)
4
2
3335 G37
ERROR (%)
5
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
4
ERROR (%)
ERROR (%)
5
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
TA = 25°C, BAT = PBAT = 3.6V, GNDA = GNDD =
5
2
–1
–4
–7
–10
–13
–16
–19
–22
–25
–28
–31
–34
–37
–40
1.8
3335 G43
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
2.3
2.8
3.3 3.8
BAT (V)
4.3
4.8
5.3
3335 G44
3335f
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11
LTC3335
Pin Functions
SDA (Pin 1 ): Serial Data Input/Output for the I2C Serial
Port. The I2C input levels are scaled with respect to DVCC
for I2C compliance. Do not float.
I2C
Serial Bus. DVCC
DVCC (Pin 2): Supply Rail for the
sets the reference level of the SDA and SCL pins for I2C
compliance. The external I2C pull-up resistors on SDA and
SCL should connect to DVCC. Depending on the particular
application, DVCC can be connected to BAT, to VOUT, or
to a separate external supply between 1.8V and 5.5V. In
most applications DVCC will be connected to the I/O rail
of the microprocessor reading the I2C registers.
OUT[2:0] (Pin 3, 4, 5): VOUT Voltage Select Bits. Tie high
to BAT or low to GNDA to select the desired VOUT (see
Table 2). Do not float.
GNDD (Pin 6): Signal ground for internal digital circuits.
Connect to GNDA and PGND.
VOUT (Pin 12): Buck-Boost Output Voltage Sense Pin.
Connect to PVOUT.
IPK[2:0] (Pin 15, 14, 13): Peak Input Current Select Bits.
Tie high to BAT or low to GNDA to select desired IPEAK
(see Table 1). Do not float.
EN (Pin 16): Buck-Boost Enable Input. Tie high to BAT or
low to GNDA to enable/disable the buck-boost. If EN is
pulled low, the buck-boost is disabled but internal register
contents are saved. Do not float.
GNDA (Pin 17): Signal ground for internal analog circuits.
Connect to GNDD and PGND.
PGOOD (Pin 18): Power Good Output. Logic level output
referenced to DVCC. This output is pulled low after the
buck-boost is enabled and remains low until VOUT reaches
regulation.
PBAT (Pin 8): Buck-Boost Input Voltage. This pin is the
power input of the regulator. Connect to BAT.
IRQ (Pin 19): Interrupt Output. Logic level output referenced
to DVCC. Active low. This pin is normally logic high but
will transition low when the preset alarm level is reached
or if there is an overflow in either the coulomb counter or
the AC(ON) time measurement.
SW1 (Pin 9): Buck-Boost Switch Pin. Connected to internal
power switches A and B. Connect an inductor (value in
Table 8) between this node and SW2.
SCL (Pin 20): Serial Clock Input for the I2C Serial Port.
The I2C input levels are scaled with respect to DVCC for
I2C compliance. Do not float.
SW2 (Pin 10): Buck-Boost Switch Pin. Connected to internal
power switches C and D. Connect an inductor (value in
Table 8) between this node and SW1.
PGND (Exposed Pad Pin 21): Power Ground. The Exposed
Pad connects to the sources of the internal N-channel
power MOSFETs. It should be soldered to the PCB and
electrically connected to system ground through the shortest and lowest impedance connection possible. Connect
to GNDA and GNDD.
BAT (Pin 7): Buck-Boost Input Voltage Sense Pin. Connect to PBAT.
PVOUT (Pin 11): Buck-Boost Output Voltage. This pin is
the power output of the regulator. Connect to VOUT.
12
3335f
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LTC3335
Block Diagram
9
10
SW1
SW2
PVOUT
PBAT
8
11
BAT
A
D
B
C
VOUT
12
7
BANDGAP
REFERENCE
GNDA
VREF
PGND
VREF_PG
GNDA
IZERO
BUCK-BOOST
CONTROL
IPEAK
IPK[2]
OUT[2]
15
14
3
IPEAK_SET
3
–
IPK[1]
SLEEP
IPK[0]
VREF
3
4
OUT[0]
+
13
OUT[1]
5
GNDA
+
EN
16
PGOOD
18
VREF_PG
AC(ON)
IPEAK
–
DVCC
2
SCL
20
IRQ
COULOMB
COUNTER
I2C
19
SDA
1
GNDD
GNDA
17
GNDD
6
PGND (EXPOSED PAD)
21
3335 BD
3335f
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13
LTC3335
Operation
Buck-Boost Regulator
The buck-boost regulator consists of four internal switches,
labeled A, B, C, and D, as shown in Figure 2, and control
circuitry which together connect the input and output
voltages to the power inductor.
SW1
PBAT
100µH
SW2
D
A
PVOUT
VOUT
BAT
B
C
3335 F02
Figure 2. Power FETs
The buck-boost operates as an H-Bridge for all BAT and
VOUT conditions when not in sleep. This means that switches
A and C are always on together, followed by switches B
and D always on together. A hysteretic voltage algorithm
is used to control the output through internal feedback
from the VOUT sense pin.
The buck-boost regulator charges the output capacitor
through the inductor. Current is delivered first by ramping
the inductor current up to IPEAK through switches A and
C, and then ramping it down to 0mA through switches B
and D. The IPEAK level is programmable via the IPK[2:0]
pins and ranges from 5mA to 250mA (see Table 1).
Table 1. IPEAK Selection
IPK2
IPK1
IPK0
IPEAK
0
0
0
5mA
0
0
1
10mA
0
1
0
15mA
0
1
1
25mA
1
0
0
50mA
1
0
1
100mA
1
1
0
150mA
1
1
1
250mA
14
This cycle repeats until the output voltage rises to a value
slightly higher than the regulation point (sleep threshold)
after which the converter enters a low quiescent current
sleep state that monitors the output voltage with a sleep
comparator. During sleep, load current is provided by the
output capacitor.
When the output voltage falls to a value slightly lower than
the regulation point (wake-up threshold) the buck-boost
regulator wakes up and then the inductor current starts
ramping up again within 3µs (typical).
This hysteretic method of providing a regulated output
voltage reduces losses associated with FET switching
while regulating at light loads.
VOUT can be set via the voltage select pins OUT[2:0] from
1.8V to 5V (see Table 2).
Table 2. Output Voltage Selection via Pins
OUT2
OUT1
OUT0
VOUT
0
0
0
1.8V
0
0
1
2.5V
0
1
0
2.8V
0
1
1
3.0V
1
0
0
3.3V
1
0
1
3.6V
1
1
0
4.5V
1
1
1
5.0V
When the sleep comparator senses that the output voltage
has reached the sleep threshold, the buck-boost converter
may be in the middle of a cycle with current still flowing
through the inductor. The converter enters the low quiescent current sleep state only at the end of a full AC-BD
cycle after the inductor current reaches 0mA. This behavior
is necessary for counting coulombs accurately.
During start-up and until VOUT rises to approximately
1.2V, switch D is held off and its body diode conducts.
This ensures proper IPEAK/IZERO operation for coulomb
counter accuracy.
3335f
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LTC3335
Operation
VOUT Power Good
A power good comparator is provided for the VOUT output.
The PGOOD pin transitions high when the LTC3335 first
goes to sleep, indicating that VOUT has reached regulation.
It transitions low when VOUT falls to 92% (typical) of its
average value at regulation.
Coulomb Counter
The LTC3335 integrates a precision coulomb counter to
monitor the accumulated charge that is transferred from
the battery whenever the buck-boost converter is delivering
current to VOUT. The buck-boost converter operates as an
H-Bridge for all BAT/VOUT conditions when not in sleep
(see Figure 3). Switches A and C turn ON at the beginning
of each burst cycle. Inductor current ramps to IPEAK and
then switches A and C turn OFF. Switches B and D then
turn ON until the inductor current ramps to zero (IZERO).
This cycle repeats until VOUT reaches the sleep threshold.
IPEAK
qAC(ON)
AC
IL
BD
SLEEP
0
AC
BURST
tAC
BD
3335 F03
Figure 3
If IPEAK and the switch AC(ON) time (tAC) are both known,
then the BAT discharge coulombs (shaded area in Figure
3) can be calculated by counting the number of AC(ON)
cycles and multiplying by the charge per AC(ON) cycle
given in Formula (1) below:
q AC(ON) =
IPEAK • t AC
2
There are a total of 50 bits in the coulomb counter chain,
but only the 8 MSBs may be read back over I2C. These
bits are contained in register C, the accumulated charge
register. The amount of charge represented by the least
significant bit (qLSB) of the accumulated charge register
(Register C) is given in the Electrical Characteristics section
for all 8 IPEAK settings for the case of the default prescaler
setting (M = 0, which uses the full length of the internal
counter). See Choosing Coulomb Counter Prescaler M
section for instructions on calculating qLSB with a nonzero
prescaler setting.
I2C Interface
The 7-bit hard-wired I2C address of the LTC3335 is
1100100[R/W]. The LTC3335 is a slave-only device meaning that the serial clock line (SCL) is only an input while
the serial data line (SDA) is bidirectional.
SLEEP
tAC
TIME
value and the ideal IPEAK value due to supply, temperature,
and process variations. This results in a very accurate
“measurement” of the charge transferred from the battery
during each AC(ON) cycle which is represented as an 8-bit
number and then added to the previous accumulated total
coulomb count each time switches A and C turn on. The
adder carry bit is the clock for the remaining 42-bit ripple
counter. When the buck-boost is in sleep, the coulomb
counter holds its state and draws no current.
(1)
When the buck-boost is operating, the LTC3335 measures
the actual AC(ON) time relative to a full scale ON time
(tFS, approximately 11.74µs) which is internally adjusted
to compensate for differences between the actual IPEAK
Internal Registers
The LTC3335 has 5 internal subaddressed I2C registers,
as shown in Table 3. Registers A, B, and E are write only,
Register C is read/write, and Register D is read only, as
shown in Tables 4, 5, and 6, respectively.
Table 3. Register Map
SUB
ADDRESS
REGISTER REGISTER
NAME
DESCRIPTION
R/W
DEFAULT
01h
A
VOUT selection and
prescaler selection
W
00h
02h
B
Alarm threshold
W
FFh
03h
C
Accumulated charge
R/W
00h
04h
D
Alarms
R
00h
05h
E
Interrupt register
W
00h
R = read, W = write
3335f
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15
LTC3335
Operation
Choosing Coulomb Counter Prescaler M
Table 4. Write Registers A, B, and E
BIT
NAME
A[3:0]
Prescaler Bits
A[7:4]
VOUT Selection Selection of output voltage
B[7:0]
OPERATION
Alarm Level
DEFAULT
Set coulomb counter
prescaling factor M from
0 to 15
11111111
To preserve digital resolution for a wide range of battery
capacities and peak current values, the LTC3335 includes
a programmable prescaler. The user can set the prescaler
value from 0 to 15 by writing bits A[3:0]. The default value
for the prescaler is 0.
To use the majority of the range of Accumulated Charge
Register C, the prescaler factor (M) should be chosen for
a given battery capacity QBAT based on Formula (2):
0000
0000
Coulomb count alarm level
threshold calculated by the
user based on battery capacity
and IPEAK current
E[0]
Clear_Int
Clear interrupt (Alarm reset)
0
E[1]
Counter Test
Counter check using IRQ pin
0
E[7:2]
Not Used
Table 5. Read/Write Register C
BIT
NAME
C[7:0]
Accumulated
Charge
OPERATION
DEFAULT
Read back 8 MSBs of counter
data
00000000
Table 6. Read Register D
BIT
NAME
OPERATION
DEFAULT
D[0]
AC(ON) Time
Overflow
AC(ON) time operating fault
(tAC > tFS) due to improperly
chosen inductor value timing
out the AC(ON) measurement
0
D[1]
Coulomb
Counter
Overflow
Coulomb counter operating
fault due to an improperly
chosen prescaler causing the
ripple counter to overflow
0
D[2]
Alarm Trip
Accumulator Register C value
has met or exceeded the Alarm
threshold set in Register B
0
D[7:3]
Not Used
00000
⎛ q • 255 ⎞
M = log2 ⎜ LSB
⎝ QBAT ⎟⎠
(2)
where QBAT is the battery size in A • hr and qLSB is the
typical value (for M=0) from the Electrical Characteristics
table for the selected IPEAK. M must be an integer, so the
result of Formula (2) must be rounded down to the next
integer value. M has a maximum value of 15.
A smaller capacity battery will require a higher prescaler
factor M than a larger capacity battery for the same IPEAK.
Likewise, a lower IPEAK will require a higher prescaler factor M than a higher IPEAK for the same capacity battery.
The amount of charge represented by the least significant
bit (qLSB_M) of the accumulated charge register is given by:
qLSB_M =
qLSB
(3)
2M
where qLSB is the typical value in Electrical Characteristics
table for the selected IPEAK.
Output Voltage Setting Via I2C
Counter Check Test
Selection of the output voltage can be done not only via
pins OUT[2:0], but also via I2C (see Table 7). The user
can change the VOUT settings dynamically by writing to
register A. Note that bit A[7] must be set to 1 for bits
A[6:4] to take effect.
Setting the bit E[1] = 1 allows the user to verify that the
coulomb counter is operating correctly without having to
wait for the accumulated charge register to increment from
00000000. In this mode the input clock of the ripple counter
is output to the IRQ pin, and the frequency of switching
seen at the IRQ pin will increase with output load.
Table 7. VOUT Selection Bits
BIT
SET
DESCRIPTION
A[4]
0/1
Overwrite OUT0 Pin
A[5]
0/1
Overwrite OUT1 Pin
A[6]
0/1
Overwrite OUT2 Pin
A[7]
1
16
Must be 1 to set output voltage via I2C
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LTC3335
Operation
Alarm
Power Up Sequence
An alarm causes the IRQ pin to be pulled low. The user
can read register D to determine what caused the alarm.
The alarm can then be cleared by writing 1 to bit E[0].
The clear interrupt bit is self-clearing after taking action
on the IRQ pin.
When the battery is first inserted and the internal circuits
are powering up, the LTC3335 resets all registers to their
default states, including the adder and the ripple counter.
The buck-boost requires a finite start up time until VOUT
charges up to the target value. When VOUT reaches the
PGOOD threshold, the PGOOD pin goes high. During the
entire start-up sequence, the coulomb counter counts
correctly.
When clearing an alarm, if another alarm trips, the IRQ
pin will go high for 1µs (typical) before returning low
again. During this time, the clear interrupt bit E[0] is also
reset to zero.
There are 3 different fault/alarm conditions:
1)An AC(ON) time overflow (D[0] is high) due to an improperly chosen inductor value timing out the AC(ON)
time measurement. After the alarm is cleared the IRQ pin
goes high and stays high at least until the next AC(ON)
pulse is measured. A different inductor or IPEAK setting
needs to be chosen to keep the alarm from continuously
tripping.
2)A coulomb counter overflow (D[1] is high) due to an
improperly chosen prescaler value causing the ripple
counter to overflow. After the alarm is cleared the IRQ
pin is released for 1µs and later pulled low again unless register C is overwritten with a lower value and the
prescaler is changed.
3)The preset alarm level is reached (D[2] is high) when
the 8 MSBs of the ripple counter are equal to or higher
than the 8 bits in register B. The user should increase
the alarm threshold in register B and then write bit E[0]
to 1 to clear the alarm.
The alarm threshold is only checked after each AC(ON)
pulse or when a write to register C is done via I2C.
Therefore, if bit E[0] is set to 1 to clear an alarm interrupt without also changing the contents of register B
and/or C, and this occurs during a long sleep time, the
IRQ pin is cleared and doesn't go back low again until
the next AC(ON) pulse.
If the EN pin is pulled low, the buck-boost is disabled.
However, the digital register contents of the coulomb
counter remain saved in memory. When re-enabled, the
coulomb counter continues counting from where it left off.
The digital registers are reset only if the BAT voltage is lost.
DVCC I2C Power Supply
The DVCC pin can be connected to BAT, to VOUT, or to
a separate external supply between 1.8V and 5.5V. A
power-on-reset circuit monitors the DVCC supply. For
DVCC voltages below 1.3V (typical), the I2C interface is
disabled. The user can't read or write, but the coulomb
counter is still fully functional.
If the BAT voltage is lost, the coulomb counter and the
buck-boost are switched off and the contents of all digital
registers are lost. The full functionality of the coulomb
counter is guaranteed for BAT voltages equal to or greater
than 1.8V.
If DVCC is connected to VOUT or to a separate external
supply, the coulomb counter is still fully functional, even
if VOUT = 0V such as during startup.
For the external pull-up resistors on the SDA and SCL
pins, 10kΩ is recommended.
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17
LTC3335
Applications Information
Input/Output Capacitor Selection
The input capacitor for the buck-boost on the BAT pin
should be bypassed with at least 4.7μF to GND. In cases
where the series resistance of the battery is high, a larger
capacitor may be desired to handle transients.
A larger capacitor may also be necessary when operating
close to 1.8V at higher IPEAK settings to prevent the battery voltage from falling below 1.8V when the buck-boost
is switching.
The duration for which the buck-boost regulator sleeps
depends on the load current and the size of the VOUT
capacitor. The sleep time decreases as the load current
increases and/or as the output capacitor decreases. The
DC sleep hysteresis window is ±6mV for the 1.8V output
setting and scales linearly with the output voltage setting
(±12mV for the 3.6V setting, etc.). Ideally this means that
the sleep time is determined by the following equation:
tSLEEP = COUT •
VDC _ HYS
ILOAD
Inductor Selection
The AC(ON) and BD(ON) times are determined to first
order by BAT, VOUT, the inductor value, and the IPEAK
current setting.
If transient load currents higher than the maximum deliverable are required, then a larger capacitor should be
used at the output. This capacitor will be continuously
discharged during a load condition and the capacitor can
be sized for an acceptable drop in VOUT:
(5)
Here VOUT+ is the value of VOUT when PGOOD goes high
and VOUT– is the desired lower limit of VOUT. IDC/DC is
the average current being delivered from the buck-boost
converter, and tLOAD is the duration of the transient load.
18
A standard surface mount ceramic capacitor can be
used for COUT. Some applications, however, may benefit
from a low leakage aluminum electrolytic capacitor or a
supercapacitor. These capacitors can be obtained from
manufacturers such as Vishay, Illinois Capacitor, AVX,
or CAP-XX.
(4)
This is true for output capacitance on the order of 100μF
or larger, but as the output capacitance decreases towards
10μF, delays in the internal sleep comparator along with the
load current itself may result in the VOUT voltage slewing
past the DC thresholds. This will lengthen the sleep time
and increase VOUT ripple. An output capacitance less than
22μF is not recommended as VOUT ripple could increase
to an undesirable level.
I
–I
COUT = tLOAD • LOAD+ DC/DC–
VOUT – VOUT
The LTC3335 always operates as an H-bridge, even at
start-up. The start-up duration is dependent on the load
current and the output capacitor; a larger output capacitor
makes the start-up time longer.
AC (ON) =
IPEAK •L
BAT
(6)
BD(ON) =
IPEAK •L
VOUT
(7)
The buck-boost is designed to work with a 100μH inductor
for typical applications using the 100mA peak current setting.
For the other seven IPEAK settings the inductor value should
scale so as to keep the IPEAK • L product approximately
constant. This maintains on-times required for accurate
coulomb counter operation. The nominal recommended
inductor value (LREC) for each IPEAK setting is given in
Table 8.
Table 8. Recommended Inductor Value LREC vs IPEAK
IPEAK SETTING (mA)
LREC (µH)
5
2200
10
1000
15
680
25
470
50
220
100
100
150
68
250
47
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LTC3335
Applications Information
Higher value inductors provide the benefit of lower switching losses by increasing both AC(ON) and BD(ON). However, care must be taken so that AC(ON) never exceeds
the max full-scale time tFS (11.74µs).
Recommended inductor values from Table 8 assure that
for BAT from 1.8V to 5.5V, VOUT from 1.8V to 5V, and
±20% inductor variation, the AC(ON) time is always below
11.74µs.
If in the application the minimum BAT voltage is higher
than 1.8V, the inductor value can be increased using the
formula below:
BATMIN •LREC
LMAX =
1.8
(8)
where LMAX is the maximum inductor value (including
production tolerance), LREC is the inductor value from
Table 8 and BATMIN is the minimum BAT voltage used
in the application. Inductors typically have production
tolerances of ±20%.
The DCR of the inductor can have an impact on efficiency
as it is a source of loss. In addition it is a source of error for
the coulomb counter because it increases the nonlinearity
of the inductor current during the AC(ON) time.
Choose an inductor with an ISAT rating at least 50% greater
than the selected IPEAK value. Table 9 lists several inductors
that work well. Trade-offs between price, size, and DCR
should be evaluated.
Load Current Capability
The maximum load current the buck-boost can support
depends on the IPEAK setting, the BAT voltage, and the
VOUT voltage and is ideally given by:
ILOAD(MAX) =
IPEAK
BAT
•
2 BAT + VOUT
(9)
However, due to finite RDS(ON) of power FETs A, B, C, and
D, as well as inductor DCR, the maximum deliverable
current is actually lower. Refer to the curves given in the
Typical Performance Characteristics section for actual load
current capability under various conditions.
Coulomb Counter Errors
The battery discharge coulombs is calculated by counting the number of AC(ON) cycles and multiplying by the
number of coulombs per AC(ON) time given by the following formula:
q AC(ON ) =
IPEAK • t AC
2
(10)
This formula assumes that the LTC3335 input quiescent
current, gate charge current, RDS(ON) of the power switches,
and the inductor DCR have negligible effect. It also assumes that every pulse starts from an inductor current
equal to 0 and ends at IPEAK. The contribution of each of
these errors will be discussed in the following sections.
Input Quiescent Current Error
The control circuit of the buck-boost consumes DC quiescent current when not in sleep. This current is dependent
on BAT voltage and temperature as shown in the Typical
Performance Characteristics section. This current, (typically 360µA) generates a small error at the 250mA peak
current setting, but can be significant for lower peak current settings as shown in Figures 4 and 5.
When the buck-boost is sleeping, the DC quiescent current
is typically 680nA. This equates to an error of 5.96mA • hr
per year of cumulative sleep time. For a battery capacity of
18.3A • hr, the error is only 0.033% per year.
As shown in Figure 6, for load currents smaller than
approximately 100µA, the sleep current can result in a
significant error.
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19
LTC3335
Applications Information
Table 9. Recommended Inductors for the LTC3335
MANUFACTURER
PART FAMILY
L
(µH)
ISAT(MAX)
(A)
DCR MAX
(Ω)
WIDTH
(mm)
LENGTH
(mm)
HEIGHT
(mm)
LPS5030
47
0.55
0.33
5.51
5.51
2.9
For 250mA IPEAK Setting
Coilcraft
Vishay
IDCS-2512
47
0.5
0.23
6.6
4.45
2.92
Sumida
CDRH4D29
47
0.36
0.239
5.1
5.1
3
Wurth
WE-TPC SMD 4828
47
0.5
0.28
4.8
4.8
2.8
LPS5030
68
0.44
0.44
5.51
5.51
2.9
For 150mA IPEAK Setting
Coilcraft
Vishay
IDCS-2512
68
0.4
0.29
6.6
4.45
2.92
Sumida
CDRH4D29
68
0.3
0.355
5.1
5.1
3
Wurth
WE-TPC SMD 4828
68
0.4
0.4
4.8
4.8
2.8
Coilcraft
LPS5030
100
0.32
0.6
5.51
5.51
2.9
Vishay
IDCS-2512
100
0.3
0.48
6.6
4.45
2.92
Sumida
CDRH4D29
100
0.24
0.523
5.1
5.1
3
Wurth
WE-TPC SMD 4828
100
0.29
0.6
4.8
4.8
2.8
Coilcraft
LPS5030
220
0.245
1.35
5.51
5.51
2.9
Vishay
IDCS-2512
220
0.22
0.77
6.6
4.45
2.92
Sumida
CDRH60D45
220
0.39
1.02
6.4
6.1
4.8
Wurth
WE-TPC SMD 4828
220
0.2
1.25
4.8
4.8
2.8
Coilcraft
LPS5030
470
0.146
2.8
5.51
5.51
2.9
Vishay
IDCS-2512
470
0.19
1.8
6.6
4.45
2.92
Sumida
CDMPIH58D28
470
0.14
3
6
6
3.2
Wurth
WE-TPC SMD 4828
470
0.125
2.6
4.8
4.8
2.8
Coilcraft
LPS5030
680
0.126
3.8
5.51
5.51
2.9
Vishay
IDCS-2512
680
0.18
2.2
6.6
4.45
2.92
Sumida
CDMPIH58D28
680
0.12
4.4
6
6
3.2
Wurth
WE-PD SMD 7332
680
0.22
5.73
7.3
7.3
3.2
Coilcraft
LPS5030
1000
0.11
5.1
5.51
5.51
2.9
Vishay
IDCS-2512
1000
0.15
3.4
6.6
4.45
2.92
Sumida
CDMPIH58D28
1000
0.09
6.6
6
6
3.2
Wurth
WE-TPC SMD 4828
1000
0.08
7
4.8
4.8
2.8
Coilcraft
LPS5030
2200
0.08
11
5.51
5.51
2.9
Vishay
IDCS-2512
2200
0.1
8.5
6.6
4.45
2.92
Sumida
CDMPIH58D28
2200
0.065
16.5
6
6
3.2
Wurth
WE-PD2 SMD 1054
2200
0.26
5.3
10
9
5.4
For 100mA IPEAK Setting
For 50mA IPEAK Setting
For 25mA IPEAK Setting
For 15mA IPEAK Setting
For 10mA IPEAK Setting
For 5mA IPEAK Setting
20
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LTC3335
Applications Information
0.0
TA = 25°C
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
–0.2
ERROR (%)
–0.4
–0.6
–0.8
–1.0
2.3
2.8
3.3 3.8 4.3
BAT VOLTAGE (V)
4.8
5.3
3335 F04
Figure 4. Typical Error Due to Input Quiescent
Current for 250mA IPEAK Setting
TA = 25°C
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
ERROR (%)
–5
The battery discharge coulombs are calculated assuming
that the inductor current rises to the IPEAK setting value
linearly. However, finite RDS(ON) of switches A and C cause
the actual inductor current to bow slightly which creates
an undercount in the coulomb counter (see Figure 10).
This error increases at lower BAT voltages and at higher
temperature.
–10
Inductor DCR Error
–15
An inductor with high DCR generates the same type of
error as the power switches RDS(ON) error due to a similar
nonlinear bowing of the inductor current waveform. Using
the recommended inductors from Table 9 assures that the
coulomb counter error due to the DCR is small.
–20
–25
–30
–35
–40
1.8
2.3
2.8
3.3 3.8 4.3
BAT VOLTAGE (V)
4.8
5.3
3335 G05
Figure 5. Typical Error Due to Input Quiescent
Current for 5mA IPEAK Setting
2
1
TA = 25°C
0
–1
–2
ERROR (%)
The gate charge current needed to turn on and off switches
A, B, and C is also a source of error for the coulomb
counter. This error increases at higher BAT voltages and is
generally higher at low IPEAK settings as shown in Figures
7, 8, and 9. Gate charge current for switch D is provided
from the output and does not create an error.
Power Switches RDS(ON) Error
–1.2
1.8
0
Gate Charge Current Error
–3
–4
Each of the individual coulomb counter error terms
discussed above results in an undercount of the battery
discharge coulombs (negative percent error). There are,
however, other error terms which can contribute to an overcount of the battery discharge coulombs (positive percent
error). For example, IZERO can be slightly negative under
some conditions, and this results in a slight overcount. This
particular error is more likely to occur at low BAT voltages,
high IPEAK settings, and/or high VOUT voltages.
Total Coulomb Counter Error
–5
–6
–7
BAT = 1.8V
BAT = 3.6V
BAT = 4.2V
BAT = 5.5V
–8
–9
–10
0.01
Other Errors
1.00
0.10
LOAD CURRENT (mA)
10.00
3335 F06
Figure 6. Typical Error Due to Sleep Current
(250mA IPEAK Setting, VOUT = 3.3V)
The total unadjusted coulomb counter error curves in
the Typical Performance Characteristics section show
actual data taken from an actual circuit and include the
effects of all of the above mentioned error sources with
the exception of the sleep current error, as these curves
were taken with continuous switching. The errors present
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21
LTC3335
Applications Information
0
–1
ERROR (%)
–2
IL
qAC(ON)
REAL
INDUCTOR
CURRENT
ERROR
–3
AC
BD
–4
250mA
100mA
25mA
10mA
–5
–6
1.8
2.3
2.8
150mA
50mA
15mA
5mA
3.3 3.8
BAT (V)
4.3
tAC
TIME
4.8
Figure 7. Typical Error Due to Gate Charge Current
VOUT = 1.8V, Ambient Temperature
0
–1
ERROR (%)
–2
–3
250mA
100mA
25mA
10mA
–6
1.8
2.3
2.8
150mA
50mA
15mA
5mA
3.3 3.8
BAT (V)
4.3
4.8
5.3
3335 F08
Figure 8. Typical Error Due to Gate Charge Current
VOUT = 3.3V, Ambient Temperature
0
–1
ERROR (%)
–2
–3
–4
–5
250mA
100mA
25mA
10mA
–6
–7
1.8
2.3
2.8
150mA
50mA
15mA
5mA
3.3 3.8
BAT (V)
4.3
4.8
5.3
3335 F09
Figure 9. Typical Error Due to Gate Charge Current
VOUT = 5V, Ambient Temperature
22
during continuous switching are well-characterized for a
given set of operating conditions and can to first order be
compensated for by applying a multiplicative scale factor
to the raw coulomb count reported by the LTC3335. The
error due to the sleep current can then be compensated
for by adding an offset term equal to the sleep current
multiplied by the cumulative sleep time (or if not known,
the battery service time). The error adjustment is given
by the following formula:
Adjusted Coulomb Count = (Raw Coulomb Count)
• [1/(1+Error)] + (5.96mA • hr) • Years/qLSB_M
–4
–5
Figure 10.
5.3
3335 F07
3335 F10
where Error is the error in % from Figures G37-G44 in the
Typical Performance Characteristics, qLSB_M is the least
significant bit of the accumulated charge register for the
chosen Prescaler M in A • hr, and Years is the number of
years of cumulative battery service.
The following two examples further illustrate how to
compensate for the raw coulomb count error.
Example 1: A Tadiran TL4903 primary cell (3.6V nominal,
2.4A • hr) is powering a 3.3V output and the IPEAK setting
is 100mA. The appropriate prescaler is M=8. From curve
G39 in the Typical Performance Characteristics, the nominal
error for continuous switching under these conditions is
only +0.5%. The raw coulomb count C[7:0] read from the
LTC3335 can be adjusted by multiplying by 1/(1+ 0.005).
To this result, the error due to the sleep current (5.96mA •
hr for each year of use) can be added, but this additional
term corresponds to less than 0.25% of the battery's capacity per year of service. In this example, the difference
between the raw and adjusted coulomb count is minimal.
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LTC3335
Applications Information
Example 2: A Panasonic CR2032 primary cell (3.0V nominal, 225mA • hr) is powering a 5V output and the IPEAK
setting is 5mA. The appropriate prescaler is M=7. From
curve G44 in the Typical Performance Characteristics, the
nominal error for continuous switching under these conditions is –16%. In this case the raw coulomb count error
is significant if left unadjusted. Suppose after 6 months
of battery service, the accumulated charge register C[7:0]
reads 28h(hex) or 40(decimal). The adjusted coulomb
count is given by:
Adjusted Coulomb Count = 40 • (1/(1 – 0.16) + (5.96mA
• hr) • 0.5/(140.6mA • hr/27) = 51
The adjusted coulomb count will more accurately represent
the actual coulombs and the preset alarm level (if used)
can be appropriately adjusted to compensate for this:
Adjusted Alarm Set Count = [(Desired Alarm Level/100) •
QBAT) - (5.96mA • hr • Years)] • (1 + Error/100) • 1/qLSB_M
where Desired Alarm Level is the percentage of the battery
capacity at which to trip the alarm.
I2C Interface
The LTC3335 communicates with a bus master using the
standard I2C 2-wire serial interface. The Timing Diagram
(Figure 1) shows the relationship of the signals on the bus.
The two bus lines, SDA and SCL, must be HIGH when the
bus is not in use. External pull-up resistors are required
on these lines. The I2C control signals, SDA and SCL,
are scaled internally to the DVCC supply. DVCC should be
connected to the same power supply as the bus pull-up
resistors.
The I2C port has an undervoltage lockout on the DVCC pin.
When DVCC is below approximately 1.3V, the I2C serial
port is disabled.
Bus Speed
The I2C port is designed to operate at speeds of up to
400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I2C compliant master
device. It also contains input filters designed to suppress
glitches.
START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave write
address or the slave read address. Once data is written
to the LTC3335, the master may transmit a STOP condition which commands the LTC3335 to act upon its new
command set. A STOP condition is sent by the master by
transitioning SDA from LOW to HIGH while SCL is HIGH.
Byte Format
Each frame sent to or received from the LTC3335 must
be eight bits long, followed by an extra clock cycle for the
acknowledge bit. The data must be sent to the LTC3335
most significant bit (MSB) first.
Master and Slave Transmitters and Receivers
Devices connected to an I2C bus may be classified as
either master or slave. A typical bus is composed of one
or more master devices and a number of slave devices.
Some devices are capable of acting as either a master or
a slave, but they may not change roles while a transaction
is in progress.
The transmitter/receiver relationship is distinct from that
of master and slave. The transmitter is responsible for
control of the SDA line during the eight bit data portion
of each frame. The receiver is responsible for control of
SDA during the ninth and final acknowledge clock cycle
of each frame.
All transactions are initiated by the master with a START
or repeat START condition. The master controls the active
(falling) edge of each clock pulse on SCL, regardless of its
status as transmitter or receiver. The slave device never
brings SCL LOW.
The LTC3335 does not clock stretch and will never hold
SCL LOW under any circumstance.
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LTC3335
Applications Information
The master device begins each I2C transaction as the
transmitter and the slave device begins each transaction
as the receiver. For bus write operations, the master acts
as the transmitter and the slave acts as receiver for the
duration of the transaction. For bus read operations, the
master and slave exchange transmit/receive roles following
the address frame for the remainder of the transaction.
Acknowledge
The acknowledge signal (ACK) is used for handshaking
between the transmitter and receiver. When the LTC3335
is written to, it acknowledges its write address as well as
the subsequent data bytes as a slave receiver. When it is
read from, the LTC3335 acknowledges its read address
as a slave receiver. The LTC3335 then changes to a slave
transmitter and the master receiver may optionally acknowledge receipt of the following data byte from the LTC3335.
The acknowledge related clock pulse is always generated by
the bus master. The transmitter (master or slave) releases
the SDA line (HIGH) during the acknowledge clock cycle.
data from it. Considering the address an 8-bit word, then
the write address is 0xC8, and the read address is 0xC9.
The LTC3335 will acknowledge both its read and write
addresses.
Subaddressed Access
The LTC3335 has three write registers for control input,
one read register for alarm reporting and one read/write
register for the accumulated battery discharge. They
are accessed by the I2C port via a subaddressed pointer
system where each subaddress value points to one of the
five control or status registers within the LTC3335. See
Table 3 for subaddress information.
The subaddress pointer is always the first byte written
immediately following the LTC3335 write address during bus write operations. The subaddress pointer value
persists after the bus write operation and will determine
which data byte is returned by the LTC3335 during any
subsequent bus read operations.
The receiver (slave or master) pulls down the SDA line
during the acknowledge clock pulse so that it is a stable
LOW during the HIGH period of this clock pulse.
Bus Write Operation
When the LTC3335 is read from, it releases the SDA line
after the eighth data bit so that the master may acknowledge receipt of the data. The I2C specification calls for a
not acknowledge (NACK) by the master receiver following
the last data byte during a read transaction. Upon receipt
of the NACK, the slave transmitter is instructed to release
control of the bus. Because the LTC3335 only transmits
one byte of data under any circumstance, a master acknowledging or not acknowledging the data sent by the
LTC3335 has no consequence. The LTC3335 will release
the bus in either case.
If the address matches that of the LTC3335, the LTC3335
returns an acknowledge. The bus master should then deliver the subaddress. The subaddress value is transferred
to a special pointer register within the LTC3335 upon the
return of the subaddress acknowledge bit by the LTC3335.
If the master wishes to continue the write transaction, it
may then deliver the data byte. The data byte is transferred
to an internal pending data register at the location of the
subaddress pointer when the LTC3335 acknowledges the
data byte. The LTC3335 is then ready to receive a new
subaddress, optionally repeating the [SUBADDRESS]
[DATA] cycle indefinitely. After the write address, the odd
position bytes always represent a subaddress pointer assignment and the even position bytes always represent data
to be stored at the location referenced by the subaddress
pointer. The master may terminate communication with
the LTC3335 after any even or odd number of bytes with
Slave Address
The LTC3335 responds to a 7-bit address which has been
factory programmed to 1100100[R/W]. The LSB of the
address byte, known as the read/write bit, should be 0
when writing data to the LTC3335, and 1 when reading
24
The bus master initiates communication with the LTC3335
with a START condition and the LTC3335’s write address.
3335f
For more information www.linear.com/LTC3335
LTC3335
Applications Information
either a repeat START or a STOP condition. If a repeat
START condition is initiated by the master, the LTC3335,
or any other chip on the I2C bus, can then be addressed.
The LTC3335 will remember, but not act on, the last input
of valid data that it received at each subaddress location.
This cycle can also continue indefinitely. Once all chips
on the bus have been addressed and sent valid data, a
global STOP can be sent and the LTC3335 will immediately
update all of its command registers with the most recent
pending data that it had previously received.
Bus Read Operation
The LTC3335 contains 2 readable registers. One is read
only and contains alarm information (Register D). The
other contains accumulated battery discharge information
(Register C) which may be both written and read back by
the bus master.
Only one subaddressed data register is accessible during
each bus read operation. The data returned by the LTC3335
is from the data register pointed to by the contents of the
subaddress pointer register. The pointer register contents
are determined by the previous bus write operation.
In preparation for a bus read operation, it may be advantageous for a bus master to prematurely terminate a
write transaction with a STOP or repeat START condition
after transmitting only an odd number of bytes. The last
transmitted byte then represents a pointer to the register
of interest for the subsequent bus read operation.
The bus master reads status data from the LTC3335
with a START or repeat START condition followed by the
LTC3335 read address. If the read address matches that
of the LTC3335, the LTC3335 returns an acknowledge.
Following the acknowledgement of its read address, the
LTC3335 returns one bit of status information for each of
the next eight clock cycles from the register selected by
the subaddress pointer. Additional clock cycles from the
master after the single data byte has been read will leave
the SDA line high (0xFF transmitted). The LTC3335 will
never acknowledge any bytes during a bus read operation
with the exception of its read address.
To read the same register again, the transaction may be
repeated starting with a START followed by the LTC3335
read address. It is not necessary to rewrite the subaddress
pointer register if the subaddress has not changed. To read
a different register, a write transaction must be initiated
with a START or repeat START followed by the LTC3335
write address and subaddress pointer byte before the read
transaction may be repeated.
When the contents of the subaddress pointer register
point to write-only command register (A, B, E), the data
returned in a bus read operation is the pending command
data at that location if it had been modified since the last
STOP condition. After a STOP condition, all pending data
is copied to the command registers for immediate effect.
When the contents of the subaddress pointer register
point to the writable and readable command register C,
the data returned in a bus read operation is data at that
location, not the pending command data from previous
write operation. After a STOP condition, all pending data
is copied to the command registers for immediate effect
and a following read operation can read the effect.
When the contents of the subaddress pointer register
point to the read-only alarm register D, the data returned
is a snapshot of the state of the LTC3335 at a particular
instant in time. If no interrupt requests are pending, the
status data is sampled when the LTC3335 acknowledges
its read address, just before the LTC3335 begins data
transmission during a bus read operation. When an alarm/
fault occurs, the IRQ pin is driven low and data is latched
in the alarm register D at that moment. Any subsequent
read operation from register D will return this frozen data
to facilitate determination of the cause of the interrupt
request. After the bus master clears the LTC3335 interrupt
request (E[0] =1), the status latches are cleared. Bus read
operations will then again return either a snapshot of the
data at the read address acknowledge, or at the time of
the next interrupt assertion, whichever comes first.
3335f
For more information www.linear.com/LTC3335
25
LTC3335
typical application
Backup Power Supply
MAIN SUPPLY
12V
100µH
IPEAK = 100mA
3.6V
Li-Ion +
BATTERY
10µF
SW1
SW2
BAT
PBAT
VOUT
PVOUT
(3V)
3.3V SYSTEM SUPPLY
3V IN BACKUP
(3.3V)
47µF
DC/DC
10µF
LTC3335
IPK[2]
IPK[1]
DVCC
IPK[0]
SCL
SDA
10k
OUT[2]
10k
I2C
µP
OUT[1]
OUT[0]
EN
IRQ
PGOOD
12V
V
MAIN SUPPLY
SYSTEM SUPPLY
3.3V
GND
3V
3335 TA03
t
Dual 5V/1.8V Regulator Where LTC3335 Counts Coulombs for Both Output Rails
47µH
3.2V
LiFePO4
BATTERY
+
IPEAK = 250mA
10µF
SW1
SW2
BAT
PBAT
VOUT
PVOUT
LTC3335
5V
47µF
10µF
IPK[2]
IPK[1]
IPK[0]
VIN
LTC3388-1
CAP
SW
OUT[2]
OUT[1]
OUT[0]
EN
EN
D1
D0
STBY
1.8V
VOUT
VIN2
DVCC
SCL
SDA
100µH
47µF
PGOOD
GND
IRQ
PGOOD
10k
GND
3335 TA04
10k
I2C
µP
26
3335f
For more information www.linear.com/LTC3335
LTC3335
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.50 REF
2.65 ±0.05
1.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ±0.05
4.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
0.75 ±0.05
1.50 REF
19
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
20
0.40 ±0.10
1
PIN 1
TOP MARK
(NOTE 6)
4.00 ±0.10
2
2.65 ±0.10
2.50 REF
1.65 ±0.10
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3335f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC3335
27
LTC3335
Typical Application
Lithium-Thionyl Chloride Primary Battery Powered Application
2.2mH
IPEAK = 5mA
3.6V
Li-SOCI2
BATTERY
+
SW1
SW2
10µF
2.5V
SYSTEM
47µF SUPPLY
VOUT
BAT
PVOUT
PBAT
LTC3335
IPK[2]
IPK[1]
IPK[0]
OUT[2]
OUT[1]
OUT[0]
EN
10k
µP
(µP COULOMBS NOT COUNTED)
10k
IRQ
PGOOD
DVCC
SCL
I2C
SDA
GND
3335 TA02
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC2941
Battery Gas Gauge with I2C Interface
2.7V to 5.5V Operation; High Side RSENSE; ±50mV Sense Voltage Range; 1%
Charge Accuracy
LTC2941-1
1A I2C Battery Gas Gauge with Internal Sense
Resistor
2.7V to 5.5V Operation; Integrated 50mΩ High Side RSENSE; ±1A Sense Current
Range; 1% Charge Accuracy
LTC2942
Battery Gas Gauge with Temperature, Voltage
Measurement
14-Bit ∆∑–ADC; Pin Compatible with LTC2941
LTC2942-1
1A Battery Gas Gauge with Internal Sense Resistor
and Temperature/Voltage Measurement
14-Bit ∆∑–ADC; Pin Compatible with LTC2941-1
LTC2943
Multicell Battery Gas Gauge with Temperature,
Voltage, and Current Measurement
3.6V to 20V Operation, High Side RSENSE; ±50mV Sense Voltage Range; 14-Bit
∆∑–ADC; 1% Voltage, Current, and Charge Accuracy
LTC3129/
LTC3129-1
Micropower 200mA Synchronous Buck-Boost
DC/DC Converter
VIN: 2.42V to 15V, VOUT: 1.4V to 15V, IQ = 1.3µA, ISD = 10nA,
MSOP-16E, 3mm × 3mm QFN-16 Packages
LTC3330
Nanopower Buck-Boost DC/DC with Energy
Harvesting Battery Life Extender
VIN: 2.7V to 20V, BAT: 1.8V to 5.5V, 750nA IQ
5mm × 5mm QFN-32 Package
LTC3331
Nanopower Buck-Boost DC/DC with Energy
Harvesting Battery Charger
VIN: 2.7V to 20V, BAT Float: 3.45V/4V/4.1V/4.2V, 950nA IQ
5mm × 5mm QFN-32 Package
LTC3388-1/
LTC3388-3
20V, 50mA High Efficiency Nanopower
Step-Down Regulator
VIN: 2.7V to 20V, VOUT: Fixed 1.1V to 5.5V, IQ = 720nA, ISD = 400nA,
MSOP-10, 3mm × 3mm DFN-10 Packages
LTC3588-1/
LTC3588-2
Nanopower Energy Harvesting Power Supply with
Up to 100mA of Output Current
VIN: 2.7V to 20V, VOUT: Fixed 1.8V to 5V, IQ = 950nA, ISD = 450nA;
MSOP-10, 3mm × 3mm DFN-10 Packages
LTC4150
Coulomb Counter/Battery Gas Gauge
2.7V to 8.5V Operation; High Side RSENSE; ±50mV Sense Voltage Range
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3335
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC3335
3335f
LT 0815 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015