V21N2 - JULY

July 2011
I N
T H I S
I S S U E
RS485 and RS232
transceivers combined in a
single device 12
Volume 21 Number 2
LTPoE++ Extends PoE to 90W with
Reliable and Easy-to-Use Standard
Heath Stewart
fast-acting IC protects
sensitive circuits from
overvoltage and reverse
supply connections 23
microprocessor power
supply works with FET
drivers, DrMOS and power
blocks 26
±5V split-voltage power
supply for analog circuits
40
Power over Ethernet, or PoE, is an increasingly popular
way to deliver both power and data over existing Ethernet
cable, thus freeing applications from the constraint of
AC-power proximity. As the number PoE solutions has
grown so has the applications’ appetite for power.
A new proprietary standard, LTPoE++™, satisfies this hunger
by extending the PoE and PoE+ specifications to 90W of PD
delivered power. LTPoE++ also dramatically reduces engineering
complexity in power sourcing equipment (PSEs) and powered
devices (PDs) when compared to other power-expansion solutions.
Plug-and-play simplicity and safe, robust
power delivery are hallmarks of LTPoE++. The
capabilities of this standard expand the field of
Ethernet-powered applications by several orders
of magnitude, enabling entirely new classes
of PDs, such as power-hungry picocells, base
stations or heaters for pan-tilt-zoom cameras.
HISTORY OF PoE
Linear offers a comprehensive lineup of PoE and LTPoE++
products. The LTC®4270/71 chipset reduces PoE costs and
complexity
by replacing undesireable opto-couplers with a
Caption
simple off-the-shelf transformer. Like all LTPoE++ products, this
chipset also extends PoE delivered power to 90W.
w w w. li n ea r.com
PoE is a standard protocol for sending DC power over copper Ethernet data
wiring. The IEEE group that administers the 802.3 Ethernet data standards
added PoE capability in 2003. The original PoE spec, known as 802.3af,
allowed for 48V DC power at up to 13W. Although the initial specification
was widely popular, the 13W cap limited the number of possible applications. In 2009, the IEEE released a new standard, known as 802.3at or PoE+,
increasing the voltage and current requirements to supply 25.5W of power.
(continued on page 4)
In this issue...
COVER STORY
LTPoE++ Extends PoE to 90W with
Reliable and Easy-to-Use Standard
Heath Stewart
1
DESIGN FEATURES
Two Wide Input Range Monolithic Switching
Regulators Make it Easy to Fit Boost, Flyback,
SEPIC and Inverting Topologies into Tight Spaces
Bin Zhang
9
Multiprotocol Transceivers Combine RS485
and RS232 in a Single Device to Simplify and
Shrink Applications that Use Both Standards
Steven Tanghe
12
Step-Down DC/DC Controller in
2mm × 3mm DFN Includes FET Drivers,
DCR Sensing and Accepts Inputs to 38V
Mike Shriver
JIM WILLIAMS REMEMBERED
20
No Blocking Diode Needed to Protect Sensitive Circuits
from Overvoltage and Reverse Supply Connections
Victor Fleury
23
Power Supply Works with FET Drivers,
DrMOS and Power Blocks for Flexible
Placement Near Microprocessors
Theo Phillips
26
DESIGN IDEAS
The Harsh Reality of Wide-Ranging 4V–36V
Automotive Batteries Is No Problem for Triple
Output Regulator in 4mm × 5mm QFN
Michael Nootbaar
32
Ultralow Power 16-Bit High Speed Signal Chain
Solution for Portable Sampling Systems
Clarence Mayott
34
Two Monolithic DC/DC Converters Take 3.6V–15V
Inputs Down to 0.6V at High Frequency,
Shrinking Battery-Powered Applications in
Everything from Handhelds to Automobiles
Mylien Tran and Theo Phillips
36
Simple Circuit Monitors Health of –48V Telecom
Lead-Acid Battery Backup Systems
Jon Munson
In the lab.
38
Easy, ±5V Split-Voltage Power Supply for Analog
Circuits Draws Only 720nA at No Load
Jim Drew
40
product briefs
42
back page circuits
44
I have known Jim Williams for 30 years. I have known him as the
consummate engineer, scientist, writer, humorist, and family man. In
all areas that Jim ventured, he excelled. His combination of personal
integrity, drive and humble interaction with other people drew
many friends, both for his writing and personal interactions.
Jim’s intuitive understanding of electronics enabled him to design
complicated circuits in his head, which he tested with real parts to
prove the circuits. The ability to design circuits also requires analysis
of the results of the testing. His strong analytical ability ensured
test results were correct and circuits were well understood.
Jim took his developments and turned them into words for publication. He
helped engineers of all ages understand circuits intuitively like he did. There
are few sources for advanced circuit understanding and design—especially the
way it was taught by Jim. His circuits and his writings provided insight so that
other people could approach his understanding of design. In all the time I’ve
known Jim, I have never known him to refuse to help someone with a circuit.
While Jim’s vocation, avocation and hobby were electronics, he had a great
sense of humor and art. His electronic sculptures are unique, beautiful and
functional. He built these structures (with much cursing) and careful selection
of aesthetically pleasing functional parts. Beyond his art, he had a great
sense of humor, which was often foisted on his friends, myself included.
In his personal life, he was a dedicated father to his son Michael and husband
to his wife Siu. Both of these people were very much a part of his life.
A successful poet is the rarest of all vocations. Jim Williams
was unique: a poet who wrote in electronics.
—Bob Dobkin
2 | July 2011 : LT Journal of Analog Innovation
Linear in the news
Linear in the News
EDN HONORS LINEAR DESIGNERS
AS INNOVATORS OF THE YEAR
TIMERBLOX FAMILY SELECTED FOR
EE TIMES ACE AWARD
Robert Dobkin and Tom Hack of Linear
were selected as Innovators of the
Year in EDN’s 21st annual Innovation
Awards. The two were selected by
the readers of EDN magazine for their
work in developing the LT®4180 Virtual
Remote Sense™ Controller, which was
also chosen by EDN as winner of the
EDN Innovation Award in the Power
ICs category for its innovative design,
providing designers with new flexibility options in power design.
Linear’s TimerBlox® family of ICs was
named winner in EE Times’ Seventh
Annual Creativity in Electronics (ACE)
Awards for Most Popular Product of
the Year in the Analog-Mixed Signal
category due to its innovative design
of simple, accurate timing solutions.
Awards are presented in 15 categories
and are judged by the editors and a
blue-ribbon panel of industry experts.
The LT4180 is a Virtual Remote Sense
DC/DC controller that eliminates the
remote sense wires required to compensate for the voltage drop in cables, wires
and circuit board trace runs. Voltage
drops in wiring and cables that cause load
regulation errors are usually corrected
by an additional set of sensing wires. The
LT4180 continuously interrogates the line
impedance and corrects the regulator’s
output voltage. The device maintains a
corrected regulated voltage at the load
regardless of current or line impedance.
The 3V to 50V input voltage range address
a variety of applications, including
remote instrumentation, battery charging,
wall adapters, notebook power, surveillance equipment and halogen lighting.
Linear’s TimerBlox family is a complete line of robust, tiny, accurate, low power devices that solve
five common timing functions:
•voltage-controlled oscillator
•low frequency oscillator
•pulse width modulated oscillator
•monostable pulse generator (one-shot)
•delay
By combining devices, just about any
timing problem can be solved easier
and faster than would be possible using
discrete components. For more information see www.linear.com/timerblox.
•Industrial—including medical, security, factory automation, instrumentation and industrial control
•Communications infrastructure—
including cellular base stations to
support worldwide growth in wireless networks, as well as networking
•Automotive electronics—including battery stack monitors for
hybrid and electric vehicles, as
well as LED lighting systems
Mr. Maier also discussed how Linear’s
high performance analog products
fit into the evolving China market,
with the growth of design-intensive
electronics industries, including
industrial, communications infrastructure and automotive markets.
CONFERENCES & EVENTS
Techno-Frontier—Power Systems Japan 2011, Tokyo
Big Sight, Tokyo, Japan, July 20-22. Linear will
showcase the latest power product offerings, including µModule® DC/DC regulators, µModule isolators, energy harvesting
solutions and LTspice® design tools. Info
at www.jma.or.jp/tf/en11/index.html.
CHINA PRESS CONFERENCE
On May 27, Linear Technology CEO Lothar
Maier held a press conference in
Shenzhen, China with 17 assembled
editors from the major technical publications in China. In his presentation, Mr.
Maier gave an overview of Linear and
discussed the company’s strategy and
commitment to the China market. In
the presentation, he discussed the company’s focus on three major markets:
EDN China Automotive Electronics Conference—
Electric Vehicle Battery Management System
Design, Shanghai Jianguo Hotel, Shanghai, China,
July 28; Shenzhen Exhibition & Conference Center,
Shenzhen, China, August 30. Linear will present
an overview of its product offering for
high performance battery management
system design for electric vehicles. n
July 2011 : LT Journal of Analog Innovation | 3
Table 1. PSE and PD power delivery matrix shows extended power levels of LTPoE++
DEVICE
PSE
STANDARD
The IEEE PoE+ specification specifies
backward compatibility with 802.3af
PSEs and PDs. The PoE+ specification
LTPoE ++
PD
The IEEE standard also defines PoE terminology, as shown in Figure 1. A device
that provides power to the network
is known as a PSE, or power sourcing
equipment, while a device that draws
power from the network is known as
a PD, or powered device. PSEs come in
two types: endpoints (typically network
switches or routers), which send both data
and power, and midspans, which inject
power but pass data through. Midspans
are typically used to add PoE capability
to existing non-PoE networks. Typical
PD applications are IP phones, wireless
access points, security cameras, cellular
femtocells, picocells and base stations.
802.3AT
(LTPoE++, continued from page 1)
LTPoE ++
802.3AT
TYPE
TYPE 1
TYPE 2
38.7W
52.7W
70W
90W
TYPE 1
13W
13W
13W
13W
13W
13W
TYPE 2
13W
25.5W
25.5W
25.5W
25.5W
25.5W
38.7W
13W
25.5W
38.7W
38.7W
38.7W
38.7W
52.7W
13W
25.5W
—
52.7W
52.7W
52.7W
70W
13W
25.5W
—
—
70W
70W
90W
13W
25.5W
—
—
—
90W
defines Type 1 PSEs and PDs to include
PSEs and PDs delivering up 13W. Type
2 PSEs and PDs deliver up to 25.5W.
to this need, the LTPoE++ specification reliably allocates up to 90W of
delivered power to an LTPoE++ PD.
LTPoE ++ EVOLUTION
The LTPoE++ specification provides reliable
detection and classification extensions
to existing IEEE PoE protocols. LTPoE++
is backward compatible and interoperable with existing Type 1 and Type 2 PDs.
Unlike other proprietary power-extending
The IEEE PoE+ 25.5W specification had
not yet been finalized when it became
clear that there was a significant
and increasing need for more than
25.5W of delivered power. In response
Figure 1. Typical PoE system
PSE
PD
GND
RJ45
DGND
AGND
PSE
CONTROLLER
VEE
–55V
SENSE GATE OUT
RJ45
1
2
1
DATA PAIR
3
6
2
3
DATA PAIR
6
0.25Ω
4
5
4
SPARE PAIR
7
8
4 | July 2011 : LT Journal of Analog Innovation
5
7
SPARE PAIR
8
GND
RCLASS
PWRGD
PD
CONTROLLER
–VIN
–VOUT
+
DC/DC
V
CONVERTER OUT
–
design features
Figure 2. IEEE 802.3at signature
resistance ranges
RESISTANCE 0Ω
LTPoE++ PSEs and PDs seamlessly interoperate with IEEE 802.3at Type 1 and Type 2
devices. Type 1 PSEs generally encompass
802.3af functionality at and below 13W.
Type 2 PSEs extend traditional PoE to 25.5W.
The following points reference Table 1:
•Type 1 PSEs will power all Type 1, Type
2 and LTPoE++ PDs with up to 13W.
•Type 2 PSEs will power Type 1
PDs with up to 13W and provide
25.5W to Type 2 and LTPoE++ PDs.
23.75k
26.25k
19k
26.5k
33k
NON-IEEE
15k
19k
26.5k
33k
Table 2. PSE vs PD vs application power
STANDARD
802.3AT
LTPoE ++
TYPE
PSE POWER
V MAX
PSE POWER
V MIN
PD POWER
V MIN
APPLICATION
POWER*
Type 1
17.8W
15.4W
13W
11.7W
Type 2
36W
34W
25.5W
23W
Dual Type 2
72W
68W
51W
46W
38.7W
47W
43W
38.7W
34.8W
52.7W
66W
63W
52.7W
47.4W
70W
94W
89W
70W
63W
90W
133W
125W
90W
81W
*Assumes DC/DC converter efficiency of 90%
power allocation scheme violating the
IEEE-mandated detection resistance
specifications risks damaging and
destroying non-PoE Ethernet devices.
The following rules define any detection methodology for the highest levels of safety and interoperability.
•LTPoE++ PSEs interoperate with Type
1 and Type 2 PDs. LTPoE++ PDs are
powered to the designed limit of
the LTPoE++ PSE. When an LTPoE++
PD is identified, the PD will be powered up if the PSE power rating meets
or exceeds the requested PD power.
For example, a 52.7W LTPoE++ PSE can
power both 38.7W and 52.7W PDs.
•Priority 1: Don’t turn on things you
shouldn’t turn on.
LTPoE++ physical detection and classification is a simple, backward-compatible extension of existing schemes.
Other power extension protocols violate the IEEE specification, as shown
in Figure 2, and risk powering up
known noncompliant NICs. Any high
150Ω (NIC)
30k
15k
•LTPoE++ PDs can power up with limited functionality even when attached
to traditional Type 1 and 2 PSEs.
IEEE-COMPLIANT PD DETECTION
20k
PSE
PD
solutions, Linear’s LTPoE++ provides
mutual identification between the
PSE and PD. LTPoE++ PSEs can differentiate between an LTPoE++ PD and all other
types of IEEE compliant PDs, allowing
LTPoE++ PSEs to remain compliant and
interoperable with existing equipment.
10k
•Priority 2: Do turn on things you
should.
Linear Technology PSEs provide extremely
robust detection schemes utilizing fourpoint detection. False positive detections
are minimized by checking for signature resistance with both forced-current
and forced voltage measurements.
LTPoE ++ ADVANTAGES
Standard PoE PSEs use two of the four
available Ethernet cable pairs for power.
Some power-extending topologies use
two PSEs and two PDs over one cable
to deliver 2 × 25.5W power. This “dual
Type 2” topology is shown in Figure 3.
The main problem with this strategy is
that it doubles the number of components, thus doubling PSE and PD costs.
Additionally, robust design considerations
require two DC/DC converters at the PD,
one for each component PD, where each
DC/DC converter is a relatively complex
flyback or forward isolated supply.
One of the DC/DC converters in a dual
Type 2 set-up can be eliminated by
ORing the PD’s output power as shown
in Figure 4. This approach still requires
two PSEs and two PDs, with the associated cost and space disadvantages. The
voltage drop incurred by the power
ORing diodes might be considered a fair
trade-off for the savings gained by using
a single DC/DC converter. In most cases
diode ORed power sharing architectures
remain attractive until surge protection
testing begins. Due to intrinsic reductions in surge protection tolerance, these
solutions rarely meet PD design goals.
July 2011 : LT Journal of Analog Innovation | 5
The increased power capability of LTPoE++ expands
the field of ethernet-powered applications by several
orders of magnitude, enabling entirely new classes of
PDs, such as power-hungry picocells, base stations
or even heaters for pan-tilt-zoom cameras.
PSE
PD
GND
RJ45
DGND
AGND
PSE
CONTROLLER
SENSE GATE OUT
VEE
–55V
RJ45
1
2
1
DATA PAIR
3
6
2
3
DATA PAIR
6
GND
RCLASS
PWRGD
PD
CONTROLLER
–VIN
–VOUT
+
DC/DC
V
CONVERTER OUT
–
0.25Ω
GND
DGND
AGND
PSE
CONTROLLER
VEE
–55V
SENSE GATE OUT
4
5
4
SPARE PAIR
7
8
5
7
SPARE PAIR
8
GND
RCLASS
PWRGD
PD
CONTROLLER
–VIN
–VOUT
+
DC/DC
V
CONVERTER OUT
–
0.25Ω
Figure 3. The expensive way to extend PoE+ power. Dual Type 2 PD provides more power than standard PoE+ PD, but it also doubles the cost and component count.
In contrast, LTPoE++ solutions, as
shown in Figure 5, require only a single
PSE, PD and DC/DC converter, resulting in significant board space, cost
and development time advantages.
LLDP INTEROPERABILITY AND
OPTIONS
During selection and architecture of a
PoE system, many PD designers are surprised to discover the hidden costs of
Link Layer Discovery Protocol (LLDP)
implementations. LLDP is the IEEEmandated PD software-level power
negotiation. LLDP requires extensions to standard Ethernet stacks and
can represent a significant software
6 | July 2011 : LT Journal of Analog Innovation
development effort. Unfortunately the
open-source community effort to provide LLDP support is still in its infancy.
While Type 2 PSEs may optionally implement LLDP, fully IEEE-compliant Type 2
PDs must implement both physical classification and LLDP power negotiation
capabilities. First, this places the burden of
LLDP software development on all Type 2
PDs. In addition, designs are complicated
by the dual power requirements inferred
by the LLDP requirement. Specifically, the
PD-side processor must be fully functional at the 13W power level and then
have the ability to negotiate, via LLDP, for
the delivery of additional power. Clearly
this requirement can increase development and system costs and complexity.
LTPoE++ offers LLDP implementation
options. LTPoE++ PSEs and PDs autonomously negotiate power level requirements
and capabilities at the hardware level
while remaining fully compatible with
LLDP-based solutions. In short, LTPoE++
gives system designers the choice to implement or not implement LLDP. Proprietary
end-to-end systems may choose to forgo
LLDP support. This creates time-to-market advantages while further reducing
BOM costs, board size and complexity.
design features
Linear Technology is committed to LTPoE++ technology and
provides an entire family of PSE and PD solutions. A full family
of PSEs, spanning 1- to 12-port solutions is now available.
PSE
PD
GND
RJ45
DGND
AGND
PSE
CONTROLLER
SENSE GATE OUT
VEE
–55V
RJ45
1
2
1
DATA PAIR
3
6
2
3
DATA PAIR
6
DC/DC
CONVERTER
GND
RCLASS
PWRGD
PD
CONTROLLER
–VIN
–VOUT
EN
+
VOUT
–
0.25Ω
GND
DGND
AGND
PSE
CONTROLLER
VEE
–55V
SENSE GATE OUT
4
5
4
SPARE PAIR
7
8
5
7
SPARE PAIR
8
GND
RCLASS
PWRGD
PD
CONTROLLER
–VIN
–VOUT
0.25Ω
Figure 4. Less expensive, but flawed, alternative for extending PoE+ power. This scheme is similar to the dual Type 2 set-up shown in Figure 3, but a diode ORed power
sharing architecture reduces some of the cost by eliminating one DC/DC converter in the PD. However, due to intrinsic reductions in surge protection tolerance, these
solutions rarely meet PD design goals.
POWER CLAIMS DEMYSTIFIED
PoE power paths can be divided into three
main components: the power produced
by the PSE, the power delivered to the
PD and the power delivered to the application. Claims of PSE and PD power
delivery capabilities must be carefully
examined before useful comparisons can
be made. One vendor may describe the
power as delivered by the PSE, another
the power delivered to the PD, while
the PD designer typically cares about
power consumed by the application.
Although the PSE power metric is the
least useful of the three, it is the one
most often cited in marketing materials.
PSE power is generally defined as the
power delivered at the PSE end of the
Ethernet cable. Power capability is
sometimes further distorted when vendors specify power at the maximum
rated voltage, which is rarely achieved.
PD power or “delivered power” is
the power delivered to the PD end of
the Ethernet cable, prior to the diode
bridge. Quoted PD power is a more
useful metric than PSE power, since it
must account for significant losses over
100 meters of CAT-5e cable. PD power
claims make no assumptions about
the application’s DC/DC converter and
diode bridge efficiencies, which are
unknown to PSE and PD silicon vendors.
A PD designer is most interested in the
power delivered to the application
when all system effects are considered,
including the resistance of the Ethernet
magnetics, diode bridge voltage drops
and DC/DC converter efficiency. This
metric, while the most telling, is the
most difficult to accurately specify.
Table 2 shows actual performance
comparisons at all stages of the power
path. Note that the dual Type 2 configuration delivers far less power than
the LTPoE++ 70W and 90W solutions.
July 2011 : LT Journal of Analog Innovation | 7
LTPoE++ offers a robust, end-to-end high power PoE
solution with up-front cost savings. Combined with Linear
Technology’s excellent application support, proven delivery
record and reputation for reliability, LTPoE++ is the most
comprehensive high power solution on the market.
PSE
PD
GND
RJ45
DGND
AGND
LTPoE++
PSE
CONTROLLER
VEE
–55V
SENSE GATE OUT
RJ45
1
2
1
DATA PAIR
2
3
3
6
6
DATA PAIR
PWRGD
LTPoE++
PD
CONTROLLER
0.25Ω
–VIN
4
5
DC/DC
V
CONVERTER OUT
–
–VOUT
4
SPARE PAIR
7
8
+
GND
RCLASS
5
7
SPARE PAIR
8
Figure 5. The LTPoE++ architecture is the only PoE power-extending solution that provides 90W at the PD while keeping complexity and costs in check.
PSE AVAILABILITY
CONCLUSION
Linear Technology is committed to LTPoE++
LTPoE++ offers a robust, end-to-end
high power PoE solution with up-front
cost savings. Combined with Linear
Technology’s excellent application support, proven delivery record and reputation for reliability, LTPoE++ is the most
comprehensive high power solution on
the market. LTPoE++ systems simplify
power delivery and allow system designers to concentrate their design efforts
on their high value applications. n
technology and provides an entire family of PSE and PD solutions. A full family
of PSEs, spanning 1- to 12-port solutions
is now available, shown in Table 3.
Table 3. LTPoE++ PSEs
8 | July 2011 : LT Journal of Analog Innovation
PSE PART
# PORTS
DELIVERED PD
POWER (MAX)
LTC4274A-1
1
38.7W
LTC4274A-2
1
52.7W
LTC4274A-3
1
70W
LTC4274A-4
1
90W
LTC4266A-1
4
38.7W
LTC4266A-2
4
52.7W
LTC4266A-3
4
70W
LTC4266A-4
4
90W
LTC4270A
12
38.7W–90W
(pin selected)
design features
Two Wide Input Range Monolithic Switching Regulators
Make it Easy to Fit Boost, Flyback, SEPIC and Inverting
Topologies into Tight Spaces
Bin Zhang
The LT3957 and LT3958 are high power monolithic switching
regulators that can generate a positive or a negative output
from a wide range of input voltages. The LT3957 operates
over an input range of 3V to 40V, making it suitable for
everything from portable electronics to automotive and
industrial applications. The LT3958 extends the input
voltage to 80V for high voltage telecommunications
supplies. Both produce high power from a small footprint
as shown by the boost converter layout in Figure 1.
FEATURES
Figure 2. A high efficiency
and very compact 3V–6V
input, 12V output boost
converter
VIN
3V TO 6V
By integrating the power MOSFET and
LDO onto the die, the LT3957 and LT3958
simplify converter design, shrink the
solution size and reduce cost when
compared to non-monolithic solutions. The LT3957 has an integrated
40V/30mΩ N-MOSFET switch with an
internally programmed current limit of
5.9A (typical). The LT3958 has an integrated 84V/90mΩ N-MOSFET switch with
an internally programmed current limit
of 4A (typical). Each IC has an internal
high voltage LDO, which allows LT3957
L1
4.7µH
CIN
100µF
6.3V
X5R
VIN
49.9k
39.2k
GND
LT3957
SENSE1
SYNC
SENSE2
105k
FBX
RT
CIN: MURATA GRM32ER60J107ME20L
COUT: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX MBRA120
L1: VISHAY IHLM-2525CZ-01
41.2k
300kHz
INTVCC
VC
SS
0.33µF
10k
10nF
10Ω
CVCC
4.7µF
10V
X5R
The LT3957 and LT3958 use a constant
frequency, peak current mode control
scheme, providing fast transient response
and an easy to stabilize feedback loop at
variable inputs and outputs. The switching frequency can be programmed over
a 100kHz to 1MHz range with a single
VOUT
12V
COUT 800mA
22µF
16V
X5R
×2
SW
SGND
to be powered from a supply as high
as 40V, and for LT3958 as high as 80V.
Figure 3. Efficiency of the converter in Figure 2
D1
EN/UVLO
Figure 1. A 10V–40V input, 48V output boost
converter board
100
95
EFFICIENCY (%)
These versatile switching regulators can
be configured as boost, flyback, SEPIC or
inverting converters. The LT3957 and
LT3958 feature a rugged low side N-channel
power MOSFET rated for 5A/40V and
3.5A/80V respectively. A novel FBX pin
architecture provides accurate regulated positive or negative output with
a simple resistor divider. These ICs also
include soft-start, frequency foldback,
input undervoltage lockout, adjustable
frequency and synchronous switching.
VIN = 5V
90
VIN = 3.3V
85
80
15.8k
VIN
75
70
0
200
400
ILOAD (mA)
600
800
July 2011 : LT Journal of Analog Innovation | 9
The LT3957 and LT3958 feature a rugged low side N-channel
power MOSFET rated for 5A/40V and 3.5A/80V respectively.
A novel FBX pin architecture provides accurate regulated
positive or negative output with a simple resistor divider.
0.1µF
50V
CIN
4.7µF
50V
X5R
•
2.4k
D1
•
COUT
100µF
6.3V
DSN
200k
VIN
SW GND
EN/UVLO
Figure 4. A simple and
compact 12V to 45V input, –5V
output flyback converter takes
advantage of the LT3958’s
rugged 84V-rated MOSFET and
the novel FBX pin architecture.
100pF
25.5k
SGND
SENSE1
SYNC
SENSE2
RT SS
82.5k
INTVCC
VC
0.47µF
10k
4.7µF
10V
X5R
15.8k
100pF
10nF
CIN: MURATA GRM32ER71H475KA88L
COUT: MURATA GRM32ER60J107ME20L
At the heart of each of the LT3957 and
LT3958 is a pair of feedback error amplifiers: one regulates a positive output and
the other, a negative output. When the
converter starts up, the output voltage
ramps positive or negative depending on
the topology selected. The appropriate
error amplifier seamlessly takes over the
feedback control, while the other becomes
inactive. In this way, these parts can automatically regulate to the desired output
voltage in different converter topologies.
The LT3957 and LT3958 contain several
features to limit the peak switch currents and output voltage overshoot
during start-up or recovery from a fault
10 | July 2011 : LT Journal of Analog Innovation
VIN = 12V
80
VIN = 45V
75
70
65
60
55
45
FBX
external resistor, which allows designers
to optimize component size and performance parameters, such as minimum/
maximum duty cycle and efficiency.
85
50
LT3958
63.4k
200kHz
90
VOUT
–5V
2A
EFFICIENCY (%)
T1
3:1
VIN
12V TO 45V
D1: VISHAY 30BQ040
DSN: VISHAY ES1C
T1: COILTRONICS VP2-0066
condition. The SS pin voltage modulates
the peak switch current, thereby allowing
the output capacitor to charge gradually
toward its final value while preventing
switch current from reaching current
limit. Selection of a capacitor on the SS pin
determines the start-up/restart time. The
frequency foldback function reduces the
switching frequency when FBX voltage
is close to 0V to ensure that the IC maintains control over the switch current. An
overvoltage protection function protects
both the positive and negative output
converters from excessive output voltage
overshoot. The internal power switch is
turned off immediately when the FBX pin
voltage exceeds the positive regulated
voltage by 8% (typical), or negative
regulated voltage by 11% (typical).
40
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
ILOAD (A)
2
Figure 5. Efficiency of the converter in Figure 4
A 3V–6V INPUT, 12V OUTPUT
BOOST CONVERTER
Figure 2 shows a 3V–6V input, 12V output
boost power supply using the LT3957. To
ensure the 3V minimum operation voltage,
the voltage drop across the internal LDO is
eliminated by connecting the INTVCC pin
directly to VIN pin through a 10Ω resistor (given that the maximum VIN operating voltage of 6V is below INTVCC ’s
maximum voltage rating of 8V). Figure 3
shows the efficiency of this converter.
A 12V–45V INPUT, –5V OUTPUT
FLYBACK CONVERTER
The LT3957 or LT3958 can be configured as
a flyback converter for applications where
the converters have multiple outputs,
isolated outputs or high input/output
voltage conversion ratios. The flyback
converter has a very low parts count
for multiple outputs, and with prudent
selection of transformer turns ratio it can
have high output/input voltage conversion ratios with a desirable duty cycle.
The frequency foldback feature of the
LT3957 and LT3958 provides robust
design features
D1
VOUT
24V
COUT 700mA
4.7µF
50V
×2
VIN
200k
SW
GND
EN/UVLO
LT3958
36.5k
100pF
SENSE1
SGND
SENSE2
SYNC
FBX
RT
SS
41.2k
300kHz
Figure 6. A simple and
compact 9V–36V input, 24V
output SEPIC converter with
short-circuit protection
•
L1B
0.47µF
280k
INTVCC
VC
10k
Figure 6 shows the LT3958 in a 9V to
36V input, 24V output SEPIC converter. This
topology allows for the input to be higher,
equal or lower than the desired output
voltage. In a SEPIC converter, no DC path
exists between the input and output, which
An inverting converter is similar to the
SEPIC converter in that it can step up or
step down the input, but with a negative
output. It also offers output disconnect
and short-circuit protection. Figure 8
shows a 4V–15V input, –5V output inverting
L1B
D1
SW
100
200
300 400
ILOAD (mA)
500
600
700
CONCLUSION
The LT3957 and LT3958 are versatile
monolithic switching regulators that can
be configured as boost, flyback, SEPIC or
inverting converters accepting a wide
range of input voltages. By integrating
the power MOSFET and LDO, they greatly
simplify converter design, shrink solution size and reduce costs. These ICs also
offer low shutdown current, soft-start,
frequency foldback, input UVLO, adjustable frequency and synchronization. The
combination of these features makes the
LT3957 and LT3958 suitable for a variety of
applications ranging from battery portable
electronics to automotive, industrial and
telecommunications power supplies. n
Figure 9. Efficiency of the converter in Figure 8
95
SGND
SENSE1
SYNC
SENSE2
82.5k
INTVCC
VC
SS
0.47µF
10k
10nF
VIN = 4V
90
FBX
RT
0
converter using LT3957 as the switching
regulator. Figure 9 shows the efficiency of
this converter at different input voltages.
LT3957
41.2k
300kHz
65
GND
EN/UVLO
37.4k
VOUT
–5V
COUT 1.6A
100µF
6.3V
•
•
VIN
70
Figure 7. Efficiency of the converter in Figure 6.
A 4V–15V INPUT, –5V OUTPUT
INVERTING CONVERTER
75k
75
50
A 9V–36V INPUT, 24V OUTPUT
SEPIC CONVERTER
Figure 8. A simple and
compact 4V–15V input,
–5V output inverting
converter with shortcircuit protection
80
55
is an advantage for applications requiring the output to be disconnected from
the input source when the circuit is shut
down. This design can sustain an indefinite output short-circuit condition due to
its topology and the frequency foldback
feature. Figure 7 shows the efficiency of
this converter at different input voltages.
CIN
10µF
25V
X5R
VIN = 36V
85
60
output short-circuit protection. Each IC’s
FBX feature allows the flyback converter to
easily produce either positive or negative
outputs. Figure 4 shows a LT3958 in a flyback converter that operates from a 12V to
45V input and delivers 2A to a –5V output. Figure 5 shows the efficiency of this
converter at different input voltages.
CDC
10µF, 25V
X5R
VIN = 24V
VIN = 9V
90
20k
CIN, COUT, CDC: MURATA GRM32ER71H475KA88L
D1: VISHAY 10BQ100
L1A, L1B: COILTRONICS DRQ127-330
L1A
95
CVCC
4.7µF
10V
X5R
10nF
VIN
4V TO 15V
100
CVCC
4.7µF
10V
X5R
15.8k
85
EFFICIENCY (%)
CIN
4.7µF
50V
X5R
EFFICIENCY (%)
L1A
•
VIN
9V TO 36V
CDC
4.7µF, 50V
X5R
VIN = 15V
80
75
70
65
60
CIN, CDC: MURATA GRM31ER61E106KA12
COUT: MURATA GRM32ER60J107ME20L
D1: VISHAY 20BQ030
L1A, L1B: COILTRONICS DRQ127-100
55
0
0.2
0.4
0.6 0.8 1
ILOAD (A)
1.2
1.4
1.6
July 2011 : LT Journal of Analog Innovation | 11
Multiprotocol Transceivers Combine RS485 and RS232 in a
Single Device to Simplify and Shrink Applications that Use
Both Standards
Steven Tanghe
The RS232 and RS4851 data transmission interface
standards are in widespread use today despite their
relatively advanced age—RS232 was introduced almost
50 years ago; RS485, 30 years ago. Such longevity for
any standard is uncommon in today’s rapidly changing
electronics landscape, where consumer demand
can force obsolescence in a handful of years.
Although the once ubiquitous RS232 port
on personal computers has largely been
replaced by USB, RS232 continues to proliferate in applications requiring rugged,
short distance, point-to-point communication, such as in sensors, test equipment,
device programming and diagnostics.
Likewise, RS485 thrives thanks to its high
performance in harsh environments. Its
differential signaling scheme and wide
common mode tolerance provide excellent
noise immunity, allowing high speed communication over relatively long distances.
Perhaps equally important in the RS485
standard is the ability to network several
devices on a single bus, thereby reducing
wiring overhead. RS485 is specified as the
physical layer for many Fieldbus networks including PROFIBUS and INTERBUS.
To simplify the design of RS485 and RS232
systems, the LTC2870 and LTC2871 multiprotocol transceivers combine both types
of transceivers on a single device. Both
support data rates as high as 20Mbps
for the single RS485 transceiver and
500kbps for two RS232 transceivers.
These devices are designed to support a
wide variety of applications with features
that make them flexible and robust:
12 | July 2011 : LT Journal of Analog Innovation
•They accept a wide range of input
supply voltages from 3V to 5.5V, as
well as a logic supply pin, allowing
a digital interface down to 1.7V with
no level translation needed.
•Integrated termination resistors are
automatically engaged for compatibility with RS232 or RS485 operation.
•Half- and full-duplex control and loopback functions provide system configurability and diagnostics capability.
•Robust performance allows continuous operation during ESD strikes
of up to 26kV on the bus pins.
•Both devices are offered in
small QFN and TSSOP packages, as shown in Figure 1.
The LTC2870 and LTC2871 differ in how
their transceiver I/Os are pinned out, as
well how they are controlled. The LTC2870
offers two RS232 transceivers that share
I/O pins with an RS485 transceiver. It can
operate in either RS232 mode or RS485
mode but not both at once. The LTC2871
provides additional flexibility by pinning the RS485 and RS232 transceivers
out separately so that all transceivers
Figure 1. The LTC2870 and LTC2871 are offered in
small QFN and TSSOP packages
can be operated concurrently as shown
in Table 1. Figure 2 shows a simplified block diagram for each device.
APPLICATIONS
The LTC2870 and LTC2871 can be
configured in a variety of ways.
Application of these devices falls
into three main categories:
•Fixed interface: The LTC2870 or the
LTC2871 can be permanently configured
as either an RS232 or RS485 interface.
For instance, Figure 3 shows both
modes of operation for the LTC2870. If
two versions of a product are offered,
one with each interface, a multiprotocol transceiver minimizes design
differences, reducing inventory, and
simplifying product qualification.
•In situ configuration changes with a
shared connector: Some applications
require the signaling interface to change
between RS232 and RS485 during normal
product usage. For example, a node in
an alarm system might be networked
with other nodes via an RS485 communication bus. However, the node can
be configured for local RS232 access,
design features
Table 1. Product selection guide
PART NUMBER
CONFIGURABLE TRANSCEIVER COMBINATIONS
(RS485 + RS232)
PACKAGES
LTC2870
(0 + 0), (1 + 0), (0 + 2)
28-Lead QFN, 28-Lead TSSOP
LTC2871
(0 + 0), (1 + 0), (1 + 1), (1 + 2), (0 + 1), (0 + 2)
38-Lead QFN, 38-Lead TSSOP
allowing programming or diagnostics. Signaling pins are shared between
the RS485 and the RS232 transceivers, with one transceiver active at any
given time, as shown in Figure 4.
The LTC2870 changes modes between
RS232 and RS485 via control of the
485/232 pin, which can be manipulated though processor control,
manual jumper settings, or protocolspecific cables that connect the pin
to VL or ground. The LTC2871 can be
used in a similar way but with independent access to all signal pins.
•Simultaneous operation. Some applications require concurrent RS485 and
RS232 communication. For example,
in point-of-sale applications, a cash
register may communicate with a server
Figure 2. Simplified block diagrams of the LTC2870 and the LTC2871
3V TO 5.5V
1.7V TO VCC
10µH
2.2µF
0.1µF
10µH
SW
CAP
VCC
VL
LTC2870
DX232
220nF
2.2µF
0.1µF
VCC
VL
3V TO 5.5V
1.7V TO VCC
220nF
SW
CAP
LT2871
DX485
VDD
VDD
RX232
CONTROL
INPUTS
H/F
MODE &
TERMINATION
CONTROL
1µF
VEE
BOOST
REGULATOR
RT485
RX485
CONTROL
INPUTS
H/F
H/F
1µF
LB
232
DIN1
1µF
VEE
BOOST
REGULATOR
RT485
H/F
1µF
CH2
FEN
DRIVERS
MODE &
TERMINATION
CONTROL
DRIVERS
232
DOUT1
Y
Y
RT485
RT485
DY
DI
485
485
120Ω
120Ω
Z
Z
DOUT2
DZ
232
DIN2
H/F
RECEIVERS
232
H/F
RECEIVERS
ROUT1
232
232
RIN1
A
RA
RT485
485
A
RO
RT485
485
120Ω
120Ω
B
RB
232
B
ROUT2
GND
RIN2
232
GND
July 2011 : LT Journal of Analog Innovation | 13
Figure 3. The LTC2870 configured for RS232 (a) or
RS485 (b) communications. The RS485 configuration
also shows the RS485 termination resistors optionally
switched in with the TE485 pin tied high.
a
VL
DXEN
LTC2870
485/232
RXEN
DY
DZ
DY
Y
RA
Y
5V/DIV
A
Z
via RS485 but also accept input from an
RS232-equipped keypad. The LTC2871,
with completely independent RS232 and
RS485 transceivers, enables separate terminals for each protocol with a single IC.
Another example of simultaneous usage
is translation between RS232 and RS485
protocols. Figure 5 shows the LTC2871
configured as an RS232 4000-foot “extension cord” implemented by converting
to RS485 for the long cable run and
converting back to RS232 at the ends.
Z
RB
B
RA
RB
1µs/DIV
b
VL
DXEN
LTC2870
RXEN
485/232
DY
5V/DIV
TE485
Y
Y
DY
120Ω
1V/DIV
Z
Z
A
RA
THE WHOLE IS BETTER THAN THE
SUM OF ITS PARTS
Using a multiprotocol device, such as the
LTC2870 with shared RS485 and RS232
interface pins, offers a number of advantages over simply combining standalone
RS485 and RS232 transceivers. First, by
combining the function of both transceivers in one device, the overall footprint
on a circuit board is reduced. Second,
all of the interface pins on the RS232
can tolerate inputs to ±15V. Most RS485
devices can only tolerate –7 to 12V, so
connecting such a device to RS232 pins
would lower the shared pin rating.
DZ
120Ω
RA
5V/DIV
B
20ns/DIV
Perhaps the biggest obstacle in combining
individual RS485 and RS232 transceivers
concerns the termination resistors used in
each signaling standard. This situation is
illustrated in Figure 6, where two different devices are connected to the same bus.
The input resistance of the RS232 receivers
is specified to be 5k (nominally), which
acts as a termination resistor for an RS232
driver connected to it. On the other hand,
the differential RS485 receiver can be
terminated with 120Ω resistors across its
inputs if it is located at the end of the signaling bus, to reduce signal reflections. The
challenge is in switching out the resistors
that are not needed in the selected transceiver mode. For example, in RS485 mode,
the 5k resistors should not be present and
likewise, in RS232 mode, the 120Ω differential termination must not be present.
The LTC2870 and LTC2871 seamlessly
switch between termination schemes
as needed, using internal components.
Table 2. Termination control in the LTC2870. The LTC2870 and LTC2871 seamlessly switch between termination schemes as needed, using internal components. The
RS485 120Ω termination resistor can be disabled in any mode by setting TE485 pin low, which is useful if the transceiver is not positioned at the end of the bus.
INPUTS
RESULTING TERMINATION
485/232
TE485
RXEN
120Ω: A TO B, Y TO Z
5k: A TO GND, B TO GND
MODE
1
0
X
No
No
RS485 Mode Without Termination
1
1
X
Yes
No
RS485 Mode With Termination
0
X
0
No
Yes
RS232 Mode, Receiver Enabled
0
X
1
No
No
RS232 Mode, Receiver Disabled
14 | July 2011 : LT Journal of Analog Innovation
design features
There is no need for external termination
components or relays to control them.
Furthermore, the RS485 120Ω termination resistor can be disabled in any mode
by setting TE485 pin low, which is useful if the transceiver is not positioned at
the end of the bus. Table 2 summarizes
the termination control in the LTC2870.
LTC2870
RS232 RS485
DY
RS485 communicates differentially over
a bus containing one or more pairs of
twisted wires. If the transition time of the
signal driven into the bus is significantly
less than the round trip delay to the
load and back, then the bus needs to be
terminated differentially with a resistor
whose characteristic impedance matches
that of the bus. This termination should
be placed at the receiver end of the bus or
both ends of the bus, but not in between.
The absence of termination or improper
termination introduces reflections that
can cause severe waveform distortion.2
When RS485 termination is enabled on
the LTC2870 or LTC2871, the 120Ω differential resistors are connected across
receiver inputs A and B and also across
RS232
RA
A
B
120Ω
RS232
MODE
RS485
MODE
RS232
MODE
Figure 4. LTC2870 protocol switching, using the 485/232 pin.
Oscilloscope traces show the driver outputs toggling data
during mode changes.
driver outputs Y and Z. The driver termination is not strictly necessary for the
case when this device is actively driving
the bus, such as the master in Figure 7.
However, the Y to Z termination is necessary in applications such as the slave at
the far end of the bus in Figure 7, where
another device is driving the bus.
The RS485 standard specifies cable with
a characteristic impedance of 120Ω while
RS422 specifies 100Ω cable. These cables
generally contain one or more twisted
pairs as well as ground shields or a ground
wire (sometimes called a drain wire). As
an alternative to shielded twisted pair,
unshielded 100Ω Category 5 (CAT5) cabling
is increasingly applied in RS485 and RS422
systems as an economic alternative.
Y
A
Z
B
120Ω
The LTC2870 and LTC2871 perform equally
well with 100Ω or 120Ω cable. Even
when the internal termination resistor,
nominally 120Ω, is used to terminate a
100Ω cable, the impedance mismatch has
negligible impact on the resulting signal.
For instance, the effect of using a 120Ω termination on each end of a 100Ω cable is
to develop an overshoot of about 10% at
the receiver end with a duration equal to
CONNECTOR
RS485
RS485
RT
120Ω
Y
Z
RS232
RO
DIN1
RIN1
DOUT1
RS485
UP TO 4000 FT
CAT5e CABLE
ROUT1
120Ω
A
Y
B
Z
120Ω
5k
RXOUT
A
RS232
RIN1
DIN1
RO
Z
LTC2871
ROUT1
DRIVER
OUT
DZ
RB
ROUT1
RXIN
Y
5V/DIV
2µs/DIV
LTC2871
DI
Y
Z
5V/DIV
The LTC2871 offers similar controls but
since the RS232 and RS485 pins are not
shared, all of the termination resistors
can be engaged simultaneously if desired.
Refer to the data sheet for details.
SOME SPECIFICS REGARDING THE
RS485 TERMINATION RESISTOR
485/232
5V/DIV
485/232
DRIVER
IN
DI
Figure 5. RS232 “Extension cord” using the LTC2871’s simultaneous RS232 and RS485 communication mode
RS232
RT
120Ω
5k
B
CONFLICT!
Figure 6. Termination resistors pose challenges
when separate RS232 and RS485 transceivers are
used in combination.
July 2011 : LT Journal of Analog Innovation | 15
The only required external components are one
10µH inductor for the boost voltage and one 220nF
cap for the voltage inversion, as well as the bypass
caps on the generated VDD and VEE rails.
SLAVE
LTC2870/
LTC2871
TE485
Figure 7. Full-duplex network with LTC2870/71 at each node
SLAVE
MASTER
LTC2870/LTC2871
120Ω
120Ω
120Ω
120Ω
TE485
Figure 8 shows the results of using the
LTC2871 internal 120Ω termination resistor to terminate 100 feet of CAT5e cable
compared to the same cable terminated
with 100Ω. Although the internal terminator is not a perfect match for the
100Ω cable, there is almost no effect on
the overall signal other than a slight
amplitude increase at the beginning of
the received signal, which can improve
system performance via increased signal
overdrive and noise margin. Normal
Y
485
500kHz
2V/DIV
Z
100'
CAT5e
CABLE
A
485
RT
120Ω
DRIVER
END
(Y – Z)
100Ω
100Ω
B
RECEIVER
END
(A – B)
200ns/DIV
RYZ = 100Ω ,RAB = ∞
RYZ = RAB = 120Ω (TERMINATION ENABLED)
RYZ = RAB = 100Ω (EXTERNAL TERMINATION)
Figure 8. Driving signal on Cat5e cable with the LTC2871 and comparing effects of the termination resistance.
Scope traces on the top show the differential signal at the driven end of the cable (Y – Z) and the bottom set
of traces show the differential signal received after traversing the cable (A – B).
16 | July 2011 : LT Journal of Analog Innovation
VL
TE485
LTC2870/LTC2871
RT
120Ω
TE485
LTC2870/LTC2871
VL
twice the one-way propagation delay in
the cable. This small deviation from ideal
is easily tolerated in most communications
systems, and can improve performance,
which is why the PROFIBUS standard
specifies a similar termination mismatch.
SLAVE
LTC2870/
LTC2871
cable variation, stub reflections and
discontinuities have a far greater impact
on signal integrity. The figure also shows
the devastating effect of leaving the cable
unterminated at the receiving end, where
reflections degrade the signal substantially.
INTERNAL RS232 SUPPLY ENOUGH
TO DRIVE TWO TRANSCEIVERS
RS232 signals are driven on a single wire
with respect to ground at levels that
must exceed 5V and –5V. A DC/DC boost
converter and capacitive inverter are
integrated into the LTC2870 and LTC2871
to produce both positive and negative
voltages used to support these drive levels
while operating on a single 3V–5.5V supply. The only required external components are one 10µ H inductor for the
boost voltage and one 220nF cap for the
voltage inversion, as well as the bypass
caps on the generated VDD and VEE rails.
Figure 9 shows the LTC2870 or LTC2871
configured in a typical application with
all of the required external components.
design features
Predictable fault handling is important for robust system
design. LTC2870 and LTC2871 receivers produce a
high output, called a failsafe condition, in response
to an idle bus, disconnected bus or shorted bus.
Two LTC2870 or LTC2871 devices can
be powered simultaneously from the
internal DC/DC converter of one device,
reducing the number of external components. Figure 10 shows two LTC2870s,
two LTC2871s or one of each sharing a single internal RS232 supply.
LOGIC SUPPLY PIN SUPPORTS 1.7V
TO 5.5V SUPPLIES
A separate logic supply pin VL allows
the LTC2870 and LTC2871 to interface
with any logic signals from 1.7V to 5.5V.
All logic I/Os use VL as their high supply. Optionally, VL can be tied to VCC .
Figure 11 shows the LTC2870 or LTC2871
used with a low voltage microprocessor.
RS485 BALANCED RECEIVER AND
FAILSAFE
Failsafe operation is a term used to
describe how a receiver reacts to various conditions, most of which are faults.
Predictable fault handling is important
for robust system design. LTC2870 and
LTC2871 receivers produce a high output,
called a failsafe condition, in response
to all of the following conditions:
3V TO 5.5V
1µF
220nF
10µH
VCC
VL
GND
CAP
SW
LTC2870/
LTC2871
VDD
VEE
1µF
1µF
INDUCTOR: TAIYO YUDEN CBC2518T220M
OR MURATA LQH32CN220K53
Figure 9. Typical supply connections with external
components shown
3V TO 5.5V
2.2µF
VCC
VL
GND
Figure 10. Running two LTC2870s or LTC2871s
from a single, shared DC/DC converter
470nF
22µH
CAP
SW
CAP
VCC
LTC2870/
LTC2871
VL
LTC2870/
LTC2871
VDD
VEE
2.2µF
VEE
VDD
SW
GND
2.2µF
INDUCTOR: TAIYO YUDEN CBC2518T220M OR MURATA LQH32CN220K53
•Idle Bus. All drivers on the bus are
disabled with high impedance outputs.
This condition is not actually a fault; it
is a normal mode of operation in RS485.
Some receivers cannot support this by
themselves but require a resistor network to bias the differential signals on
the bus in such a way that the receiver
senses it as a high input. The LTC2870
and LTC2871 support this function
without requiring a bus-biasing network,
whether the bus is terminated or not.
•Disconnected Bus. This category of
failsafe operation refers to the case
where the receiver becomes disconnected from the bus. This is similar
to the idle bus state but is truly a
fault condition. Receivers that rely
on bus biasing resistors to handle an
idle bus condition do not respond
properly to this type of fault.
•Shorted Bus. In this situation, the
receiver inputs are shorted together.
Some receivers provide failsafe operation for open, but not shorted, inputs.
Again, bus-biasing resistors are not
effective for shorted bus conditions.
Many modern RS485 receivers meet
failsafe requirements by introducing
a negative offset into the differential
threshold. In this way, whenever the bus
is shorted or undriven, but terminated,
the input to the receiver is zero, which is
interpreted as a high level. The receiver
in this case is unbalanced, since the
threshold is not symmetric around zero
volts—the average of a differential signal.
3V TO 5.5V
1.7V TO VCC
VCC
LTC2870/
LTC2871
VL
CONTROL
SIGNALS
µP
DY, DIN1
Y
RA, ROUT1
A
DZ, DIN2
Z
RB, ROUT2
B
GND
Figure 11. The VL pin permits low voltage logic
interface
July 2011 : LT Journal of Analog Innovation | 17
100Ω unshielded Category 5 (CAT5) cabling is used with RS485 and RS422
systems as an economic alternative to specialized shielded twisted pair cabling.
With this in mind, the LTC2870 and LTC2871 perform equally well with 100Ω
cable or 120Ω cable. Even when the internal 120Ω termination resistor is used
to terminate a 100Ω cable, the resulting signals are not degraded.
B
100mV/DIV
A
RO
RO
5V/DIV
RECEIVER
OUTPUT LOW
–200mV
–65mV
(A – B)
100mV/DIV
RECEIVER
OUTPUT HIGH
0V
65mV
200mV
VAB
200ns/DIV
b
a
Figure 12. (a) RS485 receiver input threshold characteristics for fast moving signals. (b) Measured 3Mbps
signal driven down 4000ft of CAT5e cable. Top Traces: receiver signals after transmission through cable;
Middle Trace: math showing the differences of the top two signals; Bottom Trace: receiver output, exhibiting
excellent duty cycle.
The unbalanced receiver can introduce
severe signal pulse-width and duty-cycle
distortion for weak signals that result
from transmission over long cables.
The LTC2870 and LTC2871 use a balanced receiver with a rising threshold of
65mV and a falling threshold of –65mV for
signals transitioning through that window
in less than 2µs, as shown in Figure 12. If
the differential signal lingers within this
window for more than 2µs, the positive
Figure 13. RS485 full- and half-duplex control in the
LTC2870
LTC2870/LTC2871
DI,
DY
RS485
FULL HALF
Y
Z
H/F
DUPLEX
RO,
RB
is low, the device is in full-duplex mode,
with the driver outputs on the Y and Z
pins and the receiver inputs on the A and B
pins. If the H/F pin is high, the RS485 transceiver enters half duplex mode where the
receiver takes its inputs from the Y and Z
pins. This works seamlessly with the termination control and has no effect on RS232
operation. Figure 13 shows the simplified
block diagram illustrating this flexibility.
A
B
18 | July 2011 : LT Journal of Analog Innovation
threshold drops down to –40mV to support
all modes of failsafe operation, as previously described. The balanced receiver
architecture permits transmission over
longer cables than an unbalanced receiver
and offers the additional benefit of excellent noise immunity due to the wide
effective differential input signal hysteresis
of 130mV for typical communications
Figure 12 highlights the performance of
the LTC2871 balanced receiver, where a
signal is driven through 4000 feet of CAT5e
cable at 3Mbps. Even though the differential signal peaks at just over ±100mV with
slow edges, the output maintains nearly
a perfect signal and the receiver introduces almost no duty cycle distortion.
DUPLEX AND LOOPBACK CONTROL
RS485 networks can be wired in a 2-wire,
half-duplex configuration or a 4-wire, fullduplex configuration. In some systems the
interface may need to support both. The
LTC2870 and LTC2871 offer on-the-fly flexibility via the H/F pin. When the H/F control
The LTC2870 and LTC2872 also feature a
logic loopback feature that can be used
for diagnostics and as a debug tool. The
loopback mode works for both the RS232
and RS485 transceivers, and provides a
logic path from the driver input pin to
the corresponding receiver output pin.
The driver and receiver are not engaged
in the loop; just logic buffers are used.
This allows diagnostic tests to be run
Figure 14. Logic loopback control in the LTC2871.
Loopback works whether or not the drivers are
enabled.
VL
DX232
DX485
LTC2871
RX232
RX485
LB
Y
DI
Z
A
RO
B
DIN1
ROUT1
DIN2
ROUT2
DOUT1
RIN1
DOUT2
RIN2
design features
The LTC2870 and LTC2871 multiprotocol transceivers
simplify the design of RS485 and RS232 systems by
combining both types of transceivers on a single device.
They support data rates as high as 20Mbps for the single
RS485 transceiver and 500kbps for two RS232 transceivers.
Figure 15. RS485 receiver
with multiplexed inputs.
LTC2870/LTC2871
H/F
SELECT
INPUT2 INPUT1
Y
RS485
INTERFACE
INPUT1
Z
RA,
RO
A
INPUT2
B
without disturbing the bus. Optionally,
the bus may be driven during loopback
by simply enabling the appropriate driver.
Figure 14 shows loopback operation.
MORE APPLICATIONS
The rich feature sets of the LTC2870
and LTC2871 make it possible to build
applications that would otherwise be
challenging to produce. For example,
Figure 15 shows an RS485 receiver
with multiplexed inputs making use
of the half- and full-duplex control.
Figure 16 shows how to combine two
LTC2871 devices to make a triple RS232
transceiver with either a selectable line
or logic interface. This application makes
use of the CH2 pin, which selectively
disables the second RS232 transceiver.
When disabled, the driver and receiver
outputs are not driven and the receiver
input becomes high-Z. This allows these
pins to be connected to the same pins on
another device whose CH2 pin is driven
with the complementary state of the first.
CONCLUSION
The LTC2870 and LTC2871 are flexible
3V to 5.5V multiprotocol transceivers
that communicate using RS485 and
RS232 signaling on either shared I/O pins
(LTC2870) or separate I/O pins (LTC2871).
Integrated selectable termination and
duplex control allow easy configuration
with minimal external components. n
Notes
1 Formally, TIA/EIA-485 and TIA/EIA-232
2 “Rugged 3.3V RS485/RS422 Transceivers with Integrated Switchable Termination,” by S. Tanghe, R. Schuler, LT
Magazine, March 2007.
a
b
LTC2871
LTC2871
Figure 16. RS232 triple transceiver with
selectable line interface (a), and logic
interface (b)
DIN1
PORT 1
LOGIC
INTERFACE
PORT 2A/2B
LOGIC
INTERFACE
DIN1
DOUT1
ROUT1
RIN1
DIN2
DOUT2
ROUT2
RIN2
PORT 1
LINE
INTERFACE
PORT 1
LOGIC
INTERFACE
PORT 2A
LINE
INTERFACE
PORT 2A
LOGIC
INTERFACE
SELECT LINE 2A
RIN1
DIN2
DOUT2
ROUT2
RIN2
PORT 1
LINE
INTERFACE
PORT 2A/2B
LINE
INTERFACE
SELECT LINE 2A
LTC2871
SELECT LINE 2B
CH2
DIN2
ROUT2
PORT 3
LOGIC
INTERFACE
ROUT1
CH2
CH2
SELECT LINE 2B
DOUT1
DIN1
ROUT1
DOUT2
RIN2
DOUT1
RIN1
PORT 2B
LINE
INTERFACE
PORT 2B
LOGIC
INTERFACE
PORT 3
LINE
INTERFACE
PORT 3
LOGIC
INTERFACE
LTC2871
CH2
DIN2
ROUT2
DIN1
ROUT1
DOUT2
RIN2
DOUT1
RIN1
PORT 3
LINE
INTERFACE
July 2011 : LT Journal of Analog Innovation | 19
Step-Down DC/DC Controller in 2mm × 3mm DFN Includes
FET Drivers, DCR Sensing and Accepts Inputs to 38V
Mike Shriver
Wide input voltage range and reliability are desirable features in any buck converter. The
LTC3854 delivers these features and more in a 2mm × 3mm DFN or MSE package.
This current mode controller with integrated N-channel FET gate drivers can produce
output voltages ranging from 0.8V to 5.5V over an input voltage range of 4.5V to 38V.
SENSING THE CURRENT
The LTC3854 employs a fixed frequency
peak current mode topology, which
provides a cycle-by-cycle current limit.
Current can be sensed with discrete
sense resistors in series with the inductor. Alternately, the DC resistance of
the inductor (DCR) can be used to sense
current instead of a sense resistor by
placing an RC filter across the inductor
to recreate the triangular current sense
waveform. The advantage of DCR sensing is improved efficiency (thanks to the
elimination of the power losses of the
sense resistor), lower parts count and
lower cost. The disadvantage is a less
accurate current limit due to DCR variations part-to-part and over temperature.
but with DCR sensing. The full load efficiency of the circuit with a sense resistor
is 86.9%, while the full load efficiency
increases to 88.7% (see Figure 3) with
DCR sensing. The 400kHz switching frequency provides a good balance between
high efficiency on one hand and a fast
load step response on the other. The load
step response shown in Figure 4 shows
that the output voltage remains within
±50mV for a 50%-to-100% load step.
Figure 1 shows a 1.5V, 15A converter that
uses a sense resistor to sense the output
current; Figure 2 shows the same circuit,
Figure 1. A 1.5V, 15A converter with a sense resistor
VIN
M1
LTC3854 TG
0.1µF
RUN/SS
ITH
2200pF
5.62k
0.1µF
VIN
4.5V TO 14V
180µF
16V
BOOST
L
0.56µH
SW
47pF
10µF
16V
×2
RSENSE
2mΩ
D1
4.7µF
FB
17.4k
SENSE–
BG
SENSE+
GND
1nF
D1 = CMDSH-3
M1 = RENESAS RJK0305DPB
M2 = RENESAS RJK0330DPB
L = TOKO FDA1055-R56M
COUT1 = SANYO 2R5TPE330M9
COUT2 = MURATA GRM31CR60J107ME39L
20 | July 2011 : LT Journal of Analog Innovation
+
INTVCC
20k
47Ω
47Ω
M2
COUT2
100µF
×2
VOUT
1.5V
15A
COUT1
330µF
×2
design features
The wide input voltage range of the LTC3854 allows it
to be used in a wide variety of applications, including
automotive, industrial and communications.
WIDE INPUT VOLTAGE RANGE
APPLICATIONS
The input voltage range of the LTC3854
allows it to be used in a wide variety of
applications, including automotive, industrial and communications. One example of
a wide input converter is the 5V, 10A converter in Figure 5, which can be used for
an input voltage range of 6V to 38V. The
strong gate drivers and low QG FETs allows
for 94% efficiency at a 32V input voltage
and 100% load as shown in Figure 6.
The small size and low pin count of the
LTC3854 allows the control section of the
2.5V/5A converter with a 4.5V to 26V input
voltage range shown in Figure 7 to fit
within a 180mm2 area. Dual channel FETs
are used to minimize the size of the power
stage. The 400kHz switching frequency
allows the use of a small 2.2µ H inductor with a 7mm × 7mm footprint. The
entire converter (minus the bulk input
capacitor) can fit in a 430mm2 area.
VIN
LTC3854 TG
0.1µF
Figure 2. Same converter shown in Figure 1, except
with DCR sensing. The filter at R1 and C1 infers the
current sense information from the inductor’s DCR.
RUN/SS
ITH
2200pF
5.62k
0.1µF
180µF
16V
BOOST
L
0.56µH
SW
47pF
VIN
4.5V TO 14V
10µF
16V
×2
M1
VOUT
1.5V
15A
D1
4.7µF
FB
17.4k
SENSE–
BG
SENSE+
GND
+
3.09k
INTVCC
20k
M2
0.1µF
COUT2
100µF
×2
0.1µF
D1 = CMDSH-3
M1 = RENESAS RJK0305DPB
M2 = RENESAS RJK0330DPB
L = TOKO FDA1055-R56M
COUT1 = SANYO 2R5TPE330M9
COUT2 = MURATA GRM31CR60J107ME39L
92
Figure 3. Efficiency of the converter with a
sense resistor versus efficiency with DCR
sensing. By eliminating the sense resistor,
the full load efficiency goes up by almost 2%.
DCR SENSE
EFFICIENCY (%)
90
RSENSE = 2mΩ
88
COUT1
330µF
×2
VOUT
50mV/DIV
(AC-COUPLED)
1.8%
86
84
82
80
VIN = 12V
0
2
4
6
8
ILOAD (A)
10
12
14
16
Figure 4. 50% to 100% load step
response of converter shown in
Figure 2.
ILOAD
10A/DIV
50µs/DIV
VOUT = 1.5V
ILOAD = 0A TO 15A
July 2011 : LT Journal of Analog Innovation | 21
VIN
RUN/SS
7.5k
0.1µF
BOOST
L
3.6µH
SW
100pF
RSENSE
3mΩ
D1
42.2k
SENSE–
BG
SENSE+
GND
98
COUT1
220µF
4.7µF
FB
100
VOUT
5V
10A
+
INTVCC
8.06k
47µF
50V
×2
96
EFFICIENCY (%)
ITH
2200pF
150µF
50V
M1
LTC3854 TG
0.1µF
VIN
6V TO 38V
M2
4.7nF
94
92
90
16Ω
D1 = ZETEX ZLLS1000
M1, M2 = INFINEON BSC093N04LS
L = COILTRONICS HC1-3R6-R
COUT1 = SANYO 6TPE220MI
16Ω
86
Figure 5. 5V, 10A converter with a 6V to 38V input voltage range
SOFT-START, LOW DROPOUT AND
HIGH STEP-DOWN RATIOS
The LTC3854 features a programmable
soft-start set with a capacitor on the
RUN/SS pin. As the output voltage ramps
up, the converter operates in discontinuous mode to prevent reverse current from
flowing into the inductor. This allows the
part to safely turn on into a prebiased
output. After ramp-up, the part operates
VIN = 6V
VIN = 12V
VIN = 24V
VIN = 32V
88
0
1
2
3
4 5 6
ILOAD (A)
7
9
10
Figure 6. Efficiency of the 5V, 10A converter
in continuous conduction mode. Other
features are a maximum duty cycle of
97% for low dropout voltage applications, a low minimum on-time of 75ns
for applications with high step-down
ratios, foldback current limit in addition
to the cycle-by-cycle current limit and
a built-in 5V linear regulator for bias.
CONCLUSION
The LTC3854 delivers reliability and
efficiency for cost-sensitive and space-constrained applications. The device can produce output voltages ranging from 0.8V to
5.5V over an input voltage range of 4.5V to
38V. The LTC3854’s 2mm × 3mm DFN and
MSE packages, along with a 400kHz switching frequency, minimize solution size. n
Figure 7. 2.5V, 5A converter with a 4.5V to 26V input voltage range
VIN
LTC3854 TG
0.1µF
RUN/SS
ITH
2200pF
15k
M1T
0.1µF
L
2.2µH
SENSE–
BG
SENSE+
10Ω
10Ω
M1B
COUT2
47µF
1nF
D1 = CMDSH-3
M1T, M1B = VISHAY Si4816BDY
L = TDK RLF7030T 2.2µH
COUT1 = SANYO 4TPE220MF
COUT2 = AVX 12106D476KAT2A
RSENSE
5mΩ
4.7µF
FB
43.2k
18µF
35V
+
INTVCC
20k
+
VIN
4.5V TO 26V
BOOST
SW
150pF
4.7µF
25V
D1
22 | July 2011 : LT Journal of Analog Innovation
8
GND
VOUT
2.5V
5A
COUT1
220µF
design features
No Blocking Diode Needed to Protect Sensitive Circuits from
Overvoltage and Reverse Supply Connections
Victor Fleury
What would happen if
someone connected 24V
to your 12V circuits? If the
power and ground lines were
inadvertently reversed, would
the circuits survive? Does
your application reside in a
harsh environment, where
the input supply can ring
very high or even below
ground? Even if these events
are unlikely, it only takes one
to destroy a circuit board.
What can you do to protect your sensitive circuits from voltages that are
too high, too low, or even negative?
To block negative supply voltages,
system designers traditionally place a
power diode in series with the supply.
However, this diode takes up valuable
board space and dissipates a significant
amount of power at high load currents.
Another common solution is to place a
high voltage P-channel MOSFET in series
with the supply. The P-channel MOSFET dissipates less power than the series diode,
but the MOSFET, and the circuitry
required to drive it, drives up costs.
UNDERVOLTAGE, OVERVOLTAGE AND
REVERSE-SUPPLY PROTECTION
The LTC4365 is a unique solution that elegantly and robustly protects sensitive circuits from unpredictably high or negative
supply voltages. The LTC4365 blocks positive voltages as high as 60V and negative
voltages as low as –40V. Only voltages in
the safe operating supply range are passed
along to the load. The only external active
component required is a dual N-channel
MOSFET connected between the unpredictable supply and the sensitive load.
Figure 1 shows a complete application.
A resistive divider sets the overvoltage
(OV) and undervoltage (UV) trip points for
connecting/disconnecting the load from
VIN . If the input supply wanders outside
this voltage window, the LTC4365 quickly
disconnects the load from the supply.
The dual N-channel MOSFET blocks both
positive and negative voltages at VIN . The
LTC4365 provides 8.4V of enhancement
Si4946
VIN
12V
GATE
VIN
VOUT
3A
VOUT
LTC4365
510k
SHDN
One drawback to both of these solutions is that they sacrifice low supply
operation, especially the series diode.
Also, neither protects against voltages that
are too high—protection that requires
more circuitry, including a high voltage
window comparator and charge pump.
1820k
UV
OV
GND
Accurate and Fast Overvoltage and
Undervoltage Protection
Two accurate (±1.5%) comparators in
the LTC4365 monitor for overvoltage (OV)
and undervoltage (UV) conditions at VIN .
If the input supply rises above the OV or
below the UV thresholds, respectively, the
gate of the external MOSFET is quickly
turned off. The external resistive divider
allows a user to select an input supply
range that is compatible with the load at
VOUT. Furthermore, the UV and OV inputs
have very low leakage currents (typically < 1n A at 100°C), allowing for large
values in the external resistive divider.
Figure 2 shows the how the circuit of
Figure 1 reacts as VIN slowly ramps from
–30V to 30V. The UV and OV thresholds
are set to 3.5V and 18V, respectively.
VOUT tracks VIN when the supply is
inside the 3.5V–18V window. Outside
of this window, the LTC4365 turns off
the N-Channel MOSFET, disconnecting
VOUT from VIN, even when VIN is negative.
Novel Reverse Supply Protection
FAULT
243k
59k
to the gate of the external MOSFET during
normal operation. The valid operating
range of the LTC4365 is as low as 2.5V and
as high as 34V—the OV–UV window can
be anywhere in this range. No protective
clamps at VIN are needed for most applications, further simplifying board design.
OV = 18V
UV = 3.5V
Figure 1. Complete 12V automotive undervoltage,
overvoltage and reverse-supply protection circuit
The LTC4365 employs a novel negative supply protection circuit. When the LTC4365
senses a negative voltage at VIN, it quickly
connects the GATE pin to VIN . There is
no diode drop between the GATE and
VIN voltages. With the gate of the external
July 2011 : LT Journal of Analog Innovation | 23
The LTC4365 is a unique solution that elegantly and robustly protects sensitive
circuits from unpredictably high or negative supply voltages. The LTC4365 blocks
positive voltages as high as 60V and negative voltages as low as –40V. Only
voltages in the safe operating supply range are passed along to the load.
VIN
30V
GND
VOUT
1V/DIV
VOUT
OV = 18V
VALID WINDOW
5V/DIV
VOUT
UV = 3.5V
GND
GND
VIN
20V/DIV
VIN
–20V
GND
GATE
GATE
–30V
10µF, 1k LOAD ON VOUT
60V DUAL NCH MOSFET
10V/DIV
2.5ms/DIV
500ns/DIV
1s/DIV
Figure 2. Load protection as VIN is swept from –30V
to 30V
Figure 3. Hot swapping VIN to –20V
Figure 4. 36ms recovery timer blocks 28V, 60Hz AC
line voltage
N-channel MOSFET at the most negative
potential (VIN), there is minimal leakage
from VOUT to the negative voltage at VIN .
ring significantly below –20V. The external MOSFET must have a breakdown
voltage that survives this overshoot.
AC BLOCKING
Figure 3 shows what happens when
VIN is hot plugged to –20V. VIN, VOUT and
GATE start out at ground just before the
connection is made. Due to the parasitic
inductance of the VIN and GATE connections, the voltage at VIN and GATE pins
The speed of the LTC4365 reverse protection circuits is evident by how closely the
GATE pin follows VIN during the negative
transients. The two waveforms are almost
indistinguishable on the scale shown.
Note that no additional external circuits
are needed to provide reverse protection.
Figure 5. OV fault with
large VIN inductance
VIN
24V
12 INCH WIRE
LENGTH
+
Figure 6. Transients during OV fault
when no TranZorb (TVS) is used
SI9945
60V
CIN
1000µF
M1
R3
100k
D1
OPTIONAL
VOUT
M2
GATE
VIN
+
VOUT
COUT
100µF
9Ω
GATE
VOUT
VOUT
GATE
GND
20V/DIV
LTC4365
VIN
SHDN
UV
GND
FAULT
IIN
2A/DIV
R2
2370k
OV
R1
40.2k
The LTC4365 has a recovery delay timer
that filters noise at VIN and helps prevent chatter at VOUT. After either an
OV or UV fault (or when VIN goes negative) has occurred, the input supply must
return to the desired operating voltage window for at least 36ms in order
to turn the external MOSFET back on.
GND
0A
OV = 30V
250ns/DIV
24 | July 2011 : LT Journal of Analog Innovation
design features
The LTC4365’s novel architecture results in a
rugged, small solution size with minimal external
components, and it is available in tiny 8-pin
3mm × 2mm DFN and TSOT-23 packages.
Going out of and then back into fault in
less than 36ms keeps the MOSFET off.
Figure 4 shows the LTC4365 blocking an AC line voltage of 40V to –40V.
The GATE pin follows VIN during the
negative portions, but remains at
ground when VIN goes positive. Note
that VOUT remains undisturbed.
HIGH VOLTAGE TRANSIENTS
DURING FAULT CONDITION
Figure 5 shows a test circuit designed to
produce transients during an overvoltage
condition. The nominal input supply is
24V with an overvoltage threshold of 30V.
Figure 6 shows the waveforms during an
overvoltage condition at VIN . These transients depend on the parasitic inductances
on the VIN and GATE pins. The circuits
survived the transients without damage,
even though the optional power clamp
(D1) was not used during the experiments.
SELECT BETWEEN TWO SUPPLIES
CONCLUSION
With the part in shutdown, the VIN and
VOUT pins can be driven by two different power supplies at different voltages.
The LTC4365 automatically drives the
GATE pin below the lower of the two
supplies, thus preventing current from
flowing in either direction through the
external MOSFET. The application of
Figure 7 uses two LTC4365s to select
between two power supplies. Care should
be taken to ensure that only one of the
two LTC4365s is enabled at any given time.
The LTC4365 controller protects sensitive circuits from overvoltage, undervoltage and reverse supply connections.
The supply voltage is passed to the
output only if it is qualified by the user
adjustable UV and OV trip thresholds.
Any voltage outside this window is
blocked, up to 60V and down to –40V.
REVERSE V IN HOT SWAP
WHEN V OUT IS POWERED
LTC4365 protects against negative VIN connections even when VOUT is driven by
a separate supply. With the LTC4365 in
shutdown and VOUT powered to 20V,
Figure 8 shows the waveforms when
VIN is hot swapped to –20V. As long as
the breakdown voltage of the external MOSFET is not exceeded (60V), the
20V supply at VOUT is not affected by
the reverse polarity connection at VIN .
The LTC4365’s novel architecture results
in a rugged, small solution size with
minimal external components, and it
is available in tiny 8-pin 3mm × 2mm
DFN and TSOT-23 packages. No reverse
voltage blocking diode in series with the
supply is needed; the LTC4365 performs
this function automatically with back-toback external MOSFETS. The LTC4365 has
a wide 2.5V to 34V operating range and
consumes only 10µ A during shutdown. n
V1
M1
M2
Figure 7. Selecting between one of two supplies
GATE
VIN
Figure 8. Negative VIN hot swap with VOUT powered
VOUT
LTC4365
OUT
SHDN
SEL OUT
0
V1
1
V2
V2
M1
M2
GATE
VIN
LTC4365
SEL
SHDN
VOUT
10V/DIV
20V
VIN
GATE
10V/DIV
GND
–20V
VOUT
M1, M2 = Si9945 DUAL, 60V
100ns/DIV
July 2011 : LT Journal of Analog Innovation | 25
Power Supply Works with FET Drivers, DrMOS and Power
Blocks for Flexible Placement Near Microprocessors
Theo Phillips
As microprocessors demand progressively more current at lower voltages, it becomes
important to minimize conduction losses by placing the power supply as close to
the load as possible. This increases the value of every square millimeter of board
space near the load—particularly when multiple power stages are used. It is also
important to locate the DC/DC controller away from high current paths, which can
be difficult when the MOSFET gate drivers are in the controller package, because the
gate traces must also be kept short. Sometimes the best solution is to use external
power train devices or discrete N-channel MOSFETs and associated gate drivers.
The LTC3860 is a dual output step-down
DC/DC controller designed to work in
conjunction with drivers or power train
devices such as DrMOS and power blocks,
enabling flexible design configurations
with PolyPhase® operation. Up to 12
stages can be paralleled to increase output
current and clocked out of phase to minimize input and output filtering (Figure 1).
In PolyPhase configurations, both output
voltage (VOUT) and ground terminals
are monitored using a single differential
amplifier, enabling tight regulation even
where IR losses occur through vias, trace
runs and interconnects. Regulation is
further enhanced by the accuracy of the
600mV reference, which is ±0.75% with
junction temperatures from 0°C to 85°C.
VSNSOUT1
VCC
0°, 180°
CLKIN
CLKOUT
PHSMD
FB1
FB2
ILIM2
COMP1
ILIM1
COMP2
IAVG TRACK/SS1,2
+60°
VCC
60°, 240°
CLKIN
CLKOUT
PHSMD
FB1
FB2
ILIM2
COMP1
ILIM1
COMP2
IAVG TRACK/SS1,2
+60°
VCC
120°, 300°
CLKIN
CLKOUT
PHSMD
FB1
FB2
ILIM2
COMP1
ILIM1
COMP2
IAVG TRACK/SS1,2
+90°
Voltage mode operation ensures that
per-phase currents up to 30A can be
achieved while a stable switching waveform is maintained. In a current mode
converter, the voltage on the output of
the error amplifier controls the peak
or valley switch current, such that the
switch current must always be monitored. With typical sense voltages of less
than 100mV and current sense elements
having resistance of less than 1mΩ, the
introduction of noise is always a concern. In contrast, the LTC3860 compares
the differentially sensed error voltage on
VOUT to a sawtooth ramp, which is on
the order of 1V. The ramp controls duty
cycle—the larger the error voltage, the
longer each phase’s top switch stays on.
A 2-PHASE, SINGLE OUTPUT
REGULATOR USING INTEGRATED
DRIVER-MOSFETs (DrMOS)
VCC
210°, 30°
CLKIN
CLKOUT
PHSMD
FB1
FB2
ILIM2
COMP1
ILIM1
COMP2
IAVG TRACK/SS1,2
+60°
VCC
270°, 90°
CLKIN
CLKOUT
PHSMD
FB1
FB2
ILIM2
COMP1
ILIM1
COMP2
IAVG TRACK/SS1,2
+60°
VCC
330°, 150°
CLKIN
CLKOUT
PHSMD
FB1
FB2
ILIM2
COMP1
ILIM1
COMP2
IAVG TRACK/SS1,2
Figure 1. Pin interconnections for a 12-phase buck converter using the LTC3860
26 | July 2011 : LT Journal of Analog Innovation
Citing needs for high power density,
increased efficiency at high switching
frequencies, and interoperability between
controllers and power devices, Intel has
issued a set of technical specifications for
integrated driver-MOSFETs (DrMOS) used
in step-down DC/DC converters powering
its microprocessors. The compact layout reduces efficiency losses due to stray
design features
Because the LTC3860 has a PWM output instead of
onboard MOSFET drivers, it can occupy board space
away from critical high current paths. Its applications
include high current power distribution and industrial
systems, and telecom, DSP and ASIC supplies.
VIN
9V
+
470µF
100pF
CMDSH-3
DRMBIAS
5V
VCC
0.1µF
100k
PGOOD
RUN
VCC
5V
30.1k
VCC
TRACK/SS1
VINSNS
IAVG
PGOOD1
RUN1
PWMEN1
PWM1
100pF
49.9Ω
3.16k
6.8nF
VDIFF
VOS
VOS
VCC
SGND
PWMEN1,2
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
LTC3860
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
1000pF
VDIFF1
20k
VCIN
DISB
PWM
PWM1
1µF
FREQ SET FOR 600kHz
HSEN BOOT
FDMF8704
VSWH
PGND
VIN
0.22µF
SW1
0.19µH**
VOSP
100µF
6.3V
×10*
1.74k
51.1k
VOSN
0.22µF
0.22µF
VCC
CGND
PWM
DISB
VCC
VCIN
4.99k
RUN
* MURATA GRM32ERG0J107M
** WÜRTH 744355019
VIN
CGND
4.99k
PWM2
TRACK/SS
22µF
4.7µF
DRMBIAS
5V
PGND
FDMF8704
VIN
VSWH
HSEN BOOT
1.74k
SW2 0.19µH**
0.22µF
22µF
4.7µF
VIN
CMDSH-3
Figure 2. A 2-phase, single output converter using the FDMF8704 in each power stage to produce a 1V, 50A converter with all ceramic output capacitors
inductance. Several manufacturers have
produced compliant devices. They are
expected to operate at >500kHz (preferably
1MHz), deliver 25A per phase at ~1V from
a 5V–16V input, and occupy 8mm × 8mm
or 6mm × 6mm packages with defined
pinouts. They must accept a PWM input,
which is used to alternately turn the top
and bottom MOSFETs on and off when the
input is high or low. It must be possible
to turn both MOSFETs off (three-state),
by leaving the PWM pin floating or by
pulling the DISB pin of the DrMOS low.
An external inductor is required.
The LTC3860 provides a PWM signal compatible with DrMOS-compliant devices. For
example, the Fairchild FDMF8704 DrMOS is
specified for operation up to 1MHz at
25A per phase, and the LTC3860 can be
programmed for a switching frequency
from 200kHz –1.2MHz. The LTC3860’s
high and low commands are interpreted
by the FDMF8704 as top MOSFET on and
bottom MOSFET on, respectively. This
DrMOS does not recognize three-state
signals on the PWM pin, but both of its
MOSFETs turn off when its DISB pin is
pulled low. The LTC3860’s PWMEN pulls
high through an open drain whenever PWM is high or low. When PWM is
three-state, an external resistor pulls the
PWMEN pin low. Thus, three-state operation of the power stage is accomplished
here by tying the PWMEN pin of the
LTC3860 to the DISB pin of the DrMOS.
Figure 2 is the schematic for a 2-phase,
single output converter using the
FDMF8704 in each power stage to produce a 1V, 50A converter. A switching
frequency of 600kHz is selected by tying
CLKIN low and FREQ high. The effective
frequency is 1.2MHz, because the two
channels operate 180° out of phase.
By reducing the latency between clock
cycles, the high switching frequency
July 2011 : LT Journal of Analog Innovation | 27
The LTC3860 has internal current sharing, and only
requires simple pin configurations and one external
capacitor at the IAVG pin to run phases together.
The IAVG pin stores a charge corresponding to the
instantaneous average current of all phases.
ILOAD
20A/DIV
IL
5A/DIV
IL
5A/DIV
VOUT
100mV/DIV
(AC-COUPLED)
VOUT
50mV/DIV
(AC-COUPLED)
VOUT
50mV/DIV
(AC-COUPLED)
20µs/DIV
LOAD STEP = 10A TO 30A
4µs/DIV
LOAD STEP = 10A TO 20A
a
Figure 3. Load transient response for the converter
of Figure 2
improves transient response. Stable
operation is possible with all ceramic
output capacitors, which minimize the
output ripple because of their low ESR.
Figure 3 shows the converter’s transient response to a large load step.
A common drawback of voltage mode
converters is that they do not play
well together when they are combined
to increase power capability. They
typically use the outputs of onboard
op amps as their loop compensation
nodes. Because these outputs are low
impedance, they cannot just be tied
together to balance the current from
each power stage. An external circuit
would be needed for each phase.
The LTC3860 has internal current sharing, and only requires simple pin configurations and one external capacitor at
the IAVG pin to run phases together. The
IAVG pin stores a charge corresponding
to the instantaneous average current of
all phases. The slave channel’s FB pin is
28 | July 2011 : LT Journal of Analog Innovation
4µs/DIV
LOAD STEP = 20A TO 10A
b
Figure 4. The converter of Figure 2 demonstrates stable current sharing at
both edges of a load transient: (a) rising edge; (b) falling edge.
connected to INTVCC , a single differential
amplifier is placed ahead of the master’s
FB pin, and each TRACK/SS, COMP, and
output is tied to the other. The power
stages are now actively balanced. One
power good indicator, PGOOD1, reports
undervoltage and overvoltage events.
The maximum current sense mismatch
between phases is ±2mV between channels on the same IC or on different ICs.
This translates to tight current sharing
between channels in PolyPhase applications, particularly when the current sense
elements are well matched. Here, the
Würth 744355019 inductors’ DC resistance
is specified to have a tolerance of ±10%
at 20°C. Figures 4a and 4b show that
the inductor current levels follow each
other closely during a load transient.
A differential amplifier provides remote
sensing of the output voltage. VSNSP and
VSNSN are tied to VOUT and PGND at the
point of load. The potential between
these pins is translated, with unity gain,
to a potential between VSNSOUT and SGND.
VSNSOUT is tied to the feedback string
leading to FB of the master channel. This
arrangement overcomes error due to
board interconnection losses, which often
result in voltage offsets between power
ground and SGND. For this 1V output,
the difference between no load and
full load VOUT is typically just 1mV.
WHEN EFFICIENCY IS THE PRIORITY
When efficiency is a higher priority than
minimizing board space, operating the
LTC3860 at a relatively low switching
frequency reduces switching losses, while
adding a synchronous MOSFET reduces
conduction losses, particularly if the
converter operates at low duty cycle.
Since DrMOS packages contain just one
main and one synchronous MOSFET, it
becomes beneficial to use discrete FETs
and drivers. The powerful LTC4449
driver is ideally suited to the task.
The LTC4449 is designed to drive top
and bottom MOSFETs in a synchronous
design features
When efficiency is a higher priority than minimizing board space, operating the
LTC3860 at a relatively low switching frequency reduces switching losses, while
adding a synchronous MOSFET reduces conduction losses, particularly if the
converter operates at low duty cycle. Since DrMOS packages contain just one main
and one synchronous MOSFET, it is beneficial to use discrete FETs and drivers.
VIN
VIN
7V TO 18V
+
150µF
DRMBIAS
5V
PWM1
1µF
VCC
IN
0.1µF
100k
VCC
TRACK/SS1
VINSNS
IAVG
PGOOD1
RUN1
PWM1
1nF
VDIFF1
20k
1% 220Ω
20k
1%
47pF
470pF
1.74k
BG
TS
TG
VOS1P
M1
BG1
TG1
SW1
M2
VDIFF1
VOS1N
VOS1P
VCC
SGND
PWMEN1,2
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
LTC3860
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
49.9k
0.3µH
+
M3
VCC
1µF
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWM2
RUN
VCC
5V
LTC4449
GND
VLOGIC
VCC
BOOST
2.2Ω
4.7µF
22µF
×2
330µF
×3
VOUT
1.2V
25A
2.74k
0.22µF
VOS1N
SW1
47µF
×3
0.22µF
M1,M2, M3: RJK0305DPB
COUT: 330µF ×3 SANYO 2R5TPE330M9
L: 0.3µH PULSE PA0515.321NL
PWM2
FREQ SET FOR 400kHz 0Ω
Figure 5. The LTC3860 can use the LTC4449 to drive discrete MOSFETs. A synchronous MOSFET is added to improve efficiency.
DC/DC converter. It accepts high, low and
three-state inputs, with thresholds proportional to the LTC3860 power supply
because the LTC4449 VLOGIC is at the same
potential as the LTC3860 VCC . The VCC of
the LTC3860 can range from 3V to 5.5V,
and if it drops below the undervoltage
lockout (UVLO) threshold (2.9V falling,
3.0V rising), both channels of the LTC3860
are disabled. UVLO ensures that the driver
operates only when VCC is at safe levels.
For maximum efficiency, the LTC4449’s
top gate has pull-up and pull-down
times of 8ns and 7ns; the bottom
gate, 7ns and 4ns, while looking into
3000pF loads. Adaptive shoot-through
protection ensures that the dead times
are short enough to avoid power loss,
but not so short that cross-conduction
can occur. The driver is available in a
low profile 2mm × 3mm DFN package.
Figure 5 shows a schematic for a single
channel, 400kHz, single phase converter
using the LTC4449 and discrete MOSFETs.
Figure 6 shows the improvement in
efficiency compared to a DrMOS solution operating at the same frequency
with the same passive components.
Discrete MOSFETs also provide an input
voltage capability higher than the
DrMOS requirement (16V). The VINSNS pin
of the LTC3860, which connects to the
supply at the drain of the main MOSFET,
can handle up to 24V. This allows
LTC3860 applications to benefit from
the large number of 30V MOSFETs available from various manufacturers.
400kHz operation is set by tying the
FREQ and CLKIN pins low. Other switching
frequencies, from 250kHz to 1.25MHz, can
be programmed with a single resistor from
FREQ to ground, or synchronized with
an external signal source, with a smooth
transition to and from the resistor-set
frequency if an interruption in the sync
signal occurs. No external PLL filter components are required for synchronization.
The VINSNS pin monitors the input voltage
and immediately adjusts the duty cycle in
a manner inversely proportional to VIN,
bypassing the feedback loop. This feature
brings two benefits: a set of compensation
values works across the entire VIN range,
and during a line transient deviation in
VOUT is minimal, as Figure 7 shows.
July 2011 : LT Journal of Analog Innovation | 29
Instead of selecting power stage components,
designers have the option of specifying an entire
power stage on a small PC board. Known as a power
block, it includes MOSFETs, a MOSFET driver, an
inductor, and minimal input and output capacitors.
100
LTC4449 + MOSFETs
90
EFFICIENCY (%)
80
PIP212-12M
70
60
SW
5V/DIV
50
IL
10A/DIV
40
VOUT
100mV/DIV
(AC-COUPLED)
30
20
VOUT
1V/DIV
SHORT CIRCUIT
10
0
0
10
1
5µs/DIV
100
VIN = 12V
VOUT = 1.2V
ILOAD (A)
20ms/DIV
L = PA0515.321NL
RLIM = 61.9k
Figure 6. The circuit of Figure 5 shows improved
efficiency compared with a typical DrMOS solution.
The compromise is in board space—a DrMOS
occupies 36mm2 or 64mm2, and the driver and three
MOSFETs occupy 101mm2, excluding the traces
connecting the components.
Figure 7. Through its VINSNS pin, the LTC3860
provides line feedforward compensation, preventing
steady state and dynamic variations in VOUT when
VIN is not constant.
Figure 8. Short circuit behavior of the LTC3860
The ILIM pin provides a handle for setting
current limit. It sources 20µ A through
an external resistor, providing a voltage
proportional to the current limit. When
current limit is reached, the LTC3860
three-states the PWM output, resets the
soft-start timer, and waits 32768 switching cycles before restarting (Figure 8).
WHEN SIMPLICITY IS REQUIRED
Connections are also provided for temperature sensing and inductor DCR sensing. They typically operate at 12V input,
switching at 400kHz –500kHz and source
20A–40A. Unlike DrMOS, power blocks
do not occupy a standard footprint.
The LTC3860 has the ability to start
up into a prebiased output. When the
TRACK/SS voltage is below the voltage at
FB, the LTC3860 will not switch (except for
refresh pulses, which keep the boost capacitor charged). When TRACK/SS exceeds
FB, switching commences, but inductor
current is not allowed to reverse until the
output reaches regulation, when continuous conduction mode begins. Thus, the
output is allowed to rise gently (Figure 9).
Instead of selecting power stage components, designers have the option of
specifying an entire power stage on a
small PC board. Known as a power block,
it includes MOSFETs, a MOSFET driver, an
inductor and minimal input and output
capacitors. Electrical and mechanical
connection is made through standoffs
which surface mount onto the main board.
Figure 9. Start-up into a prebiased output for
discrete MOSFET application
VOUT
500mV/DIV
1.2V
0.9V
TRACK/SS
500mV/DIV
IL
5A/DIV
2ms/DIV
30 | July 2011 : LT Journal of Analog Innovation
The LTC3860 is shown in Figure 10
coupled with a Delta power block. This
high current, 400kHz, 2-phase application can source 45A at its output. Since
each channel operates 180° out of phase
with respect to the other, the effective
switching frequency is doubled, minimizing stress on the input and output
capacitors. The power block’s physical
dimensions are approximately 1.0"L
× 0.5"W × 0.5"H, yielding a small solution size. Topside heat sinks are provided for the onboard MOSFETs, and
200LFM airflow at <55°C is required.
design features
The LTC3860 is a dual output step-down DC/DC
controller designed to work in conjunction with drivers or
power train devices such as DrMOS and power blocks,
enabling flexible design configurations with PolyPhase
operation. Up to 12 stages can be paralleled.
SOME OPTIONS WITH THIS
VERSATILE CONTROLLER
The applications presented here use the
drop across the inductor to sense current sharing and current limit. If a small
increase in power loss is acceptable,
greater accuracy may be achieved by using
a discrete sense resistor in series with
the inductor. The applications here also
have output voltages in the 1.x range.
Outputs as low as 0.6V (the reference
voltage) or as high as 4V (the maximum
output voltage of the differential amplifier) are also possible, with ±1% reference
CONCLUSION
voltage accuracy over an operating
temperature range of –40°C to 125°C.
The LTC3860 is a voltage mode buck
controller that supports up to 12 phases in
parallel with onboard current sharing. It
may be used with DrMOS, power blocks or
discrete MOSFETs and the LTC4449 driver.
Because the LTC3860 has a PWM output
instead of onboard MOSFET drivers, it can
occupy board space away from critical
high current paths. Its applications include
high current power distribution and
industrial systems, and telecom, DSP and
ASIC supplies. The LTC3860 is available in
a 32-lead 5mm × 5mm QFN package. n
Instead of the default 2ms soft-start used
by the applications here, adjustable softstart (>2ms) and tracking are also possible for each output. Longer soft-start
times are achieved by adding >10nF from
TRACK/SS to ground. Tracking is achieved
by driving the pin with a DC voltage of
less than 0.6V. The output regulates to the
lowest of the internal 600mV reference,
the voltage on the TRACK/SS pin, or the
internal soft-start ramp for that channel.
Figure 10. A 2-phase, single output converter using a 45A Delta power block for the power stage
VIN
10V TO 14V
+
180µF
VCC
5V
VCC
100pF
100k
1µF
VOS1P
7V BIAS
4.7µF
PGOOD
PWM1
VCC
VDIFF1
20k
1%
30.1k
1%
562Ω 100pF
4.64k
1.5nF
VDIFF1
VOS1N
VOS1P
VCC
LTC3860
VCC
RUN
0.1µF
FREQUENCY SET FOR 400kHz
34.8k
1%
53.6k
ILIM1
0.22µF
ISNS1P
ISNS1N
ISNS2N
ISNS2P
TRACK/SS1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWM2
1500pF
GND
PWMEN1,2
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
VINSNS
IAVG
PGOOD1
RUN1
RUN2
PWM1
RUN
ILIM2
PWM2
0.22µF
VCC
+7V
TEMP1 VOUT1
PWM1
POWER BLOCK
DELTA
D12S1R845A
+CS1
–CS1
–CS2
51Ω
+
100µF
×6
330µF
×6
GND
VOUT1
1V
45A
4.7µF
×2
51Ω
VOS1N
+CS2
VIN1
VIN2
TEMP2 VOUT2
PWM2
GND
22µF
16V
×4
VIN
100k
VCC
July 2011 : LT Journal of Analog Innovation | 31
The Harsh Reality of Wide-Ranging 4V–36V Automotive
Batteries Is No Problem for Triple Output Regulator in
4mm × 5mm QFN
Michael Nootbaar
DC/DC converters for automotive applications must operate
in an environment of extremes. Input transients can exceed
the nominal battery voltage by a factor of five and last
hundreds of milliseconds, while temperatures under the
hood soar far above the capability of typical commercial
grade ICs. In this harsh environment, space is tight, so even
the most robust devices must perform multiple functions.
The LT3694/LT3694-1 meets these requirements by combining a 2.6A switching
regulator and two low dropout linear
regulators in a compact 4mm × 5mm
QFN package or a thermally enhanced
TSSOP. The switching regulator requires
a single inductor and has an internal
power switch, cycle-by-cycle current
limiting and track/soft-start control. Each
LDO requires only an external NPN pass
transistor and includes foldback current limiting and track/soft-start control. An internal overvoltage detector
shuts off the switching regulator when
VIN exceeds 38V, protecting the switch and
the Schottky rectifier. This allows it to
survive transients on VIN up to 70V without damage to itself or the rectifier.
tailoring of loop bandwidth, transient response and phase margin.
TWO LOW DROPOUT
LINEAR REGULATORS
The LT3694/LT3694-1 includes two
LDO linear regulators that use an external NPN pass transistor to provide up to
0.5A of output current. The base drive
can supply up to 10m A of base current to
the pass transistor and is current limited.
The LDO is internally compensated and is
The regulator uses a current mode,
constant frequency architecture, which
keeps loop compensation simple.
External compensation allows custom
32 | July 2011 : LT Journal of Analog Innovation
The LDO drive current is drawn from
the BIAS pin if it is at least 0.9V higher
than the DRIVE pin voltage, otherwise
it’s drawn from VIN . This reduces the
power consumption of the LDO, especially when VIN is relatively high.
The LDO has foldback current limiting by
monitoring a sense resistor in the collector of the NPN pass transistor. The initial
threshold is set at 60mV, but folds back as
VFB decreases until at VFB = 0 the threshold
is at 26mV. A sense resistor of 0.1Ω sets
the operating current limit at 600m A, but
the short circuit current limit drops to
260m A. This reduces power dissipation in
the pass transistor with a shorted output.
Figure 1. The LT3694/LT3694-1 in a wide input range, triple output application.
VIN
6.3V TO 36V
TRANSIENT TO 70V
10µF
26.1k
100k
EN/UVLO
VIN BIAS
B340A
TRK/SS3
OUT1
FB1
LIM2
ZXTN25020DG
LT3694
VC1
DRV2
LIM3
2.2µF
57.6k
DA
12nF
OUT2
2.5V
450mA
OUT1
5V
1.7A
SW
TRK/SS2
0.10Ω
BST
0.22µF 5.4µH
TRK/SS1
4V–36V INPUT
SWITCHING REGULATOR
The LT3694/LT3694-1 includes a
36V monolithic switching regulator
capable of providing up to 2.6A of output current from input voltages down
to 4V. Output voltages can be set as low
as the feedback reference of 0.75V.
stable with output capacitance of 2.2µF or
greater. It uses the same 0.75V feedback
reference as the switching regulators.
24.9k
DRV3
20k
10.2k
1000pF
0.10Ω
OUT1
ZXTN25020DG
FB2
34k
10.7k
FB3
53.6k
10k
RT
SYNC GND
fSW = 800kHz
2.2µF
OUT3
3.3V
450mA
22µF
design ideas
The LT3694/LT3694-1 combines a 2.6A switching regulator
and two 500mA low dropout linear regulators in a compact
4mm × 5mm QFN package or a thermally enhanced TSSOP.
100
VIN = 6.3V
VOUT1
1V/DIV
VOUT3
1V/DIV
VOUT2
1V/DIV
EN/UVLO
5V/DIV
200µs/DIV
Figure 2. Ratiometric tracking waveforms
90
EFFICIENCY (%)
The LDOs can be shut down by pulling the FB pin above 1.25V with at least
30µ A. If independent control of the
LDOs is needed, each LDO output can
be forced to 0V by pulling its TRK/SS pin
low. If the track or soft-start functions
are needed, use an open drain output
in parallel with the track or soft-start
circuitry described below. If track and
soft-start are not necessary, then a standard CMOS output (from 1.8V to 5V)
with a 1k series resistor works fine.
VIN = 12V
VIN = 36V
80
70
60
50
0
0.5
1
1.5
ILOAD (A)
2
2.5
Figure 3. Switching regulator efficiency
TRACK/SOFT-START CONTROL
The buck regulator and each LDO has
its own track/soft-start (TRK/SS) pin.
When this pin is below the 0.75V reference, the regulator forces its feedback
pin to the TRK/SS pin voltage rather than
the reference voltage. The TRK/SS pin
has a 3µ A pull-up current source.
The soft-start function requires a capacitor
from the TRK/SS pin to ground. At startup, this capacitor is at 0V, which forces
the regulator output to 0V. The current
source slowly charges the capacitor voltage up and the regulator output ramps
up proportionally. Once the capacitor
voltage reaches 0.75V, the regulator locks
onto the internal reference instead of the
TRK/SS voltage. The TRK/SS pin is pulled
low on any shutdown event (overvoltage,
overtemperature, undervoltage) in order
to discharge the soft-start capacitor.
The track function is achieved by connecting the slave regulator’s TRK/SS pin to
a resistor divider from the master regulator output. The master regulator uses a
normal soft-start capacitor as described
above to generate the start-up ramp that
controls the other regulators. The resistor divider ratio sets the type of tracking,
either coincident (ratio equal to slave
feedback divider ratio) or ratiometric
(ratio equal to master feedback divider
ratio plus a small offset). The TRK/SS pins
can also be tied together to a single
capacitor to provide ratiometric tracking,
but only if the LDOs are not shut down
by pulling FB high (see the section “Two
Low Dropout Linear Regulators” above).
ENABLE AND UNDERVOLTAGE
PROTECTION
The LT3694/LT3694-1 includes an enable
and user programmable undervoltage
lockout function using the EN/UVLO pin.
The undervoltage lockout can protect
against pulse stretching. It can also
protect the input source from excessive current since the buck regulator
is a constant power load and draws
more current when the input source is
low. The undervoltage lockout shuts
off all three regulators when tripped.
These two functions use a pair of built-in
comparators at the EN/UVLO input. The
enable comparator has a 0.5V threshold and activates the internal bias circuits of the LT3694/LT3694-1. When
EN/UVLO is below the enable threshold,
the LT3694/LT3694-1 is in shutdown and
draws less than 1µ A with 12V input.
The undervoltage comparator has a
1.2V threshold and has 2µ A of hysteresis.
The UVLO hysteresis is a current sink that
activates when EN/UVLO drops below the
1.2V threshold. A resistor divider from
VIN to the EN/UVLO input sets the trip
voltage and hysteresis. The undervoltage
threshold is accurate over temperature to
allow tight control over the trip voltage. The EN/UVLO pin should be connected to VIN if the function isn’t used.
FREQUENCY CONTROL
The switching frequency is adjustable
from 250kHz to 2.5MHz, set by a single
resistor to the RT pin. Higher frequencies
allow smaller inductors and capacitors,
but use more power and have a smaller
(continued on page 43)
July 2011 : LT Journal of Analog Innovation | 33
Ultralow Power 16-Bit High Speed Signal Chain Solution for
Portable Sampling Systems
Clarence Mayott
The LTC2195 family of ultralow power, dual 16-bit, 25Msps to 125Msps analog-to-digital
converters (ADCs) dissipate half the power of competing 16-bit solutions, extending
battery run times in portable electronics. Despite consuming only ~1.5mW/Msps per
channel, the LTC2195 does not shirk performance to save power, yielding a 76.8dB
signal-to-noise ratio (SNR) and 90dB of spurious free dynamic range (SFDR) at baseband (0MHz–62.5MHz, the first Nyquist zone). Serial LVDS outputs reduce the number
of data lines required for routing the ADC data while minimizing digital feedback.
SIGNAL PATH DESIGN
The LTC2195 family is an ideal solution for applications that require 16-bit
performance and ultralow power consumption to extend battery life. Portable
medical imaging equipment is a perfect
example. In many imaging applications
the signal from the image sensor must
be conditioned before being sampled by
the ADC. For this task, it is important to
choose a low noise, low power amplifier that matches the performance of the
ADC, such as the LTC6406, which makes
a good match for the LTC2195 family.
The LTC6406 is a fully differential
amplifier with low noise (1.6nV/√Hz at
the input) and high linearity (+44dBm
OIP3 at 20MHz) in a small 3mm × 3mm
QFN package. External resistors set the
gain, giving the user maximum design
flexibility. Low power consumption
(59mW with a 3.3V supply) minimizes
the effect on the system power budget. This amplifier also has a common
mode voltage range that extends down
to 0.5V meaning it can be paired seamlessly with the LTC2195, which has a
nominal common mode voltage of 0.9V.
Typically the output of an image sensor is single-ended. This requires a
single-ended to differential translation
before being sampled by the ADC. If
response to DC is also required, a transformer cannot be used. This situation
mandates a low noise amplifier that is
capable of doing single-ended to differential translation, like the LTC6406.
The amplifier must be followed by a
filter to reduce the wideband noise of
the amplifier and to isolate the output
of the amplifier from the ADC inputs—
the ADC inputs produce common mode
glitches associated with the commutation
of the sample caps. A filter helps attenuate these glitches, protecting the amplifier.
A high order filter is not required, since
the noise of the amplifier is fairly low.
With a corner frequency of 12MHz, the
filter used here is adequate—it does not
degrade the performance of the ADC.
The final filter should be designed to
reduce only the wideband noise of the
amplifier, not as a selectivity filter with a
Table 1. The new generation of ultralow power 16-bit ADCs
SINGLE
CHANNEL
DUAL
CHANNEL
POWER
25Msps
40Msps
65Msps
80Msps
105Msps
125Msps
7 × 7 QFN
1.8V Single ADCs, Parallel Outputs
2160
2161
2162
2163
2164
2165
9 × 9 QFN
1.8V Dual ADCs Parallel Outputs
2180
2181
2182
2183
2184
2185
7 × 8 QFN
1.8V Dual ADCs, Serial LVDS Outputs
2190
2191
2192
2193
2194
2195
(mW/Ch)
40
60
80
100
155
185
34 | July 2011 : LT Journal of Analog Innovation
design ideas
In many imaging applications the signal from the image
sensor must be conditioned before being sampled
by the ADC. For this task, it is important to choose
a low noise, low power amplifier that matches the
performance of the ADC, such as the LTC6406, which
makes a good match for the LTC2195 family.
steep transition band. A steep transition
band in the filter increases insertion loss
and degrades the OIP3 of the amplifier,
which leads to distortion of the signal
from the image sensor. The circuit shown
in Figure 1 accomplishes this goal.
be used to produce attenuation or gain
depending on the output of the image sensor. As the gain of the amplifier increases,
the amount of compensation capacitance required to stabilize the amplifier
decreases. In this unity gain application
1.8pF is enough to produce good results.
If the amplifier is used to attenuate the
signal, more capacitance is required.
RESULTS
Figure 2 shows the performance of
this circuit. The results show that the
linearity of the amplifier does not
degrade the SFDR of the ADC at low
input frequencies. The SNR also remains
unchanged at 76.5dB. The LTC6406 does
not degrade the SNR or the SFDR of the
LTC2195 when using it at unity gain.
MODIFICATIONS
For this design there are some trade-offs
that can be made to change the performance of the system. First, the gain can
change by increasing the feedback resistors, or decreasing the source resistors.
Typically the source resistors are set by the
output impedance of the sensor itself. The
feedback resistors are then used to modify
the gain of the amplifier. The LTC6406 can
The low order, low pass filter in
Figure 1 attenuates the wideband noise
of the amplifier with a cutoff frequency
of 12MHz. This cutoff frequency can be
increased by decreasing the value of the
final capacitors. Because the amplifier
cannot drive a low impedance, and the
ADC wants to see a low impendence at its
analog inputs the impendence of the filter
has been optimized to satisfy both the
amplifier and the ADC. If a higher order
filter is required, it should be located prior
to the final drive amplifier, and more gain
should be used in the amplifier stage to
accommodate for the insertion loss in the
filter. Some filtering is required between
the final amplifier and the ADC. Even a
simple RC low pass filter is better than
driving the ADC directly into the amplifier.
ABOUT THE LTC2195
The LTC2195 is a 16-bit 125Msps, simultaneous sampling, dual ADC operating from
a single 1.8V supply. This circuit can be
easily applied to the 14- or 12-bit members
of the family or to converters that sample
at much lower sample rates. The LTC2195
family also contains dual and single
channel ADCs with parallel outputs. The
LTC2185, 2-channel ADC and the LTC2165
single channel ADC have the same excellent 16-bit performance and low power
as the LTC2195, but with parallel outputs
that can simplify the FPGA code required
to collect data. These flexible ADCs
include the choice of CMOS, DDR CMOS or
DDR LVDS outputs with programmable digital output timing, programmable LVDS output current and optional LVDS output
termination. The LTC2185 and LTC2165
also have the popular randomizer and
alternate bit polarity features that help to
reduce digital feedback. More information about alternate bit polarity mode and
(continued on page 43)
Figure 1. Imaging application
Figure 2. FFT results of circuit in Figure 1
with FS = 125Msps FIN = 1MHz
1.8pF
0
150Ω
150Ω
3V
24.9Ω
V–
0.1µF
–IN
VCM = 0.9V
+IN
–
+OUT
1.8V
22pF
680pF
49.9Ω
AIN+
22pF
24.9Ω
220nH
150Ω
1.8pF
VDD
LTC2195
+
–20
220nH
LTC6406
–OUT
150Ω
680Ω
680Ω
680pF
49.9Ω
AIN–
AMPLITUDE (dB)
SINGLE
ENDED
INPUT
–40
–60
–80
–100
–120
–140
0
20
40
60
80
FREQUENCY (MHz)
100
120
July 2011 : LT Journal of Analog Innovation | 35
Two Monolithic DC/DC Converters Take 3.6V–15V Inputs
Down to 0.6V at High Frequency, Shrinking Battery-Powered
Applications in Everything from Handhelds to Automobiles
Mylien Tran and Theo Phillips
When a relatively high voltage rail (12V) must be stepped down to a relatively low level
(3.3V, 1.8V), the traditional go-to converter is a DC/DC switching controller that drives
external MOSFETs. In many applications, replacing the typical controller-MOSFETdiode combo with a monolithic regulator would save space, design time and cost.
The problem is that 12V rails are too high for many monolithic buck converters, which
usually cannot be used with inputs above 6V. Additionally, switching losses typically
prevent practical operation above ~1MHz, precluding the use of the smallest possible
inductors, and in the end, negating some size advantages of a monolithic regulator.
The LTC3601 and LTC3604 are high
performance monolithic synchronous
step-down regulators capable of supplying up to 1.5A and 2.5A, respectively. They
operate from a wide input voltage range
of 3.6V to 15V—a range encompassing
battery chemistries found in handheld
devices, PCs, and automobiles. Their
unique constant frequency/controlled on
time architecture has a minimum on-time
of 20ns, ideal for high step-down ratio
applications that demand high switching
frequencies and fast transient response
while maintaining high efficiency.
DEFAULT CONFIGURATION WITH
MINIMAL COMPONENTS
To reduce external component count, cost,
and design time, switching frequency and
loop compensation may be set with simple
pin configurations. Figure 1 shows a typical application. To enable 2MHz operation, the oscillator frequency program pin
(RT) is tied to the internal 3.3V regulator
output pin (INTVCC). Default compensation is applied when the compensation
pin (ITH) is tied to INTVCC, producing a
clean load transient response (Figure 2).
36 | July 2011 : LT Journal of Analog Innovation
Operating frequency is programmable
from 800kHz to 4MHz with an external
resistor from RT to ground. For switchingnoise-sensitive applications, the LTC3601
and LTC3604 can be externally synchronized over the same frequency range
regardless of the state of RT. No external
PLL components are required for syncing.
Some applications call for shifting the
switching frequency during operation,
usually to avoid interference with adjacent
radio receivers. Figure 3 shows that the
deviation in output voltage is minimal
even when the sync frequency introduced
at MODE/SYNC is changing rapidly.
Both ICs feature optional Burst Mode®
operation for superior efficiency at low
load currents (Figure 4), or alternatively,
forced continuous mode, which gives
up light load efficiency for minimal
output ripple and constant frequency
operation. Even so, Burst Mode operation ripple is typically only 20mV.
The built-in internal 400µs soft-start timer
prevents current surges at VIN during
start-up. Longer soft-start times can be
implemented by ramping the TRACK pin
or connecting a capacitor from TRACK pin
to ground (tSS = 430,000 × CTRACK/SS). An
open drain PGOOD pin monitors the output
and pulls low if the output voltage is ±8%
from the regulation point. The additional
VIN overvoltage and short-circuit protection make for an all-around robust IC.
Figure 1. A wide input range to 3.3V, 2.5A application
VIN
3.6V TO 15V
22µF
VIN
RUN
BOOST
PGOOD
TRACK/SS
SW
VON
LTC3604
2.2µF
INTVCC
FB
ITH
RT
MODE/SYNC
SGND
PGND
0.1µF
1µH
182k
40.2k
22pF
VOUT
3.3V
2.5A
47µF
design ideas
The LTC3601 and LTC3604 employ a unique
constant frequency/controlled on time architecture
with a minimum on-time of 20ns—ideal for high
step-down ratio applications that demand high
switching frequencies and fast transient response.
100
10
90
SYNC
5V/DIV
EFFICIENCY (%)
SWITCH NODE
10V/DIV
VOUT
20mV/DIV
(AC-COUPLED)
VOUT
100mV/DIV
(AC-COUPLED)
1
70
60
0.1
50
40
30
VIN = 5V 0.01
VIN = 12V
20
fO = 2MHz
Burst Mode OPERATION
10
10µs/DIV
VIN = 12V
VOUT = 3.3V
LOAD STEP = 0A–1A–0A
5µs/DIV
EFFECT OF 800kHz–1MHz FREQUENCY TRANSIENT
VIN = 12V
VOUT = 3.3V
ILOAD = 0A
POWER LOSS (W)
IL
1A/DIV
80
0
0.001
0.01
0.1
1
LOAD CURRENT (A)
10
0.001
Figure 2. Fast transient response of the circuit in
Figure 1
Figure 3. The synchronized switching frequency can
be shifted on the fly, with little change in VOUT.
Figure 4. Burst Mode operation yields high
efficiency at light loads, and low RDS(ON) switches
maintain high efficiency at maximum load.
HIGH FREQUENCY, LOW DUTY
CYCLE, NO PROBLEM
on-time required for this application is
well above the LTC3604’s 20ns minimum.
oscillator (also set at 4MHz) will take over.
Finally, loop compensation is external.
Many microprocessors require low voltage 1.x volt rails, but they also reside in
applications that demand high switching
frequencies to keep passive components
small and avoid RF interference with critical frequency bands. The problem is that
achieving the magic combination of high
a step-down ratio and high switching frequency can be elusive, because it requires
such a short minimum on-time. Figure 5
shows the schematic for the LTC3604 in
a 4 MHz, 12V–1.8V application. The 38ns
The design in Figure 5 takes advantage
of a number of the LTC3604’s features.
Normally the minimum input voltage
is 3.6V, but here the undervoltage lockout is raised to 6V by adding a resistive divider from VIN to RUN. Soft-start
time is increased to 4.3ms by adding
10nF capacitance from TRACK to ground.
The switching frequency is synchronized to 4MHz from an external source.
If that source should fail, the internal
CONCLUSION
Figure 5. The LTC3604 can operate at high frequency (4 MHz) and low duty
cycle, allowing high step-down ratios from a compact footprint
VIN
12V
CIN
22µF
The LTC3601 and LTC3604 are part of a
new generation of monolithic DC/DC converters capable of handling relatively high
input voltages and lower duty cycles. Their
compact size, high performance, and minimal components design make them ideal
for compact applications. Both ICs are
offered in compact, thermally enhanced
3mm × 3mm QFN and MSOP packages. n
VIN
BOOST
0.1µF L1
154k
0.47µH
RUN
SW
VON
40.2k
80.6k
LTC3604
2.2µF
INTVCC
270pF
40.2k
PGOOD
ITH
TRACK
RT
MODE/SYNC
80.6k
COUT
22µF
FB
100k
10k
22pF
VOUT
1.8V
2.5A
SGND
PGND
10nF
EXTERNAL
CLOCK
CIN: TDK C3225X5R1C226M
COUT: TDK C3216X5R0J226M
L1: VISHAY IHLP2020BZERR47M01
July 2011 : LT Journal of Analog Innovation | 37
Simple Circuit Monitors Health of –48V Telecom Lead-Acid
Battery Backup Systems
Jon Munson
Telecommunications infrastructure has always been powered by voltages that
are negative with respect to ground to minimize corrosion in buried cable.
Telcos typically use –48V power, with backup power supplied by large battery
arrays to carry the system through utility outages. These power backup systems
traditionally comprise four 12V lead-acid batteries in series, though newer
lithium cell technology promises to make inroads as systems are updated.
Every battery backup system must be
continually monitored for the charge
state and health of the batteries. In fact,
although stacking batteries is easy, it
can be difficult to build a monitoring
system that can measure and digitize
both the condition of individual cells,
and monitor the high voltage potential
of the combined cells. Enter the LTC6803
multicell battery stack monitor.
The LTC6803 is designed to measure and
digitize individual cell potentials in large
lithium cell stacks with total potentials
100Ω
Figure 1. Isolated lead-acid
telecom battery-stack monitor
100nF
10µH
12V
SLA
10µH
12V
SLA
10µH
12V
SLA
10µH
12V
SLA
–48V
38 | July 2011 : LT Journal of Analog Innovation
beyond 60V (surviving surges to 75V).
Although the LTC6803 is ostensibly
designed to monitor lithium-based battery systems, it can just as well be used to
support traditional –48V lead-acid battery
stacks. Regardless of cell chemistry, all
the measuring potentials are below ground
CSBO
CSBI
CS2B
CSB
µC_CSB
SDOI
SDO
SDO2
SDO
µC_MISO
SCKO
SDI
SDI2
SDI
µC_MOSI
SCK2
SCK
µC_SCK
VCC2
SDOEB
V+
100Ω
PDZ7.5B
4.7µF
100Ω
PDZ7.5B
4.7µF
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
100Ω
PDZ7.5B
4.7µF
10k
10k
10k
SCKI
2.2k
C12
VMODE
S12
GPIO2
AVCC2
C11
GPIO1
I1
ON
S11
WDTB
I2
VL
C10 LTC6803-1
AV– LTM2883-5S DO1
DO2
V–
NC
S10
TOS
C9
VREG
S9
VREF
C8
VTEMP2
S8
VTEMP1
C7
NC
S7
V–
C6
S1
S6
C1
C5
S2
S5
C2
C4
S3
S4
C3
VCC
µC_VCC
1µF
AV+
1µF
1µF
V+
GND2
GND
µC_GND
design ideas
Although the LTC6803 is ostensibly designed to monitor
lithium-based battery systems, it can also be used to
support traditional –48V lead-acid battery stacks.
10µH
C(n + 3)
100Ω
10k
S(n + 3)
7.5V
4.7µF
DISCHARGE SWITCH
(LTC6803 INTERNAL)
VBAT
3
C(n + 2)
VBAT
12V
7.5V
SLA
100Ω
4.7µF
10k
S(n + 2)
DISCHARGE SWITCH
(LTC6803 INTERNAL)
VBAT
3
C(n + 1)
100Ω
10k
S(n + 1)
7.5V
10µH
4.7µF
DISCHARGE SWITCH
(LTC6803 INTERNAL)
Figure 2. Voltage-divider structure for each 12V battery measurement
or possibly floating during maintenance
procedures. Ideally, these batteries should
be measured by circuitry that is independent of the relative grounding between
the batteries and the central-office equipment, thus Galvanic isolation is desirable.
A SIMPLE SOLUTION FOR
LEAD-ACID STACKS
Since the ADC range for an individual
LTC6803 input channel maxes out at 5.37V,
divider networks are used to spread each
12V battery potential across three channels.
Figure 1 shows how. Each battery potential
is acquired by summing triplets of input
channel readings (CN inputs). Here the cellbalancing controls (SN output discharge
switches) are re-purposed to continually
activate voltage dividers using external
10k resistors by setting all DCC configuration bits to 1. In this way, each channel
is converting a 4V nominal potential.
The 4.7µF bypass capacitors accurately
hold the intermediate voltages as small
ADC sampling currents flow, while
100Ω series resistors and 10µ H inductors
provide hot-insert surge limiting. For best
accuracy, the STCVDC conversion command (0x60) should be used so that the
always-enabled discharge switches remain
on throughout the conversion process.
When communication has stopped and
the part times-out, or it is directly commanded to standby mode, the balancing
discharge switches are turned off and the
dividers are effectively disconnected so
that no appreciable battery drain occurs. A
simplified equivalent circuit of a particular divider section is shown in Figure 2.
An LTM2883 SPI data isolator is used
so that the circuit accommodates any
grounding differential with respect
VBAT
3
Cn
to the associated microprocessor circuitry. The LTM2883 also provides
isolated DC power rails that can furnish several hundred mW if needed.
CONCLUSION
The LTC6803 provides a flexible solution
for telecom battery stack measurement,
including stacks using 12V lead-acid batteries. The 12V units are measured by summing the readings of three input channels
that have been hardware configured to
split the 12V into sub-measurements,
thus achieving an effective full-scale
range of 16.1V for each battery. Isolation
of the data acquisition function from
the processor support is important for
elimination of grounding errors and
safety hazards and is readily provided
by the LTM2883 SPI isolator module. n
July 2011 : LT Journal of Analog Innovation | 39
Easy, ±5V Split-Voltage Power Supply for Analog Circuits
Draws Only 720nA at No Load
Jim Drew
Analog circuits often need a split-voltage power supply to achieve a virtual
ground at the output of an amplifier. These split-voltage power supplies are
generally low power supplies supporting tens of milliamps of differential current
loads. Figure 1 shows such a power supply using two LTC3388-3 20V high
efficiency step-down regulators powered from a 6V–12V power source.
The positive voltage rail is created by
configuring one LTC3388-3 in its standard
buck topology while the negative voltage
rail is created with a second LTC3388-3 by
grounding the VOUT connection and using
the GND pin as the negative voltage rail.
The negative voltage rail is connected to
the exposed pad of this LTC3388-3 and
must be isolated from the system ground
plane and have sufficient surface area to
provide adequate cooling of the LTC3388-3.
while maintaining output regulation. They
are capable of supplying up to 50m A of
load current and contain an accurate
undervoltage lockout (UVLO) feature to
maintain a low quiescent current when the
input is below 2.3V. The output voltage
is digitally programmable to four output
regulated voltages along with a PGOOD status pin that indicates that the outputs are
above 92% (typ) of the output setting.
The LTC3388-1 can be digitally set to 1.2V,
1.5V, 1.8V or 2.5V while the LTC3388-3
can be set to 2.8V, 3.0V, 3.3V or 5.0V.
Both devices are available in a 10-lead
MSE or a 3mm × 3mm DFN package.
The LTC3388-1 and LTC3388-3 are high
efficiency step-down regulators that draw
only 720n A (typ) of DC current at no load
Figure 1. Easy split-voltage power supply
1µF
6.3V
2.2µF
25V
4.7µF
6.3V
2.2µF
25V
4.7µF
6.3V
VIN
LTC3388-3
CAP
SW
VIN2
VOUT
100µH
IND-LPS5030
PGOOD
EN
D0, D1
STBY
VOUT
5V
100µF 50mA
6.3V
VIN2
VIN
LTC3388-3
CAP
SW
VIN2
VOUT
EN
PGOOD
STBY
D0, D1
100µH
IND-LPS5030
100µF
6.3V
100
1
0.01
0.0001
0.0001
VIN2
GND
VOUT
–5V
50mA
40 | July 2011 : LT Journal of Analog Innovation
As the output voltage decays due to an
external load, the buck regulator remains
Figure 2. Input current versus output current for the
split voltage power supply of Figure 1 (–5V curve
also applies to –5V supply shown in Figure 3)
GND
1µF
6.3V
Configuring the LTC3388 as a buck
regulator creates a positive voltage by
ramping the inductor current up to
IPEAK (150m A typ) through an internal
PMOS switch and then ramping the current down to 0m A through an internal
NMOS switch. This action charges the
output capacitor to slightly above the
regulation voltage at which time the
buck regulator enters sleep mode.
INPUT CURRENT (mA)
6V TO 12V
OPERATION OF THE
SPLIT-VOLTAGE SUPPLY
VOUT = ±5V
VOUT = –5V
VIN = 12V
1
0.01
OUTPUT CURRENT (mA)
100
design ideas
The LTC3388-1 and LTC3388-3 are high efficiency step-down regulators
that draw only 720nA (typ) of DC current at no load while maintaining
output regulation. They are capable of supplying up to 50mA of load
current and contain an accurate undervoltage lockout (UVLO) feature
to maintain a low quiescent current when the input is below 2.3V.
in sleep mode and an internal sleep
comparator monitors the output voltage.
When the output voltage drops below
the regulation voltage, the buck regulator wakes up and the cycle repeats. This
hysteretic method of providing a regulated output reduces losses associated
with MOSFET switching and maintains an
output voltage at light loads. The buck
regulator is able to support 50m A of average load current when it is switching.
A negative output voltage rail is created by grounding the VOUT node of the
buck regulator. This sets the ground
reference connection of the LTC3388
as a negative voltage rail. The voltage
from the VIN pin to the negative voltage rail is the sum of the input voltage
plus the magnitude of negative voltage
rail. This limits the source voltage to
20V (the LTC3388’s VIN(MAX)) minus the
magnitude of the negative rail voltage.
The inductor current is ramped up to
IPEAK through the internal PMOS switch
as in the buck regulator configuration
and then down to zero through the
NMOS switch, charging the output capacitor to a negative voltage. This switching action is that of an inverting critical
NEGATIVE VOLTAGE SUPPLY
conduction synchronous buck-boost
converter. The maximum output current
of this configuration is limited by the
peak current of the inductor, the input
voltage and the magnitude of the output
voltage. The expression below estimates
the maximum output current available.
IOUT =
Figure 3 shows the buck-boost configuration creating a negative output voltage
rail. In this configuration the input voltage
needs only be above the UVLO voltage
of 2.5V (typ) to start the regulator. The
–5V curve in Figure 2 applies here with
a 12V input, as in the previous circuit.
IPEAK
VIN
•
–
2
VIN + V OUT
CONCLUSION
An easy-to-implement split-voltage power
supply using the LTC3388 yields a low
quiescent current, high efficiency solution
for powering low current analog circuits
that need a virtual ground output. The
output voltage of each device is digitally
programmable to four output voltages
from 1.2V to 5.0V and will support a
load current up to 50m A. Each regulator requires only four external capacitors and one inductor, covering minimal
board real estate. A PGOOD status pin is
provided to indicate when the output
is within regulation. The LTC3388-1 and
the LTC3388-3 are available in a 10-lead
MSE or a 3mm × 3mm DFN package. n
In a split voltage power supply application, the analog circuit is connected
between the positive voltage rail and the
negative voltage rail. This results in the
load current of both regulators to be
equal in magnitude. Figure 2 is a plot of
the input current versus the output current for the circuit in Figure 1. At very
low load currents, <10µ A, the effect of
the input quiescent current can be seen
as a positive offset in the input current.
For higher load currents, >100µ A, this
effect is minimal and the input current
is approximately equal to the output
current. The expression for the input
current may be approximated as:
+
IIN =
–
IOUT V OUT + V OUT
•
+ 2 • IQ
η
VIN
h = EFFICIENCY
3V TO 15V
1µF
6.3V
Figure 3. Negative voltage power supply
2.2µF
25V
4.7µF
6.3V
VIN
LTC3388-3
CAP
SW
VIN2
VOUT
100µH
IND-LPS5030
100µF
6.3V
PGOOD
EN
D0, D1
STBY
VIN2
GND
VOUT
–5V
50mA
July 2011 : LT Journal of Analog Innovation | 41
Product Briefs
RF-TO-DIGITAL µMODULE
RECEIVERS REDUCE SIZE,
COST AND TIME-TO-MARKET FOR
BASE STATION DESIGNS
The LTM®9004 and LTM9005 are two
breakthrough RF-to-digital µModule
receivers that integrate the key components for 3G and 4G base station receivers
(WCDMA, TD-SCDMA, LTE, etc.) and smart
antenna WiMAX base stations. The integrated µModule receivers offer a dramatic
reduction in board space, integrating the
RF mixer/demodulator, amplifiers, passive
filtering and 14-bit, 125Msps ADCs in one
conveniently small package. The LTM9004
implements a direct conversion architecture with an I/Q demodulator, lowpass
filter and a dual ADC. The LTM9005 implements an IF-sampling architecture with a
downconverting mixer, SAW filter and a
single ADC. This high level of integration
enables smaller boards or higher channel
count systems, alleviating issues related
to separation and routing of signals,
while providing a significant reduction
in design and debug time. These receivers harness years of signal chain design
experience and offer it in an easy-to-use
22mm × 15mm µModule package.
Cellular service providers are under
intense pressure to reduce capital
(CAPEX) and operating (OPEX) expenses.
Supporting trends include the need for
smaller, lighter, lower power base stations
such as remote radio heads (RRH) that
can be mounted on the tower with the
antenna; and high density, high channelcount macrocell base stations with
higher efficiency; and the use of small,
42 | July 2011 : LT Journal of Analog Innovation
digital repeaters. These µModule receivers address these trends directly. At only
25% of the board space area of discrete
designs, the LTM9004 and LTM9005 save
critical space and also reduce the time and
effort required for optimizing the design
and layout of dozens of high frequency
components. This leads to lower development costs, fewer components to source
and stock, and faster time to market.
Two receiver architectures dominate base
station designs: direct conversion and
IF-sampling. Direct conversion demodulates the RF signal and downconverts to
DC (0MHz in the frequency domain). This
simplifies the filter, allowing lowpass
filters with a 10MHz cutoff (20MHz signal
bandwidth). The LTM9004 implements
this architecture. Other filter options are
available for different signal bandwidths.
IF-sampling downconverts to an intermediate frequency (IF), 140MHz in this
case, and the signal is demodulated in the
digital domain. The 20MHz signal filtering is done with a surface acoustical wave
(SAW) filter integrated in the LTM9005.
Other filter bandwidths are available.
The LTM9004 and LTM9005 are packaged in a space-saving 22mm × 15mm
LGA package, utilizing a multilayer substrate that shields sensitive analog lines
from the digital traces to minimize digital
feedback. Supply and reference bypass
capacitance is placed inside the µModule
package, tightly coupled to the die,
providing a space, cost and performance
advantage over traditional packaging.
µMODULE BATTERY CHARGERS
WITH ACTIVE CURRENT LIMIT
DELIVER 2A FROM UP TO 32V IN
The LTM8061 and LTM8062 are the first
devices in a new family of complete
system-in-a-package µModule chargers,
supporting an output charge current up to
2A. Both parts provide a complete, efficient
1MHz switching step-down charger solution with just one input capacitor. The
LTM8061 features active input current
management to protect against supply
rail droop, while providing maximum
charge current to the load. The LTM8062
actively manages the output charge current to maximize the power sourced from
a solar cell following maximum peak
power tracking (MPPT) principles. The
LTM8061 and LTM8062 operate from an
input voltage range of 4.95V to 32V with
support for preconditioning, constantcurrent and constant voltage mode operation. A 0.5% and 0.75% accurate float
voltage, respectively, ensures maximum
energy storage at charge termination set
by a minimum current threshold detection or adjustable internal timeout.
The LTM8061 is specifically targeted for
charging Li-ion or Li-polymer batteries
with float voltages of 4.1V, 4.2V, 8.2V and
8.4V. An externally adjustable float voltage
allows the LTM8062 to support charging
of single-and multicell Li-ion, Li-polymer,
lithium iron phosphate (LiFePO4) and
sealed lead acid (SLA) batteries up to 14.4V.
To maintain the battery at full charge,
the LTM8061 and LTM8062 automatically
initiate a recharge cycle once the battery
voltage drops to 2.5% below the float
product briefs
voltage. Safety features include bad-battery detection and NTC resistor input with
fault indicator suitable for use with a LED.
An internal input reverse voltage blocking diode is available to prevent leakage
current from the battery when the power
source is not present. The LTM8061 and
LTM8062 are available in an RoHS compliant 9mm × 15mm × 4.32mm LGA package.
60V BATTERY CHARGING
CONTROLLER AND POWER
MANAGER
The LTC4000 is a high voltage controller
and power manager that converts virtually
any externally compensated DC/DC power
supply into a full-featured battery charger.
The LTC4000 is capable of driving typical DC/DC converter topologies, including
buck, boost, buck-boost, SEPIC and flyback.
The device offers precision input and
charge current regulation and operates
across a wide 3V to 60V input and output
(LTC2195, continued from page 43)
digital feedback can be found in the video
“Reduce Digital Feedback in High Speed
Data Conversion Systems - LTC2261”
at www.linear.com. There are also pincompatible 14- and 12-bit versions of the
dual LTC2185 that also provide excellent
performance, and extremely low power
consumption for high speed ADCs. The
complete family can be seen in Table 1.
(LT3694, continued from page 33)
allowable step-down range due to the
minimum on and off time constraints.
This brings us to the difference between
the LT3694 and the LT3694-1. The LT3694
switching frequency can be synchronized to an external clock by connecting it to the SYNC pin. The resistor on
the RT pin should be set provide a free
running frequency 20% below the sync
frequency. The LT3694-1 replaces the
SYNC pin with a CLKOUT pin, allowing
the LT3694-1 to be used as the master
voltage range—compatible with a variety
of different input voltage sources, battery
stacks and chemistries. Typical applications include high power battery charger systems, high performance portable
instruments, battery back-up systems,
industrial battery-equipped devices and
notebook/sub-notebook computers.
The LTC4000 features an intelligent
PowerPath™ topology that preferentially
provides power to the system load when
input power is limited. The LTC4000
controls external PFETs to provide low
loss reverse current protection, efficient
charging and discharging of the battery
and instant-on operation to ensure that
system power is available at plug-in even
with a dead or deeply discharged battery. External sense resistors and precision sensing enable accurate currents at
high efficiency, allowing the LTC4000 to
CONCLUSION
The LTC2195 is the perfect ADC for powerconscious, high resolution sensor applications, while the LTC6406 is a good match
as a driver amplifier—it does not compromise the performance of the LTC2195 and
its power requirements are also low. Data
sheet performance of the ADC can be easily
achieved by using a relatively low order
clock for synchronizing other switching regulators. The CLKOUT produces a
clock signal running at ~50% duty cycle.
TRIPLE-OUTPUT CONVERTER WITH
VOLTAGE TRACKING
Figure 1 shows a wide input range,
6.3V to 36V, converter that generates three
outputs: 5V, 3.3V and 2.5V. The outputs
track ratiometrically, set via a common TRK/SS connection. Figure 2 shows
the start-up waveforms of the three
outputs along with the enable signal.
Figure 3 shows the switching regulator
efficiency at different input voltages.
work with converters that span the power
range from milliwatts to kilowatts.
The LTC4000’s full-featured controller
charges a variety of battery chemistries
including lithium-ion/polymer/phosphate,
sealed lead acid (SLA), and nickel-based.
The device also provides charge status
indicators through its FLT and CHRG pins.
Other features of the battery charger
include: ±0.2% programmable float
voltage, selectable timer or C/X current
termination, temperature-qualified charging using an NTC thermistor, automatic
recharge, C/10 trickle charge for deeply
discharged cells and bad battery detection.
The LTC4000 is housed in a low profile
(0.75mm) 28-pin 4mm × 5mm QFN package and a 28-lead SSOP package. n
filter to reduce the wideband noise of
the amplifier. The pairing of the LTC2195
and the LTC6406 is the ideal combination
for any portable image sensor application, combining excellent performance
with low power consumption. For more
information about the LTC2195 family
and the LTC6406 visit www.linear.com. n
CONCLUSION
The LT3694/LT3694-1 offers robust,
compact power supply solutions by
squeezing three regulators into a tiny
4mm × 5mm QFN or a 20-lead TSSOP package. One regulator is an efficient switching regulator and the other two are
low noise, low dropout linear regulators. Just a few small external components are needed to create an extremely
compact triple output solution. n
July 2011 : LT Journal of Analog Innovation | 43
highlights from circuits.linear.com
ADJUSTABLE CURRENT SINK
The LT3015 is a low noise, low dropout, negative linear regulator with
fast transient response. The device supplies up to 1.5A of output
current at a typical dropout voltage of 310mV. With minimal external
circuitry, the LT3015 can be configured as an adjustable current sink.
www.linear.com/3015
R1
2k
R8
100k
GND
C1
10µF LT1004-1.2
R2
82.5k
C2
10µF
LT3015
R3
2k
R4
0.01Ω
VIN < –2.3V
SHDN
ADJ
IN
OUT
R6
2.2k
R5
2.2k
C3
1µF
2
3
–
RLOAD
R7
475Ω
8
1/2
LT1350
+
1
4
C4
3.3µF
NOTE: ADJUST R3 FOR 0 TO –1.5A CONSTANT CURRENT
DIFFERENCE AMPLIFIER
The LT5400 is a quad resistor network with excellent matching specifications over the
entire temperature range. These resistor networks provide precise ratiometric stability
required in highly accurate difference amplifiers, voltage references and bridge circuits.
www.linear.com/5400
LT5400
1
INPUTS
–
2
+
3
R1
8
R2
7
R3
6
R4
4
5
–
+
THIS CIRCUIT CAN BE IMPLEMENTED USING ANY LT5400 RESISTOR OPTION
EN55022B COMPLIANT 36VIN, 15VOUT, 8A,
DC/DC µMODULE REGULATOR
VIN
The LTM4613 is a complete, ultralow noise, 8A switch mode 22V TO 36V
DC/DC power supply. Included in the package are the
switching controller, power FETs, inductor and all support
components. Only bulk input and output capacitors are
needed to finis
h the design. The onboard input filter
and noise cancellation circuits achieve low noise coupling,
effectively reducing the electromagnetic interference (EMI).
Furthermore, the part can be synchronized with an external clock to reduce undesirable frequency harmonics.
www.linear.com/4613
PULL-UP SUPPLY ≤ 5V
CLOCK SYNC
R4
51k
R3
51k
ON/OFF
CIN
10µF
50V CERAMIC
C4
0.1µF
C1 TO C3
10µF
50V
×3
VD
VIN PLLIN
VOUT
PGOOD
RUN LTM4613
VFB
COMP
INTVCC
FCB
DRVCC
MARG0
fSET
MARG1
TRACK/SS
MPGM
SGND PGND
C5
22pF
RFB
5.23k
COUT1
22µF
16V
VOUT
12V
COUT2 8A
180µF
16V
+
MARGIN
CONTROL
R1
392k
5% MARGIN
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, LTspice, PolyPhase, TimerBlox and µModule are registered trademarks, and LTPoE++, PowerPath and Virtual Remote Sense are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
© 2011 Linear Technology Corporation/Printed in U.S.A./51.5K
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