A3250 and A3251 Field-Programmable, Chopper-Stabilized Unipolar Hall-Effect Switches Discontinued Product This device is no longer in production. The device should not be purchased for new design applications. Samples are no longer available. Date of status change: October 31, 2011 Recommended Substitutions: For existing customer transition, and for new customers or new applications, contact Allegro Sales. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A3250 and A3251 Field-Programmable, Chopper-Stabilized Unipolar Hall-Effect Switches Features and Benefits Description ▪ Chopper stabilization for stable switchpoints throughout operating temperature range ▪ Externally programmable operate point (through VCC pin) ▪ On-board voltage regulator for 4.2 V to 24 V operation ▪ On-chip protection against: ▫ Supply transients ▫ Output short-circuits ▫ Reverse-battery condition The A3250 and A3251 are field-programmable, chopperstabilized, unipolar Hall-effect switches designed for use in high-temperature applications. These devices use a chopper-stabilization technique to eliminate offset inherent in single-element devices. Package: 3-pin SOT89 (suffix LT) and 3-pin SIP (suffix UA) The A3250 and A3251 are externally programmable devices. The devices have a wide range of programmability of the magnetic operate point (BOP) while the hysteresis remains fixed. This advanced feature allows for optimization of the device switchpoint and can drastically reduce the effects of variations found in a production environment, such as magnet and device placement tolerances. These devices provide on-chip transient protection. A Zener clamp on the power supply protects against overvoltage conditions on the supply line. These devices also include short-circuit protection on the output. The output of the A3250 switches LOW when subjected to a south-polarity magnetic field with a flux density that exceeds the threshold for BOP , and switches HIGH when the field drops below the magnetic release point, BRP . The output of the A3251 has the opposite polarity, switching HIGH in a south-polarity magnetic field that BOP , and switching LOW when the field drops below BRP . Continued on the next page… Not to scale Functional Block Diagram VCC Program/Lock Programming Logic Regulator Amp Sample and Hold Dynamic Offset Cancellation Offset Adjust VOUT Current Limit Low-Pass Filter GND 3250-DS Rev. 11 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Description (continued) The other differences in the devices are the power-on state. The A3250 powers-on in the HIGH state, while the A3251 powers-on in the LOW state. Three package styles provide a magnetically optimized package for most applications. Type LT is a miniature SOT89/TO-243AA surface mount package that is thermally enhanced with an exposed ground tab, and type UA is a three-lead ultramini SIP for through-hole mounting. The packages are lead (Pb) free, with 100% matte tin plated leadframes (suffix, –T). Selection Guide A3250LLTTR-T VOUT Packing1 Package TA (ºC) Power-On Running2 7-in. reel, 1000 pieces/reel Surface mount –40 to 150 High Low Part Number 1Contact Allegro for additional packing options. 2In south polarity magnetic field of sufficient strength. Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Supply Voltage VCC 26.5 V Reverse Supply Voltage VRCC –18 V VZ 30 V IOUT 20 mA Zener Overvoltage Output Current Magnetic Flux Density B Unlimited G Range E –40 to 85 ºC Range L Operating Ambient Temperature TA –40 to 150 ºC Maximum Junction Temperature TJ(max) 165 ºC Tstg –65 to 170 ºC Storage Temperature Pin-out Diagrams 1 2 Terminal List Number Name Function 1 VCC Connects power supply to chip 2 GND Ground 3 VOUT Device output 3 LT 1 2 3 UA Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches OPERATING CHARACTERISTICS valid over operating TA and VCC, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Units 4.2 – 24 V ELECTRICAL CHARACTERISTICS Supply Voltage1 Output Saturation Voltage Output Leakage Current VCC Running mode VOUT(sat) IOUT = 20 mA; Switch state = ON – 175 400 mV IOFF VOUT = 24 V; Switch state = OFF – – 10 μA A3250; B < BRP; VOUT = HIGH – 4.0 7.0 mA A3251; B > BOP; VOUT = HIGH – 4.0 7.0 mA A3250; B > BOP; VOUT = LOW – 6.0 10.0 mA A3251; B < BRP; VOUT = LOW – 6.0 10.0 mA ICC(off) Supply Current ICC(on) Output Rise Time tr RLOAD = 820 Ω, CLOAD = 10 pF – – 5.0 μs Output Fall Time tf RLOAD = 820 Ω, CLOAD = 10 pF – – 5.0 μs Chopping Frequency fC – 340 – kHz Power-Up Time ton VOUT = HIGH – 20 50 μs Short-circuit protection 60 90 120 mA A3250; B < BRP, t > ton – HIGH – mV A3251; B < BRP, t > ton – LOW – mV –20 13 50 G BOP ≤ 500 gauss –35 – 35 G Package TA range = J 5.0 18 35 G Package TA range = L 5.0 13 35 G 50 – ≥350 G Switchpoint set – 6 – Bit Programming lock – 1 – Bit – 7.0 – G 28 – – V VCC = 28 V – – 13 mA VRCC = –18 V, TJ < TJ(max) – – –5.0 mA Output Current Limit1,2 Power-On State IOUT(lim) POS MAGNETIC CHARACTERISTICS Initial Operate Point BOP Temperature Drift of BOP ΔBOP Hysteresis (BOP – BRP) Bhys PROGRAMMING CHARACTERISTICS Programmable BOP Values3 Number of Programming Bits Resolution BOP(prog) – BRES TRANSIENT PROTECTION CHARACTERISTICS Supply Zener Voltage VZ Supply Zener Current IZ Reverse Battery Current IRCC 1 Do not exceed TJ(max): Additional information on power derating is provided in the applications section. Short-circuit protection is not intended for continuous operation; permanent damage may result. Device can be used below 50 G but is not guaranteed to be a unipolar switch. It is the responsibility of the programmer to verify that the desired switchpoint has been achieved. 2 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Typical Characterization Data All data are taken with A3250 devices, the average of 3 lots, 30 pieces per lot Average BRP vs. TA Program Code: 1, VCC = 12 V 30 10 25 5 Average BRP (G) Average BOP (G) Average BOP vs. TA Program Code: 1, VCC = 12 V 20 15 10 5 0 -5 -50 -20 10 40 70 TA (°C) 100 130 0 -5 -10 -15 -20 -50 160 -20 Average BOP vs. TA Program Code: 8, VCC = 12 V 40 70 TA (°C) 100 130 160 130 160 130 160 Average BRP vs. TA Program Code: 8, VCC = 12 V 60 75 70 Average BRP (G) Average BOP (G) 10 65 60 55 50 50 40 30 45 40 -50 -20 10 40 70 TA (°C) 100 130 20 -50 160 -20 130 110 125 105 120 115 110 105 100 -50 -20 10 40 70 TA (°C) 100 40 70 TA (°C) 100 Average BRP vs. TA Program Code: 16, VCC = 12 V Average BRP (G) Average BOP (G) Average BOP vs. TA Program Code: 16, VCC = 12 V 10 130 160 100 95 90 85 80 -50 -20 10 40 70 TA (°C) 100 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Typical Characterization Data All data are taken with A3250 devices, the average of 3 lots, 30 pieces per lot Average B hys vs. Temperature Program Code: 16, VCC = 12 V 35 35 30 30 Average BHYS (G) Average BHYS (G) Average B hys vs. Temperature Program Code: 1, VCC = 12 V 25 20 15 10 5 25 20 15 10 5 0 0 -50 -20 10 40 70 100 130 160 -50 -20 10 TA (°C) Average B hys vs. Temperature Program Code: 8, VCC = 12 V 40 70 TA (°C) 100 130 160 Average BOP vs. Temperature -40°C to 25°C and 150°C to 25°C 30 Average BOP (G) Average BHYS (G) 35 30 25 20 15 10 20 10 0 Code 1 -10 5 Code 8 -20 0 -50 -20 10 40 TA (°C) 70 100 130 160 -30 Code 16 -40°C to 25°C 150°C to 25°C TA (°C) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Typical Characterization Data All data are taken with A3250 devices, the average of 3 lots, 30 pieces per lot Average ICC(on) vs. Temperature Average ICC(off) vs. Temperature 10 10 ICC(off) @ 3.8 V ICC(off) (mA) 8 6 4 ICC(on) @ 3.8 V 2 ICC(on) @ 12.0 V ICC(off) @ 12.0 V ICC(off) @ 26.5 V 6 4 2 ICC(on) @ 26.5 V 0 -50 -20 10 40 70 100 130 0 -50 160 -20 10 40 70 100 130 160 TA (°C) TA (°C) Average VOUT(SAT) vs. Temperature VCC = 3.8 V, Iout = 20 mA 280 VOUT(SAT) (mV) ICC(on) (mA) 8 260 240 220 200 180 160 140 -50 -20 10 40 70 100 130 160 TA (°C) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol RθJA Package Thermal Resistance Test Conditions Value Units Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W Package LT, 1-layer PCB with copper limited to solder pads 180 ºC/W Package LT, 2-layer PCB with 0.94 in2 copper each side 78 ºC/W Power Dissipation Power Dissipation, PD (m W) VCC(max) 1-layer PCB, Package LT (RθJA = 180 ºC/W) 1-layer PCB, Package UA (RθJA = 165 ºC/W) 2-layer PCB, Package LT (RθJA = 78 ºC/W) VCC(min) 40 60 80 100 120 140 160 180 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 2 (R -lay θJ A er = PC 78 B ºC , Pa /W ck ) ag 1-la (R yer P CB θJA = 165 , Pac 1-la ºC/ kage y e W) rP (R UA CB θJA = , 180 Pac ºC/ kage W) LT 20 40 TA (ºC) 60 e LT 80 100 120 Temperature (°C) 140 160 180 Hysteresis Curves A3251 A3250 V+ Hysteresis of ΔVOUT Switching Due to ΔB V+ Hysteresis of ΔVOUT Switching Due to ΔB VOUT(off) Switch to High VOUT Switch to Low Switch to Low Switch to High VOUT(off) VOUT(on)(sat) BRP BOP BHYS B+ BOP VOUT(on)(sat) BRP 20 VOUT Maximum Allowable VCC (V) Power Derating Curve 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 B+ BHYS Output voltage in relation to impinging magnetic flux density in a south polarity magnetic field of sufficient strength. Transition through BOP must precede transition through BRP. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Functional Description Chopper-Stabilized Technique The Hall circuit is based on a Hall element, a small sheet of semiconductor material in which a constant bias current flows when a constant voltage source is applied. The output takes the form of a voltage measured across the width of the Hall element, and has negligible value in the absence of a magnetic field. When a magnetic field is applied with flux lines at right angles to the current in the Hall element, a small signal voltage directly proportional to the strength of the magnetic field occurs at the output of the Hall element. This small signal voltage is disproportionally small relative to the offset produced at the input of the device. This makes it very difficult to process the signal and maintain an accurate, reliable output over the specified temperature and voltage range. Therefore, it is important to reduce any distortion of the signal that could be amplified when the signal is processed. Chopper stabilization is a unique approach used to minimize input offset on the Hall IC. This technique removes a key source of output drift due to temperature and mechanical stress, and produces a 3X reduction in offset in comparison to other, conventional methods. This offset reduction chopping technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetically-induced signal in the frequency domain. The offset (and any low-frequency noise) component of the signal can be seen as signal distortion added after the signal modulation process has taken place. Therefore, the DC offset is not modulated and remains a low-frequency component. Consequently, the signal demodulation process acts as a modulation process for the offset, causing the magneticallyinduced signal to recover its original spectrum at baseband while the DC offset becomes a high-frequency signal. Then, the signal passes using a low-pass filter, while the modulated DC offset is suppressed. The advantage of this approach is significant offset reduction, which desensitizes the Hall IC against the effects of temperature and mechanical stress. The disadvantage is that this technique features a demodulator that uses a sample-and-hold block to store and recover the signal. This sampling process can slightly degrade the SNR (signal-to-noise ratio) by producing replicas of the noise spectrum at the baseband. This degradation is a function of the ratio between the white noise spectrum and the sampling frequency. The effect of the degradation of the SNR is higher jitter, also known as signal repeatability. However, the jitter in a continuous-time device can be 5X that of the A3250/A3251. Amp Sample and Hold / LPF Regulator Chopper stabilization circuit (dynamic quadrature offset cancellation) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches V+ Programming Protocol VPH The operate switchpoint, BOP , can be field-programmed. To do so, a coded series of voltage pulses through the VCC pin is used to set bitfields in onboard registers. The effect on the device output can be monitored, and the registers can be cleared and set repeatedly until the required BOP is achieved. To make the setting permanent, bitfield-level solid state fuses are blown, and finally, a device-level fuse is blown, blocking any further coding. It is not necessary to program the release switchpoint, BRP , because the difference between BOP and BRP , referred to as the hysteresis, BHYS , is fixed. The range of values between BOP(min) and BOP(max) is scaled to 64 increments. The actual change in magnetic flux (G) represented by each increment is indicated by BRES (see the Operating Characteristics table; however, testing is the only method for verifying the resulting BOP). For programming, the 64 increments are individually identified using 6 data bits, which are physically represented by 6 bitfields in the onboard registers. By setting these bitfields, the corresponding calibration value is programmed into the device. Three voltage levels are used in programming the device: a low voltage, VPL , a minimum required to sustain register settings; a mid-level voltage, VPM , used to increment the address counter in the device; and a high voltage, VPH , used to separate sets of VPM pulses (when short in duration) and to blow fuses (when long in duration). A fourth voltage level, essentially 0 V, is used to clear the registers between pulse sequences. The pulse values are shown in the Programming Protocol Characteristics table and in figure 1. VPM VPL Td(P) 0 Td(0) Td(1) t Figure 1. Pulse amplitudes and durations Additional information on device programming and programming products is available on www. allegromicro.com. Programming hardware is available for purchase, and programming software is available free of charge. Code Programming. Each bitfield must be individually set. To do so, a pulse sequence must be transmitted for each bitfield that is being set to 1. If more than one bitfield is being set to 1, all pulse sequences must be sent, one after the other, without allowing VCC to fall to zero (which clears the registers). The same pulse sequence is used to provisionally set bitfields as is used to permanently set bitfield-level fuses. The only difference is that when provisionally setting bitfields, no fuse-blowing pulse is sent at the end of the pulse sequence. PROGRAMMING PROTOCOL CHARACTERISTICS, TA = 25ºC, unless otherwise noted Characteristic Symbol Min. Typ. Max. Units 4.5 5.0 5.5 V VPM 10 11 12 V VPH 23 25 26 V VPL Programming Voltage1 Programming Current2 Pulse Width Test Conditions Minimum voltage range during programming IPP Maximum supply current during programming – 500 – mA td(0) OFF time between programming bits 20 – – μs td(1) Pulse duration (ON time) for enable, address, fuse blowing or lock bits 20 – – μs td(P) Pulse duration (ON time) for fuse blowing 100 300 – μs Pulse Rise Time tr VPL to VPM; VPL to VPH 11 – – μs Pulse Fall Time tf VPM to VPL; VPH to VPL 5 – – μs 1Programming voltages are measured at the VCC pin. capacitor with a minimum capacitance of 0.1 μF must be connected from VCC to the GND pin of the device in order to provide the current necessary to blow the fuse. 2A bypass Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches The pulse sequences consist of the following groups of pulses: 1. An enable sequence. 2. A bitfield address sequence. 3. When permanently setting the bitfield, a long VPH fuse-blowing pulse. (Note: Blown bit fuses cannot be reset.) 4. When permanently setting the bitfield, the level of VCC must be allowed to drop to zero between each pulse sequence, in order to clear all registers. However, when provisionally setting bitfields, VCC must be maintained at VPL between pulse sequences, in order to maintain the prior bitfield settings while preparing to set additional bitfields. Bitfields that are not set are evaluated as zeros. The bitfield-level fuses for 0 value bitfields are never blown. This prevents inad- vertently setting the bitfield to 1. Instead, blowing the devicelevel fuse protects the 0 bitfields from being accidentally set in the future. When provisionally trying the calibration value, one pulse sequence is used, using decimal values. The sequence for setting the value 510 is shown in figure 2. When permanently setting values, the bitfields must be set individually, and 510 must be programmed as binary 101. Bit 3 is set to 1 (0001002, which is 410), then bit 1 is set to 1 (0000012, which is 110). Bit 2 is ignored, and so remains 0.Two pulse sequences for permanently setting the calibration value 5 are shown in figure 3. The final VPH pulse is maintained for a longer period, enough to blow the corresponding bitfield-level fuse. V+ VPH VPM VPL 0 Enable Address Try 510 Optional Monitoring Clear t Figure 2. Pulse sequence to provisionally try calibration value 5. V+ VPH VPM VPL Address 0 Enable Address Encode 001002 (410) Blow Enable Blow Encode 000012 (110) Figure 3. Pulse sequence to permanently encode calibration value 5 (101 binary, or bitfield address 3 and bitfield address 1). t 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches V+ VPH Enabling Addressing Mode. The first segment of code is a keying sequence used to enable the bitfield addressing mode. As shown in figure 4, this segment consists of one short VPH pulse, seven or more VPM pulses, and one short VPH pulse, with no supply interruptions. This sequence is designed to prevent the device from being programmed accidentally, such as by noise on the supply line. VPM VPL Minimum 7 pulses 0 t Figure 4. Addressing mode enable pulse sequence V+ Address Selection. After addressing mode is enabled, the target bitfield address, is indicated by a series of VPM pulses, as shown in figure 3. When provisionally trying a value, this sequence is followed by a short VPH pulse, which serves to delimit the address and set the corresponding bitfield. When permanently setting a bitfield, the VPH pulse is continued for a longer period of time, suffienct to not only set the bitfield to 1, but also to blow the bitfield fuse. VPH Address 1 Address 2 Address n ( ≤ 63) VPM VPL 0 t Figure 5. Pulse sequence to select addresses V+ Falling edge of final BOP address digit VPH Lock Bit Programming. After the desired BOP calibration value is programmed, and all of the corresponding bitfield-level fuses are blown, the device-level fuse should be blown. To do so, the lock bit (bitfield address 65) should be encoded as 1 and have its fuse blown. This is done in the same manner as permanently setting the other bitfields, as shown in figure 6. VPM VPL 7 pulses 65 pulses 0 Enable Address Blow Encode Lock Bit Figure 6. Pulse sequence to encode lock bit t 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Application Information For additional general application information, visit the Allegro MicroSystems Web site at www. allegromicro.com. Typical Application Circuit RS 100 Ω It is strongly recommended that an external ceramic bypass capacitor, CBYP, in the range of 0.01 μF to 0.1 μF be connected between the VCC pin and the supply and GND pin to reduce both external noise and noise generated by the chopper-stabilization technique. (The diagram at the right shows CBYP at 0.1 μF.) CBYP should be installed so that the traces that connect it to the A3250/A3251 are no greater than 5 mm in length. (For programming the device, the capacitor may be further away from the device, including mounting on the board used for programming the device.) The series resistor RS, in combination with CBYP creates a filter for EMI pulses. (Additional information on EMC is provided on the Allegro MicroSystems Web site.) RS will have a drop of approximately 800 mV. This must be taken into consideration when determining the minimum VCC requirement for the A3250/A3251. The pull-up resistor, RL, should be chosen to limit the current through the output transistor; do not exceed the maximum continuous output current of the device. 5V A VSupply CBYP 0.1 μF VCC A3250/A3251 RL 1.2 kΩ VOUT GND A A Maximum separation 5 mm from CBYP to device Typical application circuit 12 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RJC, is relatively small component of RJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN (1) T = PD × RJA (2) TJ = TA + ΔT Example: Reliability for VCC at TA = 150°C, package UA, using minimum-K PCB. Observe the worst-case ratings for the device, specifically: RJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 10 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 10 mA = 9 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. (3) For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 4 mA, and RJA = 165 °C/W, then: PD = VCC × ICC = 12 V × 4 mA = 48 mW T = PD × RJA = 48 mW × 165 °C/W = 8°C TJ = TA + T = 25°C + 8°C = 33°C A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RJA and TA. 13 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Package LT, 3-Pin SOT89 4.50±0.10 +0.10 1.73 –0.11 2.50 2.00 A 2.24 0.80 1.14 +0.15 4.10 –0.16 +0.15 2.45 –0.16 +0.09 2.20 –0.07 2.60 +0.20 1.00 –0.11 1 2 3 4.60 Parting Line 1.00 +0.04 0.40 –0.05 0.70 1.50±0.10 B 1.50 PCB Layout Reference View Basic pads for low-stress, not self-aligning Additional pad for low-stress, self-aligning Additional area for IPC reference layout 0.42±0.06 0.50±0.06 2X 1.50 BSC For Reference Only; not for tooling use (reference JEDEC. TO-243AA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Active Area Depth, 0.78 mm REF B C Reference land pattern layout (reference IPC7351 SOT89N); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branding scale and appearance at supplier discretion D Hall element, not to scale NNT 1 C Standard Branding Reference View = Supplier emblem N = Last two digits of device part number T = Temperature code 14 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3250 and A3251 Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches Package UA, 3-Pin SIP +0.08 4.09 –0.05 45° B C E 2.06 1.52 ±0.05 1.45 E Mold Ejector Pin Indent +0.08 3.02 –0.05 E Branded Face 45° 1 2.16 MAX D Standard Branding Reference View = Supplier emblem N = Last two digits of device part number T = Temperature code 0.79 REF A 0.51 REF NNT 1 2 3 +0.03 0.41 –0.06 15.75 ±0.51 For Reference Only; not for tooling use (reference DWG-9049) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Dambar removal protrusion (6X) B Gate burr area C Active Area Depth, 0.50 mm REF +0.05 0.43 –0.07 D Branding scale and appearance at supplier discretion E Hall element, not to scale 1.27 NOM Copyright ©2004-2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 15 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com