A3936 DMOS Three-Phase PWM Motor Driver Features and Benefits Description ▪ ±3 A, 50 V continuous output rating ▪ Low rDS(on) outputs (typically 500 mΩ source, 315 mΩ sink) ▪ Configurable mixed-, fast- and slow-current-decay modes ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO and thermal shutdown circuitry ▪ Crossover-current protection ▪ Tachometer output for external speed control loop Designed for pulse-width-modulated (PWM) current control of three-phase brushless DC motors, the A3936 is capable of peak output currents to ±3 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be configured to operate in slow-, fast- and mixed-decay modes. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover current protection. Special power-up sequencing is not required. Package: 44-pin PLCC (suffix ED) The A3936 is supplied in a 44-pin plastic PLCC with internally fused leads (three on each side) for enhanced heat dissipation. These leads are at ground potential and need no electrical isolation. This device is lead (Pb) free version, with 100% matte tin leadframe plating. Not to scale Typical Application VREG CP1 OSC Regulator VDD TACH HBIAS SLEEP DIR EXT MODE BRAKE SR Osc TSD UVLO [VDD VREG VCP] Charge Pump 3X Half Bridge VBB1 OUTA OUTB M OUTC Control Logic and Gate Drive Fixed Off-Time PWM Current Ctrl. Blanking Time Crossover Current Protection BLANK Fast, Slow, and Mixed Decay PFD1 Sync. Rect. LSS1 Zero Current Detect Current Sense GND LSS2 SENSE HA– HB– HC– HA+ HB+ HC+ PFD2 4X GND VCP VBB2 ENABLE A3936-DS, Rev. 8 CP2 GND VDD A3936 DMOS Three-Phase PWM Motor Driver Selection Guide Part Number Packing Package A3936SEDTR-T* 450 pieces per reel 44-pin PLCC with internally fused leads *Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change November 2, 2009. Deadline for receipt of LAST TIME BUY orders is April 30, 2010. Absolute Maximum Ratings Rating Units Load Supply Voltage Characteristic VBB 50 V Logic Supply Voltage VDD 7.0 V VIN tw > 30 ns –0.3 to VDD + 0.3 V Logic Input Votage Range tw < 30 ns –1.0 to VDD + 1 V 0.5 V VDD V ±3 A Sense Voltage Reference Voltage Output Current Symbol Notes VSENSE VREF IOUT Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Operating Ambient Temperature TA –20 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Range S Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3936 DMOS Three-Phase PWM Motor Driver TACH B ANDG AP HBIAS VREG HA+ HA- HALL CP1 CP2 R E G U LA T O R C HAR G E P UMP VCP .22uf/50V VDD .22uf/100V VREG .22uf/50V Functional Block Diagram OVERVOLTAGE UNDERVOLTAGE AND FAULT DETECT VBB1 VCP VBB2 Comm Log ic HB+ HB- HALL OUTA HC+ Control Log ic HC- HALL GATE DRIVE OUTB SLEEP OUTC DIR EXTMODE LSS2 BRAKE LSS1 SR SENSE - ZERO CURRENT DETECT RS + GND .1uF ENABLE VDD OSC - PFD1 PWM TIMER CURRENT SENSE + BLANK BUFFER/ DIVIDER REF PFD2 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3936 DMOS Three-Phase PWM Motor Driver ELECTRICAL CHARACTERISTICS at TJ = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Sym bol Test Conditions M in. Typ. M ax. Units Operating 9 – 50 V During Sleep Mode 0 50 V VOUT = VBB – <1.0 20 μA VOUT = 0 V – <–1.0 -20 MA Source Driver, IOUT = -3A – .55 7 Sink Driver, IOUT = 3A – .35 7 Source Diode, IF = -3A – – 1.4 V Sink Diode, IF = 3A – – 1.3 V fPWM < 50 kHz – 4 7 mA Charge Pump On, Outputs Disabled – 2 5 mA Sleep Mode – – 20 uA fPWM < 50 kHz – 10 mA Outputs Off – 8 mA 100 MA Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current VBB IDSS RDSON VF IBB IDD Sleep Mode (Inputs below .5V) Control Logic Logic Supply Voltage Range VDD Logic Input Voltage Operating 3 5.0 5.5 V VIN(1) VDD*.5 – – V VIN(0) – – VDD*.2 V Logic Input Current IIN(1) VIN = VDD*.5 -20 <1.0 20 μA (except ENABLE) IIN(0) VIN = VDD*.2 -20 <-1.0 20 μA Logic Input Current IIN(1) VIN = VDD*.5 – 100 μA ENABLE Input IIN(0) VIN = VDD*.2 – 30 μA Internal Oscillator fOSC OSC shorted to GND 3 4 5 MHz 3.4 4 4.6 MHz ROSC= 51K Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3936 DMOS Three-Phase PWM Motor Driver ELECTRICALCHARACTERISTICS (continued) at TJ= +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Sym bol Test Conditions M in. Typ. M ax. Units Control Logic Buffer Input Offset Volt. VIO VREF Input Voltage Range ±10 mV Operating 0.0 – VDD V -.5 0 0.5 MA Reference Input Current IREF VREF = VDD ,VBB=0 to 50V Comparator Input Offset Volt. VIO VREF = 0 V VERR VREF = VDD -4 4 % (Note 3) VREF = .5V -14 14 % GM Error Propagation Delay Times Crossover Delay Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis tpd ±5 mV 50% TO 90%, SR Enabled PWM CHANGE TO SOURCE ON 600 750 1000 ns PWM CHANGE TO SOURCE OFF 50 150 350 ns PWM CHANGE TO SINK ON 600 750 1000 ns PWM CHANGE TO SINK OFF 50 100 150 ns SR Enabled 300 600 1000 ns TJ – 165 – °C $TJ – 15 – °C 2.45 2.7 2.95 V 0.05 0.10 – V tCOD Rising VDD Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3936 DMOS Three-Phase PWM Motor Driver ELECTRICALCHARACTERISTICS (continued) at TJ= +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Sym bol Test Conditions M in. Typ. M ax. Units -1 0 1 MA 2.5 V Hall Logic Hall Input Current IHALL VIN = 1.2V VCMR .3 AC Input Voltage Range VHALL .120 Hysteresis VHYS Common Mode Input Range TA= -20 to 85 deg C. 10 3 Pulse Reject Filter Hall Bias Output Sat Voltage VHB IOUT=40mA, TA= -20 to 85 deg C. IHB Tach Output NOTES: 1. 2. 3. VOL Vp-p IOUT= 500uA 30 mV 5.5 8 Ms .4 .5 V 40 mA .5 V Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin. VERR =((VREF/10) – VSENSE)/(VREF/10) Commutation Truth Table 120 spacing HB HC + + + + + + + + + + + + + + + + + + + + + HA 1 2 3 4 5 6 1 2 3 4 5 6 DIR FOR FOR FOR FOR FOR FOR REV REV REV REV REV REV X X OUTA HI HI Z LO LO Z LO LO Z HI HI Z Z Z Outputs OUTB OUTC LO Z Z LO HI LO HI Z Z HI LO HI HI Z Z HI LO HI LO Z Z LO HI LO Z Z Z Z Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3936 DMOS Three-Phase PWM Motor Driver Functional Description VREG. The VREG pin should be decoupled with a 0.22 μF capacitor to ground. This supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The Charge Pump is used to generate a supply above VBB to drive the source side DMOS gates. A 0.22 uF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 uF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high side DMOS devices. The VCP Voltage is internally monitored and in the case of a fault condition the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers. Extmode Logic. When using external PWM current control, the EXTMODE input determines the current path during the chopped cycle. With EXTMODE set low, fast decay mode, both the source and sink drivers are chopped OFF during the decay time (ENABLE=0). With EXTMODE high, slow decay mode, only the source driver turns off during the current decay time. EXTMODE 0 1 Decay Fast Slow Sleep Mode. The input pin SLEEP is dedicated to put the device into a minimum current draw mode. When asserted low, all circuits are disabled. Fixed Off-Time. The 3936 is set for a fixed off time of 96 counts of the internal oscillator, typically 24 μs with 4Mhz oscillator. Internal Current Control Mode. Input pins PFD1 Current Regulation. Load current is regulated by an internal fixed off time PWM control circuit. When the outputs of the DMOS H-bridge are turned on, current increases in the motor winding until it reaches a value given by: ITRIP = VREF/(10*RSENSE) At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed off time period. The current path during recirculation is determined by the configuration of slow/mixed decay mode and the synchronous rectification control setting. and PFD2 determine the current decay method after an overcurrent event is detected at sense input. In slow decay mode both sink side drivers are turned on for the fixed off time period. Mixed decay mode starts out in fast decay mode for the selected percentage of the fixed off time, and then is followed by slow decay for the rest of the period. PFD2 0 0 1 1 PFD1 0 1 0 1 % tOFF 0 15 48 100 Decay Slow Mixed Mixed Fast Enable Logic. The Enable input terminal allows external PWM. ENABLE high turns ON the selected sinksource pair, enable low switches off the appropriate drivers and the load current decays. If the ENABLE pin is held high, the current will rise until it reaches the level set by the internal current control circuit. ENABLE 0 1 Outputs Source Chopped ON Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3936 DMOS Three-Phase PWM Motor Driver PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. The blank timer runs after the off time counter to provide the blanking function. The blank timer is reset when ENABLE is chopped or DIR is changed. For external PWM control, a DIR change or ENABLE ON will trigger the blanking function. The duration is adjusted by control input BLANK. BLANK 0 1 tBLANK 6/f OSC 12/f OSC Synchronous Rectification. Logic high applied to the SR terminal enables synchronous rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off time cycle, load current will recirculate according to the decay mode selected by control logic. The A3936 synchronous rectification feature will turn on the appropriate MOSFET(s)during the current decay and effectively short out the body diodes with the low Rdson driver. This will lower power dissipation significantly and can eliminate the need for external schottky diodes. Reversal of load current is prevented by turning off synchronous rectification when a zero current level is detected. Brake. Logic high to the brake terminal activates the brake function, logic low allows normal operation. Brake will turn all three sink drivers ON and effectively shorts out the motor generated BEMF. It is important to note that the internal PWM current control circuit will not limit the current when braking, since the current does not flow through the sense resistor. The maximum current can be approximated by VBEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations of high speed and high inertial loads. Oscillator. The PWM timer is based on an internal oscillator set by a resistor connected from the OSC terminal to VDD. Typical value of 4Mhz is set with 51k resistor. FOSC = 204E9/ROSC. Tach. A tachometer signal is available for speed measurement. This open collector output toggles at each Hall transition. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3936 DMOS Three-Phase PWM Motor Driver 40 EXTMODE 41 BLANK 42 PFD2 43 PFD1 1 GND 44 GND 2 GND 3 HA+ 4 HA- 5 HB+ 6 HB- Pin-out Diagram HC+ 7 39 ENABLE HC- 8 38 DIR VDD 9 37 VREG REF 10 36 OSC GND 11 35 GND GND 12 34 GND GND 13 33 GND OUTC 28 TACH 27 LSS2 25 VBB2 26 GND 24 GND 23 GND 22 29 VCP OUTB 21 30 CP1 OUTA 17 LSS1 20 31 CP2 SR 16 VBB1 19 32 SLEEP SENSE 15 HBIAS 18 BRAKE 14 Terminal List Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name GND GND HA+ HAHB+ HBHC+ HCVDD REF GND GND GND BRAKE SENSE SR OUTA HBIAS VBB1 LSS1 OUTB GND GND GND LSS2 VBB2 TACH OUTC VCP CP1 CP2 SLEEP GND GND GND OSC VREG DIR ENABLE EXTMODE BLANK PFD2 PFD1 GND Pin Description Hall input Hall input Hall input Hall input Hall input Hall input Logic Supply Voltage Gm Reference Input Voltage Logic Input Sense Resistor Connection Logic Input (Disabled = Low, Active SR = High) DMOS H – Bridge A Connection for hall element neg side Load Supply Voltage Low Side Source connection DMOS H – Bridge B Low Side Source connection Load Supply Voltage Speed output DMOS H – Bridge C Reservoir Capacitor Terminal Charge Pump Capacitor Terminal Charge Pump Capacitor Terminal Logic input for SLEEP mode Oscillator Terminal Regulator decoupling Terminal Logic Input Logic Input Logic Input Logic Input Logic Input Logic Input Power Ground Tab Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3936 DMOS Three-Phase PWM Motor Driver Package ED 44-Pin PLCC 17.53 ±0.13 16.59 ±0.08 0.51 2 1 44 7.75 ±0.36 A 17.53 ±0.13 16.59 ±0.08 7.75 ±0.36 0.74 ±0.08 4.57 MAX 44X SEATING PLANE 0.10 C 0.43 ±0.10 C 1.27 7.75 ±0.36 7.75 ±0.36 For Reference Only (reference JEDEC MS-018 AC) Dimensions in millimeters Internally fused pins: 1, 2, and 44; 11, 12, and 13; 22, 23, and 24; and 33, 34, and 35. Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Copyright ©2002-2009, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10