Data Sheet 29319.37E 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER CP2 2 CP1 3 PHASE 4 ROSC 5 GROUND 6 GROUND 7 LOGIC SUPPLY 8 ENABLE 99 PFD2 10 BLANK 11 PFD1 12 NC θ VBB LOGIC 1 V DD PWM TIMER CP CHARGE PUMP A3959SLB (SOIC) NC ÷10 24 VREG 23 SLEEP 22 NO CONNECTION 21 OUTB 20 LOAD SUPPLY 19 GROUND 18 GROUND 17 SENSE 16 OUTA 15 NO CONNECTION 14 EXT MODE 13 REF Dwg. PP-069-4 Note that the A3959SLB(SOIC), A3959SB (DIP), and A3959SLP (TSSOP) do not share a common terminal assignment. ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB ......................... 50 V Output Current, IOUT (Repetitive) ........... ±3.0 A (Peak, <3 µs) ................................... ±6.0 A Logic Supply Voltage, VDD ....................... 7.0 V Logic Input Voltage Range, VIN (Continuous) ............ -0.3 V to VDD + 0.3 V (tw <30 ns) ............... -1.0 V to VDD + 1.0 V Sense Voltage, VS (Continuous) .............. 0.5 V (tw <3 µs) ........................................... 2.5 V Reference Voltage, VREF ............................ VDD Package Power Dissipation (TA = 25°C), PD A3959SB ........................................ 3.3 W* A3959SLB ...................................... 2.5 W* A3959SLP ...................................... 3.1 W* Operating Temp. Range, TA .... -20°C to +85°C Junction Temperature, TJ ..................... +150°C Storage Temp. Range, TS ..... -55°C to +150°C Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Designed for pulse-width modulated (PWM) current control of dc motors, the A3959SB, A3959SLB, and A3959SLP are capable of output currents to ±3 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be adjusted via control inputs to operate in slow, fast, and mixed current-decay modes. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM-control signals. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of supply and charge pump, and crossover-current protection. Special power-up sequencing is not required. The A3959SB/SLB/SLP is a choice of three power packages, a 24-pin plastic DIP with a copper batwing tab (package suffix ‘B’), a 24-lead plastic SOIC with a copper batwing tab (package suffix ‘LB’), and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal pad (suffix ‘LP’). In all cases, the power tab is at ground potential and needs no electrical isolation. Each package is available in a lead- free version (100% matte tin leadframe). FEATURES ■ ■ ■ ■ ■ ■ ■ ±3 A, 50 V Output Rating Low rDS(on) Outputs (270 mΩ, Typical) Mixed, Fast, and Slow Current-Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal-Shutdown Circuitry Crossover-Current Protection Internal Oscillator for Digital PWM Timing Always order by complete part number: Part Number RθJA* Rθ JT 24-pin batwing DIP 38°C/W 6°C/W A3959SB-T 24-pin batwing DIP; Lead-free 38°C/W 6°C/W A3959SLB 24-lead batwing SOIC 50°C/W 6°C/W 24-lead batwing SOIC; Lead-free 50°C/W 6°C/W 28-lead thin shrink SOIC 40°C/W — 28-lead thin shrink SOIC; Lead-free 40°C/W — A3959SB A3959SLB-T A3959SLP A3959SLP-T Package * Double-sided board, one square inch copper each side. See also, Layout, page 7. 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL BLOCK DIAGRAM VBB VDD CP CP1 CHARGE PUMP BANDGAP VDD CREG TSD CP2 + LOGIC SUPPLY LOAD SUPPLY CHARGE PUMP UNDERVOLTAGE & FAULT DETECT BANDGAP REGULATOR OUTA EXT MODE GATE DRIVE SLEEP VREG CONTROL LOGIC PHASE ENABLE OUTB SENSE TO VDD PWM TIMER PFD1 CS ZERO CURRENT DETECT BLANK RS PFD2 CURRENT SENSE OSC ROSC REFERENCE BUFFER & ÷10 REF VREF Dwg. FP-048-2A 1 24 CP CP1 2 23 VREG PHASE 3 22 SLEEP ROSC 4 21 OUTB GROUND 5 20 LOAD SUPPLY A3959SB (DIP) GROUND 6 19 GROUND 7 18 GROUND Note that the A3959SLB (SOIC), A3959SB (DIP), and A3959SLP (TSSOP) do not share a common terminal assignment. GROUND GROUND 8 17 SENSE LOGIC SUPPLY 99 16 OUTA ENABLE 10 15 EXT MODE PFD2 11 ÷ 10 14 REF BLANK 12 PWM TIMER 13 PFD1 CHARGE PUMP θ VBB LOGIC CP2 V DD Dwg. PP-069-5A 2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2001, 2003 Allegro MicroSystems, Inc. 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance VBB IDSS rDS(on) Operating 9.5 – 50 V During sleep mode 0 – 50 V VOUT = VBB – <1.0 20 µA VOUT = 0 V – <-1.0 -20 µA Source driver, IOUT = -3 A – 270 300 mΩ Sink driver, IOUT = 3 A – 270 300 mΩ 300 600 1000 ns Source diode, IF = -3 A – – 1.6 V Sink diode, IF = 3 A – – 1.6 V fPWM < 50 kHz – 4.0 7.0 mA Charge pump on, outputs disabled – 2.0 5.0 mA Sleep Mode – – 20 µA 4.5 5.0 5.5 V Crossover Delay Body Diode Forward Voltage Load Supply Current VF IBB Control Logic Logic Supply Voltage Range VDD Operating Logic Input Voltage VIN(1) 2.0 – – V VIN(0) – – 0.8 V Logic Input Current (all inputs except ENABLE) IIN(1) VIN = 2.0 V – <1.0 20 µA IIN(0) VIN = 0.8 V – <-2.0 -20 µA ENABLE Input Current IIN(1) VIN = 2.0 V – 40 100 µA IIN(0) VIN = 0.8 V – 16 40 µA fOSC ROSC shorted to GROUND 3.25 4.25 5.25 MHz ROSC = 51 kΩ 3.65 4.25 4.85 MHz Internal OSC frequency Reference Input Volt. Range VREF Operating 0.0 – VDD V Reference Input Current IREF VREF = VDD – – ±1.0 µA Comparator Input Offset Volt. VIO VREF = 0 V – ±5.0 – mV Continued next page … www.allegromicro.com 3 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise), continued. Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Control Logic Reference Divider Ratio Gm Error – – 10 – – VREF = VDD – – ±4.0 % VREF = 0.5 V – – ±14 % 600 50 600 50 750 150 750 100 1200 350 1200 150 ns ns ns ns TJ – 165 – °C ∆TJ – 15 – °C 3.90 4.2 4.45 V 0.05 0.10 – V fPWM < 50 kHz – 6.0 10 mA Sleep Mode – – 2.0 mA EGm (Note 3) Propagation Delay Times Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current tpd UVLO 0.5 Ein to 0.9 Eout: PWM change to source on PWM change to source off PWM change to sink on PWM change to sink off Increasing VDD ∆UVLO IDD NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. Gm error = ([VREF/10] – VSENSE)/(VREF/10) where VSENSE = ITRIP•RS. 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL DESCRIPTION VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The charge pump is used to generate a gate-supply voltage greater than VBB to drive the sourceside DMOS gates. A 0.22 µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 µF ceramic capacitor should be connected between CP and VBB to act as a reservoir to operate the high-side DMOS devices. The CP voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. PHASE Logic. The PHASE input terminal determines if the device is operating in the “forward” or “reverse” state. PHASE OUTA OUTB 0 Low High 1 High Low ENABLE Logic. The ENABLE input terminal allows external PWM. ENABLE high turns on the selected sinksource pair. ENABLE low switches off the source driver or the source and sink driver, depending on EXT MODE, and the load current decays. If ENABLE is kept high, the current will rise until it reaches the level set by the internal current-control circuit. ENABLE Outputs 0 Chopped 1 On EXT MODE Logic. When using external PWM current control, the EXT MODE input determines the current path during the chopped cycle. With EXT MODE low, fast decay mode, the opposite pair of selected outputs will be enabled during the off cycle. With EXT MODE high, slow decay mode, both sink drivers are on with ENABLE low. EXT MODE Decay 0 Fast 1 Slow Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the DMOS H bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (RS) and the applied analog reference voltage (VREF): ITRIP = VREF/10RS At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance then causes the current to recirculate for the fixed off-time period. The current path during recirculation is determined by the configuration of slow/ mixed/fast current-decay mode via PFD1 and PFD2. Oscillator. The PWM timer is based on an internal oscillator set by a resistor connected from the ROSC terminal to VDD. Typical value of 4 MHz is set with a 51 kΩ resistor. The allowable range of the resistor is from 20 kΩ to 100 kΩ. fOSC = 204 x 109/ROSC. If ROSC is not pulled up to VDD, it must be shorted to ground. Fixed Off Time. The A3959 is set for a fixed off time of 96 cycles of the internal oscillator, typically 24 µs with a 4 MHz oscillator. www.allegromicro.com 5 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL DESCRIPTION (continued) Internal Current-Control Mode. Inputs PFD1 and PFD2 determine the current-decay method after an overcurrent event is detected at the SENSE input. In slow-decay mode, both sink drivers are turned on for the fixed off-time period. Mixed-decay mode starts out in fast-decay mode for a portion (15% or 48%) of the fixed off time, and then is followed by slow decay for the remainder of the period. PFD2 PFD1 % toff Decay 0 0 0 Slow 0 1 15 Mixed 1 0 48 Mixed 1 1 100 Fast PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time counter to provide the blanking function. The blank timer is reset when ENABLE is chopped or PHASE is changed. For external PWM control, a PHASE change or ENABLE on will trigger the blanking function. The duration is determined by the BLANK input and the oscilator. BLANK tblank 0 6/fosc 1 12/fosc Synchronous Rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3959 synchronous rectification feature will turn on the appropriate pair of DMOS outputs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and can eliminate the need for external Schottky diodes. Synchronous rectification will prevent reversal of load current by turning off all outputs when a zero-current level is detected. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on CP or VREG) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers. Braking. The braking function is implemented by driving the device in slow-decay mode via EXTMODE and applying an enable chop command. Because it is possible to drive current in either direction through the DMOS drivers, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. It is important to note that the internal PWM current-control circuit will not limit the current when braking, because the current does not flow through the sense resistor. The maximum brake current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads. SLEEP Logic. The SLEEP input terminal is used to minimize power consumption when when not in use. This disables much of the internal circuitry including the regulator and charge pump. Logic low will put the device into sleep mode, logic high will allow normal operation. 6 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL DESCRIPTION (continued) Current Sensing. To minimize inaccuracies in sensing the ITRIP current level, which may be caused by ground trace IR drops, the sense resistor should have an independent ground return to the ground terminal of the device. For low-value sense resistors the IR drops in the PCB sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. The maximum value of RS is given as RS ≤ 0.5/ITRIP where ITRIP ≤ 3.0 A. ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. 5 SUFFIX 'B', RθJA = 26°C/W SUFFIX 'LP', RθJA = 28°C/W SUFFIX 'LB', RθJA = 35°C/W MULTI-LAYER HIGH-K BOARD 4 * The thermal resistance, RθJA, and absolute maximum allowable package power dissipation specified on page 1 is measured on a typical two-sided PCB with one square inch copper ground area on each side. With minimal copper on a single-sided PCB (worst-case), the ‘B’ package RθJA is 40°C/W, ‘LB’ is 77°C/W, and ‘LP’ is 80°C/W. See also, Application Note 29501.5, Improving Batwing Power Dissipation. For specification purposes, the multi-layer high-K board performance graphed here is per JEDEC Standard JESD51. 3 2 The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. 1 SUFFIX 'B', RθJA = 38°C/W 0 Layout. A star ground system located close to the driver is recommended. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance*, the driver should be soldered directly onto the board. The ground side of RS should have an individual path to the ground terminals of the device. This path should be as short as is possible physically and should not have any other components connected to it. It is recommended that a 0.1 µF capacitor be placed between SENSE and ground as close to the device as possible; the load supply terminal, VBB, should be decoupled with an electrolytic capacitor (> 47 µF is recommended) placed as close to the device as is possible. On the 28-lead TSSOP package, the copper ground plane located under the exposed thermal pad is typically used as a star ground. SUFFIX 'LP', RθJA = 40°C/W SUFFIX 'LB', RθJA = 50°C/W DOUBLE-SIDED BOARD, 1 SQ. IN. COPPER EA. SIDE 25 50 75 100 TEMPERATURE IN ° C 125 150 Dwg. GP-049-6 www.allegromicro.com Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 7 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER Terminal List Terminal Name CP CP1 & CP2 NC PHASE ROSC GROUND LOGIC SUPPLY ENABLE NC PFD2 BLANK PFD1 REF EXT MODE NO CONNECT OUTA NC SENSE NC Terminal Description Reservoir capacitor (typically 0.22 µF) The charge pump capacitor (typically 0.22 µF) No (internal) connection Logic input for direction control Oscillator resistor Grounds LB B LP (SOIC) (DIP) (TSSOP) 1 2&3 24 1&2 1 2&3 — 4 — 3 4 5 5 4 6, 7 5, 6, 7, 8* 6 7, 8* VDD, the low voltage (typically 5 V) supply Logic input for enable control 8 9 9 10 9 10 No (internal) connection Logic-level input for fast decay – 10 – 11 11 12 Logic-level input for blanking control Logic-level input for fast decay VREF, the load current reference input voltage 11 12 13 12 13 14 13 14 15 Logic input for PWM mode control No (Internal) connection 14 15 15 — 16 17 One of two DMOS bridge outputs to the motor No (internal) connection 16 – 16 – 18 19, 20 Sense resistor No (internal) connection 17 – 17 – 21 22 GROUND LOAD SUPPLY Grounds VBB, the high-current, 9.5 V to 50 V, motor supply OUTB NO CONNECT One of two DMOS bridge outputs to the motor No (Internal) connection 21 22 21 — 24 25 Logic-level Input for sleep operation Regulator decoupling capacitor (typically 0.22 µF) 23 24 22 23 26 27 Ground — — 28* SLEEP VREG GROUND 18, 19 18, 19* 20 20 — 23 * For the A3959SB (DIP) only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. For the A3959SLP (TSSOP) the grounds at terminals 7, 8, and 28 should be connected together at the exposed pad beneath the device. 8 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER A3959SB Dimensions in Inches (controlling dimensions) 24 0.014 0.008 13 NOTE 1 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 6 7 0.100 1.280 1.230 12 0.005 BSC MIN 0.210 MAX 0.015 0.150 0.115 MIN 0.022 0.014 Dwg. MA-001-25A in Dimensions in Millimeters (for reference only) 24 0.355 0.204 13 NOTE 1 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 6 7 2.54 32.51 31.24 12 BSC 0.13 MIN 5.33 MAX 0.39 3.81 2.93 MIN 0.558 0.356 NOTES: 1. 2. 3. 4. 5. Dwg. MA-001-25A mm Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 15 devices. www.allegromicro.com 9 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER A3959SLB 24 13 0.0125 0.0091 Dimensions in Inches (for reference only) 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 3 0.6141 0.5985 0.050 BSC 0° TO 8° NOTE 1 NOTE 3 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-25A in 24 0.32 0.23 10.65 10.00 7.60 7.40 Dimensions in Millimeters (controlling dimensions) 1.27 0.40 0.51 0.33 1 2 3 15.60 15.20 1.27 BSC 0° TO 8° NOTE 1 NOTE 3 2.65 2.35 0.10 MIN. NOTES: 1. 2. 3. 4. 10 Dwg. MA-008-25A mm Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER A3959SLP 28-pin TSSOP 9.8 9.6 .386 .378 8” 0” 28 0.20 .008 0.09 .004 4.5 4.3 6.6 6.2 A .177 .169 3 .118 BSC .260 .244 1 .039 REF 1 2 5 .200 BSC 0.75 .030 0.45 .018 0.25 .010 BSC Seating Plane Gauge Plane 0.30 .012 0.19 .007 1.20 .047 MAX 0.65 .026 BSC 0.15 .006 0.00 .000 0.65 .026 BSC 0.30 .012 BSC 6.6 .260 BSC 2.7 .106 BSC 4.5 .138 BSC 0.75 .030 BSC Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface) www.allegromicro.com 11 3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER MOTOR DRIVERS Function Output Ratings* Part Number† INTEGRATED CIRCUITS FOR BRUSHLESS DC MOTORS 3-Phase Power MOSFET Controller — 28 V 3933 3-Phase Power MOSFET Controller — 40 V 3935 3-Phase Power MOSFET Controller — 50 V 3932 & 3938 3-Phase Back-EMF Controller/Driver ±900 mA 14 V 8904 3-Phase PWM Current-Controlled DMOS Driver ±3.0 A 50 V 3936 INTEGRATED BRIDGE DRIVERS FOR DC AND BIPOLAR STEPPER MOTORS PWM Current-Controlled Dual Full Bridge ±500 mA 18 V 3965 Dual Full Bridge with Protection & Diagnostics ±500 mA 30 V 3976 PWM Current-Controlled Dual Full Bridge ±650 mA 30 V 3966 PWM Current-Controlled Dual Full Bridge ±650 mA 30 V 3968 Microstepping Translator/Dual Full Bridge ±750 mA 30 V 3967 PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 2916 PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 2919 PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 6219 PWM Current-Controlled Dual Full Bridge ±800 mA 33 V 3964 PWM Current-Controlled Dual DMOS Full Bridge ±1.0 A 35 V 3973 PWM Current-Controlled Full Bridge ±1.3 A 50 V 3953 PWM Current-Controlled Dual Full Bridge ±1.5 A 45 V 2917 PWM Current-Controlled DMOS Full Bridge ±1.5 A 50 V 3948 PWM Current-Controlled Microstepping Full Bridge ±1.5 A 50 V 3955 PWM Current-Controlled Microstepping Full Bridge ±1.5 A 50 V 3957 PWM Current-Controlled Dual DMOS Full Bridge ±1.5 A 50 V 3972 PWM Current-Controlled Dual DMOS Full Bridge ±1.5 A 50 V 3974 PWM Current-Controlled Full Bridge ±2.0 A 50 V 3952 PWM Current-Controlled DMOS Full Bridge ±2.0 A 50 V 3958 Microstepping Translator/Dual DMOS Full Bridge ±2.5 A 35 V 3977 PWM Current-Controlled DMOS Full Bridge ±3.0 A 50 V 3959 UNIPOLAR STEPPER MOTOR & OTHER DRIVERS Unipolar Stepper-Motor Translator/Driver 1.0 A 46 V 7050 Unipolar Stepper-Motor Translator/Driver 1.25 A 50 V 5804 Unipolar Stepper-Motor Quad Drivers 1.5 A 46 V 7024 & 7029 Unipolar Microstepper-Motor Quad Driver 1.5 A 46 V 7042 Unipolar Stepper-Motor Quad Driver 1.8 A 50 V 2540 Unipolar Stepper-Motor Translator/Driver 2.0 A 46 V 7051 Unipolar Stepper-Motor Quad Driver 3.0 A 46 V 7026 Unipolar Microstepper-Motor Quad Driver 3.0 A 46 V 7044 Unipolar Stepper-Motor Translator/Driver 3.0 A 46 V 7052 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits or over-current protection voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. Also, see 3175, 3177, 3235, and 3275 Hall-effect sensors for use with brushless dc motors. 12 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000