ADC9708 6-Channel 8-Bit mP Compatible A/D Converter General Description Features The ADC9708 is a single slope 8-bit, 6-channel ADC subsystem that provides all of the necessary analog functions for a microprocessor-based data control system. The device uses an external microprocessor system to provide the necessary addressing, timing and counting functions and includes a 1-of-8 decoder, 8-channel analog multiplexer, sample and hold, ramp integrator, precision ramp reference, and a comparator on a single monolithic chip. Y Y Y Y Y Y Y Y Y Connection Diagram MPU compatible Excellent linearity over full temperature range g 0.2% maximum Typical 300 ms conversion time per channel Wide dynamic range includes ground Auto-zero and full-scale correction capability Ratiometric conversionÐno precision reference required Single-supply operation TTL compatible Does not require access to data bus or address bus Ordering Information All Packages Commercial (0§ C s TA s 70§ C) ADC9708CCN ADC9708CCJ Military (b55§ C s TA s 125§ C) ADC9708CMJ Package N16E J16A Package J16A TL/H/10409 – 2 (Top View) Block Diagram TL/H/10409 – 1 C1995 National Semiconductor Corporation TL/H/10409 RRD-B30M115/Printed in U. S. A. ADC9708 6-Channel 8-Bit mP Compatible A/D Converter October 1991 Absolute Maximum Ratings (Notes 1, 2) Pin Temperature Ceramic DIP (Soldering, 60 Sec.) Molded DIP (Soldering, 10 Sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Comparator Output (Ramp Stop) Analog Input Range Digital Input Range Output Sink Current Storage Temperature Range Continuous Total Dissipation (Note 8) Ceramic DIP Package Molded DIP Package ESD Susceptibility (Note 9) 18V 300§ C 260§ C Operating Ratings (Notes 1, 2) Operating Temperature Range ADC9708CCN, ADC9708CCJ 0§ C to a 70§ C b 55§ C to a 125§ C ADC9708CMJ b 0.3V to a 18V b 0.3V to a 30V b 0.3V to a 30V 10 mA Supply Voltage (VCC) Reference Voltage (VREF) (Note 3) Ramp Capacitor (CH) Reference Current (IR) Analog Input Range Ramp Stop Output Current b 65§ C to a 150§ C 900 mW 1000 mW TBD 4.75V to 15V 2.8V to 5.25V 300 pF 12 mA to 50 mA 0V to VREF 1.6 mA Electrical Characteristics Over recommended operating conditions, VCC e 5.0V, b55§ C s TA s a 125§ C for ADC9708CMJ and 0§ C s TA s a 70§ C for ADC9708CCJ or ADC9708CCN; unless otherwise specified. Symbol Parameter Conditions EA Conversion Accuracy Over Entire Temperature Range (Note 4) ER Linearity Applies to Any One Channel (Note 5) VOSM Multiplexer Input Offset Voltage Typical (Note 10) Limit (Note 11) Units (Limit) g 0.2 g 0.3 % (max) g 0.08 g 0.2 % (max) Channel ON, TA e 25§ C 2.0 4.0 mV (max) Channel ON 2.0 7.0 mV (max) tC Conversion Time per Channel Analog Input e 0V to VREF CH e 300 pF, IREF e 50 mA 296 350 ms (max) tA Acquisition Time CH e 1000 pF 20 40 ms (max) IA Acquisition Current ADC9708CCN, CCJ 150 mA (min) ADC9708CMJ 115 mA (min) tO Ramp Start Delay Time 100 ns tM Multiplexer Address Time 1.0 ms VIH Digital Input HIGH Voltage A0, A1, A2, Ramp Start 2.0 VIL Digital Input LOW Voltage A0, A1, A2, Ramp Start 0.8 V IB Analog Input Current Channel ON or OFF b 1.0 b 3.0 mA (min) IIL Input LOW Current A0, A1, A2, Ramp Start e 0.4V b5 b 15 mA (min) IIH Input HIGH Current A0, A1, A2, Ramp Start e 5.5V 1.0 mA (max) IOS Input Offset Current 3.0 mA (max) IOH Comparator Logic ‘‘1’’ Output Leakage Current VOH e 15V 10 mA (max) VOL Comparator Logic ‘‘0’’ Output Voltage IOL e 1.6 mA 0.4 V (max) Power Supply Rejection Ratio (Note 6) 40 dB (min) Cross Talk between Any Two Channels (Note 7) 60 dB (min) PSRR 1.0 2 V (min) Electrical Characteristics Over recommended operating conditions, VCC e 5.0V, b55§ C s TA s a 125§ C for ADC9708CMJ and 0§ C s TA s a 70§ C for ADC9708CCJ or ADC9708CCN; unless otherwise specified. (Continued) Symbol Conditions Typical (Note 10) Limit (Note 11) Units (Limit) VCC e 5V to 15V, I0 e 0 7.5 15 mA (max) Parameter ICC Power Supply Current CIN Input Capacitance 3.0 pF COUT Comparator Output Capacitance 5.0 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: VREF should not exceed VCC b 2V. Note 4: Conversion accuracy is defined as the deviations from a straight line drawn between the points defined by channel address 000 (0 scale) and channel address 111 (full scale) for all channels. Note 5: Linearity is defined as the deviation from a straight line drawn between the 0 and full scale points for each channel. Note 6: Power supply rejection ratio is defined as the conversion error contributed by power supply voltage variations while resolving mid scale on any channel. Note 7: Cross Talk between channels e 20 log DVCH . DVI Note 8: Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex. when any inputs or outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), iJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax e (TJmax b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax e 150§ C, and the typical thermal resistance (iJA) for board mounting follow: ADC9708CCN 62§ C/W ADC9708CCJ, ADC9708CMJ 58§ C/W Note 9: Human body model, 100 pF discharged through a 1.5 kX resistor. Timing Diagram Test Circuits TL/H/10409 – 7 FIGURE 1. Equivalent Timing Waveform for Test Circuits and Applications Note 10: Typicals are at a 25§ C and represent most likely parametric norm. Input Timing: Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). tA l 400 ms VREF e IR e TL/H/10409 – 8 # 2 kX 3.3 kX a 3.3 kX J 5V e 3.1 5 b 3.1 e 19 mA 100 kX tR l max e full scale ramp time e 0.01 c 10b6 c 3.1 e 1.6 ms 19 c 10b6 Note: For evaluation purposes,the ramp start timing generation can be implemented with an LM555 timer (astable operation) or MPU evaluation kit, and a time interval meter for ramp time measurement. The TIM meter will measure the time between to 0 to 1 transition of the ramp start and the 1 to 0 transition of the ramp stop. The ramp stop is open collector, and must have an external pull-up resistor to VCC. FIGURE 2. Slow Speed Evaluation Circuit for Ratiometric Operation 3 Test Circuits (Continued) ed is selected via address terminals A0 – A2. The analog input voltage level is transferred to the external ramp capacitor connected to pin 4 when the input to the ramp start terminal (pin 3) is at a logic 0 (See Figure 1 ). The time to charge the capacitor is the acquisition time which is a function of the output impedance of an amplifier internal to the A/D converter and the value of the capacitor. After charging the external capacitor the ramp start terminal is switched to a logic 1 which introduces a high impedance between the analog input voltage and the external capacitor. The capacitor begins to discharge at a controlled rate. The controlled rate of discharge (ramp) is established by the external reference voltage, the external reference resistor, the value of the external capacitor and the internal leakage of the A/D converter. Connected to the capacitor terminal is a comparator internal to the A/D converter with its output going to the ramp stop terminal (pin 7). The comparator output is a logic one when the capacitor is charged and switches to a logic 0 when the capacitor is in a discharged state. The ramp time is from the time when ramp start goes HIGH (logic ‘‘1’’) to when ramp stop goes LOW (logic ‘‘0’’). The microprocessor must be programmed to determine this conversion time. The ideal (no undesirable internal source impedances, leakage paths, errors on levels where comparator switches or delay time) conversion time is calculated as follows: TL/H/10409–9 FIGURE 3. Linearity/Acquisition Time/ Conversion Time Test Circuit CH Ramp Time e V1 IR Where V1 e Analog Input Voltage Being Measured CH e External Ramp Capacitor VCC b VREF IR e RREF Where VCC e Power Supply Voltage VREF e Reference Voltage RREF e Reference Resistor In actual use the errors due to a nonideal A/D converter can be minimized by using a microprocessor to make the calculations. (See Figures 5 through 8 .) TL/H/10409–10 FIGURE 4. Static Measurements Functional Description This Analog to Digital Converter is a single-slope 8-bit, 6-channel A/D converter that provides all of the necessary analog functions for a microprocessor-based data/control system. The device uses the processor system to provide the necessary addressing, timing and counting functions and includes a 1-of-8 decoder, 8-channel analog multiplexer, sample and hold, precision current reference, ramp integrator and comparator on a single monolithic chip. Applications that require auto-zero or auto-calibration, (See Figures 5–8 ) can use selection of address 000 and 111, for input address lines A0–A2, in conjunction with the arithmetic capability of a microprocessor to provide ground and scaling factors. Address 0, 0, 0 internally connects the input of the ramp generator to ground and may be used for zero offset correction in subsequent conversions. Address 1, 1, 1, internally connects the input of the ramp generator to the voltage reference, VREF, and may be used for scale factor correction in subsequent conversions. For the following, refer to the Functional Block Diagram. Six separate external analog voltage inputs may come into terminals I1 – I6 and the specific analog input to be convert- Channel Selection Input Address Line 4 A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected Analog Input Ground I1 I2 I3 I4 I5 I6 VREF Functional Description (Continued) Auto-Zero and Full-Scale Features No Zero Offset No Full-Scale Error Count (n) e TL/H/10409 – 3 i NZ 0 i 256 TL/H/10409 – 4 (N) has both full-scale and zero errors VIN c 256 VREF FIGURE 6. Transfer Function with Zero and Full-Scale Error FIGURE 5. Ideal Transfer Function NÊ e N b NZ NF.S. TL/H/10409 – 5 N× e (N b NZ) c NÊ has Full-Scale Error 256 (NF.S. b NZ) TL/H/10409 – 6 FIGURE 8. Transfer Function with both Zero and Full-Scale Correction Added FIGURE 7. Transfer Functions with Zero-Correction Added 9. 2V s VREF s (VCC b 2V) 10. Address lines A0, A1, A2 must be stable throughout the sampling interval, tA. Typical Applications Application Suggestions and Formulas 1. The capacitor node impedance is approximately 30 mX and should have no parallel resistance for proper operation. 2. tR when VIN e 0V will be finite (i.e., the comparator will always toggle for VIN t 0V). 3. The ramp stop output is open collector, and an external pull-up resistor is required. 4. All digital inputs and outputs are TTL compatible. 5. For proper operation, timing commences on the 0 to 1 transition of ramp start and terminates on the 1 to 0 transition of ramp stop. 11. Pin 6 (RREF) should be bypassed to ground via a 0.02 mF capacitor. Microprocessor Considerations Several alternatives exist from a hardware/software standpoint in microprocessor based systems using the ADC9708. 1. The ramp time measurement may be implemented in software using a register increment, followed by a branch back depending on the status of the ramp stop. 2. Alternately, the ramp stop may be tied into the interrupt structure in systems containing a programmable binary timer. This scheme has the following advantages: a. The CPU is not committed during the ramp time interval. b. It requires only 5 bits of an I/O port for control signals. CH c VREF (See Figure 1 ) IA b IR CH C c VIN, tR l max e H c VREF 7. tR (ramp time) e IR IR (See Figure 1 ) VCC b VREF 8. IR e RREF 6. tA t 5 Typical Applications (Continued) 3. The auto-zero/auto-full-scale (See Figures 5–8 ) should use double precision, rounded (as opposed to truncated) arithmatic. Several points are worth noting: These schemes have the following advantages: a. No access to the data bus or address bus is required, by the A/D system. b. 5 I/O bits completely support the A/D system. c. Since auto full scale/auto zero are implemented in software and long term drift (aging) effects are eliminated. d. Software overhead is minimal (typically 30 bytes). e. Where ratiometric operation is permissible, the 4 external components may be g 5% tolerance, including the power supply. a. The subtractions are single op code instructions. b. The full scale correction uses a multiply by 256 and can be accomplished by a shift left 8 bits (usually one instruction) or placing (N b NZ) in the MSB register and setting the LSB register to zero, for the double precision divide. c. The divisor (NF.S. b NZ) of the MSB register will always be zero. TL/H/10409 – 11 Note: DVI e (Applied Force) and can be Linearized (if necessary) in Software. FIGURE 9. Ratiometric Strain Gage Sensore/Controller TL/H/10409 – 12 Applications Beverage Brewers/Dispensers Chemical Solution Control Automatic Liquid Mixing Control Ramp Current e IR e VCC VI e #R RX X a RB J Ramp Time e VI a #R R1 1 a R2 J #R J 1 3 VCC a # I J #R CH e R FIGURE 10 6 RX X a RB J #1 a R2 R1 J #C R J H 3 Physical Dimensions inches (millimeters) Dual-In-Line Package (J) Order Number ADC9708CCJ or ADC9708CMJ NS Package Number J16A 7 ADC9708 6-Channel 8-Bit mP Compatible A/D Converter Physical Dimensions inches (millimeters) (Continued) 16 Lead Dual-In-Line Package (N) Order Number ADC9708CCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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