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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300002-E-V13
F²MC-8L/8FX/16LX16FX FAMILY
8/16-BIT MICROCONTROLLER
MB89XXX / MB95XXX / MB90XXX /
MB96XXX
PERFORMING SPI
APPLICATION NOTE
PERFORMING SPI
Revision History
Revision History
Date
2003-02-26
2005-10-04
2006-04-05
2010-06-11
Issue
MWi; First version
MWi; 8FX series, UART cross table, and appendix added
MWi; SPI-Slave chapter added
MWi; CPOL, CPHA logic corrected
This document contains 16 pages.
MCU-AN-30002-E-V13
-2-
© Fujitsu Microelectronics Europe GmbH
PERFORMING SPI
Warranty and Disclaimer
Warranty and Disclaimer
The use of the deliverables (e.g. software, application examples, target boards, evaluation boards,
starter kits, schematics, engineering samples of IC’s etc.) is subject to the conditions of Fujitsu
Microelectronics Europe GmbH (“FME”) as set out in (i) the terms of the License Agreement and/or
the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the
technical descriptions and (iii) all accompanying written materials.
Please note that the deliverables are intended for and must only be used for reference in an
evaluation laboratory environment.
The software deliverables are provided on an as-is basis without charge and are subject to
alterations. It is the user’s obligation to fully test the software in its environment and to ensure proper
functionality, qualification and compliance with component specifications.
Regarding hardware deliverables, FME warrants that they will be free from defects in material and
workmanship under use and service as specified in the accompanying written materials for a duration
of 1 year from the date of receipt by the customer.
Should a hardware deliverable turn out to be defect, FME’s entire liability and the customer’s
exclusive remedy shall be, at FME´s sole discretion, either return of the purchase price and the
license fee, or replacement of the hardware deliverable or parts thereof, if the deliverable is returned
to FME in original packing and without further defects resulting from the customer’s use or the
transport. However, this warranty is excluded if the defect has resulted from an accident not
attributable to FME, or abuse or misapplication attributable to the customer or any other third party not
relating to FME or to unauthorised decompiling and/or reverse engineering and/or disassembling.
FME does not warrant that the deliverables do not infringe any third party intellectual property right
(IPR). In the event that the deliverables infringe a third party IPR it is the sole responsibility of the
customer to obtain necessary licenses to continue the usage of the deliverable.
In the event the software deliverables include the use of open source components, the provisions of
the governing open source license agreement shall apply with respect to such software deliverables.
To the maximum extent permitted by applicable law FME disclaims all other warranties, whether
express or implied, in particular, but not limited to, warranties of merchantability and fitness for a
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To the maximum extent permitted by applicable law, FME’s liability is restricted to intention and gross
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Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect.
The contents of this document are subject to change without a prior notice, thus contact FME about
the latest one.
© Fujitsu Microelectronics Europe GmbH
-3-
MCU-AN-300002-E-V13
PERFORMING SPI
Contents
Contents
REVISION HISTORY.............................................................................................................. 2
WARRANTY AND DISCLAIMER............................... ERROR! BOOKMARK NOT DEFINED.
CONTENTS ............................................................................................................................ 3
0 INTRODUCTION................................................................................................................ 5
1 SPI FORMATS................................................................................................................... 6
1.1
General SPI .............................................................................................................. 6
1.2
SPI Clock (SCK)........................................................................................................ 6
1.3
Data direction ............................................................................................................ 6
1.4
Communication speed .............................................................................................. 6
1.5
SPI protocols............................................................................................................. 7
1.5.1
CPOL = 0, CPHA = 0 .................................................................................. 7
1.5.2
CPOL = 1, CPHA = 0 .................................................................................. 7
1.5.3
CPOL = 0, CPHA = 1 .................................................................................. 8
1.5.4
CPOL = 1, CPHA = 1 .................................................................................. 8
2 IMPLEMENTING SPI-MASTER COMMUNICATION ........................................................ 9
2.1
2.2
Implementing SPI Formats with CPHA = 0 ............................................................... 9
2.1.1
SPI with CPHA = 0 and CPOL = 0 .............................................................. 9
2.1.2
SPI with CPHA = 0 and CPOL = 1 .............................................................. 9
Implementing SPI Formats with CPHA = 1 ............................................................... 9
2.2.1
SPI with SIO and CPHA = 1, CPOL = 0...................................................... 9
2.2.2
SPI with SIO and CPHA = 1, CPOL = 1.................................................... 10
2.2.3
SPI with UART synchronous and CPHA = 1, CPOL = 0 ........................... 11
2.2.4
SPI with UART synchronous and CPHA = 1, CPOL = 0 ........................... 13
3 IMPLEMENTING SPI-SLAVE COMMUNICATION ......................................................... 14
3.1
Preface.................................................................................................................... 14
3.2
SPI-Slave Communication with LIN-U(S)ART ........................................................ 14
4 OVERVIEW OF SPI-MASTER CAPABILITY OF SEVERAL MCU FAMILIES ............... 15
4.1
SPI capability table.................................................................................................. 15
5 APPENDIX A ................................................................................................................... 16
5.1
Related documents ................................................................................................. 16
5.2
Software example archives ..................................................................................... 16
MCU-AN-30002-E-V13
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© Fujitsu Microelectronics Europe GmbH
PERFORMING SPI
Introduction
0 Introduction
It is said that SPI (Serial Peripheral Interface) is a simple communication between two digital
devices. Because of no general specification and much different formats, SPI is not so
simple at all.
This application note describes the most common SPI formats and how to implement them
on Fujitsu 8-, and16-Bit MCUs.
© Fujitsu Microelectronics Europe GmbH
-5-
MCU-AN-300002-E-V13
PERFORMING SPI
Chapter 1 SPI Formats
1 SPI Formats
THIS CHAPTER DESCRIBES THE MOST COMMON SPI FORMATS
1.1
General SPI
SPI is a single master single slave synchronous serial communication. Each data bit from
and to the master has its own clock pulse. Therefore SPI uses at least three different
signals:
1. SCK
Serial Clock
2. SI
Serial Input (Data from Slave to Master)
3. SO
Serial Output (Data from Master to Slave)
Some SPI formats use a fourth signal called “Chip Select” (CS) which enables the
communication by the master. This signal can be positive or negative active.
1.2
SPI Clock (SCK)
Because there exists no common SPI specification, the timing of the SPI clock signal is
device dependent and it seems so, that every producer uses its own timing.
For most SPI protocols four different settings are possible, which are mostly defined by the
internal SPI master control settings: CPOL (Clock polarity) and CPHA (Clock phase).
•
CPOL defines the active state of the SPI serial clock and thus the mark level.
•
CPHA defines the clock phase in respect of the SO-data bit.
There is no common classification of SPI protocols and SPI devices, which defines the
settings of CPOL and CPHA in respect of the protocol itself. So this document defines the
settings as follows:
•
CPOL = 0 :
SPI clock has mark level “0”
•
CPOL = 1 :
SPI clock has mark level “1”
•
CPHA = 0 :
SPI clock is delayed by a half bit time in respect of SO-data bit
•
CPHA = 1 :
SPI clock is synchronous to SO-data bits
1.3
Data direction
In the most SPI formats the serial data direction is MSB first.
1.4
Communication speed
The transfer rate of SPI communication is defined by the hardware itself. Mostly the speed is
limited by set-up and hold timing of the data signals.
SPI is used in a wide communication speed range. The range reaches from some K Bits/s to
some M Bits/s.
MCU-AN-30002-E-V13
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© Fujitsu Microelectronics Europe GmbH
PERFORMING SPI
Chapter 1 SPI Formats
1.5
SPI protocols
This section describes the most common different SPI protocol timings.
1.5.1 CPOL = 1, CPHA = 1
This SPI format is in accordance with the “standard” serial synchronous format. The timing of
the signals is shown in the illustration below:
1. SPI clock in phase with data (mark level = “1”)
CS/CS
tCYCLE
= Bit time
SCK
SO
D7
D6
D5
D4
D3
D2
D1
D0
1.5.2 CPOL = 0, CPHA = 1
This SPI format is in accordance with the “standard” serial synchronous format with inverted
clock signal.
2. SPI clock in phase with data (mark level = “0”, inverted)
CS/CS
SCK
SO
D7
D6
D5
© Fujitsu Microelectronics Europe GmbH
D4
D3
-7-
D2
D1
D0
MCU-AN-300002-E-V13
PERFORMING SPI
Chapter 1 SPI Formats
1.5.3 CPOL = 1, CPHA = 0
In this SPI format the clock signal is delayed by a half bit time to the “standard” synchronous
format.
3. SPI clock delayed by half bit time (mark level = “1”)
CS/CS
SCK
SO
D7
D6
D5
D4
D3
D2
D1
D0
Note, that in this format the first data bit has to be set on SO before the first clock pulse
occurs.
1.5.4 CPOL = 0, CPHA = 0
In this SPI format the clock signal is delayed by a half bit time to the “standard” synchronous
protocol and the clock signal is inverted.
3. SPI clock delayed by half bit time (mark level = “0”, inverted)
CS/CS
SCK
SO
D7
D6
D5
D4
D3
D2
D1
D0
Note, that in this format the first data bit has to be set on SO before the first clock pulse
occurs.
MCU-AN-30002-E-V13
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© Fujitsu Microelectronics Europe GmbH
PERFORMING SPI
Chapter 2 Implementing SPI-Master Communication
2 Implementing SPI-Master Communication
THIS CHAPTER DESCRIBES HOW TO IMPLEMENT THE DIFFERENT SPI FORMATS
2.1
Implementing SPI Formats with CPHA = 1
2.1.1 SPI with CPHA = 1 and CPOL = 1
This SPI format is available for all Fujitsu SIO interfaces.
Fujitsu UARTs with synchronous mode can also handle this format.
2.1.2 SPI with CPHA = 1 and CPOL = 0
This SPI format is available for all Fujitsu SIO interfaces with serial clock inversion (NEGBit).
Fujitsu UARTs with synchronous mode and serial clock inversion can also handle this format
(NEG- or SCES-Bit).
2.2
Implementing SPI Formats with CPHA = 0
This format is available for the LIN-UART since MB90340 series. To implement this the
programmer has to use synchronous mode and SCDE = 1 (Serial Clock Delay Enable) and
SCES = x (Serial Clock Edge Select, means CPOL = x).
For all other SIOs or UARTs some tricks have to do.
2.2.1 SPI with SIO and CPHA = 0, CPOL = 1
The SIO can only handle SPI formats with CPHA = 1 in its normal operation mode. When
external shift clock mode is selected, the SIO can be clocked by the toggling the port in
respect of its SCK pin.
An undocumented feature is that the SIO can also be clocked by toggling the NEG bit of the
SES register (Serial Edge Select). Thus it is possible to set the first data bit to SO before the
clock is generated via the port pin.
The following C code shows an example of this method. Note, that the maximum
communication speed depends on the execution time of the instructions (MCU speed) and
the function SPI_Byte must not be broken by an Interrupt:
Example C code of CPHA = 0 and CPOL = 1 with SIO
void InitSIO (void)
{
PDR4 = 0x80;
DDR4 = 0x80;
SMCS_SOE = 1;
SMCS_SCOE = 0;
SES2_NEG = 1;
SMCS_STOP = 0;
SMCS_SMD = 0x05;
SMCS_BDS = 1;
// SCK2 port 47 pin MB90540 series
// SCK2 set to "1"
//
//
//
//
//
//
Serial Output enable
Internal serial clock disable
Invert clock
Reset STOP
External shift clock mode
Set MSB first
}
© Fujitsu Microelectronics Europe GmbH
6
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MCU-AN-300002-E-V13
PERFORMING SPI
Chapter 2 Implementing SPI-Master Communication
7
unsigned char SPI_Byte(data)
{
SDR = data;
// Write data to shifter
SMCS_STRT = 1;
// Set communication start
}
SES2_NEG = 0;
SES2_NEG = 1;
// Generate "internal clock" pulse
//
to set first data bit on SOT2
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
// generate 8 clock pulses on SCK2
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
SES2_NEG = 0;
SES2_NEG = 1;
// "internal clock" pulse to fulfill
//
SIO communication
data = SDR;
return data;
// read shifter
Note: A CS signal can easily performed using another port pin.
2.2.2 SPI with SIO and CPHA = 0, CPOL = 0
The method for CPOL = 0 is much like the method above (2.2.1).
The following C code shows an example of this method. Note, that the maximum
communication speed also depends on the execution time of the instructions (MCU speed)
and the function SPI_Byte must not be broken by an Interrupt:
Example C code of CPHA = 0 and CPOL = 0 with SIO
void InitSIO (void)
{
PDR4 = 0x00;
DDR4 = 0x80;
SMCS_SOE = 1;
SMCS_SCOE = 0;
SES2_NEG = 0;
SMCS_STOP = 0;
SMCS_SMD = 0x05;
SMCS_BDS = 1;
// SCK2 port 47 pin MB90540 series
// SCK2 set to "0"
//
//
//
//
//
//
Serial Output enable
Internal serial clock disable
Normal clock
Reset STOP
External shift clock mode
Set MSB first
}
6
MCU-AN-30002-E-V13
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© Fujitsu Microelectronics Europe GmbH
PERFORMING SPI
Chapter 2 Implementing SPI-Master Communication
7
unsigned char SPI_Byte(data)
{
SDR = data;
// Write data to shifter
SMCS_STRT = 1;
// Set communication start
SES2_NEG = 1;
SES2_NEG = 0;
// Generate "internal clock" pulse
//
to set first data bit on SOT2
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
PDR4_P47
// generate 8 clock pulses on SCK2
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
SES2_NEG = 1;
SES2_NEG = 0;
// "internal clock" pulse to fulfill
//
SIO communication
data = SDR;
return data;
// read shifter
}
Note: A CS signal can easily performed using another port pin.
2.2.3 SPI with UART synchronous and CPHA = 0, CPOL = 1
The method for SPI (CPHA = 0 and CPOL = 1) with a UART in synchronous mode is similar
to the method used with the SIO.
In this example the clock of the UART is also generated internal with toggling the NEG-Bit
and generating an “external” clock via the Port state of the corresponding SCK pin.
Note, that this example only works for UARTs, which support a synchronous serial mode
and a prescaler, not a reload counter. Those UARTs are identifiable by the CDC register
(Clock Division Control).
Example C code of CPHA = 0 and CPOL = 1 with UART synchronous
void InitUART(void)
{
SMR1_MD1 = 1;
SMR1_MD0 = 0;
SMR1_CS2 = 1;
SMR1_CS1 = 1;
SMR1_CS0 = 1;
SMR1_SCKE = 0;
// Set synchronous mode
// Set external clock source
// External clock
© Fujitsu Microelectronics Europe GmbH
- 11 -
6
MCU-AN-300002-E-V13
PERFORMING SPI
Chapter 2 Implementing SPI-Master Communication
7
SMR1_SOE = 1;
SES1_NEG = 1;
SCR1_TXE = 1;
// Serial Output Enable
// Invert Clock
// Transmission Enable
PDR4 = 0x10;
DDR4 = 0x10;
// SCK1 Port 44 pin on MB90540 series
// SCK1 set to "1"
}
unsigned char SPI_Byte(data)
{
SODR1 = data;
// Write data to transmission register
}
DI();
// Disable all interrupts
SES1_NEG = 0;
SES1_NEG = 1;
// Generate "internal clock" pulse
//
to set first data bit on SOT1
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
// generate 8 clock pulses on SCK1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
SES1_NEG = 0;
SES1_NEG = 1;
// "internal clock" pulse to fulfill
//
serial task
EI();
// Enable all interrupts (optional)
data = SIDR;
return data;
// read from reception register
Note: A CS signal can easily performed using another port pin.
MCU-AN-30002-E-V13
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© Fujitsu Microelectronics Europe GmbH
PERFORMING SPI
Chapter 2 Implementing SPI-Master Communication
2.2.4 SPI with UART synchronous and CPHA = 0, CPOL = 1
The method for SPI (CPHA = 0 and CPOL = 1) with a UART in synchronous mode is much
like the example above (2.2.3)
Example C code of CPHA = 0 and CPOL = 1 with UART synchronous
void InitUART(void)
{
SMR1_MD1 = 1;
SMR1_MD0 = 0;
SMR1_CS2 = 1;
SMR1_CS1 = 1;
SMR1_CS0 = 1;
SMR1_SCKE = 0;
SMR1_SOE = 1;
SES1_NEG = 0;
SCR1_TXE = 1;
PDR4 = 0x00;
DDR4 = 0x10;
// Set synchronous mode
// Set external clock source
//
//
//
//
External clock
Serial Output Enable
Normal Clock
Transmission Enable
// SCK1 Port 44 pin on MB90540 series
// SCK1 set to "0"
}
unsigned char SPI_Byte(data)
{
SODR1 = data;
// Write data to transmission register
}
DI();
// Disable all interrupts
SES1_NEG = 1;
SES1_NEG = 0;
// Generate "internal clock" pulse
//
to set first data bit on SOT1
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
PDR4_P44
// generate 8 clock pulses on SCK1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
1;
0;
SES1_NEG = 1;
SES1_NEG = 0;
// "internal clock" pulse to fulfill
//
serial task
EI();
// Enable all interrupts (optional)
data = SIDR;
return data;
// read from reception register
Note: A CS signal can easily performed using another port pin.
© Fujitsu Microelectronics Europe GmbH
- 13 -
MCU-AN-300002-E-V13
PERFORMING SPI
Chapter 3 Implementing SPI-Slave Communication
3 Implementing SPI-Slave Communication
HOW TO IMPLEMENT SPI SLAVE COMMUNICATION
3.1
Preface
SPI is a 1 master to n slave communication. All described SPI modes are valid for both
master and slave. The main difference is, that a slave does not generate a serial clock
signal, but is clocked by the master.
3.2
SPI-Slave Communication with LIN-U(S)ART
The following program flow should be used to set the LIN-U(S)ART (to be found e. g. in the
MB90340 series) in the synchronous serial SPI mode, so that its state is well defined for
communication.
Register
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
CPHA = 0
CPOL = 0
CPHA = 0
SSR
0x00
0x00
0x00
0x00
Disallow interrupts, if
previously enabled
SCR
0x04
0x04
0x04
0x04
Cut of all possible previous
communication, clear
possible reception errors
SMR
0xB1
0xB1
0xB1
0xB1
Mode2, One-to-one external
clock, enable SOT pin
ECCR
0x20
0x20
0x30
0x30
Slave mode, adjust Clock
phase
ESCR
0x00
0x01
0x00
0x01
Adjust Clock polarity
SMR
0xB9
0xB9
0xB9
0xB9
Reset LIN-U(S)ART
SSR*
0x03
0x03
0x03
0x03
Allow interrupts (optional)
SCR
0x03
0x03
0x03
0x03
Allow communication
Remark
* optional - only needed, if interrupts are used
Note, that the TXE and RXE control bits of the Serial Communication Register (SCR) should
be enabled as the last step in the initialization process. Otherwise a correct behaviour of the
LIN-U(S)ART cannot be guaranteed.
MCU-AN-30002-E-V13
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© Fujitsu Microelectronics Europe GmbH
PERFORMING SPI
Chapter 4 Overview of SPI-Master capability of several MCU families
4 Overview of SPI-Master capability of several MCU families
THE SPI-MASTER CAPABILITY OF UARTS IN SEVERAL MCU FAMILIES
4.1
SPI capability table
Note, that this table gives an overview of the UART SPI-Master mode capability without “port
clocking”.
MCU family
CPOL = 1
CPOL = 0
CPHA = 1
CPHA = 0
MB89210
X
X
X
X1
MB90330/335
X2
X2
X2
X2
MB90340/350/360
X
X
X
X
MB90390
X
3
X
X3
MB90385
X
X
MB90495
X
X
MB90540
X
X
X
3
X
X3
MB90945
X
X
MB95xxx
X
X
X
X
MB96xxx
X
X
X
X
X = setting possible in serial synchronous mode of UART
1
delay only by 1 MCU clock, not by half serial communication bit time
only two combinations possible: CPOL = CPHA = 1 or CPOL = CPHA = 0
3
only UART3
2
© Fujitsu Microelectronics Europe GmbH
- 15 -
MCU-AN-300002-E-V13
PERFORMING SPI
Chapter 5 Appendix A
5 Appendix A
FURTHER INFORMATIONS
5.1
Related documents
•
an-900104-SPI_EEPROM
•
an-900105-SPI_ADC
•
an-900106-SPI_PORT
5.2
Software example archives
•
90340_uart_sync_spi_nm93cs46-v10.zip
•
90340_uart_sync_sio_max1286-v10.zip
Archives downloadable at:
http://www.fme.gsdc.de/gsdc.htm
N Microcontrollers N Software N Samples N Smpl16 N MB90340 Series
MCU-AN-30002-E-V13
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