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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300239-E-V11
F²MC-16FX FAMILY
16-BIT MICROCONTROLLER
MB96340
SOFTWARE PWM BY USE OF
DMA TRANSFER
APPLICATION NOTE
Software PWM by use of DMA Transfer
Revision History
Revision History
Date
2007-09-20
2009-04-02
Issue
V1.0 Markus Vogel
First version
V1.1 Markus Vogel
Some changes because of updated software example
This document contains 26 pages.
MCU-AN-300239-E-V11
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© Fujitsu Microelectronics Europe GmbH
Software PWM by use of DMA Transfer
Warranty and Disclaimer
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permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties
and liabilities for the performance of the Product and any consequential damages in cases of
unauthorised decompiling and/or reverse engineering and/or disassembling. Note, all these
products are intended and must only be used in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform
substantially in accordance with the accompanying written materials for a period of 90
days from the date of receipt by the customer. Concerning the hardware components
of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be
free from defects in material and workmanship under use and service as specified in
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2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire
liability and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics
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or replacement of the Product or parts thereof, if the Product is returned to Fujitsu
Microelectronics Europe GmbH in original packing and without further defects
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Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
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the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the
remaining stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
-3-
MCU-AN-300239-E-V11
Software PWM by use of DMA Transfer
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION.............................................................................................................. 5
2 PRINCIPLE ...................................................................................................................... 6
3 SOFTWARE................................................................................................................... 10
3.1
General................................................................................................................. 10
3.2
Initialize IO Ports ................................................................................................. 11
3.3
Initialize Reload Timer......................................................................................... 11
3.4
Initialize DMA Channel ........................................................................................ 13
3.5
Setup PWM Table ................................................................................................ 14
3.6
Start PWM ............................................................................................................ 14
3.7
Interrupt Handler ................................................................................................. 14
3.8
Interrupt levels and interrupt table..................................................................... 15
3.9
Main...................................................................................................................... 15
4 PERFORMANCE ........................................................................................................... 16
4.1
4.2
Accuracy .............................................................................................................. 16
4.1.1
Accuracy given by prescaler and reload value.................................... 16
4.1.2
Influence of CPU access on peripheral bus......................................... 21
4.1.3
Influence of other DMA channel operations ........................................ 23
4.1.4
Influence of other interrupts ................................................................. 23
Influence on CPU operation................................................................................ 24
5 APPENDIX ..................................................................................................................... 26
5.1
Additional Information ........................................................................................ 26
5.2
Figures ................................................................................................................. 26
MCU-AN-300239-E-V11
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© Fujitsu Microelectronics Europe GmbH
Software PWM by use of DMA Transfer
Chapter 1 Introduction
1 Introduction
This application note describes the possibility of adding additional, preferably low
speed, software PWM channels to the already implemented hardware resources
(16bit-PPG). These low speed PWM signals can be for example used for LED or lamp
dimming.
By use of a reload timer, a DMA channel and IO ports, up to 16 additional channels
can be implemented. Using the DMA function influences CPU operation only very low.
This document explains the basic principle and shows example code for 8/16
channels with 8bit PWM resolution. It is possible, of course, to add more than these
16 channels if more DMA channels and IO ports are used. Also it is possible to
change resolution of the PWM signal according to needs and available RAM/ROM
space.
Please refer also to the software example 96340_sw_pwm_rlt_dma_io.
The application note and the software example are based on the MB96340 series
(MB96F346RSA), but can be easily transferred to other MB96xxx series devices.
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 2 Principle
2 Principle
This chapter presents the basic idea of the software PWM.
Basic idea of the software PWM via DMA is the transfer of a predefined PWM table via
DMA byte or word transfer from the memory to Port Data Register of one single or two
consecutive IO ports of the MCU without CPU interruption.
Depending on application needs the PWM table can be located in Flash ROM (fixed
duty value) or in RAM (variable duty value).
DMA transfer
Memory
- triggered by reload timer
pwm table
IO port
0
0
DMA source address pointer
0
with auto incremented function
0
0
1
1
1
Figure 1: Basic Idea
The PWM signal is divided in smaller parts of same length. Number of these parts
depends on the resolution. Figure 2 shows an example of 8 parts, which equals 3bit
resolution. Most common will be resolution of 8bit which divides the PWM signal into
256 parts.
For each part, the PWM table has to have an entry in the PWM table, which is
outputted directly to the IO port by DMA transfer of this value to the Port Data
Register of the adequate IO port. This DMA transfer is triggered by an overflow of the
reload timer. Therefore the reload timer’s cycle time has to be adjusted to the duration
of such a timing part.
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Software PWM by use of DMA Transfer
Chapter 2 Principle
Re loadTimerCycleTime =
PWMFrequency
2 RESOLUTION
0 0 0 0 0 1 1 1
Reload Timer Cycle Time
PWM Period:
Reload Timer Cycle Time * DMA Transfer Count
Figure 2: PWM Signal
The reload timer overflow generates an interrupt request. This interrupt request is not
handled by the CPU, but triggers the automatic DMA transfer of one byte or word. So
there is no influence on CPU operation in this case. The reload timer’s interrupt
request is cleared also automatically by the DMA.
DMA automatically transfers the selected amount of data (byte or word) from the PWM
table. DMA source address register has to be automatically updated for each transfer
(location in the PWM table), whereas the destination address register keeps on the
same value (Port Data Register). DMA transfer count has to be set to 2RESOLUTION for
byte transfer, 2x 2RESOLUTION for word transfer in the beginning. With each DMA
transfer, this value is decremented by 1 or 2, depending on transfer width. When the
transfer count reaches 0, then the resource interrupt is not handled by the DMA
anymore and interrupt request is forwarded to CPU.
Now CPU operation is shortly interrupted to clear reload timer / DMA interrupt request
and to reinitialize DMA channel for next PWM cycle. After that, next PWM period is
started again via DMA transfer.
0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1
ISR: re-init DMA
ISR: re-init DMA
Figure 3: PWM Generation
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 2 Principle
MCU internal
MSB
LSB
Address
1
1
1
1
1
1
1
1
+1
1
1
1
1
1
1
1
1
+2
1
1
1
1
1
1
0
0
+3
1
1
1
1
1
1
0
0
+4
1
1
1
1
0
0
0
0
+5
1
1
1
1
0
0
0
0
+6
1
1
0
0
0
0
0
0
+7
1
1
0
0
0
0
0
0
Byte to be
transferred
PWM
Table in
Memory
DMA
transfer
7
6
5
4
3
2
1
0
PDRx[n]
Pins
0
+1
+2
+3
+4
PWM
output
+5
+6
+7
0
+1
…
t
t
t
t
t
t
t
t
Figure 4: 3bit PWM signal generation
Figure 4 shows the assignment of values in a PWM table in memory to the adequate
IO pins for an example with 8 channels and 3bit resolution. With one DMA transfer,
one line (equals one byte!) is transferred to the port data register of an IO port and
outputted to IO pins.
MCU-AN-300239-E-V11
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Software PWM by use of DMA Transfer
Chapter 2 Principle
Reload
timer
cycle time
Figure 5: Extract from SW-PWM signal with 8bit resolution
Figure 5 shows a screenshot for an 8bit PWM signal at one single pin. You can see
PWM signals rising edge and the output signal of the reload timer. TOT0 pin is
toggled with each reload timer interrupt, so each high or low phase equals the reload
timer cycle time.
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 3 Software
3 Software
This chapter show example code for realising software PWM.
3.1
General
For the following sample code, some general definitions are made which include the
resolution of the PWM signal, the number of channels and the PWM frequency.
/*---------------------------------------------------------------------*/
/*****
S E T T I N G S ******
*/
/*---------------------------------------------------------------------*/
#define RES8BIT
#define RES9BIT
#define RES10BIT
256u
512u
1024u
/* 8bit pwm resolution */
/* 9bit pwm resolution */
/* 10bit pwm resolution */
/***********************************************************************/
#define RESOLUTION
RES8BIT
/* <<**** set pwm resolution here */
/***********************************************************************/
#define CH8
#define CH16
0u
1u
/* 8 pwm channels -> one IO port */
/* 16 pwm channels -> two IO ports */
/***********************************************************************/
#define NUMBER_OF_CHANNELS CH8 /* <<*** set number of pwm channels here*/
/***********************************************************************/
/***********************************************************************/
#define PWM_FREQUENCY
100
/* <<***** set pwm frequency in Hz here */
/* range from 10Hz to 300Hz will be
*/
/* below 0.5% frequency deviation
*/
/* with initial values of demo sample
*/
/***********************************************************************/
As stated in the introduction, PWM frequency should be low to minimize impact on
CPU operation. Some more information on PWM frequencies and PWM accuracy can
be found in chapter 4 of this application note.
The definition of the number of channels will be used later on when initializing the IO
ports and setting up the DMA channel.
The value defined as resolution is the number of steps the PWM signal is divided to.
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Software PWM by use of DMA Transfer
Chapter 3 Software
3.2
Initialize IO Ports
The function init_gpio() initializes the used IO pins to output mode. Depending on the
selected number of channels one or two consecutive IO ports are used. The ports are
set to an initial value and data direction is set to output.
void init_gpio(void)
{
PDR00 = 0x00;
DDR00 = 0xFF;
}
/* set P00-P07 to low level */
/* set pins P00-P07 to output */
#if (NUMBER_OF_CHANNELS == CH16)
PDR01 = 0x00;
/* set P10-P17 to low level */
DDR01 = 0xFF;
/* set pins P10-P17 to output */
#endif
If you want to use a pin within an IO port assigned to the software PWM in different
function, it is possible to use it in resource mode (e.g. analogue input, CAN-TX/RX
etc.) or as digital input using the External Pins State Register (EPSRx), not the PDRx
register. The adequate bit of the data transferred to the Port Data Register of this port
is then not outputted to the pin. It is not possible to use the pin in digital output mode
as the DMA transfer regularly would overwrite the PDRxx register with the value
defined in the PWM table.
3.3
Initialize Reload Timer
The reload value for the reload timer can be calculated with following formula based
on peripheral clock 1 frequency (CLKP1), the PWM frequency and the PWM
resolution. It is necessary to select a prescaler value for the input signal of the reload
timer.
Re loadValue
CLKP1
Pr escaler 2
RESOLUTION
PWMfrequency
1
Combination of the selected prescaler value and the calculated reload value are the
basic values for the PWM accuracy. As reload value has to be rounded to an integer
value, for better accuracy try to select a prescaler value that reload value fits best.
For initialization of the reload timer, first stop counter operation. Set reload and
prescaler value, set timer to reload mode, clear interrupt flag and enable interrupt
request. Set activation by software trigger (done in main function) and enable counter
operation.
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 3 Software
#define
#define
#define
#define
#define
#define
PRESCALER2
PRESCALER4
PRESCALER8
PRESCALER16
PRESCALER32
PRESCALER64
4u
0u
5u
1u
6u
2u
/*
/*
/*
/*
/*
/*
prescaler
prescaler
prescaler
prescaler
prescaler
prescaler
#define RELOAD_PRESCALER PRESCALER4
#define CLKP1_SPEED
56000000
for
for
for
for
for
for
reload
reload
reload
reload
reload
reload
timer
timer
timer
timer
timer
timer
0:
0:
0:
0:
0:
0:
2^1
2^2
2^3
2^4
2^5
2^6
=
=
=
=
=
=
div2 */
div4 */
div8 */
div16 */
div32 */
div64 */
/* prescaler selection */
/* set CLKP1 speed here */
/* set correct divider for reload value calculation */
#if (RELOAD_PRESCALER == PRESCALER2)
#define DIV_VAL
2lu
#endif
#if (RELOAD_PRESCALER == PRESCALER4)
#define DIV_VAL
4lu
#endif
#if (RELOAD_PRESCALER == PRESCALER8)
#define DIV_VAL
8lu
#endif
#if (RELOAD_PRESCALER == PRESCALER16)
#define DIV_VAL
16lu
#endif
#if (RELOAD_PRESCALER == PRESCALER32)
#define DIV_VAL
32lu
#endif
#if (RELOAD_PRESCALER == PRESCALER64)
#define DIV_VAL
64lu
#endif
#define RELOAD_VALUE CLKP1_SPEED/(DIV_VAL*RESOLUTION*PWM_FREQUENCY)-1
/* calculate reload value for reload timer 0 */
void init_rlt0(void)
{
TMCSR0_CNTE = 0;
/* stop counter operation */
TMRLR0 = RELOAD_VALUE; /* set reload value */
TMCSR0 = 0x005A | RELOAD_PRESCALER<<10;
/* set presc., reload mode, interrupt enable, TOT0 output enable */
}
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Software PWM by use of DMA Transfer
Chapter 3 Software
3.4
Initialize DMA Channel
Select correct interrupt number as DMA trigger source (51 is reload timer channel 0).
Workaround for all unused DMA trigger sources (setting to 12 - delayed interrupt) is
only necessary for some 16FX devices.
Set data transfer count to the number of steps (2RESOLUTION). Set I/O address pointer to
PDR00 register address and buffer address pointer to start address of pwm_table.
Select no I/O pointer update, but buffer pointer update. Set transfer width to byte or
word, depending on number of channels. Select direction of transfer from buffer to
I/O.
Enable DMA channel operation.
/* lookup table for pwm data for 8 channels */
#if (NUMBER_OF_CHANNELS == CH8)
char pwm_table[RESOLUTION];
#else if (NUMBER_OF_CHANNELS == CH16)
short int pwm_table[RESOLUTION];
#endif
void init_dma(void)
{
DER = 0x0000;
/* disable DMA channel 0 */
DISEL0 = 51;
/* DMA trigger: RLT0 interrupt */
DISEL1 = 12;
/* set all not used DMA channels to a non-used
interrupt source */
/* refer to functional limitation list for details */
/* this workaround is not needed for all devices */
DISEL2
DISEL3
DISEL4
DISEL5
=
=
=
=
12;
12;
12;
12;
DCT0 = RESOLUTION;
/* transfer count 256/512/1024 bytes for
8/9/10bit resolution */
IOA0 = (unsigned int) &PDR00;
/* buffer address: pwm lookup
BAPH0 = (__far unsigned long)
BAPM0 = (__far unsigned long)
BAPL0 = (__far unsigned long)
/* IO address: Port0 data register */
table */
&pwm_table[0] >> 16;
&pwm_table[0] >> 8;
&pwm_table[0] & 0xFF;
DMACS0 = 0x12 | (NUMBER_OF_CHANNELS<<3);
/* no IOA update, BAP update, transfer width, BAP -> IOA */
}
DER = 0x0001;
/* enable DMA channel 0 */
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 3 Software
3.5
Setup PWM Table
Initialize the pwm_table with 0xFF, which equals 100% duty cycle. On SK-16FX100PMC this equals all LEDs on 7-segment display off.
int pwm_config[(NUMBER_OF_CHANNELS+1)*8];
/* save actual configuration of pwm channel */
void init_pwm_table(void)
{
volatile int j;
for(j=0;j<RESOLUTION;j++)
{
#if (NUMBER_OF_CHANNELS == CH8)
pwm_table[j] = 0xFF;
/* fill table with 1 -> all LEDs off */
#else if (NUMBER_OF_CHANNELS == CH16)
pwm_table[j] = 0xFFFF;
/* fill table with 1 -> all LEDs off */
#endif
}
3.6
Start PWM
Function start_pwm() triggers the reload counter.
void start_pwm (void)
{
TMCSR0_TRG = 1;
}
3.7
/* start RLT0 */
Interrupt Handler
In the interrupt handler routine the DMA channel is re-initialized for next transfer.
Clear first reload timer interrupt flag and then clear DMA interrupt.
__interrupt void irq_rlt_dma (void)
{
init_dma();
/* re-init DMA channel */
TMCSR0_UF = 0;
/* Clear reload timer 0 interrupt request */
DSR = 0x0000;
/* Clear DMA interrupt */
}
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© Fujitsu Microelectronics Europe GmbH
Software PWM by use of DMA Transfer
Chapter 3 Software
3.8
Interrupt levels and interrupt table
Set interrupt level for reload timer 0 to a value below 7. Set correct interrupt vector for
reload timer 0 in interrupt vector table.
#define MIN_ICR
#define MAX_ICR
12
96
#define DEFAULT_ILM_MASK 7
void InitIrqLevels(void)
{
volatile int irq;
for (irq = MIN_ICR; irq <= MAX_ICR; irq++)
{
ICR = (irq << 8) | DEFAULT_ILM_MASK;
}
ICR = 51<<8 | 6; /* change interrupt level of reload timer 0 */
}
__interrupt void DefaultIRQHandler (void);
__interrupt void irq_rlt_dma (void);
...
#pragma intvect DefaultIRQHandler 50
#pragma intvect irq_rlt_dma
51
#pragma intvect DefaultIRQHandler 52
...
3.9
/* PPG15
/* RLT0
/* RLT1
*/
*/
*/
Main
Function main() calls all the initialization functions, globally enables the interrupt an
then triggers the reload timer. Then it runs in a while loop, which can be replaced by
other code to be executed.
void main(void)
{
InitIrqLevels();
__set_il(7);
/* allow all levels
initialize
initialize
initialize
initialize
*/
init_gpio();
init_rlt0();
init_dma();
init_pwm_table();
/*
/*
/*
/*
IO ports */
Reload Timer 0 */
DMA channel 0 */
PWM lookup table-duty cycle 100% */
__EI();
/* globally enable interrupts */
start_pwm();
/* start pwm generation */
while(1)
{
/* here can be your source code */
}
}
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 4 Performance
4 Performance
This chapter gives information on accuracy and performance influence.
4.1
Accuracy
4.1.1 Accuracy given by prescaler and reload value
As the reload timer is the time base for the software PWM, it is necessary to select
prescaler and reload value so that a minimum difference between calculated and real
timing is reached.
Example 1: CLKP1 = 56MHz, prescaler = 4; PWM = 100Hz, 8bit resolution, automatic
calculation like shown in the example before (take only integer part of result)
56000000
1 = 545.875
4 2 8 100
Re loadValue
f RLT
56000000
=
= 25688 Hz
4 Re loadValue
f PWM =
545
12844 Hz @ TOT 0
56000000
= 100.34 Hz
4 2 Re loadValue
8
Reload timer toggles TOT0 pin
once each timer period by
reaching
an
overflow
and
generating an interrupt. So only
half the frequency of the timer
can be seen at the pin!
Example 2: CLKP1 = 56MHz, prescaler = 4; PWM = 100Hz, 8bit resolution, manual
calculation (round up to nearest integer), duty value set to 50%
56000000
1 = 545.875
4 2 8 100
Re loadValue
546
f RLT =
56000000
= 25641Hz
4 Re loadValue
f PWM =
56000000
= 100.16 Hz
4 2 Re loadValue
12882 Hz @ TOT 0
8
If the reload value is closer to an integer value, the reload timer cycle time and
therefore the PWM signal frequency itself will fit to the expected values.
Figure 6 and Figure 7 show screenshots for the settings from example 2. As you can
see, the reload timer output and the PWM signal very well fit to expected values.
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Software PWM by use of DMA Transfer
Chapter 4 Performance
Figure 6: Reload Timer output for example 2
Figure 7: PWM signal output at IO pin for example 2
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 4 Performance
Figure 8 to Figure 11 show more detailed screenshots of the rising and falling edges
of the PWM signal (triggered on PWM signal). As you can see, there is a delay
between the edge of reload timer output signal and edges of the PWM signal.
At rising and falling edge of PWM signal, there is a fixed delay of about 140ns (176ns36ns @ rising edge, 195ns-54ns @ falling edge). These 140ns, which are around 8
internal clock cycles (CLKB & CLKP1; 17ns @ 56MHz) are needed internally for
detecting the interrupt signal, triggering the DMA transfer, reading data from RAM and
transferring to PDR register to output the changed signal.
You can see also a jitter in the delay of +36ns for the rising edge (~2 CPU cycles) and
+54ns for the falling edge (~3 CPU cycles), which sum up to a maximum jitter of +90ns
for one period of the PWM signal. Taking the long period time of 10ms @ 100Hz as
well as taking the resolution of ~78ms (reload timer cycle time) into account, this
small jitter can be disregarded in nearly all cases.
Figure 8: Rising Edge for example 2 - Jitter
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© Fujitsu Microelectronics Europe GmbH
Software PWM by use of DMA Transfer
Chapter 4 Performance
Figure 9: Rising Edge for example 2 – Delay
Figure 10: Falling Edge for example 2 - Jitter
© Fujitsu Microelectronics Europe GmbH
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Software PWM by use of DMA Transfer
Chapter 4 Performance
Figure 11: Falling Edge for example 2 - Delay
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© Fujitsu Microelectronics Europe GmbH
Software PWM by use of DMA Transfer
Chapter 4 Performance
4.1.2 Influence of CPU access on peripheral bus
To measure the influence of CPU accesses to the peripheral bus, a small code writing
to and reading from another port data register is implemented inside the while-loop of
previous example. This short example represents bus accesses as they may be
implemented in application. There are always short releases of the bus as instructions
to update registers or branch instruction are implemented. 100% access to the
peripheral bus (only MOV A,I:09 instruction) is absolutely unlikely.
See C source code and generated assembly code below:
234:
while(1)
235:
{
236:
buf = PDR09;
FC02F5: 5009
MOV
A,I:09
FC02F7: 98
MOVW
RW0,A
FC02F8: 3001
ADD
A,#01
FC02FA: 98
MOVW
RW0,A
MOV
I:09,A
BRA
FC02F5
237:
buf++;
238:
PDR09 = buf;
FC02FB: 5109
239:
Write to
peripheral bus
}
FC02FD: 60F6
Read from
peripheral bus
240: }
Figure 12 and Figure 13 show the rising edge of the PWM signal in correlation to the
reload timer output signal. You can see again same jitter of +36ns like without the
CPU access to the peripheral bus, but now the delay itself is increased to 194ns
(230ns-36ns, ~ 13 CPU cycles) due to blocked internal busses by CPU access.
Regarding the long period time of PWM signal and reload timer cycle time, again this
value is negligibly small.
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Software PWM by use of DMA Transfer
Chapter 4 Performance
Figure 12: Rising Edge with CPU influence – Jitter
Figure 13: Rising Edge with CPU influence - Delay
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Software PWM by use of DMA Transfer
Chapter 4 Performance
4.1.3 Influence of other DMA channel operations
The 16FX Family offers up to 16 DMA transfer channels that can be used
independently. The channels have different priorities for requesting the internal
busses, starting from channel 0 with highest priority down to channel 16 with lowest
priority.
If two resources ask for a DMA transfer at the same time, DMA channel with lower
number and therefore higher priority will get access to the bus. Nevertheless, the
higher prior DMA channel has to wait a currently running lower prior DMA transfer to
be ready. As on 16FX maximum amount of data to be transferred at one time is only a
16bit word, delay is very short (ideally two CPU cycles).
Therefore you have to analyze your system regarding DMA transfer with different
priorities if you phase problems with the accuracy of the PWM signal. For best
accuracy PWM DMA channel has to be highest priority. In this case only CPU request
for the bus is more important.
4.1.4 Influence of other interrupts
Different interrupt levels may also have an impact on the accuracy of the PWM signal.
Within a PWM cycle the interrupt level does not matter, as the interrupt requests are
only passed to the DMA controller to trigger a transfer, but at the end of one PWM
period the interrupt request is forwarded to the CPU, which exploits the level of an
incoming interrupt request before executing the adequate interrupt service routine.
So interrupts with higher priority or currently running interrupt service routines of
interrupts with the same priority may delay the execution of the interrupt service
routine to re-initialize the DMA transfer for the PWM. These interrupt service routines
are no problem if the execution of the PWM ISR (or rather the reload timer interrupt
service routine) is guaranteed within the time needed for one run of the reload timer
(reload timer cycle time).
Interrupts with lower priority are not problematic as they are interruptible by the PWM
ISR.
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Software PWM by use of DMA Transfer
Chapter 4 Performance
4.2
Influence on CPU operation
There should be hardly any influence of the software PWM generation on CPU
execution as the DMA transfer from the PWM table in RAM or ROM to IO register is
executed in parallel to CPU instruction execution. Only after a full PWM cycle when
the predefined number of DMA transfers is finished, CPU operation is shortly
interrupted for execution of the interrupt service routine. Here the DMA is re-initialized
and interrupt flags are cleared.
To measure the influence of the software PWM generation on CPU performance, a
simple implementation of Dhrystone benchmark V2.1 is used. Please keep in mind
that the final benchmark results are not optimized ones! Benchmark is executed with
not optimized standard settings just to show impact of the software PWM on
performance.
First Dhrystone test is run without generating software PWM. See logfile of
benchmark output:
DHRYSTONE BENCHMARK V2.1 FOR MB96F346RSA - SW-PWM OFF !!!
Dhrystone Benchmark, Version 2.1 (Language: C or C++)
Register option not selected
1000
10000
20000
40000
80000
160000
runs
runs
runs
runs
runs
runs
0.04
0.39
0.79
1.57
3.14
6.28
seconds
seconds
seconds
seconds
seconds
seconds
Final values (* implementation-dependent):
Int_Glob:
O.K.
Ch_1_Glob:
O.K.
Arr_1_Glob[8]: O.K.
Ptr_Glob->
Discr:
O.K.
Int_Comp:
O.K.
Next_Ptr_Glob->
Discr:
O.K.
Int_Comp:
O.K.
Int_1_Loc:
O.K.
Int_3_Loc:
O.K.
Str_1_Loc:
Str_2_Loc:
5
A
7
Bool_Glob:
Ch_2_Glob:
Arr_2_Glob8/7:
Ptr_Comp:
0 Enum_Comp:
17 Str_Comp:
Ptr_Comp:
0 Enum_Comp:
18 Str_Comp:
5 Int_2_Loc:
7 Enum_Loc:
O.K.
O.K.
WRONG
*
O.K.
O.K.
*
O.K.
O.K.
O.K.
O.K.
O.K.
O.K.
Microseconds for one run through Dhrystone:
Dhrystones per Second:
VAX MIPS rating =
1
B
28938
17234
2
DHRYSTONE PROGRAM, SOME
17234 same as above
1
DHRYSTONE PROGRAM, SOME
13
1
DHRYSTONE PROGRAM, 1'ST
DHRYSTONE PROGRAM, 2'ND
STRING
STRING
STRING
STRING
39.25
25476
14.50
DHRYSTONE END !!!
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Software PWM by use of DMA Transfer
Chapter 4 Performance
Secondly, Dhrystone test was run with software PWM generated in background.
Settings for PWM are the same as used in example 2 in chapter 4.1.1.
DHRYSTONE BENCHMARK V2.1 FOR MB96F346RSA - SW-PWM ON !!!
Dhrystone Benchmark, Version 2.1 (Language: C or C++)
Register option not selected
1000
10000
20000
40000
80000
160000
runs
runs
runs
runs
runs
runs
0.04
0.40
0.79
1.58
3.16
6.32
seconds
seconds
seconds
seconds
seconds
seconds
Final values (* implementation-dependent):
Int_Glob:
O.K.
Ch_1_Glob:
O.K.
Arr_1_Glob[8]: O.K.
Ptr_Glob->
Discr:
O.K.
Int_Comp:
O.K.
Next_Ptr_Glob->
Discr:
O.K.
Int_Comp:
O.K.
Int_1_Loc:
O.K.
Int_3_Loc:
O.K.
Str_1_Loc:
Str_2_Loc:
5
A
7
Bool_Glob:
Ch_2_Glob:
Arr_2_Glob8/7:
Ptr_Comp:
0 Enum_Comp:
17 Str_Comp:
Ptr_Comp:
0 Enum_Comp:
18 Str_Comp:
5 Int_2_Loc:
7 Enum_Loc:
O.K.
O.K.
WRONG
*
O.K.
O.K.
*
O.K.
O.K.
O.K.
O.K.
O.K.
O.K.
Microseconds for one run through Dhrystone:
Dhrystones per Second:
VAX MIPS rating =
1
B
28938
17234
2
DHRYSTONE PROGRAM, SOME
17234 same as above
1
DHRYSTONE PROGRAM, SOME
13
1
DHRYSTONE PROGRAM, 1'ST
DHRYSTONE PROGRAM, 2'ND
STRING
STRING
STRING
STRING
39.53
25297
14.40
DHRYSTONE END !!!
Comparing these results, you can see that in second case there is loss of
performance of around 0.7%. This value is of course depending on the PWM
frequency, but you can see that impact on CPU performance is very low.
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Software PWM by use of DMA Transfer
Chapter 5 Appendix
5 Appendix
5.1
Additional Information
Information about FUJITSU Microcontrollers can be found on the following Internet
page:
http://mcu.emea.fujitsu.com/
The software example related to this application note is:
96340_sw_pwm_rlt_dma_io
It can be found on the following Internet page:
http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm
5.2
Figures
Figure 1: Basic Idea ............................................................................................................. 6
Figure 2: PWM Signal .......................................................................................................... 7
Figure 3: PWM Generation .................................................................................................. 7
Figure 4: 3bit PWM signal generation................................................................................. 8
Figure 5: Extract from SW-PWM signal with 8bit resolution............................................. 9
Figure 6: Reload Timer output for example 2................................................................... 17
Figure 7: PWM signal output at IO pin for example 2 ...................................................... 17
Figure 8: Rising Edge for example 2 - Jitter..................................................................... 18
Figure 9: Rising Edge for example 2 - Delay .................................................................... 19
Figure 10: Falling Edge for example 2 - Jitter .................................................................. 19
Figure 11: Falling Edge for example 2 - Delay ................................................................. 20
Figure 12: Rising Edge with CPU influence – Jitter......................................................... 22
Figure 13: Rising Edge with CPU influence - Delay......................................................... 22
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