The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR DATA SHEET DS702–00013–0v02-E 8-bit Microcontrollers New 8FX MB95850K/860K/870K Series MB95F856K/F866K/F876K ■ DESCRIPTION The MB95850K/860K/870K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of these series contain a variety of peripheral resources. ■ FEATURES • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instructions • Bit manipulation instructions, etc. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. • Clock • Selectable main clock source Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) Main CR clock (4 MHz ±2%) Main CR PLL clock The main CR PLL clock frequency becomes 8 MHz ±2% when the PLL multiplier is 2. The main CR PLL clock frequency becomes 10 MHz ±2% when the PLL multiplier is 2.5. The main CR PLL clock frequency becomes 12 MHz ±2% when the PLL multiplier is 3. The main CR PLL clock frequency becomes 16 MHz ±2% when the PLL multiplier is 4. • Selectable subclock source Sub-oscillation clock (32.768 kHz) External clock (32.768 kHz) Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) (Continued) FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website. The website contains information useful for customers. http://edevice.fujitsu.com/micom/en-support/ Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.1 MB95850K/860K/870K Series • Timer • 8/16-bit composite timer MB95F856K: 1 channel MB95F866K/F876K: 2 channels • 8/16-bit PPG MB95F856K: 1 channel MB95F866K: 2 channels MB95F876K: 3 channels • Time-base timer × 1 channel • Watch counter × 1 channel • Watch prescaler × 1 channel • UART/SIO × 1 channel • Full duplex double buffer • Capable of clock-asynchronized (UART) serial data transfer and clock-synchronized (SIO) serial data transfer • I2C bus interface × 1 channel • Built-in wake-up function • External interrupt • MB95F856K: 6 channels MB95F866K: 8 channels MB95F876K: 10 channels • Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) • Can be used to wake up the device from different low power consumption (standby) modes • 8/10-bit A/D converter • MB95F856K: 4 channels MB95F866K: 6 channels MB95F876K: 8 channels • 8-bit or 10-bit resolution can be selected. • Low power consumption (standby) modes There are four standby modes as follows: • Stop mode • Sleep mode • Watch mode • Time-base timer mode In standby mode, two further options can be selected: normal standby mode and deep standby mode. • I/O port • MB95F856K (no. of I/O ports: 21) General-purpose I/O ports (CMOS I/O) : 17 General-purpose I/O ports (N-ch open drain) :4 • MB95F866K (no. of I/O ports: 29) General-purpose I/O ports (CMOS I/O) : 25 General-purpose I/O ports (N-ch open drain) :4 • MB95F876K (no. of I/O ports: 45) General-purpose I/O ports (CMOS I/O) : 41 General-purpose I/O ports (N-ch open drain) :4 • On-chip debug • 1-wire serial control • Serial writing supported (asynchronous mode) • Hardware/software watchdog timer • Built-in hardware watchdog timer • Built-in software watchdog timer • Power-on reset • A power-on reset is generated when the power is switched on. • Low-voltage detection (LVD) reset circuit • Built-in low-voltage detection function (The combination of detection voltage and release voltage can be selected from four options.) (Continued) 2 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • Comparator × 1 channel • Built-in dedicated BGR • The comparator reference voltage can be selected between the BGR voltage and the comparator pin. • Clock supervisor counter • Built-in clock supervisor counter • Dual operation Flash memory • The program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. • Flash memory security function • Protects the content of the Flash memory. • Touch sensor (TS) • Adjacent Pattern Interference Suppression (APIS™) • Three modes in APIS: APIS mode 1, APIS mode 2 and APIS mode 3 • Configurable Automatic Impedance Calibration (AIC™) • Direct output (DIO) function Note: APIS and AIC are registered trademarks of ATLab, Inc., South Korea. • Beep output unit × 1 channel DS702–00013–0v02-E 3 MB95850K/860K/870K Series ■ PRODUCT LINE-UP Part number MB95F856K MB95F866K MB95F876K Parameter Type Clock supervisor counter Flash memory product It supervises the main clock oscillation and the subclock oscillation. Flash memory capacity 36 Kbyte RAM capacity 1 Kbyte Power-on reset Yes Low-voltage detection reset Yes Reset input Selected through software • • • CPU functions • • • Generalpurpose I/O Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time • I/O port • CMOS I/O • N-ch open drain : 21 : 17 :4 : 136 : 8 bits : 1 to 3 bytes : 1, 8 and 16 bits : 61.5 ns (machine clock frequency = 16.25 MHz) : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O port • CMOS I/O • N-ch open drain : 29 : 25 :4 • I/O port • CMOS I/O • N-ch open drain : 45 : 41 :4 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ Main oscillation clock at 10 MHz: 105 ms (Min) software watchdog timer • The sub-CR clock can be used as the source clock of the software watchdog timer. Wild register It can be used to replace three bytes of data. 8/10-bit A/D converter 4 channels 6 channels 8 channels 8-bit or 10-bit resolution can be selected. 1 channel 2 channels 2 channels • The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”. 8/16-bit • It has the following functions: interval timer function, PWC function, PWM function and input composite timer capture function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. External interrupt On-chip debug 6 channels 8 channels 10 channels • Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.) • It can be used to wake up the device from different standby modes. • 1-wire serial control • It supports serial writing (asynchronous mode). (Continued) 4 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) Part number MB95F856K MB95F866K MB95F876K Parameter 1 channel UART/SIO • Data transfer with UART/SIO is enabled. • It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. • It uses the NRZ type transfer format. • LSB-first data transfer and MSB-first data transfer are available to use. • Clock-asynchronized (UART) serial data transfer and clock-synchronized (SIO) serial data transfer is enabled. 1 channel I2C bus interface • Master/slave transmission and receiving • It has the following functions: bus error function, arbitration function, transmission direction detection function, wake-up function, and functions of generating and detecting repeated START conditions. 1 channels 8/16-bit PPG 3 channels • Each channel can used as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”. • The counter operating clock can be selected from eight clock sources. 5 touch channels Touch sensor (TS) 2 channels • • • • 8 touch channels 12 touch channels Two types of interrupt: GINT for general purpose and TINT for touch detection 8-bit resolution of touch strength data (256 steps) Five DIO pins as direct touch outputs Beep generation for tactile feeling Beep output unit The beep output unit can be activated by using the software or the TS. • Count clock: it can be selected from eight clock sources from the watch prescaler. Watch counter • The counter value can be selected from 0 to 63. (The watch counter can count for one minute when the clock source of one second is selected and 60 is selected as the counter value.) Watch prescaler Eight different time intervals can be selected. 1 channel Comparator Flash memory The comparator reference voltage can be selected between the BGR voltage and the comparator pin. • It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 20 years 10000 10 years 100000 5 years There are four standby modes as follows: • Stop mode • Sleep mode Standby mode • Watch mode • Time-base timer mode In standby mode, two further options can be selected: normal standby mode and deep standby mode. Package DS702–00013–0v02-E FPT-24P-M10 FPT-24P-M34 FPT-32P-M30 FPT-48P-M49 FPT-52P-M02 5 MB95850K/860K/870K Series ■ PACKAGES AND CORRESPONDING PRODUCTS Part number MB95F856K MB95F866K MB95F876K FPT-24P-M10 Ο X X FPT-24P-M34 Ο X X FPT-32P-M30 X Ο X FPT-48P-M49 X X Ο FPT-52P-M02 X X Ο Package Ο: Available X: Unavailable 6 DS702–00013–0v02-E MB95850K/860K/870K Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION • Current consumption When using the on-chip debug function, take account of the current consumption of Flash program/erase. For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSION”. • Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of operating voltage, see “■ ELECTRICAL CHARACTERISTICS”. • On-chip debug function The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details of the connection method, refer to “CHAPTER 24 EXAMPLE OF SERIAL PROGRAMMING CONECTION” in the hardware manual of the MB95850K/860K/870K Series. DS702–00013–0v02-E 7 MB95850K/860K/870K Series ■ PIN ASSIGNMENT 24 23 22 21 P10/DBG/EC0 P07*/AN03/CMP0_P/PPG01 20 19 18 17 P04/AN00/BEEP/DIO01/TO01 P47/INT07/SCL P46/INT06/SDA P13/INT04/UI0/DIO02 P14/INT01/UO0/DIO00 P15/INT00/UCK0 PF2/RST P63/AREF P70/S04 P67/S03 1 2 3 4 5 6 7 8 9 10 P66/S02 11 16 15 14 P65/S01 12 13 PG2/X1A/DIO03 PG1/X0A/DIO04 C PF1/X1 PF0/X0 Vss Vcc P71/S05 (TOP VIEW) SOP24 TSSOP24 FPT-24P-M10 FPT-24P-M34 P06*/AN02/CMP0_O/PPG00 P05/INT05/AN01/CMP0_N/TO00 32 31 30 29 28 27 26 25 C PG1/X0A/DIO04 PG2/X1A/DIO03 P10/DBG/EC0 P45*/AN07/TO01/DIO04/PPG11 P44*/AN06/TO00/DIO03/PPG10 P07*/AN03/CMP0_P/PPG01 P06*/AN02/CMP0_O/PPG00 *: High-current pin (8 mA/12 mA) 1 2 3 4 5 6 7 8 (TOP VIEW) LQFP32 FPT-32P-M30 24 23 22 21 P05/INT05/AN01/CMP0_N P04/AN00/BEEP/DIO01 P03/INT03/TO11 P02/INT02/TO10 20 19 18 17 P47/INT07/SCL P46/INT06/SDA P13/INT04/UI0/DIO02 P14/INT01/UO0 P67/S03 P66/S02 P65/S01 P64/S00 P63/AREF PF2/RST P60/EC1/DIO00 P15/INT00/UCK0 9 10 11 12 13 14 15 16 PF1/X1 PF0/X0 Vss Vcc P73/S07 P72/S06 P71/S05 P70/S04 *: High-current pin (8 mA/12 mA) (Continued) 8 DS702–00013–0v02-E PF1/X1 PF0/X0 Vss Vcc P77/S11 P76/S10 P75/S09 P74/S08 C PG1/X0A/DIO04 PG2/X1A/DIO03 P10/DBG P45*/AN07/TO01/DIO04 P44*/AN06/TO00/DIO03 P43*/INT07/PPG11 P42*/INT06/PPG10 P41*/AN05/PPG01 P40*/AN04/PPG00 P07*/AN03/CMP0_P P06*/AN02/CMP0_O 48 47 46 45 44 43 42 41 40 39 38 37 MB95850K/860K/870K Series 36 35 34 33 P05/INT05/AN01/CMP0_N P04/INT04/AN00 P03/INT03 P02/INT02 32 31 30 29 P01/INT01 P00/INT00 P47/SCL P46/SDA P73/S07 1 2 3 4 5 6 7 8 9 28 P11/EC0/DIO01 P72/S06 10 27 P12/BEEP P71/S05 11 26 P13/UI0/DIO02 P70/S04 12 25 P14/UO0 (TOP VIEW) LQFP48 20 21 22 23 24 P61/PPG20 P60/EC1/DIO00 P17/TO10/INT08 P16/TO11/INT09 P15/UCK0 13 14 15 16 17 18 19 P67/S03 P66/S02 P65/S01 P64/S00 P63/AREF PF2/RST P62/PPG21 FPT-48P-M49 *: High-current pin (8 mA/12 mA) (Continued) DS702–00013–0v02-E 9 MB95850K/860K/870K Series P40*/AN04/PPG00 P07*/AN03/CMP0_P 43 42 41 40 1 2 3 4 5 6 7 8 9 P06*/AN02/CMP0_O P41*/AN05/PPG01 44 52 51 50 49 48 47 46 45 C PG1/X0A/DIO04 PG2/X1A/DIO03 P10/DBG P45*/AN07/TO01/DIO04 P44*/AN06/TO00/DIO03 NC P43*/INT07/PPG11 P42*/INT06/PPG10 (Continued) PF1/X1 PF0/X0 Vss Vcc P77/S11 P76/S10 NC P75/S09 P74/S08 P73/S07 31 P05/INT05/AN01/CMP0_N P04/INT04/AN00 P03/INT03 P02/INT02 P01/INT01 P00/INT00 NC P47/SCL P46/SDA 10 30 P11/EC0/DIO01 P72/S06 11 29 P12/BEEP P71/S05 12 13 28 27 P13/UI0/DIO02 (TOP VIEW) LQFP52 24 25 26 P17/INT08/TO10 P14/UO0 P15/UCK0 23 P16/INT09/TO11 22 P61/PPG20 P60/EC1/DIO00 20 14 15 16 17 18 19 21 FPT-52P-M02 P67/S03 P66/S02 P65/S01 P64/S00 P63/AREF PF2/RST NC P62/PPG21 P70/S04 39 38 37 36 35 34 33 32 *: High-current pin (8 mA/12 mA) 10 DS702–00013–0v02-E MB95850K/860K/870K Series ■ PIN FUNCTIONS (MB95850K SERIES) Pin no. Pin name I/O circuit type*1 PG2 1 2 X1A C 4 5 Subclock oscillation I/O pin DIO03 TS direct output ch. 3 pin PG1 General-purpose I/O port X0A C PF1 X1 PF0 X0 I/O type Input Output OD*2 PU*3 General-purpose I/O port C DIO04 3 Function Subclock oscillation input pin Hysteresis CMOS — Ο Hysteresis CMOS — Ο — — Hysteresis CMOS — — Hysteresis CMOS — — TS direct output ch. 4 pin — B B Decoupling capacitor connection pin General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin — — 6 VSS — Power supply pin (GND) — — — — 7 VCC — Power supply pin — — — — Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis CMOS Ο — Hysteresis CMOS — Ο Hysteresis CMOS — Ο — Ο 8 9 10 11 12 13 14 P71 S05 P70 S04 P67 S03 P66 S02 P65 S01 P63 AREF PF2 RST F F F F F F A P15 15 INT00 G 17 UO0 General-purpose I/O port TS touch ch. 4 input pin General-purpose I/O port TS touch ch. 3 input pin General-purpose I/O port TS touch ch. 2 input pin General-purpose I/O port TS touch ch. 1 input pin General-purpose I/O port TS reference impedance input pin General-purpose I/O port Reset pin External interrupt input pin UART/SIO ch. 0 clock I/O pin P14 INT01 TS touch ch. 5 input pin General-purpose I/O port UCK0 16 General-purpose I/O port General-purpose I/O port G External interrupt input pin UART/SIO ch. 0 data output pin DIO00 TS direct output ch. 0 pin P13 General-purpose I/O port INT04 UI0 DIO02 J External interrupt input pin UART/SIO ch. 0 data input pin CMOS CMOS TS direct output ch. 2 pin (Continued) DS702–00013–0v02-E 11 MB95850K/860K/870K Series (Continued) Pin no. Pin name I/O circuit type*1 P46 18 19 INT06 I 21 I C bus interface ch. 0 data I/O pin P47 General-purpose I/O port I I C bus interface ch. 0 clock I/O pin P04 General-purpose I/O port E TO01 8/16-bit composite timer ch. 0 output pin P05 General-purpose I/O port INT05 External interrupt input pin E 8/10-bit A/D converter analog input pin CMP0_N Comparator ch. 0 inverting analog input (negative input) pin TO00 8/16-bit composite timer ch. 0 output pin K — CMOS CMOS Ο — Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο — Ο Ο — General-purpose I/O port High-current pin K PPG01 8/10-bit A/D converter analog input pin Hysteresis/ CMOS analog Comparator ch. 0 non-inverting analog input (positive input) pin 8/16-bit PPG ch. 0 output pin P10 EC0 Ο 8/16-bit PPG ch. 0 output pin CMP0_P DBG 8/10-bit A/D converter analog input pin Comparator ch. 0 digital output pin P07 AN03 CMOS General-purpose I/O port High-current pin PPG00 24 Beep output pin TS direct output ch. 1 pin AN02 CMOS 8/10-bit A/D converter analog input pin DIO01 AN01 Output OD*2 PU*3 2 CMP0_O 23 External interrupt input pin SCL BEEP Input 2 P06 22 External interrupt input pin SDA INT07 I/O type General-purpose I/O port AN00 20 Function General-purpose I/O port H DBG input pin Hysteresis CMOS 8/16-bit composite timer ch. 0 clock input pin (Ο: Available) *1: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. *2: N-ch open drain *3: Pull-up 12 DS702–00013–0v02-E MB95850K/860K/870K Series ■ PIN FUNCTIONS (MB95860K SERIES) Pin no. Pin name 1 2 I/O circuit type*1 PF1 X1 PF0 X0 B B Function General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin I/O type Input Output OD*2 PU*3 Hysteresis CMOS — — Hysteresis CMOS — — 3 VSS — Power supply pin (GND) — — — — 4 VCC — Power supply pin — — — — Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis CMOS Ο — 8/16-bit composite timer ch. 1 clock input pin Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο — Ο 5 6 7 8 9 10 11 12 13 14 P73 S07 P72 S06 P71 S05 P70 S04 P67 S03 P66 S02 P65 S01 P64 S00 P63 AREF PF2 RST F F F F F F F F F A P60 15 16 EC1 G General-purpose I/O port TS touch ch. 6 input pin General-purpose I/O port TS touch ch. 5 input pin General-purpose I/O port TS touch ch. 4 input pin General-purpose I/O port TS touch ch. 3 input pin General-purpose I/O port TS touch ch. 2 input pin General-purpose I/O port TS touch ch. 1 input pin General-purpose I/O port TS touch ch. 0 input pin General-purpose I/O port TS reference impedance input pin General-purpose I/O port Reset pin DIO00 TS direct output ch. 0 pin P15 General-purpose I/O port INT00 G INT01 External interrupt input pin UART/SIO ch. 0 clock I/O pin P14 18 TS touch ch. 7 input pin General-purpose I/O port UCK0 17 General-purpose I/O port General-purpose I/O port G External interrupt input pin UO0 UART/SIO ch. 0 data output pin P13 General-purpose I/O port INT04 UI0 DIO02 J External interrupt input pin UART/SIO ch. 0 data input pin CMOS CMOS TS direct output ch. 2 pin (Continued) DS702–00013–0v02-E 13 MB95850K/860K/870K Series Pin no. Pin name I/O circuit type*1 P46 19 20 21 INT06 I I C bus interface ch. 0 data I/O pin P47 General-purpose I/O port I I C bus interface ch. 0 clock I/O pin P02 General-purpose I/O port INT03 G BEEP G E 8/10-bit A/D converter analog input pin Beep output pin General-purpose I/O port External interrupt input pin E CMOS Ο — Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis/ CMOS analog — Ο 8/10-bit A/D converter analog input pin Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο — Ο — Ο General-purpose I/O port High-current pin K CMP0_O 8/10-bit A/D converter analog input pin Comparator ch. 0 digital output pin PPG00 8/16-bit PPG ch. 0 output pin General-purpose I/O port High-current pin P07 K CMP0_P PPG01 8/10-bit A/D converter analog input pin Hysteresis/ CMOS analog Comparator ch. 0 non-inverting analog input (positive input) pin 8/16-bit PPG ch. 0 output pin General-purpose I/O port High-current pin P44 AN06 TO00 CMOS Comparator ch. 0 inverting analog input (negative input) pin P06 27 — General-purpose I/O port P05 AN03 Ο 8/16-bit composite timer ch. 1 output pin CMP0_N 26 External interrupt input pin TS direct output ch. 1 pin AN02 CMOS General-purpose I/O port INT05 25 External interrupt input pin DIO01 AN01 CMOS 8/16-bit composite timer ch. 1 output pin P04 AN00 Output OD*2 PU*3 2 TO11 24 External interrupt input pin SCL INT02 Input 2 P03 23 External interrupt input pin SDA INT07 I/O type General-purpose I/O port TO10 22 Function 8/10-bit A/D converter analog input pin K 8/16-bit composite timer ch. 0 output pin DIO03 TS direct output ch. 3 pin PPG10 8/16-bit PPG ch. 1 output pin Hysteresis/ CMOS analog (Continued) 14 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) Pin no. Pin name I/O circuit type*1 AN07 TO01 8/10-bit A/D converter analog input pin K 30 31 TS direct output ch. 4 pin PPG11 8/16-bit PPG ch. 1 output pin DBG H DBG input pin EC0 8/16-bit composite timer ch. 0 clock input pin PG2 General-purpose I/O port X1A C Subclock oscillation I/O pin DIO03 TS direct output ch. 3 pin PG1 General-purpose I/O port X0A C Input Output OD*2 PU*3 Hysteresis/ CMOS analog — Ο Hysteresis CMOS Ο — Hysteresis CMOS — Ο Hysteresis CMOS — Ο — — General-purpose I/O port C DIO04 32 8/16-bit composite timer ch. 0 output pin DIO04 P10 29 I/O type General-purpose I/O port High-current pin P45 28 Function Subclock oscillation input pin TS direct output ch. 4 pin — Decoupling capacitor connection pin — — (Ο: Available) *1: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. *2: N-ch open drain *3: Pull-up DS702–00013–0v02-E 15 MB95850K/860K/870K Series ■ PIN FUNCTIONS (MB95870K SERIES) Pin no. LQFP48*1 I/O Pin name circuit LQFP52*2 type*3 PF1 General-purpose I/O port Input 1 1 2 2 3 3 VSS — Power supply pin (GND) — 4 4 VCC — Power supply pin — 5 5 6 6 — 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 X1 PF0 X0 P77 S11 P76 S10 NC P75 S09 P74 S08 P73 S07 P72 S06 P71 S05 P70 S04 P67 S03 P66 S02 P65 S01 B I/O type Function B F F — F F F F F F F F F Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin General-purpose I/O port TS touch ch. 11 input pin General-purpose I/O port TS touch ch. 10 input pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port TS touch ch. 9 input pin General-purpose I/O port TS touch ch. 8 input pin General-purpose I/O port TS touch ch. 7 input pin General-purpose I/O port TS touch ch. 6 input pin General-purpose I/O port TS touch ch. 5 input pin General-purpose I/O port TS touch ch. 4 input pin General-purpose I/O port TS touch ch. 3 input pin General-purpose I/O port TS touch ch. 2 input pin General-purpose I/O port TS touch ch. 1 input pin Output OD*4 PU*5 Hysteresis CMOS — — Hysteresis CMOS — — — — — — — — Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο — — Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο — — (Continued) 16 DS702–00013–0v02-E MB95850K/860K/870K Series Pin no. LQFP48*1 16 I/O Pin name circuit LQFP52*2 type*3 17 P64 S00 F P63 17 18 18 19 — 20 19 21 20 22 AREF PF2 RST NC P62 PPG21 P61 PPG20 22 23 24 EC1 F A — G G G 26 25 27 28 29 INT08 G 30 General-purpose I/O port 8/16-bit PPG ch. 2 output pin General-purpose I/O port 8/16-bit PPG ch. 2 output pin INT09 P15 UCK0 P14 UO0 UI0 P12 BEEP EC0 DIO01 Output OD*4 PU*5 Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis CMOS Ο — — — Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο — — 8/16-bit composite timer ch. 1 clock input pin External interrupt input pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port G External interrupt input pin 8/16-bit composite timer ch. 1 output pin G G General-purpose I/O port UART/SIO ch. 0 clock I/O pin General-purpose I/O port UART/SIO ch. 0 data output pin General-purpose I/O port J UART/SIO ch. 0 data input pin CMOS TS direct output ch. 2 pin G P11 28 It is an internally connected pin. Always leave it unconnected. General-purpose I/O port DIO02 27 Reset pin P17 P13 26 General-purpose I/O port TS direct output ch. 0 pin TO11 24 TS reference impedance input pin DIO00 P16 25 TS touch ch. 0 input pin Input General-purpose I/O port TO10 23 General-purpose I/O port General-purpose I/O port P60 21 I/O type Function General-purpose I/O port Beep output pin General-purpose I/O port G 8/16-bit composite timer ch. 0 clock input pin TS direct output ch. 1 pin (Continued) DS702–00013–0v02-E 17 MB95850K/860K/870K Series Pin no. LQFP48*1 I/O Pin name circuit LQFP52*2 type*3 P46 29 31 SDA 32 — 33 31 34 32 35 33 36 34 37 SCL NC P00 INT00 P01 INT01 P02 INT02 P03 INT03 I 38 INT04 I — G G G G 39 E AN01 E AN02 AN03 AN04 PPG00 CMOS CMOS Ο — CMOS CMOS Ο — — — — — Hysteresis CMOS — Ο External interrupt input pin Hysteresis CMOS — Ο General-purpose I/O port External interrupt input pin Hysteresis CMOS — Ο General-purpose I/O port External interrupt input pin Hysteresis CMOS — Ο External interrupt input pin Hysteresis/ CMOS analog — Ο 8/10-bit A/D converter analog input pin Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Comparator ch. 0 inverting analog input (negative input) pin General-purpose I/O port High-current pin K 8/10-bit A/D converter analog input pin Comparator ch. 0 digital output pin General-purpose I/O port High-current pin K 8/10-bit A/D converter analog input pin Comparator ch. 0 non-inverting analog input (positive input) pin General-purpose I/O port High-current pin P40 42 General-purpose I/O port External interrupt input pin CMP0_P 39 External interrupt input pin INT05 P07 41 General-purpose I/O port General-purpose I/O port CMP0_O 38 It is an internally connected pin. Always leave it unconnected. P05 P06 40 I2C bus interface ch. 0 clock I/O pin 8/10-bit A/D converter analog input pin CMP0_N 37 I2C bus interface ch. 0 data I/O pin General-purpose I/O port AN00 36 Output OD*4 PU*5 General-purpose I/O port P04 35 Input General-purpose I/O port P47 30 I/O type Function K 8/10-bit A/D converter analog input pin 8/16-bit PPG ch. 0 output pin (Continued) 18 DS702–00013–0v02-E MB95850K/860K/870K Series Pin no. LQFP48*1 I/O Pin name circuit LQFP52*2 type*3 43 AN05 K PPG01 44 INT06 D INT07 46 NC D 43 44 45 47 48 49 — 50 External interrupt input pin It is an internally connected pin. Always leave it unconnected. K 8/10-bit A/D converter analog input pin TO00 DIO03 TS direct output ch. 3 pin P45 General-purpose I/O port High-current pin K 8/10-bit A/D converter analog input pin TO01 8/16-bit composite timer ch. 0 output pin DIO04 TS direct output ch. 4 pin P10 DBG X1A DIO03 Hysteresis CMOS — Ο Hysteresis CMOS — Ο — — Hysteresis/ CMOS analog — Ο Hysteresis/ CMOS analog — Ο Hysteresis CMOS Ο — Hysteresis CMOS — Ο — — General-purpose I/O port High-current pin H PG2 46 External interrupt input pin 8/16-bit composite timer ch. 0 output pin AN07 Ο 8/16-bit PPG ch. 1 output pin P44 AN06 — General-purpose I/O port High-current pin PPG11 — Hysteresis/ CMOS analog 8/16-bit PPG ch. 1 output pin P43 45 8/10-bit A/D converter analog input pin General-purpose I/O port High-current pin PPG10 42 Output OD*4 PU*5 8/16-bit PPG ch. 0 output pin P42 41 Input General-purpose I/O port High-current pin P41 40 I/O type Function General-purpose I/O port DBG input pin General-purpose I/O port C Subclock oscillation I/O pin TS direct output ch. 3 pin (Continued) DS702–00013–0v02-E 19 MB95850K/860K/870K Series (Continued) Pin no. LQFP48*1 I/O Pin name circuit LQFP52*2 type*3 PG1 47 51 X0A 52 C Input Output OD*4 PU*5 General-purpose I/O port C DIO04 48 I/O type Function Subclock oscillation input pin Hysteresis CMOS — Ο — — TS direct output ch. 4 pin — Decoupling capacitor connection pin — — (Ο: Available) *1: FPT-48P-M49 *2: FPT-52P-M02 *3: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. *4: N-ch open drain *5: Pull-up 20 DS702–00013–0v02-E MB95850K/860K/870K Series ■ I/O CIRCUIT TYPE Type Circuit A Remarks Reset input / Hysteresis input Reset output / Digital output • N-ch open drain output • Hysteresis input • Reset output N-ch B P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input • Oscillation circuit • High-speed side Feedback resistance: approx. 1 MΩ • CMOS output • Hysteresis input Clock input X1 X0 Standby control / Port select P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input C Port select R Pull-up control P-ch P-ch • Oscillation circuit • Low-speed side Feedback resistance: approx. 5 MΩ Digital output N-ch Digital output Standby control Hysteresis input • CMOS output • Hysteresis input • Pull-up control Clock input X1A X0A Standby control / Port select Port select R Pull-up control Digital output P-ch Digital output N-ch Digital output Standby control Hysteresis input (Continued) DS702–00013–0v02-E 21 MB95850K/860K/870K Series Type Circuit Remarks D Pull-up control R P-ch Digital output P-ch • • • • CMOS output Hysteresis input Pull-up control High current output • • • • CMOS output Hysteresis input Pull-up control Analog input • • • • • CMOS output Hysteresis input Pull-up control Touch input High electrostatic discharge (ESD) Digital output N-ch Standby control Hysteresis input E Pull-up control R P-ch Digital output P-ch Digital output N-ch Analog input A/D control Standby control Hysteresis input F Pull-up control R P-ch Digital output P-ch Digital output N-ch Touch input TS control Standby control Hysteresis input G Pull-up control R P-ch • CMOS output • Hysteresis input • Pull-up control Digital output P-ch Digital output N-ch Standby control Hysteresis input H Standby control • N-ch open drain output • Hysteresis input Hysteresis input Digital output N-ch (Continued) 22 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) Type Circuit Remarks I Digital output • N-ch open drain output • CMOS input N-ch Standby control CMOS input J Pull-up control R P-ch • CMOS output • CMOS input • Pull-up control Digital output P-ch Digital output N-ch Standby control CMOS input K Pull-up control R P-ch Digital output P-ch • • • • • CMOS output Hysteresis input Pull-up control Analog input High-current output Digital output N-ch Analog input A/D control Standby control Hysteresis input DS702–00013–0v02-E 23 MB95850K/860K/870K Series ■ HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your FUJITSU SEMICONDUCTOR semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. • Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. • Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. • Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Code: DS00-00004-1E 24 DS702–00013–0v02-E MB95850K/860K/870K Series • Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. • Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. • Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. • Precautions Related to Usage of Devices FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under FUJITSU SEMICONDUCTOR’s recommended conditions. For detailed information about mount conditions, contact your sales representative. • Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. DS702–00013–0v02-E 25 MB95850K/860K/870K Series • Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions. • Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. • Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 °C and 30 °C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly moistureresistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. • Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU SEMICONDUCTOR recommended conditions for baking. Condition: 125 °C/24 h • Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 26 DS702–00013–0v02-E MB95850K/860K/870K Series 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://edevice.fujitsu.com/fj/handling-e.pdf DS702–00013–0v02-E 27 MB95850K/860K/870K Series ■ NOTES ON DEVICE HANDLING • Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in “1. Absolute Maximum Ratings” of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. • Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. • Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. ■ PIN CONNECTION • Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. • Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. 28 DS702–00013–0v02-E MB95850K/860K/870K Series • DBG pin Connect the DBG pin to an external pull-up resistor of 2 kΩ or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. The recommended layout method illustrated in the following diagram aims to avoid noise coupled between the subclock oscillation I/O pin (X1A) and the DBG pin, which may cause the suboscillator to malfunction. DBG C X0A X1A GND MB95850K/860K/870K Series • RST pin Connect the RST pin to an external pull-up resistor of 2 kΩ or above. To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O function can be selected by the RSTEN bit in the SYSC register. DS702–00013–0v02-E 29 MB95850K/860K/870K Series • C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG/RST/C pins connection diagram DBG C RST Cs • Note on serial communication In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed circuit board to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. If an error is detected, retransmit the data. 30 DS702–00013–0v02-E MB95850K/860K/870K Series ■ BLOCK DIAGRAM (MB95850K SERIES) F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Dual operation Flash with security function (36 Kbyte) 2 PF0/X0* PF1/X1*2 PG1/X0A*2 Oscillator circuit CR oscillator RAM (1 Kbyte) PG2/X1A*2 Interrupt controller Clock control (P04/TO00) C Watch prescaler 8/16-bit composite timer ch. 0 (P05/TO01) (P10*1/EC0) Watch counter (P07*3/CMP0_P) P10*1/DBG On-chip debug Comparator ch. 0 (P05/CMP0_N) (P06*3/CMP0_O) P15/INT00 P14/INT01 P13/INT04 P05/INT05 External interrupt ch. 0 to ch. 5 P46*1/INT06 Internal bus Wild register P47*1/INT07 (P13/UI0) (P14/UO0) UART/SIO ch. 0 Beep output unit (P15/UCK0) P06*3/PPG00 P07*3/PPG01 8/16-bit PPG ch. 0 (P04/BEEP) P63/AREF P65/S01 to P67/S03 P04/AN00 (P05/AN01) (P06*3/AN02) P70/S04 8/10-bit A/D converter P71/S05 Touch sensor (P07*3/AN03) (P14/DIO00) (P04/DIO01) (P13/DIO02) (P47*1/SCL) (P46*1/SDA) (PG1/DIO04) I2C bus interface ch. 0 Port (PG2/DIO03) Port Vcc Vss *1: P10, P46, P47 and PF2 are N-ch open drain pins. *2: Software select *3: P06 and P07 are high-current pins. Note: Pins in parentheses indicate that those pins are shared among different peripheral functions. DS702–00013–0v02-E 31 MB95850K/860K/870K Series ■ BLOCK DIAGRAM (MB95860K SERIES) F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Dual operation Flash with security function (36 Kbyte) PF0/X0*2 PF1/X1*2 PG1/X0A*2 Oscillator circuit CR oscillator RAM (1 Kbyte) PG2/X1A*2 Interrupt controller Clock control (P44*3/TO00) C Watch prescaler 8/16-bit composite timer ch. 0 (P45*3/TO01) (P10*1/EC0) Watch counter (P02/TO10) P10*1/DBG On-chip debug 8/16-bit composite timer ch. 1 (P03/TO11) P60/EC1 Wild register (P07*3/CMP0_P) P15/INT00 Comparator ch. 0 (P05/CMP0_N) (P06*3/CMP0_O) P14/INT01 P03/INT03 P13/INT04 External interrupt ch. 0 to ch. 7 P05/INT05 P46*1/INT06 P47*1/INT07 Internal bus P02/INT02 (P13/UI0) (P14/UO0) UART/SIO ch. 0 (P15/UCK0) P06*3/PPG00 P07*3/PPG01 8/16-bit PPG ch. 0 Beep output unit P44*3/PPG10 P45*3/PPG11 (P04/BEEP) 8/16-bit PPG ch. 1 P63/AREF P04/AN00 P64/S00 to P67/S03 (P05/AN01) P70/S04 to P73/S07 (P06*3/AN02) (P07*3/AN03) (P60/DIO00) 8/10-bit A/D converter Touch sensor (P44*3/AN06) (P45*3/AN07) (P04/DIO01) (P13/DIO02) (P44*3/DIO03) (PG2/DIO03) (P47*1/SCL) (P46*1/SDA) I2C (P45*3/DIO04) bus interface ch. 0 Port (PG1/DIO04) Port Vcc Vss *1: P10, P46, P47 and PF2 are N-ch open drain pins. *2: Software select *3: P06, P07, P44 and P45 are high-current pins. Note: Pins in parentheses indicate that those pins are shared among different peripheral functions. 32 DS702–00013–0v02-E MB95850K/860K/870K Series ■ BLOCK DIAGRAM (MB95870K SERIES) F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Dual operation Flash with security function (36 Kbyte) PF0/X0*2 PF1/X1*2 PG1/X0A*2 Oscillator circuit CR oscillator RAM (1 Kbyte) PG2/X1A*2 Interrupt controller Clock control (P44*3/TO00) C Watch prescaler 8/16-bit composite timer ch. 0 (P45*3/TO01) P11/EC0 Watch counter (P16/TO10) P10*1/DBG On-chip debug 8/16-bit composite timer ch. 1 (P17/TO11) P60/EC1 Wild register (P07*3/CMP0_P) P00/INT00 to P05/INT05 Comparator ch. 0 P42*3/INT06 P43*3/INT07 (P05/CMP0_N) (P06*3/CMP0_O) External interrupt ch. 0 to ch. 9 P16/INT09 P13/UI0 P14/UO0 UART/SIO ch. 0 P15/UCK0 P40*3/PPG00 P41*3/PPG01 (P42*3/PPG10) (P43*3/PPG11) P61/PPG20 P62/PPG21 Internal bus P17/INT08 8/16-bit PPG ch. 0 8/16-bit PPG ch. 1 8/16-bit PPG ch. 2 Beep output unit P12/BEEP (P04/AN00) (P05/AN01) P63/AREF P06*3/AN02 P64/S00 to P67/S03 P07*3/AN03 (P40*3/AN04) P70/S04 to P77/S11 8/10-bit A/D converter (P41*3/AN05) (P60/DIO00) Touch sensor P44*3/AN06 P45*3/AN07 (P11/DIO01) (P13/DIO02) (P44*3/DIO03) (PG2/DIO03) P47*1/SCL P46*1/SDA I2C (P45*3/DIO04) bus interface ch. 0 Port (PG1/DIO04) Port Vcc Vss *1: P10, P46, P47 and PF2 are N-ch open drain pins. *2: Software select *3: P06, P07, and P40 to P45 are high-current pins. Note: Pins in parentheses indicate that those pins are shared among different peripheral functions. DS702–00013–0v02-E 33 MB95850K/860K/870K Series ■ CPU CORE • Memory space The memory space of the MB95850K/860K/870K Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas intended for specific pur poses such as general-pur pose registers and a vector table. The memor y maps of the MB95850K/860K/870K Series are shown below. • Memory maps 0x0000 0x0080 0x0090 0x0100 0x0200 I/O area Access prohibited RAM 1 Kbyte Registers 0x0490 Access prohibited 0x0E00 0x0F00 0x0F80 0x1000 Extended I/O area Access prohibited Extended I/O area Flash memory 4 Kbyte 0x2000 Access prohibited 0x8000 Flash memory 32 Kbyte 0xFFFF 34 DS702–00013–0v02-E MB95850K/860K/870K Series ■ MEMORY SPACE The memory space of the MB95850K/860K/870K Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table. • I/O area (addresses: 0x0000 to 0x007F) • This area contains the control registers and data registers for built-in peripheral functions. • As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also be accessed at high-speed by using direct addressing instructions. • Extended I/O area (addresses: 0x0E00 to 0x0EFF and 0x0F80 to 0x0FFF) • This area contains the control registers and data registers for built-in peripheral functions. • As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory. • Data area • Static RAM is incorporated in the data area as the internal data area. • The internal RAM size varies according to product. • The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions. • The area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. • The area from 0x0100 to 0x01FF can be used as a general-purpose register area. • Program area • The Flash memory is incorporated in the program area as the internal program area. • The Flash memory size varies according to product. • The area from 0xFFC0 to 0xFFFF is used as the vector table. • The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. DS702–00013–0v02-E 35 MB95850K/860K/870K Series • Memory space map 0x0000 0x0080 0x0090 0x0100 I/O area Direct addressing area Access prohibited Registers (General-purpose register area) 0x0200 Extended direct addressing area Data area 0x047F 0x048F 0x0490 Access prohibited 0x0E00 0x0F00 0x0F80 0x0FFF 0x1000 Extended I/O area Access prohibited Extended I/O area Program area 0xFFC0 0xFFFF 36 Vector table area DS702–00013–0v02-E MB95850K/860K/870K Series ■ AREAS FOR SPECIFIC APPLICATIONS The general-purpose register area and vector table area are used for the specific applications. • General-purpose register area (Addresses: 0x0100 to 0x01FF) • This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc. • As this area forms part of the RAM area, it can also be used as conventional RAM. • When the area is used as general-purpose registers, general-purpose register addressing enables highspeed access with short instructions. • Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF) • The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “CHAPTER 24 NON-VOLATILE REGISTER (NVR) INTERFACE” in the hardware manual of the MB95850K/860K/870K Series. • Vector table area (Addresses: 0xFFC0 to 0xFFFF) • This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets. • The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set to an address in the vector table in the form of data. “■ INTERRUPT SOURCE TABLE (MB95850K SERIES)”, “■ INTERRUPT SOURCE TABLE (MB95860K SERIES)” and “■ INTERRUPT SOURCE TABLE (MB95870K SERIES)” list the vector table addresses corresponding to vector call instructions, interrupts, and resets. For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS” and “A.2 Special Instruction ■ Special Instruction ● CALLV #vct” in the hardware manual of the MB95850K/860K/870K Series. • Direct bank pointer and access area Direct bank pointer (DP[2:0]) Operand-specified dir Access area 0bXXX (It does not affect mapping.) 0x0000 to 0x007F 0x0000 to 0x007F 0b000 (Initial value) 0x0090 to 0x00FF 0x0090 to 0x00FF 0b001 0x0100 to 0x017F 0b010 0x0180 to 0x01FF 0b011 0x0200 to 0x027F 0b100 0x0080 to 0x00FF 0x0280 to 0x02FF 0b101 0x0300 to 0x037F 0b110 0x0380 to 0x03FF 0b111 0x0400 to 0x047F DS702–00013–0v02-E 37 MB95850K/860K/870K Series ■ I/O MAP (MB95850K SERIES) Address Register abbreviation 0x0000 PDR0 0x0001 Register name R/W Initial value Port 0 data register R/W 0b00000000 DDR0 Port 0 direction register R/W 0b00000000 0x0002 PDR1 Port 1 data register R/W 0b00000000 0x0003 DDR1 Port 1 direction register R/W 0b00000000 0x0004 — — — 0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111 0x0006 PLLC PLL control register R/W 0b000X0000 0x0007 SYCC System clock control register R/W 0bXXX11011 0x0008 STBC Standby control register R/W 0b00000000 0x0009 RSRR Reset source register R/W 0b000XXXXX 0x000A TBTC Time-base timer control register R/W 0b00000000 0x000B WPCR Watch prescaler control register R/W 0b00000000 0x000C WDTC Watchdog timer control register R/W 0b00XX0000 0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011 0x000E to 0x0011 — — — 0x0012 PDR4 Port 4 data register R/W 0b00000000 0x0013 DDR4 Port 4 direction register R/W 0b00000000 0x0014, 0x0015 — — — 0x0016 PDR6 Port 6 data register R/W 0b00000000 0x0017 DDR6 Port 6 direction register R/W 0b00000000 0x0018 PDR7 Port 7 data register R/W 0b00000000 0x0019 DDR7 Port 7 direction register R/W 0b00000000 0x001A, 0x001B — — — 0x001C STBC2 R/W 0b00000000 0x001D to 0x0027 — — — 0x0028 PDRF Port F data register R/W 0b00000000 0x0029 DDRF Port F direction register R/W 0b00000000 0x002A PDRG Port G data register R/W 0b00000000 0x002B DDRG Port G direction register R/W 0b00000000 0x002C PUL0 Port 0 pull-up register R/W 0b00000000 0x002D PUL1 Port 1 pull-up register R/W 0b00000000 0x002E to 0x0031 — — — (Disabled) (Disabled) (Disabled) (Disabled) Standby control register 2 (Disabled) (Disabled) (Continued) 38 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x0032 PUL7 0x0033 PUL6 0x0034 — 0x0035 PULG 0x0036 R/W Initial value Port 7 pull-up register R/W 0b00000000 Port 6 pull-up register R/W 0b00000000 — — Port G pull-up register R/W 0b00000000 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000 0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000 0x0038, 0x0039 — — — 0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000 0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000 0x003C to 0x0047 — — — 0x0048 EIC00 R/W 0b00000000 0x0049 — — — 0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000 0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000 0x004C, 0x004D — — — 0x004E LVDR LVD reset voltage selection ID register R/W 0b00000000 0x004F LVDCC LVD reset circuit control register R/W 0b00000001 0x0050 to 0x0055 — — — 0x0056 SMC10 UART/SIO serial mode control register 1 ch. 0 R/W 0b00000000 0x0057 SMC20 UART/SIO serial mode control register 2 ch. 0 R/W 0b00100000 0x0058 SSR0 UART/SIO serial status and data register ch. 0 R/W 0b00000001 0x0059 TDR0 UART/SIO serial output data register ch. 0 R/W 0b00000000 0x005A RDR0 UART/SIO serial input data register ch. 0 R 0b00000000 0x005B CMR0 Comparator control register ch. 0 R/W 0b11000101 0x005C to 0x005F — — — 0x0060 IBCR00 0x0061 0x0062 0x0063 0x0064 IBCR10 IBSR0 IDDR0 IAAR0 0x0065 ICCR0 0x0066 to 0x006B — Register name (Disabled) (Disabled) (Disabled) External interrupt circuit control register ch. 0/ch. 1 (Disabled) (Disabled) (Disabled) (Disabled) I2C bus control register 0 ch. 0 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 — — I C bus control register 1 ch. 0 I C bus status register ch. 0 I C data register ch. 0 I C address register ch. 0 I C clock control register ch. 0 (Disabled) (Continued) DS702–00013–0v02-E 39 MB95850K/860K/870K Series Address Register abbreviation 0x006C ADC1 0x006D Register name R/W Initial value 8/10-bit A/D converter control register 1 R/W 0b00000000 ADC2 8/10-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/10-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/10-bit A/D converter data register (lower) R/W 0b00000000 0x0070 WCSR Watch counter control register R/W 0b00000000 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — — — 0x0E10 BPFREQ Beep output frequency register R/W 0b00000000 0x0E11 TER0 TS touch channel enable register 0 R/W 0b00000000 0x0E12 TER1 TS touch channel enable register 1 R/W 0b00000000 0x0E13 PSC TS prescaler control register R/W 0b00100000 0x0E14 WRESET TS warm reset register R/W 0b00000000 0x0E15 RSEL0 TS sensitivity select register 0 R/W 0b00000010 0x0E16 RSEL1 TS sensitivity select register 1 R/W 0b00010010 0x0E17 RSEL2 TS sensitivity select register 2 R/W 0b00010010 0x0E18 RSEL3 TS sensitivity select register 3 R/W 0b00010010 0x0E19 to 0x0E1B — — — 0x0E1C BPDUR TS beep duration setting register R/W 0b00000000 0x0E1D DIOR1 TS direct output control register 1 R/W 0b00000000 Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) (Disabled) 0x0E1E DIOR2 TS direct output control register 2 R/W 0b00000000 0x0E1F DIOR3 TS direct output control register 3 R/W 0b00000000 0x0E20 FTSEL TS feature select register R/W 0b00000100 (Continued) 40 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x0E21 AICWAT 0x0E22 Register name R/W Initial value TS AIC wait time setting register R/W 0b00100111 CALITV TS calibration interval setting register R/W 0b00110000 0x0E23 ITGTM TS integration time setting register R/W 0b00001111 0x0E24 IDLETM TS idle time setting register R/W 0b00001111 0x0E25 CONTROL TS control register R/W 0b00000000 0x0E26 INTMR TS interrupt mask register R/W 0b00011000 0x0E27 INTCR TS interrupt clear register R/W 0b00000000 0x0E28 FLTP TS filter period setting register R/W 0b00000000 0x0E29 FLTTH TS filter threshold setting register R/W 0b00000000 0x0E2A REFDLY TS reference delay setting register R/W 0b00000000 0x0E2B to 0x0E30 — — — 0x0E31 ALPH1 TS alpha value setting register ch. 1 R/W 0b00001000 0x0E32 ALPH2 TS alpha value setting register ch. 2 R/W 0b00001000 0x0E33 ALPH3 TS alpha value setting register ch. 3 R/W 0b00001000 0x0E34 ALPH4 TS alpha value setting register ch. 4 R/W 0b00001000 0x0E35 ALPH5 TS alpha value setting register ch. 5 R/W 0b00001000 0x0E36 to 0x0E3F — — — 0x0E40 BETA R/W 0b00000100 0x0E41 to 0x0E50 — — — 0x0E51 STRTH1 TS touch strength threshold setting register ch. 1 R/W 0b00000001 0x0E52 STRTH2 TS touch strength threshold setting register ch. 2 R/W 0b00000001 0x0E53 STRTH3 TS touch strength threshold setting register ch. 3 R/W 0b00000001 0x0E54 STRTH4 TS touch strength threshold setting register ch. 4 R/W 0b00000001 0x0E55 STRTH5 TS touch strength threshold setting register ch. 5 R/W 0b00000001 0x0E56 to 0x0E60 — (Disabled) — — 0x0E61 STR1 TS touch strength register ch. 1 R 0bXXXXXXXX 0x0E62 STR2 TS touch strength register ch. 2 R 0bXXXXXXXX 0x0E63 STR3 TS touch strength register ch. 3 R 0bXXXXXXXX 0x0E64 STR4 TS touch strength register ch. 4 R 0bXXXXXXXX 0x0E65 STR5 TS touch strength register ch. 5 R 0bXXXXXXXX 0x0E66 to 0x0E70 — (Disabled) — — (Disabled) (Disabled) TS beta value setting register (Disabled) (Continued) DS702–00013–0v02-E 41 MB95850K/860K/870K Series Address Register abbreviation 0x0E71 CALIP1 0x0E72 Register name R/W Initial value TS calibrated impedance register ch. 1 R 0b0XXXXXXX CALIP2 TS calibrated impedance register ch. 2 R 0b0XXXXXXX 0x0E73 CALIP3 TS calibrated impedance register ch. 3 R 0b0XXXXXXX 0x0E74 CALIP4 TS calibrated impedance register ch. 4 R 0b0XXXXXXX 0x0E75 CALIP5 TS calibrated impedance register ch. 5 R 0b0XXXXXXX 0x0E76 to 0x0E80 — — — 0x0E81 IMPE1 TS impedance register ch. 1 R 0b0XXXXXXX 0x0E82 IMPE2 TS impedance register ch. 2 R 0b0XXXXXXX 0x0E83 IMPE3 TS impedance register ch. 3 R 0b0XXXXXXX 0x0E84 IMPE4 TS impedance register ch. 4 R 0b0XXXXXXX 0x0E85 IMPE5 TS impedance register ch. 5 R 0b0XXXXXXX 0x0E86 to 0x0E8F — — — 0x0E90 TOUCHL TS touch data register (lower) R 0bXXXXXXXX 0x0E91 TOUCHH TS touch data register (upper) R 0b0000XXXX 0x0E92 INTPR TS interrupt pending register R 0b000XXXXX 0x0E93 to 0x0F7F — — — 0x0F80 WRARH0 Wild register address setting register (upper) ch. 0 R/W 0b00000000 0x0F81 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 to 0x0F9B — — — (Disabled) (Disabled) (Disabled) (Disabled) (Disabled) (Continued) 42 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x0F9C PPS01 0x0F9D Register name R/W Initial value 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111 PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111 0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111 0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111 0x0FA0 to 0x0FA3 — — — 0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000 0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000 0x0FA6 to 0x0FBD — (Disabled) — — 0x0FBE PSSR0 UART/SIO dedicated baud generator prescaler select register ch. 0 R/W 0b00000000 0x0FBF BRSR0 UART/SIO dedicated baud generator baud rate setting register ch. 0 R/W 0b00000000 0x0FC0 TIDR0 Touch input disable register 0 R/W 0b00000000 0x0FC1 TIDR1 Touch input disable register 1 R/W 0b00000000 0x0FC2 — — — 0x0FC3 AIDRL A/D input disable register (lower) R/W 0b00000000 0x0FC4 LVDPW LVD reset circuit password register R/W 0b00000000 0x0FC5 to 0x0FE2 — — — 0x0FE3 WCDR Watch counter data register R/W 0b00111111 0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX 0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX 0x0FE6 — — — 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R/W 0b000XXXXX 0x0FE8 SYSC System configuration register R/W 0b11000011 0x0FE9 CMCR Clock monitoring control register R/W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 0x0FEB WDTH Watchdog timer selection ID register (upper) R 0bXXXXXXXX 0x0FEC WDTL Watchdog timer selection ID register (lower) R 0bXXXXXXXX (Disabled) (Disabled) (Disabled) (Disabled) (Continued) DS702–00013–0v02-E 43 MB95850K/860K/870K Series (Continued) Address Register abbreviation Register name R/W Initial value 0x0FED, 0x0FEE — (Disabled) — — 0x0FEF WICR R/W 0b01000000 0x0FF0 to 0x0FFF — — — Interrupt pin selection circuit control register (Disabled) • R/W access symbols R/W : Readable/Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 44 DS702–00013–0v02-E MB95850K/860K/870K Series ■ I/O MAP (MB95860K SERIES) Address Register abbreviation 0x0000 PDR0 0x0001 Register name R/W Initial value Port 0 data register R/W 0b00000000 DDR0 Port 0 direction register R/W 0b00000000 0x0002 PDR1 Port 1 data register R/W 0b00000000 0x0003 DDR1 Port 1 direction register R/W 0b00000000 0x0004 — — — 0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111 0x0006 PLLC PLL control register R/W 0b000X0000 0x0007 SYCC System clock control register R/W 0bXXX11011 0x0008 STBC Standby control register R/W 0b00000000 0x0009 RSRR Reset source register R/W 0b000XXXXX 0x000A TBTC Time-base timer control register R/W 0b00000000 0x000B WPCR Watch prescaler control register R/W 0b00000000 0x000C WDTC Watchdog timer control register R/W 0b00XX0000 0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011 0x000E to 0x0011 — — — 0x0012 PDR4 Port 4 data register R/W 0b00000000 0x0013 DDR4 Port 4 direction register R/W 0b00000000 0x0014, 0x0015 — — — 0x0016 PDR6 Port 6 data register R/W 0b00000000 0x0017 DDR6 Port 6 direction register R/W 0b00000000 0x0018 PDR7 Port 7 data register R/W 0b00000000 0x0019 DDR7 Port 7 direction register R/W 0b00000000 0x001A, 0x001B — — — 0x001C STBC2 R/W 0b00000000 0x001D to 0x0027 — — — 0x0028 PDRF Port F data register R/W 0b00000000 0x0029 DDRF Port F direction register R/W 0b00000000 0x002A PDRG Port G data register R/W 0b00000000 0x002B DDRG Port G direction register R/W 0b00000000 0x002C PUL0 Port 0 pull-up register R/W 0b00000000 0x002D PUL1 Port 1 pull-up register R/W 0b00000000 0x002E, 0x002F — — — 0x0030 PUL4 R/W 0b00000000 0x0031 — — — 0x0032 PUL7 R/W 0b00000000 (Disabled) (Disabled) (Disabled) (Disabled) Standby control register 2 (Disabled) (Disabled) Port 4 pull-up register (Disabled) Port 7 pull-up register (Continued) DS702–00013–0v02-E 45 MB95850K/860K/870K Series Address Register abbreviation 0x0033 PUL6 0x0034 — 0x0035 PULG 0x0036 Register name R/W Initial value R/W 0b00000000 — — Port G pull-up register R/W 0b00000000 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000 0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000 0x0038 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000 0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000 0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000 0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000 0x003C PC11 8/16-bit PPG timer 11 control register R/W 0b00000000 0x003D PC10 8/16-bit PPG timer 10 control register R/W 0b00000000 0x003E to 0x0047 — — — 0x0048 EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 0b00000000 0x0049 EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 0b00000000 0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000 0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000 0x004C, 0x004D — — — 0x004E LVDR LVD reset voltage selection ID register R/W 0b00000000 0x004F LVDCC LVD reset circuit control register R/W 0b00000001 0x0050 to 0x0055 — — — 0x0056 SMC10 UART/SIO serial mode control register 1 ch. 0 R/W 0b00000000 0x0057 SMC20 UART/SIO serial mode control register 2 ch. 0 R/W 0b00100000 0x0058 SSR0 UART/SIO serial status and data register ch. 0 R/W 0b00000001 Port 6 pull-up register (Disabled) (Disabled) (Disabled) (Disabled) 0x0059 TDR0 UART/SIO serial output data register ch. 0 R/W 0b00000000 0x005A RDR0 UART/SIO serial input data register ch. 0 R 0b00000000 0x005B CMR0 Comparator control register ch. 0 R/W 0b11000101 0x005C to 0x005F — — — 0x0060 IBCR00 0x0061 0x0062 0x0063 0x0064 IBCR10 IBSR0 IDDR0 IAAR0 0x0065 ICCR0 0x0066 to 0x006B — (Disabled) I2C bus control register 0 ch. 0 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 — — I C bus control register 1 ch. 0 I C bus status register ch. 0 I C data register ch. 0 I C address register ch. 0 I C clock control register ch. 0 (Disabled) (Continued) 46 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x006C ADC1 0x006D Register name R/W Initial value 8/10-bit A/D converter control register 1 R/W 0b00000000 ADC2 8/10-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/10-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/10-bit A/D converter data register (lower) R/W 0b00000000 0x0070 WCSR Watch counter control register R/W 0b00000000 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — — — 0x0E10 BPFREQ Beep output frequency register R/W 0b00000000 0x0E11 TER0 TS touch channel enable register 0 R/W 0b00000000 0x0E12 TER1 TS touch channel enable register 1 R/W 0b00000000 0x0E13 PSC TS prescaler control register R/W 0b00100000 0x0E14 WRESET TS warm reset register R/W 0b00000000 0x0E15 RSEL0 TS sensitivity select register 0 R/W 0b00000010 0x0E16 RSEL1 TS sensitivity select register 1 R/W 0b00010010 0x0E17 RSEL2 TS sensitivity select register 2 R/W 0b00010010 0x0E18 RSEL3 TS sensitivity select register 3 R/W 0b00010010 TS sensitivity select register 4 R/W 0b00010010 — — Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) 0x0E19 RSEL4 0x0E1A, 0x0E1B — 0x0E1C BPDUR TS beep duration setting register R/W 0b00000000 0x0E1D DIOR1 TS direct output control register 1 R/W 0b00000000 0x0E1E DIOR2 TS direct output control register 2 R/W 0b00000000 0x0E1F DIOR3 TS direct output control register 3 R/W 0b00000000 0x0E20 FTSEL TS feature select register R/W 0b00000100 0x0E21 AICWAT TS AIC wait time setting register R/W 0b00100111 0x0E22 CALITV TS calibration interval setting register R/W 0b00110000 (Disabled) (Continued) DS702–00013–0v02-E 47 MB95850K/860K/870K Series Address Register abbreviation 0x0E23 Register name R/W Initial value ITGTM TS integration time setting register R/W 0b00001111 0x0E24 IDLETM TS idle time setting register R/W 0b00001111 0x0E25 CONTROL TS control register R/W 0b00000000 0x0E26 INTMR TS interrupt mask register R/W 0b00011000 0x0E27 INTCR TS interrupt clear register R/W 0b00000000 0x0E28 FLTP TS filter period setting register R/W 0b00000000 0x0E29 FLTTH TS filter threshold setting register R/W 0b00000000 0x0E2A REFDLY TS reference delay setting register R/W 0b00000000 0x0E2B to 0x0E2F — — — 0x0E30 ALPH0 TS alpha value setting register ch. 0 R/W 0b00001000 0x0E31 ALPH1 TS alpha value setting register ch. 1 R/W 0b00001000 0x0E32 ALPH2 TS alpha value setting register ch. 2 R/W 0b00001000 0x0E33 ALPH3 TS alpha value setting register ch. 3 R/W 0b00001000 0x0E34 ALPH4 TS alpha value setting register ch. 4 R/W 0b00001000 0x0E35 ALPH5 TS alpha value setting register ch. 5 R/W 0b00001000 0x0E36 ALPH6 TS alpha value setting register ch. 6 R/W 0b00001000 0x0E37 ALPH7 TS alpha value setting register ch. 7 R/W 0b00001000 0x0E38 to 0x0E3F — — — 0x0E40 BETA R/W 0b00000100 0x0E41 to 0x0E4F — — — 0x0E50 STRTH0 TS touch strength threshold setting register ch. 0 R/W 0b00000001 0x0E51 STRTH1 TS touch strength threshold setting register ch. 1 R/W 0b00000001 0x0E52 STRTH2 TS touch strength threshold setting register ch. 2 R/W 0b00000001 0x0E53 STRTH3 TS touch strength threshold setting register ch. 3 R/W 0b00000001 0x0E54 STRTH4 TS touch strength threshold setting register ch. 4 R/W 0b00000001 0x0E55 STRTH5 TS touch strength threshold setting register ch. 5 R/W 0b00000001 0x0E56 STRTH6 TS touch strength threshold setting register ch. 6 R/W 0b00000001 0x0E57 STRTH7 TS touch strength threshold setting register ch. 7 R/W 0b00000001 0x0E58 to 0x0E5F — — — (Disabled) (Disabled) TS beta value setting register (Disabled) (Disabled) (Continued) 48 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x0E60 STR0 0x0E61 Register name R/W Initial value TS touch strength register ch. 0 R 0bXXXXXXXX STR1 TS touch strength register ch. 1 R 0bXXXXXXXX 0x0E62 STR2 TS touch strength register ch. 2 R 0bXXXXXXXX 0x0E63 STR3 TS touch strength register ch. 3 R 0bXXXXXXXX 0x0E64 STR4 TS touch strength register ch. 4 R 0bXXXXXXXX 0x0E65 STR5 TS touch strength register ch. 5 R 0bXXXXXXXX 0x0E66 STR6 TS touch strength register ch. 6 R 0bXXXXXXXX 0x0E67 STR7 TS touch strength register ch. 7 R 0bXXXXXXXX 0x0E68 to 0x0E6F — (Disabled) — — 0x0E70 CALIP0 TS calibrated impedance register ch. 0 R 0b0XXXXXXX 0x0E71 CALIP1 TS calibrated impedance register ch. 1 R 0b0XXXXXXX 0x0E72 CALIP2 TS calibrated impedance register ch. 2 R 0b0XXXXXXX 0x0E73 CALIP3 TS calibrated impedance register ch. 3 R 0b0XXXXXXX 0x0E74 CALIP4 TS calibrated impedance register ch. 4 R 0b0XXXXXXX 0x0E75 CALIP5 TS calibrated impedance register ch. 5 R 0b0XXXXXXX 0x0E76 CALIP6 TS calibrated impedance register ch. 6 R 0b0XXXXXXX 0x0E77 CALIP7 TS calibrated impedance register ch. 7 R 0b0XXXXXXX 0x0E78 to 0x0E7F — — — 0x0E80 IMPE0 TS impedance register ch. 0 R 0b0XXXXXXX 0x0E81 IMPE1 TS impedance register ch. 1 R 0b0XXXXXXX 0x0E82 IMPE2 TS impedance register ch. 2 R 0b0XXXXXXX 0x0E83 IMPE3 TS impedance register ch. 3 R 0b0XXXXXXX 0x0E84 IMPE4 TS impedance register ch. 4 R 0b0XXXXXXX 0x0E85 IMPE5 TS impedance register ch. 5 R 0b0XXXXXXX 0x0E86 IMPE6 TS impedance register ch. 6 R 0b0XXXXXXX 0x0E87 IMPE7 TS impedance register ch. 7 R 0b0XXXXXXX 0x0E88 to 0x0E8F — — — 0x0E90 TOUCHL TS touch data register (lower) R 0bXXXXXXXX 0x0E91 TOUCHH TS touch data register (upper) R 0b0000XXXX 0x0E92 INTPR TS interrupt pending register R 0b000XXXXX 0x0E93 to 0x0F7F — — — (Disabled) (Disabled) (Disabled) (Continued) DS702–00013–0v02-E 49 MB95850K/860K/870K Series Address Register abbreviation 0x0F80 WRARH0 0x0F81 Register name R/W Initial value Wild register address setting register (upper) ch. 0 R/W 0b00000000 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 T11CR0 8/16-bit composite timer 11 status control register 0 R/W 0b00000000 0x0F98 T10CR0 8/16-bit composite timer 10 status control register 0 R/W 0b00000000 0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000 0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000 0x0F9B TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 0b00000000 0x0F9C PPS01 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111 0x0F9D PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111 0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111 0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111 0x0FA0 PPS11 8/16-bit PPG11 cycle setting buffer register R/W 0b11111111 0x0FA1 PPS10 8/16-bit PPG10 cycle setting buffer register R/W 0b11111111 0x0FA2 PDS11 8/16-bit PPG11 duty setting buffer register R/W 0b11111111 0x0FA3 PDS10 8/16-bit PPG10 duty setting buffer register R/W 0b11111111 0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000 0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000 0x0FA6 to 0x0FBD — (Disabled) — — 0x0FBE PSSR0 UART/SIO dedicated baud generator prescaler select register ch. 0 R/W 0b00000000 0x0FBF BRSR0 UART/SIO dedicated baud generator baud rate setting register ch. 0 R/W 0b00000000 (Disabled) (Continued) 50 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) Address Register abbreviation 0x0FC0 TIDR0 0x0FC1 TIDR1 0x0FC2 — 0x0FC3 AIDRL 0x0FC4 LVDPW 0x0FC5 to 0x0FE2 — 0x0FE3 WCDR 0x0FE4 Register name R/W Initial value Touch input disable register 0 R/W 0b00000000 Touch input disable register 1 R/W 0b00000000 — — A/D input disable register (lower) R/W 0b00000000 LVD reset circuit password register R/W 0b00000000 — — Watch counter data register R/W 0b00111111 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX 0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX 0x0FE6 — — — 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R/W 0b000XXXXX 0x0FE8 SYSC System configuration register R/W 0b11000011 0x0FE9 CMCR Clock monitoring control register R/W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 0x0FEB WDTH Watchdog timer selection ID register (upper) R 0bXXXXXXXX 0x0FEC WDTL Watchdog timer selection ID register (lower) R 0bXXXXXXXX 0x0FED, 0x0FEE — — — 0x0FEF WICR R/W 0b01000000 0x0FF0 to 0x0FFF — — — (Disabled) (Disabled) (Disabled) (Disabled) Interrupt pin selection circuit control register (Disabled) • R/W access symbols R/W : Readable/Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. DS702–00013–0v02-E 51 MB95850K/860K/870K Series ■ I/O MAP (MB95870K SERIES) Address Register abbreviation 0x0000 PDR0 0x0001 Register name R/W Initial value Port 0 data register R/W 0b00000000 DDR0 Port 0 direction register R/W 0b00000000 0x0002 PDR1 Port 1 data register R/W 0b00000000 0x0003 DDR1 Port 1 direction register R/W 0b00000000 0x0004 — — — 0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111 0x0006 PLLC PLL control register R/W 0b000X0000 0x0007 SYCC System clock control register R/W 0bXXX11011 0x0008 STBC Standby control register R/W 0b00000000 0x0009 RSRR Reset source register R/W 0b000XXXXX 0x000A TBTC Time-base timer control register R/W 0b00000000 0x000B WPCR Watch prescaler control register R/W 0b00000000 0x000C WDTC Watchdog timer control register R/W 0b00XX0000 0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011 0x000E to 0x0011 — — — 0x0012 PDR4 Port 4 data register R/W 0b00000000 0x0013 DDR4 Port 4 direction register R/W 0b00000000 0x0014, 0x0015 — — — 0x0016 PDR6 Port 6 data register R/W 0b00000000 0x0017 DDR6 Port 6 direction register R/W 0b00000000 0x0018 PDR7 Port 7 data register R/W 0b00000000 0x0019 DDR7 Port 7 direction register R/W 0b00000000 0x001A, 0x001B — — — 0x001C STBC2 R/W 0b00000000 0x001D to 0x0027 — — — 0x0028 PDRF Port F data register R/W 0b00000000 0x0029 DDRF Port F direction register R/W 0b00000000 0x002A PDRG Port G data register R/W 0b00000000 0x002B DDRG Port G direction register R/W 0b00000000 0x002C PUL0 Port 0 pull-up register R/W 0b00000000 0x002D PUL1 Port 1 pull-up register R/W 0b00000000 0x002E, 0x002F — — — 0x0030 PUL4 R/W 0b00000000 0x0031 — — — 0x0032 PUL7 R/W 0b00000000 (Disabled) (Disabled) (Disabled) (Disabled) Standby control register 2 (Disabled) (Disabled) Port 4 pull-up register (Disabled) Port 7 pull-up register (Continued) 52 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x0033 PUL6 0x0034 — 0x0035 PULG 0x0036 Register name R/W Initial value R/W 0b00000000 — — Port G pull-up register R/W 0b00000000 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000 0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000 0x0038 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000 0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000 0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000 0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000 0x003C PC11 8/16-bit PPG timer 11 control register R/W 0b00000000 0x003D PC10 8/16-bit PPG timer 10 control register R/W 0b00000000 0x003E PC21 8/16-bit PPG timer 21 control register R/W 0b00000000 0x003F PC20 8/16-bit PPG timer 20 control register R/W 0b00000000 0x0040 to 0x0047 — — — 0x0048 EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 0b00000000 0x0049 EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 0b00000000 0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000 0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000 0x004C EIC01 External interrupt circuit control register ch. 8/ch. 9 R/W 0b00000000 0x004D — — — 0x004E LVDR LVD reset voltage selection ID register R/W 0b00000000 0x004F LVDCC LVD reset circuit control register R/W 0b00000001 0x0050 to 0x0055 — — — 0x0056 SMC10 UART/SIO serial mode control register 1 ch. 0 R/W 0b00000000 0x0057 SMC20 UART/SIO serial mode control register 2 ch. 0 R/W 0b00100000 0x0058 SSR0 UART/SIO serial status and data register ch. 0 R/W 0b00000001 Port 6 pull-up register (Disabled) (Disabled) (Disabled) (Disabled) 0x0059 TDR0 UART/SIO serial output data register ch. 0 R/W 0b00000000 0x005A RDR0 UART/SIO serial input data register ch. 0 R 0b00000000 0x005B CMR0 Comparator control register ch. 0 R/W 0b11000101 0x005C to 0x005F — — — 0x0060 IBCR00 0x0061 0x0062 0x0063 0x0064 0x0065 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 (Disabled) I2C bus control register 0 ch. 0 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 I C bus control register 1 ch. 0 I C bus status register ch. 0 I C data register ch. 0 I C address register ch. 0 I C clock control register ch. 0 (Continued) DS702–00013–0v02-E 53 MB95850K/860K/870K Series Address Register abbreviation Register name R/W Initial value 0x0066 to 0x006B — (Disabled) — — 0x006C ADC1 8/10-bit A/D converter control register 1 R/W 0b00000000 0x006D ADC2 8/10-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/10-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/10-bit A/D converter data register (lower) R/W 0b00000000 0x0070 WCSR Watch counter control register R/W 0b00000000 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — — — 0x0E10 BPFREQ Beep output frequency register R/W 0b00000000 0x0E11 TER0 TS touch channel enable register 0 R/W 0b00000000 0x0E12 TER1 TS touch channel enable register 1 R/W 0b00000000 0x0E13 PSC TS prescaler control register R/W 0b00100000 0x0E14 WRESET TS warm reset register R/W 0b00000000 0x0E15 RSEL0 TS sensitivity select register 0 R/W 0b00000010 0x0E16 RSEL1 TS sensitivity select register 1 R/W 0b00010010 0x0E17 RSEL2 TS sensitivity select register 2 R/W 0b00010010 0x0E18 RSEL3 TS sensitivity select register 3 R/W 0b00010010 0x0E19 RSEL4 TS sensitivity select register 4 R/W 0b00010010 0x0E1A RSEL5 TS sensitivity select register 5 R/W 0b00010010 Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) 0x0E1B RSEL6 TS sensitivity select register 6 R/W 0b00010010 0x0E1C BPDUR TS beep duration setting register R/W 0b00000000 0x0E1D DIOR1 TS direct output control register 1 R/W 0b00000000 0x0E1E DIOR2 TS direct output control register 2 R/W 0b00000000 0x0E1F DIOR3 TS direct output control register 3 R/W 0b00000000 0x0E20 FTSEL TS feature select register R/W 0b00000100 (Continued) 54 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x0E21 AICWAT 0x0E22 Register name R/W Initial value TS AIC wait time setting register R/W 0b00100111 CALITV TS calibration interval setting register R/W 0b00110000 0x0E23 ITGTM TS integration time setting register R/W 0b00001111 0x0E24 IDLETM TS idle time setting register R/W 0b00001111 0x0E25 CONTROL TS control register R/W 0b00000000 0x0E26 INTMR TS interrupt mask register R/W 0b00011000 0x0E27 INTCR TS interrupt clear register R/W 0b00000000 0x0E28 FLTP TS filter period setting register R/W 0b00000000 0x0E29 FLTTH TS filter threshold setting register R/W 0b00000000 0x0E2A REFDLY TS reference delay setting register R/W 0b00000000 0x0E2B to 0x0E2F — — — 0x0E30 ALPH0 TS alpha value setting register ch. 0 R/W 0b00001000 0x0E31 ALPH1 TS alpha value setting register ch. 1 R/W 0b00001000 0x0E32 ALPH2 TS alpha value setting register ch. 2 R/W 0b00001000 0x0E33 ALPH3 TS alpha value setting register ch. 3 R/W 0b00001000 0x0E34 ALPH4 TS alpha value setting register ch. 4 R/W 0b00001000 0x0E35 ALPH5 TS alpha value setting register ch. 5 R/W 0b00001000 0x0E36 ALPH6 TS alpha value setting register ch. 6 R/W 0b00001000 0x0E37 ALPH7 TS alpha value setting register ch. 7 R/W 0b00001000 0x0E38 ALPH8 TS alpha value setting register ch. 8 R/W 0b00001000 0x0E39 ALPH9 TS alpha value setting register ch. 9 R/W 0b00001000 0x0E3A ALPH10 TS alpha value setting register ch. 10 R/W 0b00001000 0x0E3B ALPH11 TS alpha value setting register ch. 11 R/W 0b00001000 0x0E3C to 0x0E3F — — — 0x0E40 BETA R/W 0b00000100 0x0E41 to 0x0E4F — — — 0x0E50 STRTH0 TS touch strength threshold setting register ch. 0 R/W 0b00000001 0x0E51 STRTH1 TS touch strength threshold setting register ch. 1 R/W 0b00000001 0x0E52 STRTH2 TS touch strength threshold setting register ch. 2 R/W 0b00000001 0x0E53 STRTH3 TS touch strength threshold setting register ch. 3 R/W 0b00000001 0x0E54 STRTH4 TS touch strength threshold setting register ch. 4 R/W 0b00000001 0x0E55 STRTH5 TS touch strength threshold setting register ch. 5 R/W 0b00000001 0x0E56 STRTH6 TS touch strength threshold setting register ch. 6 R/W 0b00000001 0x0E57 STRTH7 TS touch strength threshold setting register ch. 7 R/W 0b00000001 0x0E58 STRTH8 TS touch strength threshold setting register ch. 8 R/W 0b00000001 0x0E59 STRTH9 TS touch strength threshold setting register ch. 9 R/W 0b00000001 (Disabled) (Disabled) TS beta value setting register (Disabled) (Continued) DS702–00013–0v02-E 55 MB95850K/860K/870K Series Address Register abbreviation 0x0E5A STRTH10 0x0E5B STRTH11 0x0E5C to 0x0E5F — 0x0E60 Register name R/W Initial value TS touch strength threshold setting register ch. 10 R/W 0b00000001 TS touch strength threshold setting register ch. 11 R/W 0b00000001 (Disabled) — — STR0 TS touch strength register ch. 0 R 0bXXXXXXXX 0x0E61 STR1 TS touch strength register ch. 1 R 0bXXXXXXXX 0x0E62 STR2 TS touch strength register ch. 2 R 0bXXXXXXXX 0x0E63 STR3 TS touch strength register ch. 3 R 0bXXXXXXXX 0x0E64 STR4 TS touch strength register ch. 4 R 0bXXXXXXXX 0x0E65 STR5 TS touch strength register ch. 5 R 0bXXXXXXXX 0x0E66 STR6 TS touch strength register ch. 6 R 0bXXXXXXXX 0x0E67 STR7 TS touch strength register ch. 7 R 0bXXXXXXXX 0x0E68 STR8 TS touch strength register ch. 8 R 0bXXXXXXXX 0x0E69 STR9 TS touch strength register ch. 9 R 0bXXXXXXXX 0x0E6A STR10 TS touch strength register ch. 10 R 0bXXXXXXXX 0x0E6B STR11 TS touch strength register ch. 11 R 0bXXXXXXXX 0x0E6C to 0x0E6F — — — 0x0E70 CALIP0 TS calibrated impedance register ch. 0 R 0b0XXXXXXX 0x0E71 CALIP1 TS calibrated impedance register ch. 1 R 0b0XXXXXXX 0x0E72 CALIP2 TS calibrated impedance register ch. 2 R 0b0XXXXXXX 0x0E73 CALIP3 TS calibrated impedance register ch. 3 R 0b0XXXXXXX 0x0E74 CALIP4 TS calibrated impedance register ch. 4 R 0b0XXXXXXX 0x0E75 CALIP5 TS calibrated impedance register ch. 5 R 0b0XXXXXXX 0x0E76 CALIP6 TS calibrated impedance register ch. 6 R 0b0XXXXXXX 0x0E77 CALIP7 TS calibrated impedance register ch. 7 R 0b0XXXXXXX 0x0E78 CALIP8 TS calibrated impedance register ch. 8 R 0b0XXXXXXX 0x0E79 CALIP9 TS calibrated impedance register ch. 9 R 0b0XXXXXXX 0x0E7A CALIP10 TS calibrated impedance register ch. 10 R 0b0XXXXXXX 0x0E7B CALIP11 TS calibrated impedance register ch. 11 R 0b0XXXXXXX 0x0E7C to 0x0E7F — — — (Disabled) (Disabled) 0x0E80 IMPE0 TS impedance register ch. 0 R 0b0XXXXXXX 0x0E81 IMPE1 TS impedance register ch. 1 R 0b0XXXXXXX 0x0E82 IMPE2 TS impedance register ch. 2 R 0b0XXXXXXX 0x0E83 IMPE3 TS impedance register ch. 3 R 0b0XXXXXXX 0x0E84 IMPE4 TS impedance register ch. 4 R 0b0XXXXXXX 0x0E85 IMPE5 TS impedance register ch. 5 R 0b0XXXXXXX (Continued) 56 DS702–00013–0v02-E MB95850K/860K/870K Series Address Register abbreviation 0x0E86 IMPE6 0x0E87 R/W Initial value TS impedance register ch. 6 R 0b0XXXXXXX IMPE7 TS impedance register ch. 7 R 0b0XXXXXXX 0x0E88 IMPE8 TS impedance register ch. 8 R 0b0XXXXXXX 0x0E89 IMPE9 TS impedance register ch. 9 R 0b0XXXXXXX 0x0E8A IMPE10 TS impedance register ch. 10 R 0b0XXXXXXX 0x0E8B IMPE11 TS impedance register ch. 11 R 0b0XXXXXXX 0x0E8C to 0x0E8F — — — 0x0E90 TOUCHL TS touch data register (lower) R 0bXXXXXXXX 0x0E91 TOUCHH TS touch data register (upper) R 0b0000XXXX 0x0E92 INTPR TS interrupt pending register R 0b000XXXXX 0x0E93 to 0x0F7F — — — 0x0F80 WRARH0 Wild register address setting register (upper) ch. 0 R/W 0b00000000 0x0F81 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 T11CR0 8/16-bit composite timer 11 status control register 0 R/W 0b00000000 0x0F98 T10CR0 8/16-bit composite timer 10 status control register 0 R/W 0b00000000 0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000 0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000 TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 0b00000000 0x0F9B Register name (Disabled) (Disabled) (Disabled) (Continued) DS702–00013–0v02-E 57 MB95850K/860K/870K Series Address Register abbreviation 0x0F9C PPS01 0x0F9D Register name R/W Initial value 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111 PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111 0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111 0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111 0x0FA0 PPS11 8/16-bit PPG11 cycle setting buffer register R/W 0b11111111 0x0FA1 PPS10 8/16-bit PPG10 cycle setting buffer register R/W 0b11111111 0x0FA2 PDS11 8/16-bit PPG11 duty setting buffer register R/W 0b11111111 0x0FA3 PDS10 8/16-bit PPG10 duty setting buffer register R/W 0b11111111 0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000 0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000 0x0FA6 PPS21 8/16-bit PPG21 cycle setting buffer register R/W 0b11111111 0x0FA7 PPS20 8/16-bit PPG20 cycle setting buffer register R/W 0b11111111 0x0FA8, 0x0FA9 — — — 0x0FAA PDS21 8/16-bit PPG21 duty setting buffer register R/W 0b11111111 0x0FAB PDS20 8/16-bit PPG20 duty setting buffer register R/W 0b11111111 0x0FAC to 0x0FBD — — — 0x0FBE PSSR0 UART/SIO dedicated baud generator prescaler select register ch. 0 R/W 0b00000000 0x0FBF BRSR0 UART/SIO dedicated baud generator baud rate setting register ch. 0 R/W 0b00000000 0x0FC0 TIDR0 Touch input disable register 0 R/W 0b00000000 0x0FC1 TIDR1 Touch input disable register 1 R/W 0b00000000 0x0FC2 — — — 0x0FC3 AIDRL A/D input disable register (lower) R/W 0b00000000 0x0FC4 LVDPW LVD reset circuit password register R/W 0b00000000 0x0FC5 to 0x0FE2 — — — 0x0FE3 WCDR Watch counter data register R/W 0b00111111 0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX 0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX 0x0FE6 — — — 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R/W 0b000XXXXX 0x0FE8 SYSC System configuration register R/W 0b11000011 0x0FE9 CMCR Clock monitoring control register R/W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 (Disabled) (Disabled) (Disabled) (Disabled) (Disabled) (Continued) 58 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) Address Register abbreviation 0x0FEB WDTH 0x0FEC WDTL 0x0FED, 0x0FEE — 0x0FEF WICR 0x0FF0 to 0x0FFF — Register name R/W Initial value Watchdog timer selection ID register (upper) R 0bXXXXXXXX Watchdog timer selection ID register (lower) R 0bXXXXXXXX — — R/W 0b01000000 — — (Disabled) Interrupt pin selection circuit control register (Disabled) • R/W access symbols R/W : Readable/Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. DS702–00013–0v02-E 59 MB95850K/860K/870K Series ■ I/O PORTS (MB95850K SERIES) • List of port registers Register name Read/Write Initial value Port 0 data register PDR0 R, RM/W 0b00000000 Port 0 direction register DDR0 R/W 0b00000000 Port 1 data register PDR1 R, RM/W 0b00000000 Port 1 direction register DDR1 R/W 0b00000000 Port 4 data register PDR4 R, RM/W 0b00000000 Port 4 direction register DDR4 R/W 0b00000000 Port 6 data register PDR6 R, RM/W 0b00000000 Port 6 direction register DDR6 R/W 0b00000000 Port 7 data register PDR7 R, RM/W 0b00000000 Port 7 direction register DDR7 R/W 0b00000000 Port F data register PDRF R, RM/W 0b00000000 Port F direction register DDRF R/W 0b00000000 Port G data register PDRG R, RM/W 0b00000000 Port G direction register DDRG R/W 0b00000000 Port 0 pull-up register PUL0 R/W 0b00000000 Port 1 pull-up register PUL1 R/W 0b00000000 Port 6 pull-up register PUL6 R/W 0b00000000 Port 7 pull-up register PUL7 R/W 0b00000000 Port G pull-up register PULG R/W 0b00000000 A/D input disable register (lower) AIDRL R/W 0b00000000 Touch input disable register 0 TIDR0 R/W 0b00000000 Touch input disable register 1 TIDR1 R/W 0b00000000 R/W : Readable/writable (The read value is the same as the write value.) R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write (RMW) type of instruction.) 60 DS702–00013–0v02-E MB95850K/860K/870K Series 1. Port 0 Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 0 configuration Port 0 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 0 data register (PDR0) • Port 0 direction register (DDR0) • Port 0 pull-up register (PUL0) • A/D input disable register (lower) (AIDRL) (2) Block diagrams of port 0 • P04/AN00/BEEP/DIO01/TO01 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN00) • Beep output pin (BEEP) • TS direct output ch. 1 pin (DIO01) • 8/16-bit composite timer ch. 0 output pin (TO01) • P06/AN02/CMP0_O/PPG00 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN02) • Comparator ch. 0 digital output pin (CMP0_O) • 816-bit PPG ch. 0 output pin (PPG00) • Block diagram of P04/AN00/BEEP/DIO01/TO01 and P06/AN02/CMP0_O/PPG00 Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write (Continued) DS702–00013–0v02-E 61 MB95850K/860K/870K Series • P05/INT05/AN01/CMP0_N/TO00 pin This pin has the following peripheral functions: • External interrupt input pin (INT05) • 8/10-bit A/D converter analog input pin (AN01) • Comparator ch. 0 inverting analog input (negative input) pin (CMP0_N) • 8/16-bit composite timer ch. 0 output pin (TO00) • Block diagram of P05/INT05/AN01/CMP0_N/TO00 Comparator analog input Comparator analog input disable Peripheral function input Peripheral function input enable (INT05) Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write (Continued) 62 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • P07/AN03/CMP0_P/PPG01 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN03) • Comparator ch. 0 non-inverting analog input (positive input) pin (CMP0_P) • 8/16-bit PPG ch. 0 output pin (PPG01) • Block diagram of P07/AN03/CMP0_P/PPG01 Comparator analog input Comparator analog input disable Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write DS702–00013–0v02-E 63 MB95850K/860K/870K Series (3) Port 0 registers • Port 0 register functions Register abbreviation PDR0 DDR0 PUL0 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Analog input enabled 1 Port input enabled • Correspondence between registers and pins for port 0 Correspondence between related register bits and pins Pin name P07 P06 P05 P04 bit7 bit6 bit5 bit4 bit5 bit4 bit1 bit0 - - - - - - - - PDR0 DDR0 PUL0 AIDRL 64 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port 0 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR0 register to external pins. • If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR0 register returns the PDR0 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the analog input function as an input port, set the bit in the A/D input disable register (lower) (AIDRL) corresponding to that pin to “1”. • If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”. • When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”. • Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with the analog input function, its port input is disabled because the AIDRL register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT05), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the corresponding bit in the PUL0 register to “0”. (Continued) DS702–00013–0v02-E 65 MB95850K/860K/870K Series (Continued) • Operation as an external interrupt input pin • Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register. • Operation as a comparator input pin • Set the bit in the AIDRL register corresponding to the comparator input pin to “0”. • Regardless of the value of the PDR0 register and that of the DDR0 register, if the comparator analog input enable bit in the comparator control register (CMR0:VCID) is set to “0”, the comparator input function is enabled. • To disable the comparator input function, set the VCID bit to “1”. • For details of the comparator, refer to “CHAPTER 25 COMPARATOR” in the hardware manual of the MB95850K/860K/870K Series. 66 DS702–00013–0v02-E MB95850K/860K/870K Series 2. Port 1 Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 1 configuration Port 1 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 1 data register (PDR1) • Port 1 direction register (DDR1) • Port 1 pull-up register (PUL1) (2) Block diagrams of port 1 • P10/DBG/EC0 pin This pin has the following peripheral functions: • DBG input pin (DBG) • 8/16-bit composite timer ch. 0 clock input pin (EC0) • Block diagram of P10/DBG/EC0 Peripheral function input Hysteresis 0 1 PDR1 read Internal bus PDR1 Pin OD PDR1 write Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) (Continued) DS702–00013–0v02-E 67 MB95850K/860K/870K Series • P13/INT04/UI0/DIO02 pin This pin has the following peripheral functions: • External interrupt input pin (INT04) • UART/SIO ch. 0 data input pin (UI0) • TS direct output ch. 2 pin (DIO02) • Block diagram of P13/INT04/UI0/DIO02 Peripheral function input Peripheral function input enable (INT04) Peripheral function output enable Peripheral function output Pull-up 0 1 PDR1 read CMOS 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write (Continued) 68 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • P14/INT01/UO0/DIO00 pin This pin has the following peripheral functions: • External interrupt input pin (INT01) • UART/SIO ch. 0 data output pin (UO0) • TS direct output ch. 0 pin (DIO00) • P15/INT00/UCK0 pin This pin has the following peripheral functions: • External interrupt input pin (INT00) • UART/SIO ch. 0 clock I/O pin (UCK0) • Block diagram of P14/INT01/UO0/DIO00 and P15/INT00/UCK0 Peripheral function input Peripheral function input enable (INT00 and INT01) Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write DS702–00013–0v02-E 69 MB95850K/860K/870K Series (3) Port 1 registers • Port 1 register functions Register abbreviation PDR1 DDR1 PUL1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 1 Correspondence between related register bits and pins Pin name - - P15 P14 P13 - - P10 - - bit5 bit4 bit3 - - bit0* PDR1 DDR1 PUL1 *: Though P10 has no pull-up function, bit0 in the PUL1 register can still be accessed. The operation of P10 is not affected by the setting of bit0 in the PUL1 register. 70 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port 1 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR1 register to external pins. • If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR1 register returns the PDR1 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input from the external interrupt (INT00, INT01 and INT04) is enabled, or if the interrupt input of P10/DBG/EC0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an external interrupt input pin • Set the bit in the DDR1 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register. DS702–00013–0v02-E 71 MB95850K/860K/870K Series 3. Port 4 Port 4 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 4 configuration Port 4 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 4 data register (PDR4) • Port 4 direction register (DDR4) (2) Block diagrams of port 4 • P46/INT06/SDA pin This pin has the following peripheral functions: • External interrupt input pin (INT06) • I2C bus interface ch. 0 data I/O pin (SDA) • P47/INT07/SCL pin This pin has the following peripheral functions: • External interrupt input pin (INT07) • I2C bus interface ch. 0 clock I/O pin (SCL) • Block diagram of P46/INT06/SDA and P47/INT07/SCL Peripheral function input Peripheral function input enable (INT06 and INT07) Peripheral function output enable Peripheral function output CMOS 0 1 PDR4 read PDR4 Internal bus Pin 1 0 OD PDR4 write Executing bit manipulation instruction DDR4 read DDR4 DDR4 write 72 Stop mode, watch mode (SPL = 1) DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 4 registers • Port 4 register functions Register abbreviation PDR4 DDR4 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR4 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR4 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 4 Correspondence between related register bits and pins Pin name PDR4 DDR4 P47 P46 - - - - - - bit7 bit6 - - - - - - DS702–00013–0v02-E 73 MB95850K/860K/870K Series (4) Port 4 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR4 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR4 register to external pins. • If data is written to the PDR4 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR4 register returns the PDR4 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR4 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR4 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR4 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR4 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR4 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR4 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR4 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR4 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR4 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT06 and INT07), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an external interrupt input pin • Set the bit in the DDR4 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. 74 DS702–00013–0v02-E MB95850K/860K/870K Series 4. Port 6 Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 6 configuration Port 6 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 6 data register (PDR6) • Port 6 direction register (DDR6) • Port 6 pull-up register (PUL6) • Touch input disable register 0 (TIDR0) (2) Block diagrams of port 6 • P63/AREF pin This pin has the following peripheral function: • TS reference input pin (AREF) • P65/S01 pin This pin has the following peripheral function: • TS touch ch. 1 input pin (S01) • P66/S02 pin This pin has the following peripheral function: • TS touch ch. 2 input pin (S02) • P67/S03 pin This pin has the following peripheral function: • TS touch ch. 3 input pin (S03) • Block diagram of P63/AREF, P65/S01, P66/S02 and P67/S03 Touch input Hysteresis 0 Pull-up 1 PDR6 read PDR6 Pin PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write TIDR0 read TIDR0 TIDR0 write DS702–00013–0v02-E 75 MB95850K/860K/870K Series (3) Port 6 registers • Port 6 register functions Register abbreviation PDR6 DDR6 PUL6 TIDR0 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Touch input or reference input enabled 1 Port input enabled • Correspondence between registers and pins for port 6 Correspondence between related register bits and pins Pin name P67 P66 P65 bit7 bit6 bit5 bit7 bit6 bit5 - P63 - - - - - - PDR6 DDR6 PUL6 TIDR0 76 - bit3 bit3 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port 6 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”. • When a pin is used as an output port, it outputs the value of the PDR6 register to external pins. • If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR6 register returns the PDR6 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”. • When using a pin shared with the touch input function as an input port, set the bit in the touch input disable register 0 (TIDR0) corresponding to that pin to “1”. • If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. As for a pin shared with the touch input function, its port input is disabled because the TIDR0 register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • When the stop enable bit in the TS prescaler control register (PSC:STPE) is set to “1”, the TS can operate in stop mode or watch mode, the touch input is enabled and is not blocked. The TS wakes up in stop mode or watch mode provided that the TINT (touch interrupt) and the GINT (general interrupt) are set to enable the TS to wake up in stop mode or watch mode. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as a touch input pin Set the bit in the DDR6 register corresponding to the touch input pin to “0”, the bit in the TIDR0 register corresponding to the same pin to “0”, and the bit in the PUL6 register corresponding to the same pin to “0”. • Operation of the pull-up register Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register. DS702–00013–0v02-E 77 MB95850K/860K/870K Series 5. Port 7 Port 7 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 7 configuration Port 7 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 7 data register (PDR7) • Port 6 direction register (DDR7) • Port 6 pull-up register (PUL7) • Touch input disable register 1 (TIDR1) (2) Block diagrams of port 7 • P70/S04 pin This pin has the following peripheral function: • TS touch ch. 4 input pin (S04) • P71/S05 pin This pin has the following peripheral function: • TS touch ch. 5 input pin (S05) • Block diagram of P70/S04 and P71/S05 Touch input Hysteresis 0 Pull-up 1 PDR7 read PDR7 Pin PDR7 write Internal bus Executing bit manipulation instruction DDR7 read DDR7 DDR7 write Stop mode, watch mode (SPL = 1) PUL7 read PUL7 PUL7 write TIDR1 read TIDR1 TIDR1 write 78 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 7 registers • Port 7 register functions Register abbreviation PDR7 DDR7 PUL7 TIDR1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR7 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR7 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Touch input enabled 1 Port input enabled • Correspondence between registers and pins for port 7 Correspondence between related register bits and pins Pin name - - - - - - P71 P70 - - - - - - bit1 bit0 PDR7 DDR7 PUL7 TIDR1 DS702–00013–0v02-E 79 MB95850K/860K/870K Series (4) Port 7 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR7 register corresponding to that pin is set to “1”. • When a pin is used as an output port, it outputs the value of the PDR7 register to external pins. • If data is written to the PDR7 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR7 register returns the PDR7 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR7 register corresponding to that pin is set to “0”. • When using a pin shared with the touch input function as an input port, set the bit in the touch input disable register 1 (TIDR1) corresponding to that pin to “1”. • If data is written to the PDR7 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR7 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR7 register, the PDR7 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR7 register are initialized to “0” and port input is enabled. As for a pin shared with the touch input function, its port input is disabled because the TIDR1 register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR7 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • When the stop enable bit in the TS prescaler control register (PSC:STPE) is set to “1”, the TS can operate in stop mode or watch mode, the touch input is enabled and is not blocked. The TS wakes up in stop mode or watch mode provided that the TINT (touch interrupt) and the GINT (general interrupt) are set to enable the TS to wake up in stop mode or watch mode. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as a touch input pin Set the bit in the DDR7 register corresponding to the touch input pin to “0”, the bit in the TIDR1 register corresponding to the same pin to “0”, and the bit in the PUL7 register corresponding to the same pin to “0”. • Operation of the pull-up register Setting the bit in the PUL7 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL7 register. 80 DS702–00013–0v02-E MB95850K/860K/870K Series 6. Port F Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port F configuration Port F is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port F data register (PDRF) • Port F direction register (DDRF) (2) Block diagrams of port F • PF0/X0 pin This pin has the following peripheral function: • Main clock input oscillation pin (X0) • PF1/X1 pin This pin has the following peripheral function: • Main clock I/O oscillation pin (X1) • Block diagram of PF0/X0 and PF1/X1 Hysteresis 0 1 PDRF read Internal bus PDRF Pin PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) (Continued) DS702–00013–0v02-E 81 MB95850K/860K/870K Series (Continued) • PF2/RST pin This pin has the following peripheral function: • Reset pin (RST) • Block diagram of PF2/RST Reset input Reset input enable Reset output enable Reset output Hysteresis 0 1 PDRF read Internal bus Pin 1 PDRF 0 OD PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write 82 Stop mode, watch mode (SPL = 1) DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port F registers • Port F register functions Register abbreviation PDRF DDRF Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port F Correspondence between related register bits and pins Pin name PDRF DDRF - - - - - PF2 PF1 PF0 - - - - - bit2 bit1 bit0 DS702–00013–0v02-E 83 MB95850K/860K/870K Series (4) Port F operations • Operation as an output port • A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRF register to external pins. • If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRF register returns the PDRF register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”. • If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRF register, the PDRF register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. 84 DS702–00013–0v02-E MB95850K/860K/870K Series 7. Port G Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port G configuration Port G is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port G data register (PDRG) • Port G direction register (DDRG) • Port G pull-up register (PULG) (2) Block diagram of port G • PG1/X0A/DIO04 pin This pin has the following peripheral functions: • Subclock input oscillation pin (X0A) • TS direct output ch. 4 pin (DIO04) • PG2/X1A/DIO03 pin This pin has the following peripheral functions: • Subclock I/O oscillation pin (X1A) • TS direct output ch. 3 pin (DIO03) • Block diagram of PG1/X0A/DIO04 and PG2/X1A/DIO03 Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDRG read 1 PDRG 0 Pin PDRG write Internal bus Executing bit manipulation instruction DDRG read DDRG DDRG write Stop mode, watch mode (SPL = 1) PULG read PULG PULG write DS702–00013–0v02-E 85 MB95850K/860K/870K Series (3) Port G registers • Port G register functions Register abbreviation PDRG DDRG PULG Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled • Correspondence between registers and pins for port G Correspondence between related register bits and pins Pin name - - - - - PG2 PG1 - - - - - - bit2 bit1 - PDRG DDRG PULG 86 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port G operations • Operation as an output port • A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRG register to external pins. • If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRG register returns the PDRG register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDRG register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDRG register. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register. DS702–00013–0v02-E 87 MB95850K/860K/870K Series ■ I/O PORTS (MB95860K SERIES) • List of port registers Register name Read/Write Initial value Port 0 data register PDR0 R, RM/W 0b00000000 Port 0 direction register DDR0 R/W 0b00000000 Port 1 data register PDR1 R, RM/W 0b00000000 Port 1 direction register DDR1 R/W 0b00000000 Port 4 data register PDR4 R, RM/W 0b00000000 Port 4 direction register DDR4 R/W 0b00000000 Port 6 data register PDR6 R, RM/W 0b00000000 Port 6 direction register DDR6 R/W 0b00000000 Port 7 data register PDR7 R, RM/W 0b00000000 Port 7 direction register DDR7 R/W 0b00000000 Port F data register PDRF R, RM/W 0b00000000 Port F direction register DDRF R/W 0b00000000 Port G data register PDRG R, RM/W 0b00000000 Port G direction register DDRG R/W 0b00000000 Port 0 pull-up register PUL0 R/W 0b00000000 Port 1 pull-up register PUL1 R/W 0b00000000 Port 4 pull-up register PUL4 R/W 0b00000000 Port 6 pull-up register PUL6 R/W 0b00000000 Port 7 pull-up register PUL7 R/W 0b00000000 Port G pull-up register PULG R/W 0b00000000 A/D input disable register (lower) AIDRL R/W 0b00000000 Touch input disable register 0 TIDR0 R/W 0b00000000 Touch input disable register 1 TIDR1 R/W 0b00000000 R/W : Readable/writable (The read value is the same as the write value.) R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write (RMW) type of instruction.) 88 DS702–00013–0v02-E MB95850K/860K/870K Series 1. Port 0 Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 0 configuration Port 0 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 0 data register (PDR0) • Port 0 direction register (DDR0) • Port 0 pull-up register (PUL0) • A/D input disable register (lower) (AIDRL) (2) Block diagrams of port 0 • P02/INT02/TO10 pin This pin has the following peripheral functions: • External interrupt input pin (INT02) • 8/16-bit composite timer ch. 1 output pin (TO10) • P03/INT03/TO11 pin This pin has the following peripheral functions: • External interrupt input pin (INT03) • 8/16-bit composite timer ch. 1 output pin (TO11) • Block diagram of P02/INT02/TO10 and P03/INT03/TO11 Peripheral function input Peripheral function input enable (INT02 and INT03) Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write (Continued) DS702–00013–0v02-E 89 MB95850K/860K/870K Series • P04/AN00/BEEP/DIO01 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN00) • Beep output pin (BEEP) • TS direct output ch. 1 pin (DIO01) • P06/AN02/CMP0_O/PPG00 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN02) • Comparator ch. 0 digital output pin (CMP0_O) • 816-bit PPG ch. 0 output pin (PPG00) • Block diagram of P04/AN00/BEEP/DIO01 and P06/AN02/CMP0_O/PPG00 Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write (Continued) 90 DS702–00013–0v02-E MB95850K/860K/870K Series • P05/INT05/AN01/CMP0_N pin This pin has the following peripheral functions: • External interrupt input pin (INT05) • 8/10-bit A/D converter analog input pin (AN01) • Comparator ch. 0 inverting analog input (negative input) pin (CMP0_N) • Block diagram of P05/INT05/AN01/CMP0_N Comparator analog input Comparator analog input disable Peripheral function input Peripheral function input enable (INT05) A/D analog input Hysteresis 0 Pull-up 1 PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write (Continued) DS702–00013–0v02-E 91 MB95850K/860K/870K Series (Continued) • P07/AN03/CMP0_P/PPG01 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN03) • Comparator ch. 0 non-inverting analog input (positive input) pin (CMP0_P) • 8/16-bit PPG ch. 0 output pin (PPG01) • Block diagram of P07/AN03/CMP0_P/PPG01 Comparator analog input Comparator analog input disable Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write 92 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 0 registers • Port 0 register functions Register abbreviation PDR0 DDR0 PUL0 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Analog input enabled 1 Port input enabled • Correspondence between registers and pins for port 0 Correspondence between related register bits and pins Pin name P07 P06 P05 P04 P03 P02 bit7 bit6 bit5 bit4 bit3 bit2 bit5 bit4 bit1 bit0 - - - - - - PDR0 DDR0 PUL0 AIDRL DS702–00013–0v02-E 93 MB95850K/860K/870K Series (4) Port 0 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR0 register to external pins. • If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR0 register returns the PDR0 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the analog input function as an input port, set the bit in the A/D input disable register (lower) (AIDRL) corresponding to that pin to “1”. • If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”. • When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”. • Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with the analog input function, its port input is disabled because the AIDRL register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT02, INT03 and INT05), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the corresponding bit in the PUL0 register to “0”. (Continued) 94 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • Operation as an external interrupt input pin • Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register. • Operation as a comparator input pin • Set the bit in the AIDRL register corresponding to the comparator input pin to “0”. • Regardless of the value of the PDR0 register and that of the DDR0 register, if the comparator analog input enable bit in the comparator control register (CMR0:VCID) is set to “0”, the comparator input function is enabled. • To disable the comparator input function, set the VCID bit to “1”. • For details of the comparator, refer to “CHAPTER 25 COMPARATOR” in the hardware manual of the MB95850K/860K/870K Series. DS702–00013–0v02-E 95 MB95850K/860K/870K Series 2. Port 1 Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 1 configuration Port 1 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 1 data register (PDR1) • Port 1 direction register (DDR1) • Port 1 pull-up register (PUL1) (2) Block diagrams of port 1 • P10/DBG/EC0 pin This pin has the following peripheral functions: • DBG input pin (DBG) • 8/16-bit composite timer ch. 0 clock input pin (EC0) • Block diagram of P10/DBG/EC0 Peripheral function input Hysteresis 0 1 PDR1 read Internal bus PDR1 Pin OD PDR1 write Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) (Continued) 96 DS702–00013–0v02-E MB95850K/860K/870K Series • P13/INT04/UI0/DIO02 pin This pin has the following peripheral functions: • External interrupt input pin (INT04) • UART/SIO ch. 0 data input pin (UI0) • TS direct output ch. 2 pin (DIO02) • Block diagram of P13/INT04/UI0/DIO02 Peripheral function input Peripheral function input enable (INT04) Peripheral function output enable Peripheral function output Pull-up 0 1 PDR1 read CMOS 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write (Continued) DS702–00013–0v02-E 97 MB95850K/860K/870K Series (Continued) • P14/INT01/UO0 pin This pin has the following peripheral functions: • External interrupt input pin (INT01) • UART/SIO ch. 0 data output pin (UO0) • P15/INT00/UCK0 pin This pin has the following peripheral functions: • External interrupt input pin (INT00) • UART/SIO ch. 0 clock I/O pin (UCK0) • Block diagram of P14/INT01/UO0 and P15/INT00/UCK0 Peripheral function input Peripheral function input enable (INT00 and INT01) Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write 98 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 1 registers • Port 1 register functions Register abbreviation PDR1 DDR1 PUL1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 1 Correspondence between related register bits and pins Pin name - - P15 P14 P13 - - P10 - - bit5 bit4 bit3 - - bit0* PDR1 DDR1 PUL1 *: Though P10 has no pull-up function, bit0 in the PUL1 register can still be accessed. The operation of P10 is not affected by the setting of bit0 in the PUL1 register. DS702–00013–0v02-E 99 MB95850K/860K/870K Series (4) Port 1 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR1 register to external pins. • If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR1 register returns the PDR1 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input from the external interrupt (INT00, INT01 and INT04) is enabled, or if the interrupt input of P10/DBG/EC0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an external interrupt input pin • Set the bit in the DDR1 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register. 100 DS702–00013–0v02-E MB95850K/860K/870K Series 3. Port 4 Port 4 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 4 configuration Port 4 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 4 data register (PDR4) • Port 4 direction register (DDR4) • Port 4 pull-up register (PUL4) • A/D input disable register (lower) (AIDRL) (2) Block diagrams of port 4 • P44/AN06/TO00/DIO03/PPG10 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN06) • 8/16-bit composite timer ch. 0 output pin (TO00) • TS direct output ch. 3 pin (DIO03) • 8/16-bit PPG ch. 1 output pin (PPG10) • P45/AN07/TO01/DIO04/PPG11 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN07) • 8/16-bit composite timer ch. 0 output pin (TO01) • TS direct output ch. 4 pin (DIO04) • 8/16-bit PPG ch. 1 output pin (PPG11) • Block diagram of P44/AN06/TO00/DIO03/PPG10 and P45/AN07/TO01/DIO04/PPG11 Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR4 read 1 PDR4 0 Pin PDR4 write Internal bus Executing bit manipulation instruction DDR4 read DDR4 DDR4 write Stop mode, watch mode (SPL = 1) PUL4 read PUL4 PUL4 write AIDRL read AIDRL AIDRL write (Continued) DS702–00013–0v02-E 101 MB95850K/860K/870K Series (Continued) • P46/INT06/SDA pin This pin has the following peripheral functions: • External interrupt input pin (INT06) • I2C bus interface ch. 0 data I/O pin (SDA) • P47/INT07/SCL pin This pin has the following peripheral functions: • External interrupt input pin (INT07) • I2C bus interface ch. 0 clock I/O pin (SCL) • Block diagram of P46/INT06/SDA and P47/INT07/SCL Peripheral function input Peripheral function input enable (INT06 and INT07) Peripheral function output enable Peripheral function output CMOS 0 1 PDR4 read Internal bus Pin 1 PDR4 0 OD PDR4 write Executing bit manipulation instruction DDR4 read DDR4 DDR4 write 102 Stop mode, watch mode (SPL = 1) DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 4 registers • Port 4 register functions Register abbreviation PDR4 DDR4 PUL4 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR4 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR4 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Analog input enabled 1 Port input enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 4 Correspondence between related register bits and pins Pin name PDR4 DDR4 PUL4 AIDRL P47 P46 bit7 bit6 - DS702–00013–0v02-E - P45 P44 bit5 bit4 bit7 bit6 - - - - - - - - 103 MB95850K/860K/870K Series (4) Port 4 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR4 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR4 register to external pins. • If data is written to the PDR4 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR4 register returns the PDR4 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR4 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the analog input function as an input port, set the bit in the A/D input disable register (lower) (AIDRL) corresponding to that pin to “1”. • If data is written to the PDR4 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR4 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR4 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR4 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR4 register corresponding to the input pin of a peripheral function to “0”. • When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”. • Reading the PDR4 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR4 register are initialized to “0” and port input is enabled. As for a pin shared with the analog input function, its port input is disabled because the AIDRL register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR4 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT06 and INT07), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR4 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the corresponding bit in the PUL4 register to “0”. (Continued) 104 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • Operation as an external interrupt input pin • Set the bit in the DDR4 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL4 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL4 register. DS702–00013–0v02-E 105 MB95850K/860K/870K Series 4. Port 6 Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 6 configuration Port 6 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 6 data register (PDR6) • Port 6 direction register (DDR6) • Port 6 pull-up register (PUL6) • Touch input disable register 0 (TIDR0) (2) Block diagrams of port 6 • P60/EC1/DIO00 pin This pin has the following peripheral functions: • 8/16-bit composite timer ch. 1 clock input pin (EC1) • TS direct output ch. 0 pin (DIO00) • Block diagram of P60/EC1/DIO00 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR6 read 1 PDR6 0 Pin PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write (Continued) 106 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • P63/AREF pin This pin has the following peripheral function: • TS reference input pin (AREF) • P64/S00 pin This pin has the following peripheral function: • TS touch ch. 0 input pin (S00) • P65/S01 pin This pin has the following peripheral function: • TS touch ch. 1 input pin (S01) • P66/S02 pin This pin has the following peripheral function: • TS touch ch. 2 input pin (S02) • P67/S03 pin This pin has the following peripheral function: • TS touch ch. 3 input pin (S03) • Block diagram of P63/AREF, P64/S00, P65/S01, P66/S02 and P67/S03 Touch input Hysteresis 0 Pull-up 1 PDR6 read PDR6 Pin PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write TIDR0 read TIDR0 TIDR0 write DS702–00013–0v02-E 107 MB95850K/860K/870K Series (3) Port 6 registers • Port 6 register functions Register abbreviation PDR6 DDR6 PUL6 TIDR0 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Touch input or reference input enabled 1 Port input enabled • Correspondence between registers and pins for port 6 Correspondence between related register bits and pins Pin name P67 P66 P65 P64 P63 bit7 bit6 bit5 bit4 bit3 bit7 bit6 bit5 bit4 bit3 - - - - P60 PDR6 DDR6 PUL6 TIDR0 108 bit0 - DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port 6 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR6 register to external pins. • If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR6 register returns the PDR6 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the touch input function as an input port, set the bit in the touch input disable register 0 (TIDR0) corresponding to that pin to “1”. • If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR6 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR6 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. As for a pin shared with the touch input function, its port input is disabled because the TIDR0 register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P60/EC1/DIO00 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • When the stop enable bit in the TS prescaler control register (PSC:STPE) is set to “1”, the TS can operate in stop mode or watch mode, the touch input is enabled and is not blocked. The TS wakes up in stop mode or watch mode provided that the TINT (touch interrupt) and the GINT (general interrupt) are set to enable the TS to wake up in stop mode or watch mode. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as a touch input pin Set the bit in the DDR6 register corresponding to the touch input pin to “0”, the bit in the TIDR0 register corresponding to the same pin to “0”, and the bit in the PUL6 register corresponding to the same pin to “0”. (Continued) DS702–00013–0v02-E 109 MB95850K/860K/870K Series (Continued) • Operation of the pull-up register Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register. 110 DS702–00013–0v02-E MB95850K/860K/870K Series 5. Port 7 Port 7 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 7 configuration Port 7 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 7 data register (PDR7) • Port 6 direction register (DDR7) • Port 6 pull-up register (PUL7) • Touch input disable register 1 (TIDR1) DS702–00013–0v02-E 111 MB95850K/860K/870K Series (2) Block diagrams of port 7 • P70/S04 pin This pin has the following peripheral function: • TS touch ch. 4 input pin (S04) • P71/S05 pin This pin has the following peripheral function: • TS touch ch. 5 input pin (S05) • P72/S06 pin This pin has the following peripheral function: • TS touch ch. 6 input pin (S06) • P73/S07 pin This pin has the following peripheral function: • TS touch ch. 7 input pin (S07) • Block diagram of P70/S04, P71/S05, P72/S06 and P73/S07 Touch input Hysteresis 0 Pull-up 1 PDR7 read PDR7 Pin PDR7 write Internal bus Executing bit manipulation instruction DDR7 read DDR7 DDR7 write Stop mode, watch mode (SPL = 1) PUL7 read PUL7 PUL7 write TIDR1 read TIDR1 TIDR1 write 112 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 7 registers • Port 7 register functions Register abbreviation PDR7 DDR7 PUL7 TIDR1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR7 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR7 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Touch input enabled 1 Port input enabled • Correspondence between registers and pins for port 7 Correspondence between related register bits and pins Pin name - - - - P73 P72 P71 P70 - - - - bit3 bit2 bit1 bit0 PDR7 DDR7 PUL7 TIDR1 DS702–00013–0v02-E 113 MB95850K/860K/870K Series (4) Port 7 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR7 register corresponding to that pin is set to “1”. • When a pin is used as an output port, it outputs the value of the PDR7 register to external pins. • If data is written to the PDR7 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR7 register returns the PDR7 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR7 register corresponding to that pin is set to “0”. • When using a pin shared with the touch input function as an input port, set the bit in the touch input disable register 1 (TIDR1) corresponding to that pin to “1”. • If data is written to the PDR7 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR7 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR7 register, the PDR7 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR7 register are initialized to “0” and port input is enabled. As for a pin shared with the touch input function, its port input is disabled because the TIDR1 register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR7 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • When the stop enable bit in the TS prescaler control register (PSC:STPE) is set to “1”, the TS can operate in stop mode or watch mode, the touch input is enabled and is not blocked. The TS wakes up in stop mode or watch mode provided that the TINT (touch interrupt) and the GINT (general interrupt) are set to enable the TS to wake up in stop mode or watch mode. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as a touch input pin Set the bit in the DDR7 register corresponding to the touch input pin to “0”, the bit in the TIDR1 register corresponding to the same pin to “0”, and the bit in the PUL7 register corresponding to the same pin to “0”. • Operation of the pull-up register Setting the bit in the PUL7 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL7 register. 114 DS702–00013–0v02-E MB95850K/860K/870K Series 6. Port F Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port F configuration Port F is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port F data register (PDRF) • Port F direction register (DDRF) (2) Block diagrams of port F • PF0/X0 pin This pin has the following peripheral function: • Main clock input oscillation pin (X0) • PF1/X1 pin This pin has the following peripheral function: • Main clock I/O oscillation pin (X1) • Block diagram of PF0/X0 and PF1/X1 Hysteresis 0 1 PDRF read Internal bus PDRF Pin PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) (Continued) DS702–00013–0v02-E 115 MB95850K/860K/870K Series (Continued) • PF2/RST pin This pin has the following peripheral function: • Reset pin (RST) • Block diagram of PF2/RST Reset input Reset input enable Reset output enable Reset output Hysteresis 0 1 PDRF read Internal bus Pin 1 PDRF 0 OD PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write 116 Stop mode, watch mode (SPL = 1) DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port F registers • Port F register functions Register abbreviation PDRF DDRF Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port F Correspondence between related register bits and pins Pin name PDRF DDRF - - - - - PF2 PF1 PF0 - - - - - bit2 bit1 bit0 DS702–00013–0v02-E 117 MB95850K/860K/870K Series (4) Port F operations • Operation as an output port • A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRF register to external pins. • If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRF register returns the PDRF register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”. • If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRF register, the PDRF register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. 118 DS702–00013–0v02-E MB95850K/860K/870K Series 7. Port G Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port G configuration Port G is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port G data register (PDRG) • Port G direction register (DDRG) • Port G pull-up register (PULG) (2) Block diagram of port G • PG1/X0A/DIO04 pin This pin has the following peripheral functions: • Subclock input oscillation pin (X0A) • TS direct output ch. 4 pin (DIO04) • PG2/X1A/DIO03 pin This pin has the following peripheral functions: • Subclock I/O oscillation pin (X1A) • TS direct output ch. 3 pin (DIO03) • Block diagram of PG1/X0A/DIO04 and PG2/X1A/DIO03 Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDRG read 1 PDRG 0 Pin PDRG write Internal bus Executing bit manipulation instruction DDRG read DDRG DDRG write Stop mode, watch mode (SPL = 1) PULG read PULG PULG write DS702–00013–0v02-E 119 MB95850K/860K/870K Series (3) Port G registers • Port G register functions Register abbreviation PDRG DDRG PULG Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled • Correspondence between registers and pins for port G Correspondence between related register bits and pins Pin name - - - - - PG2 PG1 - - - - - - bit2 bit1 - PDRG DDRG PULG 120 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port G operations • Operation as an output port • A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRG register to external pins. • If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRG register returns the PDRG register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDRG register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDRG register. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register. DS702–00013–0v02-E 121 MB95850K/860K/870K Series ■ I/O PORTS (MB95870K SERIES) • List of port registers Register name Read/Write Initial value Port 0 data register PDR0 R, RM/W 0b00000000 Port 0 direction register DDR0 R/W 0b00000000 Port 1 data register PDR1 R, RM/W 0b00000000 Port 1 direction register DDR1 R/W 0b00000000 Port 4 data register PDR4 R, RM/W 0b00000000 Port 4 direction register DDR4 R/W 0b00000000 Port 6 data register PDR6 R, RM/W 0b00000000 Port 6 direction register DDR6 R/W 0b00000000 Port 7 data register PDR7 R, RM/W 0b00000000 Port 7 direction register DDR7 R/W 0b00000000 Port F data register PDRF R, RM/W 0b00000000 Port F direction register DDRF R/W 0b00000000 Port G data register PDRG R, RM/W 0b00000000 Port G direction register DDRG R/W 0b00000000 Port 0 pull-up register PUL0 R/W 0b00000000 Port 1 pull-up register PUL1 R/W 0b00000000 Port 4 pull-up register PUL4 R/W 0b00000000 Port 6 pull-up register PUL6 R/W 0b00000000 Port 7 pull-up register PUL7 R/W 0b00000000 Port G pull-up register PULG R/W 0b00000000 A/D input disable register (lower) AIDRL R/W 0b00000000 Touch input disable register 0 TIDR0 R/W 0b00000000 Touch input disable register 1 TIDR1 R/W 0b00000000 R/W : Readable/writable (The read value is the same as the write value.) R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write (RMW) type of instruction.) 122 DS702–00013–0v02-E MB95850K/860K/870K Series 1. Port 0 Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 0 configuration Port 0 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 0 data register (PDR0) • Port 0 direction register (DDR0) • Port 0 pull-up register (PUL0) • A/D input disable register (lower) (AIDRL) (2) Block diagrams of port 0 • P00/INT00 pin This pin has the following peripheral function: • External interrupt input pin (INT00) • P01/INT01 pin This pin has the following peripheral function: • External interrupt input pin (INT01) • P02/INT02 pin This pin has the following peripheral function: • External interrupt input pin (INT02) • P03/INT03 pin This pin has the following peripheral function: • External interrupt input pin (INT03) • Block diagram of P00/INT00, P01/INT01, P02/INT02 and P03/INT03 Peripheral function input Peripheral function input enable (INT00 to INT03) Hysteresis 0 Pull-up 1 PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write (Continued) DS702–00013–0v02-E 123 MB95850K/860K/870K Series • P04/INT04/AN00 pin This pin has the following peripheral functions: • External interrupt input pin (INT04) • 8/10-bit A/D converter analog input pin (AN00) • Block diagram of P04/INT04/AN00 Peripheral function input Peripheral function input enable (INT04) A/D analog input Hysteresis 0 Pull-up 1 PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write (Continued) 124 DS702–00013–0v02-E MB95850K/860K/870K Series • P05/INT05/AN01/CMP0_N pin This pin has the following peripheral functions: • External interrupt input pin (INT05) • 8/10-bit A/D converter analog input pin (AN01) • Comparator ch. 0 inverting analog input (negative input) pin (CMP0_N) • Block diagram of P05/INT05/AN01/CMP0_N Comparator analog input Comparator analog input disable Peripheral function input Peripheral function input enable (INT05) A/D analog input Hysteresis 0 Pull-up 1 PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write (Continued) DS702–00013–0v02-E 125 MB95850K/860K/870K Series • P06/AN02/CMP0_O pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN02) • Comparator ch. 0 digital output pin (CMP0_O) • Block diagram of P06/AN02/CMP0_O Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write (Continued) 126 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • P07/AN03/CMP0_P pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN03) • Comparator ch. 0 non-inverting analog input (positive input) pin (CMP0_P) • Block diagram of P07/AN03/CMP0_P Comparator analog input Comparator analog input disable A/D analog input Hysteresis 0 Pull-up 1 PDR0 read PDR0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) PUL0 read PUL0 PUL0 write AIDRL read AIDRL AIDRL write DS702–00013–0v02-E 127 MB95850K/860K/870K Series (3) Port 0 registers • Port 0 register functions Register abbreviation PDR0 DDR0 PUL0 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Analog input enabled 1 Port input enabled • Correspondence between registers and pins for port 0 Correspondence between related register bits and pins Pin name P07 P06 P05 P04 P03 P02 P01 P00 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit5 bit4 bit1 bit0 - - - - PDR0 DDR0 PUL0 AIDRL 128 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port 0 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR0 register to external pins. • If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR0 register returns the PDR0 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the analog input function as an input port, set the bit in the A/D input disable register (lower) (AIDRL) corresponding to that pin to “1”. • If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”. • When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”. • Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with the analog input function, its port input is disabled because the AIDRL register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT00 to INT05), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the corresponding bit in the PUL0 register to “0”. (Continued) DS702–00013–0v02-E 129 MB95850K/860K/870K Series (Continued) • Operation as an external interrupt input pin • Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register. • Operation as a comparator input pin • Set the bit in the AIDRL register corresponding to the comparator input pin to “0”. • Regardless of the value of the PDR0 register and that of the DDR0 register, if the comparator analog input enable bit in the comparator control register (CMR0:VCID) is set to “0”, the comparator input function is enabled. • To disable the comparator input function, set the VCID bit to “1”. • For details of the comparator, refer to “CHAPTER 25 COMPARATOR” in the hardware manual of the MB95850K/860K/870K Series. 130 DS702–00013–0v02-E MB95850K/860K/870K Series 2. Port 1 Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 1 configuration Port 1 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 1 data register (PDR1) • Port 1 direction register (DDR1) • Port 1 pull-up register (PUL1) (2) Block diagrams of port 1 • P10/DBG pin This pin has the following peripheral function: • DBG input pin (DBG) • Block diagram of P10/DBG ヒステリシス 0 1 PDR1リード PDR1 端子 内部バス OD PDR1ライト ビット操作命令実行時 DDR1リード DDR1 DDR1ライト ストップモード, 時計モード(SPL = 1) (Continued) DS702–00013–0v02-E 131 MB95850K/860K/870K Series • P11/EC0/DIO01 pin This pin has the following peripheral functions: • 8/16-bit composite timer ch. 0 clock input pin (EC0) • TS direct output ch. 1 pin (DIO01) • P15/UCK0 pin This pin has the following peripheral function: • UART/SIO ch. 0 clock I/O pin (UCK0) • P16/INT09/TO11 pin This pin has the following peripheral functions: • External interrupt input pin (INT09) • 8/16-bit composite timer ch. 1 output pin (TO11) • P17/INT08/TO10 pin This pin has the following peripheral functions: • External interrupt input pin (INT08) • 8/16-bit composite timer ch. 1 output pin (TO10) • Block diagram of P11/EC0/DIO01, P15/UCK0, P16/INT09/TO11 and P17/INT08/TO10 Peripheral function input Peripheral function input enable (INT08 and INT09) Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write (Continued) 132 DS702–00013–0v02-E MB95850K/860K/870K Series • P12/BEEP pin This pin has the following peripheral function: • Beep output pin (BEEP) • P14/UO0 pin This pin has the following peripheral function: • UART/SIO ch. 0 data output pin (UO0) • Block diagram of P12/BEEP and P14/UO0 Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write (Continued) DS702–00013–0v02-E 133 MB95850K/860K/870K Series (Continued) • P13/UI0/DIO02 pin This pin has the following peripheral functions: • UART/SIO ch. 0 data input pin (UI0) • TS direct output ch. 2 pin (DIO02) • Block diagram of P13/UI0/DIO02 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Pull-up 0 1 PDR1 read CMOS 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write 134 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 1 registers • Port 1 register functions Register abbreviation PDR1 DDR1 PUL1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 1 Correspondence between related register bits and pins Pin name P17 P16 P15 P14 P13 P12 P11 P10 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0* PDR1 DDR1 PUL1 *: Though P10 has no pull-up function, bit0 in the PUL1 register can still be accessed. The operation of P10 is not affected by the setting of bit0 in the PUL1 register. DS702–00013–0v02-E 135 MB95850K/860K/870K Series (4) Port 1 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR1 register to external pins. • If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR1 register returns the PDR1 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input from the external interrupt (INT08 and INT09) is enabled, or if the interrupt input of P11/EC0, P13/UI0 and P15/UCK0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an external interrupt input pin • Set the bit in the DDR1 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register. 136 DS702–00013–0v02-E MB95850K/860K/870K Series 3. Port 4 Port 4 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 4 configuration Port 4 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 4 data register (PDR4) • Port 4 direction register (DDR4) • Port 4 pull-up register (PUL4) • A/D input disable register (lower) (AIDRL) DS702–00013–0v02-E 137 MB95850K/860K/870K Series (2) Block diagrams of port 4 • P40/AN04/PPG00 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN04) • 8/16-bit PPG ch. 0 output pin (PPG00) • P41/AN05/PPG01 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN05) • 8/16-bit PPG ch. 0 output pin (PPG01) • P44/AN06/TO00/DIO03 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN06) • 8/16-bit composite timer ch. 0 output pin (TO00) • TS direct output ch. 3 pin (DIO03) • P45/AN07/TO01/DIO04 pin This pin has the following peripheral functions: • 8/10-bit A/D converter analog input pin (AN07) • 8/16-bit composite timer ch. 0 output pin (TO01) • TS direct output ch. 4 pin (DIO04) • Block diagram of P40/AN04/PPG00, P41/AN05/PPG01, P44/AN06/TO00/DIO03 and P45/AN07/TO01/DIO04 Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up 0 1 PDR4 read 1 PDR4 0 Pin PDR4 write Internal bus Executing bit manipulation instruction DDR4 read DDR4 DDR4 write Stop mode, watch mode (SPL = 1) PUL4 read PUL4 PUL4 write AIDRL read AIDRL AIDRL write (Continued) 138 DS702–00013–0v02-E MB95850K/860K/870K Series • P42/INT06/PPG10 pin This pin has the following peripheral functions: • External interrupt input pin (INT06) • 8/16-bit PPG ch. 1 output pin (PPG10) • P43/INT07/PPG11 pin This pin has the following peripheral functions: • External interrupt input pin (INT07) • 8/16-bit PPG ch. 1 output pin (PPG11) • Block diagram of P42/INT06/PPG10 and P43/INT07/PPG11 Peripheral function input Peripheral function input enable (INT06 and INT07) Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR4 read 1 PDR4 0 Pin PDR4 write Internal bus Executing bit manipulation instruction DDR4 read DDR4 DDR4 write Stop mode, watch mode (SPL = 1) PUL4 read PUL4 PUL4 write (Continued) DS702–00013–0v02-E 139 MB95850K/860K/870K Series (Continued) • P46/SDA pin This pin has the following peripheral function: • I2C bus interface ch. 0 data I/O pin (SDA) • P47/SCL pin This pin has the following peripheral function: • I2C bus interface ch. 0 clock I/O pin (SCL) • Block diagram of P46/SDA and P47/SCL Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output CMOS 0 1 PDR4 read Internal bus Pin 1 PDR4 0 OD PDR4 write Executing bit manipulation instruction DDR4 read DDR4 DDR4 write 140 Stop mode, watch mode (SPL = 1) DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 4 registers • Port 4 register functions Register abbreviation PDR4 DDR4 PUL4 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR4 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR4 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Analog input enabled 1 Port input enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 4 Correspondence between related register bits and pins Pin name PDR4 DDR4 PUL4 AIDRL P47 P46 bit7 bit6 - - DS702–00013–0v02-E P45 P44 P43 P42 P41 P40 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 - - bit3 bit2 141 MB95850K/860K/870K Series (4) Port 4 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR4 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR4 register to external pins. • If data is written to the PDR4 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR4 register returns the PDR4 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR4 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the analog input function as an input port, set the bit in the A/D input disable register (lower) (AIDRL) corresponding to that pin to “1”. • If data is written to the PDR4 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR4 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR4 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR4 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR4 register corresponding to the input pin of a peripheral function to “0”. • When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”. • Reading the PDR4 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR4 register are initialized to “0” and port input is enabled. As for a pin shared with the analog input function, its port input is disabled because the AIDRL register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR4 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT06 and INT07), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR4 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the corresponding bit in the PUL4 register to “0”. (Continued) 142 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • Operation as an external interrupt input pin • Set the bit in the DDR4 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. • Operation of the pull-up register Setting the bit in the PUL4 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL4 register. DS702–00013–0v02-E 143 MB95850K/860K/870K Series 4. Port 6 Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 6 configuration Port 6 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 6 data register (PDR6) • Port 6 direction register (DDR6) • Port 6 pull-up register (PUL6) • Touch input disable register 0 (TIDR0) (2) Block diagrams of port 6 • P60/EC1/DIO00 pin This pin has the following peripheral functions: • 8/16-bit composite timer ch. 1 clock input pin (EC1) • TS direct output ch. 0 pin (DIO00) • Block diagram of P60/EC1/DIO00 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR6 read 1 PDR6 0 Pin PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write (Continued) 144 DS702–00013–0v02-E MB95850K/860K/870K Series • P61/PPG20 pin This pin has the following peripheral function: • 8/16-bit PPG ch. 2 output pin (PPG20) • P62/PPG21 pin This pin has the following peripheral function: • 8/16-bit PPG ch. 2 output pin (PPG21) • Block diagram of P61/PPG20 and P62/PPG21 Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDR6 read 1 PDR6 0 Pin PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write (Continued) DS702–00013–0v02-E 145 MB95850K/860K/870K Series (Continued) • P63/AREF pin This pin has the following peripheral function: • TS reference input pin (AREF) • P64/S00 pin This pin has the following peripheral function: • TS touch ch. 0 input pin (S00) • P65/S01 pin This pin has the following peripheral function: • TS touch ch. 1 input pin (S01) • P66/S02 pin This pin has the following peripheral function: • TS touch ch. 2 input pin (S02) • P67/S03 pin This pin has the following peripheral function: • TS touch ch. 3 input pin (S03) • Block diagram of P63/AREF, P64/S00, P65/S01, P66/S02 and P67/S03 Touch input Hysteresis 0 Pull-up 1 PDR6 read PDR6 Pin PDR6 write Internal bus Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) PUL6 read PUL6 PUL6 write TIDR0 read TIDR0 TIDR0 write 146 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port 6 registers • Port 6 register functions Register abbreviation PDR6 DDR6 PUL6 TIDR0 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Touch input or reference input enabled 1 Port input enabled • Correspondence between registers and pins for port 6 Correspondence between related register bits and pins Pin name P67 P66 P65 P64 P63 P62 P61 P60 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 - - - PDR6 DDR6 PUL6 TIDR0 DS702–00013–0v02-E 147 MB95850K/860K/870K Series (4) Port 6 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR6 register to external pins. • If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR6 register returns the PDR6 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using a pin shared with the touch input function as an input port, set the bit in the touch input disable register 0 (TIDR0) corresponding to that pin to “1”. • If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR6 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR6 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. As for a pin shared with the touch input function, its port input is disabled because the TIDR0 register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P60/EC1/DIO00 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • When the stop enable bit in the TS prescaler control register (PSC:STPE) is set to “1”, the TS can operate in stop mode or watch mode, the touch input is enabled and is not blocked. The TS wakes up in stop mode or watch mode provided that the TINT (touch interrupt) and the GINT (general interrupt) are set to enable the TS to wake up in stop mode or watch mode. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as a touch input pin Set the bit in the DDR6 register corresponding to the touch input pin to “0”, the bit in the TIDR0 register corresponding to the same pin to “0”, and the bit in the PUL6 register corresponding to the same pin to “0”. (Continued) 148 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • Operation of the pull-up register Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register. DS702–00013–0v02-E 149 MB95850K/860K/870K Series 5. Port 7 Port 7 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port 7 configuration Port 7 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 7 data register (PDR7) • Port 7 direction register (DDR7) • Port 7 pull-up register (PUL7) • Touch input disable register 1 (TIDR1) (2) Block diagrams of port 7 • P70/S04 pin This pin has the following peripheral function: • TS touch ch. 4 input pin (S04) • P71/S05 pin This pin has the following peripheral function: • TS touch ch. 5 input pin (S05) • P72/S06 pin This pin has the following peripheral function: • TS touch ch. 6 input pin (S06) • P73/S07 pin This pin has the following peripheral function: • TS touch ch. 7 input pin (S07) • P74/S08 pin This pin has the following peripheral function: • TS touch ch. 8 input pin (S08) • P75/S09 pin This pin has the following peripheral function: • TS touch ch. 9 input pin (S09) • P76/S10 pin This pin has the following peripheral function: • TS touch ch. 10 input pin (S10) • P77/S11 pin This pin has the following peripheral function: • TS touch ch. 11 input pin (S11) (Continued) 150 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • Block diagram of P70/S04, P71/S05, P72/S06, P73/S07, P74/S08, P75/S09, P76/S10 and P77/S11 Touch input Hysteresis 0 Pull-up 1 PDR7 read PDR7 Pin PDR7 write Internal bus Executing bit manipulation instruction DDR7 read DDR7 DDR7 write Stop mode, watch mode (SPL = 1) PUL7 read PUL7 PUL7 write TIDR1 read TIDR1 TIDR1 write DS702–00013–0v02-E 151 MB95850K/860K/870K Series (3) Port 7 registers • Port 7 register functions Register abbreviation PDR7 DDR7 PUL7 TIDR1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR7 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR7 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled 0 Touch input enabled 1 Port input enabled • Correspondence between registers and pins for port 7 Correspondence between related register bits and pins Pin name P77 P76 P75 P74 P73 P72 P71 P70 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PDR7 DDR7 PUL7 TIDR1 152 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port 7 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR7 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR7 register to external pins. • If data is written to the PDR7 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR7 register returns the PDR7 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR7 register corresponding to that pin is set to “0”. • When using a pin shared with the touch input function as an input port, set the bit in the touch input disable register 1 (TIDR1) corresponding to that pin to “1”. • If data is written to the PDR7 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR7 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR7 register, the PDR7 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR7 register are initialized to “0” and port input is enabled. As for a pin shared with the touch input function, its port input is disabled because the TIDR1 register is initialized to “0”. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR7 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • When the stop enable bit in the TS prescaler control register (PSC:STPE) is set to “1”, the TS can operate in stop mode or watch mode, the touch input is enabled and is not blocked. The TS wakes up in stop mode or watch mode provided that the TINT (touch interrupt) and the GINT (general interrupt) are set to enable the TS to wake up in stop mode or watch mode. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as a touch input pin Set the bit in the DDR7 register corresponding to the touch input pin to “0”, the bit in the TIDR1 register corresponding to the same pin to “0”, and the bit in the PUL7 register corresponding to the same pin to “0”. • Operation of the pull-up register Setting the bit in the PUL7 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL7 register. DS702–00013–0v02-E 153 MB95850K/860K/870K Series 6. Port F Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port F configuration Port F is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port F data register (PDRF) • Port F direction register (DDRF) (2) Block diagrams of port F • PF0/X0 pin This pin has the following peripheral function: • Main clock input oscillation pin (X0) • PF1/X1 pin This pin has the following peripheral function: • Main clock I/O oscillation pin (X1) • Block diagram of PF0/X0 and PF1/X1 Hysteresis 0 1 PDRF read Internal bus PDRF Pin PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) (Continued) 154 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) • PF2/RST pin This pin has the following peripheral function: • Reset pin (RST) • Block diagram of PF2/RST Reset input Reset input enable Reset output enable Reset output Hysteresis 0 1 PDRF read Internal bus Pin 1 PDRF 0 OD PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) DS702–00013–0v02-E 155 MB95850K/860K/870K Series (3) Port F registers • Port F register functions Register abbreviation PDRF DDRF Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port F Correspondence between related register bits and pins Pin name PDRF DDRF 156 - - - - - PF2 PF1 PF0 - - - - - bit2 bit1 bit0 DS702–00013–0v02-E MB95850K/860K/870K Series (4) Port F operations • Operation as an output port • A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRF register to external pins. • If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRF register returns the PDRF register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”. • If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRF register, the PDRF register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00013–0v02-E 157 MB95850K/860K/870K Series 7. Port G Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in the hardware manual of the MB95850K/860K/870K Series. (1) Port G configuration Port G is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port G data register (PDRG) • Port G direction register (DDRG) • Port G pull-up register (PULG) (2) Block diagram of port G • PG1/X0A/DIO04 pin This pin has the following peripheral functions: • Subclock input oscillation pin (X0A) • TS direct output ch. 4 pin (DIO04) • PG2/X1A/DIO03 pin This pin has the following peripheral functions: • Subclock I/O oscillation pin (X1A) • TS direct output ch. 3 pin (DIO03) • Block diagram of PG1/X0A/DIO04 and PG2/X1A/DIO03 Peripheral function output enable Peripheral function output Hysteresis Pull-up 0 1 PDRG read 1 PDRG 0 Pin PDRG write Internal bus Executing bit manipulation instruction DDRG read DDRG DDRG write Stop mode, watch mode (SPL = 1) PULG read PULG PULG write 158 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Port G registers • Port G register functions Register abbreviation PDRG DDRG PULG Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled • Correspondence between registers and pins for port G Correspondence between related register bits and pins Pin name - - - - - PG2 PG1 - - - - - - bit2 bit1 - PDRG DDRG PULG DS702–00013–0v02-E 159 MB95850K/860K/870K Series (4) Port G operations • Operation as an output port • A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRG register to external pins. • If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRG register returns the PDRG register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDRG register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDRG register. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register. 160 DS702–00013–0v02-E MB95850K/860K/870K Series ■ INTERRUPT SOURCE TABLE (MB95850K SERIES) Interrupt source External interrupt ch. 0 Interrupt request number Vector table address Upper Lower Interrupt level setting register Register Bit IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0] External interrupt ch. 6 IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0] External interrupt ch. 7 IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0] UART/SIO ch. 0 IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 0xFFF0 0xFFF1 ILR1 L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 0xFFEE 0xFFEF ILR1 L06 [1:0] Touch interrupt (TINT) IRQ07 0xFFEC 0xFFED ILR1 L07 [1:0] General interrupt (GINT) IRQ08 0xFFEA 0xFFEB ILR2 L08 [1:0] — IRQ09 0xFFE8 0xFFE9 ILR2 L09 [1:0] — IRQ10 0xFFE6 0xFFE7 ILR2 L10 [1:0] — IRQ11 0xFFE4 0xFFE5 ILR2 L11 [1:0] 8/16-bit PPG ch. 0 (upper) IRQ12 0xFFE2 0xFFE3 ILR3 L12 [1:0] 8/16-bit PPG ch. 0 (lower) IRQ13 0xFFE0 0xFFE1 ILR3 L13 [1:0] — IRQ14 0xFFDE 0xFFDF ILR3 L14 [1:0] — IRQ15 0xFFDC 0xFFDD ILR3 L15 [1:0] IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0] IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0] 8/10-bit A/D converter IRQ18 0xFFD6 0xFFD7 ILR4 L18 [1:0] Time-base timer IRQ19 0xFFD4 0xFFD5 ILR4 L19 [1:0] IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0] IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0] IRQ22 0xFFCE 0xFFCF ILR5 L22 [1:0] IRQ23 0xFFCC 0xFFCD ILR5 L23 [1:0] External interrupt ch. 4 External interrupt ch. 1 External interrupt ch. 5 2 I C bus interface ch. 0 — Watch prescaler Watch counter Comparator ch. 0 — Flash memory DS702–00013–0v02-E Priority order of interrupt sources of the same level (occurring simultaneously) High Low 161 MB95850K/860K/870K Series ■ INTERRUPT SOURCE TABLE (MB95860K SERIES) Interrupt source External interrupt ch. 0 Interrupt request number Vector table address Upper Lower Interrupt level setting register Register Bit Priority order of interrupt sources of the same level (occurring simultaneously) IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0] IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0] IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0] UART/SIO ch. 0 IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 0xFFF0 0xFFF1 ILR1 L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 0xFFEE 0xFFEF ILR1 L06 [1:0] Touch interrupt (TINT) IRQ07 0xFFEC 0xFFED ILR1 L07 [1:0] General interrupt (GINT) IRQ08 0xFFEA 0xFFEB ILR2 L08 [1:0] 8/16-bit PPG ch. 1 (lower) IRQ09 0xFFE8 0xFFE9 ILR2 L09 [1:0] 8/16-bit PPG ch. 1 (upper) IRQ10 0xFFE6 0xFFE7 ILR2 L10 [1:0] IRQ11 0xFFE4 0xFFE5 ILR2 L11 [1:0] 8/16-bit PPG ch. 0 (upper) IRQ12 0xFFE2 0xFFE3 ILR3 L12 [1:0] 8/16-bit PPG ch. 0 (lower) IRQ13 0xFFE0 0xFFE1 ILR3 L13 [1:0] 8/16-bit composite timer ch. 1 (upper) IRQ14 0xFFDE 0xFFDF ILR3 L14 [1:0] IRQ15 0xFFDC 0xFFDD ILR3 L15 [1:0] IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0] IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0] 8/10-bit A/D converter IRQ18 0xFFD6 0xFFD7 ILR4 L18 [1:0] Time-base timer IRQ19 0xFFD4 0xFFD5 ILR4 L19 [1:0] IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0] Comparator ch. 0 IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0] 8/16-bit composite timer ch. 1 (lower) IRQ22 0xFFCE 0xFFCF ILR5 L22 [1:0] Flash memory IRQ23 0xFFCC 0xFFCD ILR5 L23 [1:0] External interrupt ch. 4 External interrupt ch. 1 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 — — 2 I C bus interface ch. 0 — Watch prescaler Watch counter 162 High Low DS702–00013–0v02-E MB95850K/860K/870K Series ■ INTERRUPT SOURCE TABLE (MB95870K SERIES) Interrupt source External interrupt ch. 0 Interrupt request number Vector table address Upper Lower Interrupt level setting register Register Bit IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0] IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0] IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0] UART/SIO ch. 0 IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 0xFFF0 0xFFF1 ILR1 L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 0xFFEE 0xFFEF ILR1 L06 [1:0] Touch interrupt (TINT) IRQ07 0xFFEC 0xFFED ILR1 L07 [1:0] General interrupt (GINT) IRQ08 0xFFEA 0xFFEB ILR2 L08 [1:0] 8/16-bit PPG ch. 1 (lower) IRQ09 0xFFE8 0xFFE9 ILR2 L09 [1:0] 8/16-bit PPG ch. 1 (upper) IRQ10 0xFFE6 0xFFE7 ILR2 L10 [1:0] 8/16-bit PPG ch. 2 (upper) IRQ11 0xFFE4 0xFFE5 ILR2 L11 [1:0] 8/16-bit PPG ch. 0 (upper) IRQ12 0xFFE2 0xFFE3 ILR3 L12 [1:0] 8/16-bit PPG ch. 0 (lower) IRQ13 0xFFE0 0xFFE1 ILR3 L13 [1:0] 8/16-bit composite timer ch. 1 (upper) IRQ14 0xFFDE 0xFFDF ILR3 L14 [1:0] 8/16-bit PPG ch. 2 (lower) IRQ15 0xFFDC 0xFFDD ILR3 L15 [1:0] IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0] IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0] 8/10-bit A/D converter IRQ18 0xFFD6 0xFFD7 ILR4 L18 [1:0] Time-base timer IRQ19 0xFFD4 0xFFD5 ILR4 L19 [1:0] IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0] Comparator ch. 0 IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0] 8/16-bit composite timer ch. 1 (lower) IRQ22 0xFFCE 0xFFCF ILR5 L22 [1:0] Flash memory IRQ23 0xFFCC 0xFFCD ILR5 L23 [1:0] External interrupt ch. 4 External interrupt ch. 1 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 2 I C bus interface ch. 0 External interrupt ch. 8 External interrupt ch. 9 Watch prescaler Watch counter DS702–00013–0v02-E Priority order of interrupt sources of the same level (occurring simultaneously) High Low 163 MB95850K/860K/870K Series ■ PIN STATES IN EACH MODE (MB95850K SERIES) Pin name Normal operation Sleep mode Oscillation input Oscillation input PF0/X0 I/O port*1 I/O port*1 Oscillation input Oscillation input PF1/X1 PF2/RST I/O port*1 I/O port*1 Reset input*4 Reset input*4 I/O port I/O port Oscillation input Oscillation input PG1/X0A/ DIO04 I/O port*1/ peripheral function I/O I/O port*1/ peripheral function I/O Oscillation input Oscillation input Stop mode Watch mode SPL=0 SPL=1 SPL=0 SPL=1 Hi-Z Hi-Z Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 1, *2 blocked* Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 1, 2 blocked* * Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 1, *2 blocked* Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 1, 2 blocked* * Hi-Z Hi-Z - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 blocked*1, *2 On reset — - Hi-Z - Input enabled*3 (However, it does not function.) — - Hi-Z - Input enabled*3 (However, it does not function.) Reset input*4 - Hi-Z - Input enabled*3 (However, it does not function.) — - Hi-Z - Input enabled*3 (However, it does not function.) — - Hi-Z - Input enabled*3 (However, it does not function.) I/O port*1/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 blocked*1, *2 I/O port/ P04/AN00/ peripheral BEEP/ function I/O/ DIO01/TO01 analog input I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z - Previous state - Hi-Z*6 - Hi-Z*6 kept*5, *10 - Input kept*5, *10 2 2 Input blocked* Input blocked* - Input blocked*2 - Input blocked*2 blocked*2 P05/INT05/ AN01/ CMP0_N/ TO00 I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Previous state - Hi-Z*6 - Hi-Z*6 - Hi-Z kept kept - Input - Input - Input - Input - Input blocked*2, *7, *8 blocked*2, *7, *8 blocked*2 2, 7, 8 2, 7, 8 blocked* * * blocked* * * P06/AN02/ CMP0_O/ PPG00 I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Previous state - Hi-Z - Hi-Z*6 - Hi-Z*6 kept*9 kept*9 - Input 2 2 - Input blocked* - Input blocked* - Input blocked*2 - Input blocked*2 blocked*2 P07/AN03/ CMP0_P/ PPG01 I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *8 2, 8 blocked* * - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *8 2, 8 blocked* * - Hi-Z - Input blocked*2 I/O port/ peripheral function I/O - Previous state - Hi-Z kept - Input - Input blocked*2, *7 blocked*2, *7 - Previous state - Hi-Z kept - Input - Input blocked*2, *7 blocked*2, *7 - Hi-Z - Input enabled*3 (However, it does not function.) PG2/X1A/ DIO03 P10/DBG/ EC0 I/O port*1/ peripheral function I/O I/O port/ peripheral function I/O (Continued) 164 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) Pin name Normal operation I/O port/ P13/INT04/ peripheral UI0/DIO02 function I/O I/O port/ P14/INT01/ peripheral UO0/DIO00 function I/O I/O port/ P15/INT00/ peripheral UCK0 function I/O P46/INT06/ SDA I/O port/ peripheral P47/INT07/ function I/O SCL Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, 7 blocked* * - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, *7 blocked* - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, *7 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Hi-Z - Previous state - Input - Previous state - Hi-Z - Hi-Z kept enabled*3 kept - Input - Input (However, it Input - Input blocked*2, *7, *11 blocked*2, *7, *11 does not blocked*2, *7, *11 blocked*2, *7, *11 function.) I/O port/ touch input - Previous state - Hi-Z*12 kept*12 - Input - Input blocked*2, *13 blocked*2, *13 P63/AREF P65/S01 P66/S02 P67/S03 I/O port/ touch input P70/S04 - Previous state - Hi-Z*12 kept*12 - Input - Input blocked*2, *13 blocked*2, *13 - Hi-Z - Input blocked*2 P71/S05 SPL: Pin state setting bit in the standby control register (STBC:SPL) Hi-Z: High impedance *1: The pin stays at the state shown when configured as a general-purpose I/O port. *2: “Input blocked” means direct input gate operation from the pin is disabled. *3: “Input enabled” means that the input function is enabled. While the input function is enabled, a pull-up or pull-down operation has to be performed in order to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other ports. *4: The PF2/RST pin stays at the state shown when configured as a reset pin. *5: In stop mode and watch mode, the pin functions as a TS direct output pin only when the SPL bit is set to “0” and the TS direct output function is enabled. *6: The pull-up control setting is still effective. *7: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *8: Though input is blocked, an analog signal can be input to generate a comparator interrupt when the comparator interrupt is enabled. *9: In stop mode and watch mode, comparator input varies according to the register settings of the comparator, and the pin functions as a comparator output pin only when the SPL bit is set to “0” and the comparator output function is enabled. *10: In stop mode and watch mode, the pin functions as a beep output pin only when the SPL bit is set to “0” and the beep output function is enabled. *11: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled. For details of the MCU standby mode wakeup function, refer to “CHAPTER 21 I2C BUS INTERFACE” in the hardware manual of the MB95850K/860K/870K Series. *12: In stop mode and watch mode, the pin outputs SNCLK only when it is used as a TS touch input pin and the TS is in operation. *13: Though input is blocked, a touch signal can be input to generate a touch interrupt (TINT) when the TINT is enabled. DS702–00013–0v02-E 165 MB95850K/860K/870K Series ■ PIN STATES IN EACH MODE (MB95860K SERIES) Pin name Normal operation Sleep mode Oscillation input Oscillation input PF0/X0 I/O port*1 I/O port*1 Oscillation input Oscillation input PF1/X1 PF2/RST I/O port*1 I/O port*1 Reset input*4 Reset input*4 I/O port I/O port Oscillation input Oscillation input PG1/X0A/ DIO04 I/O port*1/ peripheral function I/O I/O port*1/ peripheral function I/O Oscillation input Oscillation input Stop mode Watch mode SPL=0 SPL=1 SPL=0 SPL=1 Hi-Z Hi-Z Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 1, *2 blocked* Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 1, 2 blocked* * Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 1, *2 blocked* Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 1, 2 blocked* * Hi-Z Hi-Z On reset — - Hi-Z - Input enabled*3 (However, it does not function.) — - Hi-Z - Input enabled*3 (However, it does not function.) Reset input*4 - Hi-Z - Input enabled*3 (However, it does not function.) — - Hi-Z - Input enabled*3 (However, it does not function.) — I/O port*1/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 blocked*1, *2 - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 blocked*1, *2 - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 blocked*2, *7 - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 blocked*2, *7 - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z - Previous state - Hi-Z*6 - Hi-Z*6 kept*5, *10 - Input kept*5, *10 2 2 Input blocked* Input blocked* - Input blocked*2 - Input blocked*2 blocked*2 I/O port/ P05/INT05/ peripheral AN01/ function I/O/ CMP0_N analog input I/O port/ peripheral function I/O/ analog input - Previous state - Previous state - Hi-Z*6 - Hi-Z*6 - Hi-Z kept kept - Input - Input - Input - Input - Input blocked*2 blocked*2, *7, *8 blocked*2, *7, *8 2, *7, *8 2, *7, *8 blocked* blocked* P06/AN02/ CMP0_O/ PPG00 I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Previous state - Hi-Z - Hi-Z*6 - Hi-Z*6 kept*9 kept*9 - Input 2 2 - Input blocked* - Input blocked* - Input blocked*2 - Input blocked*2 blocked*2 P07/AN03/ CMP0_P/ PPG01 I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *8 2, *8 blocked* PG2/X1A/ DIO03 I/O port*1/ peripheral function I/O P02/INT02/ TO10 I/O port/ peripheral P03/INT03/ function I/O TO11 P04/AN00/ BEEP/ DIO01 - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *8 2, *8 blocked* - Hi-Z - Input blocked*2 (Continued) 166 DS702–00013–0v02-E MB95850K/860K/870K Series Pin name P10/DBG/ EC0 Normal operation I/O port/ peripheral function I/O I/O port/ P13/INT04/ peripheral UI0/DIO02 function I/O I/O port/ P14/INT01/ peripheral UO0 function I/O I/O port/ P15/INT00/ peripheral UCK0 function I/O P44/AN06/ TO00/ DIO03/ PPG10 P45/AN07/ TO01/ DIO04/ PPG11 I/O port/ peripheral function I/O/ analog input P46/INT06/ SDA I/O port/ peripheral P47/INT07/ function I/O SCL P60/EC1/ DIO00 I/O port/ peripheral function I/O Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset I/O port/ peripheral function I/O - Previous state - Hi-Z kept - Input - Input blocked*2, *7 2, *7 blocked* - Previous state - Hi-Z kept - Input - Input blocked*2, *7 2, *7 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, *7 blocked* - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, *7 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z - Previous state - Hi-Z*6 - Hi-Z*6 kept*5 - Input kept*5 2 2 Input blocked* Input blocked* - Input blocked*2 - Input blocked*2 blocked*2 I/O port/ peripheral function I/O - Hi-Z - Previous state - Input - Previous state - Hi-Z - Hi-Z kept enabled*3 kept - Input - Input (However, it Input - Input blocked*2, *7, *11 blocked*2, *7, *11 does not blocked*2, *7, *11 blocked*2, *7, *11 function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, 7 blocked* * - Hi-Z - Input enabled*3 (However, it does not function.) (Continued) DS702–00013–0v02-E 167 MB95850K/860K/870K Series (Continued) Pin name Normal operation Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset P63/AREF P64/S00 P65/S01 P66/S02 P67/S03 P70/S04 I/O port/ touch input I/O port/ touch input - Previous state - Hi-Z*12 kept*12 - Input - Input blocked*2, *13 2, 13 blocked* * - Previous state - Hi-Z*12 kept*12 - Input - Input blocked*2, *13 2, 13 blocked* * - Hi-Z - Input blocked*2 P71/S05 P72/S06 P73/S07 SPL: Pin state setting bit in the standby control register (STBC:SPL) Hi-Z: High impedance *1: The pin stays at the state shown when configured as a general-purpose I/O port. *2: “Input blocked” means direct input gate operation from the pin is disabled. *3: “Input enabled” means that the input function is enabled. While the input function is enabled, a pull-up or pull-down operation has to be performed in order to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other ports. *4: The PF2/RST pin stays at the state shown when configured as a reset pin. *5: In stop mode and watch mode, the pin functions as a TS direct output pin only when the SPL bit is set to “0” and the TS direct output function is enabled. *6: The pull-up control setting is still effective. *7: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *8: Though input is blocked, an analog signal can be input to generate a comparator interrupt when the comparator interrupt is enabled. *9: In stop mode and watch mode, comparator input varies according to the register settings of the comparator, and the pin functions as a comparator output pin only when the SPL bit is set to “0” and the comparator output function is enabled. *10: In stop mode and watch mode, the pin functions as a beep output pin only when the SPL bit is set to “0” and the beep output function is enabled. *11: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled. For details of the MCU standby mode wakeup function, refer to “CHAPTER 21 I2C BUS INTERFACE” in the hardware manual of the MB95850K/860K/870K Series. *12: In stop mode and watch mode, the pin outputs SNCLK only when it is used as a TS touch input pin and the TS is in operation. *13: Though input is blocked, a touch signal can be input to generate a touch interrupt (TINT) when the TINT is enabled. 168 DS702–00013–0v02-E MB95850K/860K/870K Series ■ PIN STATES IN EACH MODE (MB95870K SERIES) Pin name Normal operation Sleep mode Oscillation input Oscillation input PF0/X0 I/O port*1 I/O port*1 Oscillation input Oscillation input PF1/X1 PF2/RST I/O port*1 I/O port*1 Reset input*4 Reset input*4 I/O port I/O port Oscillation input Oscillation input PG1/X0A/ DIO04 I/O port*1/ peripheral function I/O I/O port*1/ peripheral function I/O Oscillation input Oscillation input Stop mode Watch mode SPL=0 SPL=1 SPL=0 SPL=1 Hi-Z Hi-Z Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 1, *2 blocked* Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 1, 2 blocked* * Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*1, *2 1, *2 blocked* Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*1, *2 blocked*1, *2 Hi-Z Hi-Z - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 1, 2 blocked* * Hi-Z Hi-Z On reset — - Hi-Z - Input enabled*3 (However, it does not function.) — - Hi-Z - Input enabled*3 (However, it does not function.) Reset input*4 - Hi-Z - Input enabled*3 (However, it does not function.) — - Hi-Z - Input enabled*3 (However, it does not function.) — I/O port*1/ peripheral function I/O I/O port*1/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 blocked*1, *2 - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*1, *2 blocked*1, *2 - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ P04/INT04/ peripheral AN00 function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Hi-Z - Input blocked*2 I/O port/ P05/INT05/ peripheral AN01/ function I/O/ CMP0_N analog input I/O port/ peripheral function I/O/ analog input - Previous state - Previous state - Hi-Z*6 - Hi-Z*6 - Hi-Z kept kept - Input - Input - Input - Input - Input blocked*2, *7, *8 blocked*2, *7, *8 blocked*2 2, 7, 8 2, 7, 8 blocked* * * blocked* * * P06/AN02/ CMP0_O I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z - Previous state - Hi-Z*6 - Hi-Z*6 kept*9 - Input kept*9 2 2 Input blocked* Input blocked* - Input blocked*2 - Input blocked*2 blocked*2 P07/AN03/ CMP0_P I/O port/ analog input I/O port/ analog input - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *8 2, 8 blocked* * PG2/X1A/ DIO03 P00/INT00 P01/INT01 P02/INT02 P03/INT03 - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *8 2, *8 blocked* - Hi-Z - Input blocked*2 (Continued) DS702–00013–0v02-E 169 MB95850K/860K/870K Series Pin name Normal operation Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset I/O port/ peripheral function I/O - Hi-Z - Input - Previous state - Previous state - Hi-Z - Hi-Z enabled*3 kept kept 2 2 (However, it Input blocked* Input blocked* - Input blocked*2 - Input blocked*2 does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* I/O port/ peripheral function I/O - Hi-Z - Input - Previous state - Previous state 6 6 Hi-Z* Hi-Z* enabled*3 kept*10 kept*10 2 2 Input blocked* Input blocked* (However, it - Input blocked*2 - Input blocked*2 does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, 7 blocked* * I/O port/ peripheral function I/O - Hi-Z - Input - Previous state - Previous state - Hi-Z*6 - Hi-Z*6 enabled*3 kept kept 2 2 Input blocked* Input blocked* (However, it - Input blocked*2 - Input blocked*2 does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, 7 blocked* * - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z - Previous state - Hi-Z*6 - Hi-Z*6 kept - Input kept 2 2 Input blocked* Input blocked* - Input blocked*2 blocked*2 - Input blocked*2 P42/INT06/ PPG10 I/O port/ peripheral P43/INT07/ function I/O PPG11 I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, *7 blocked* P44/AN06/ I/O port/ TO00/DIO03 peripheral P45/AN07/ function I/O/ TO01/DIO04 analog input I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z - Previous state - Hi-Z*6 - Hi-Z*6 kept*5 - Input kept*5 2 2 Input blocked* Input blocked* - Input blocked*2 - Input blocked*2 blocked*2 P10/DBG P11/EC0/ DIO01 P12/BEEP P13/UI0/ DIO02 P14/UO0 P15/UCK0 I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ peripheral function I/O I/O port/ peripheral function I/O P16/INT09/ TO11 I/O port/ peripheral P17/INT08/ function I/O TO10 P40/AN04/ PPG00 P41/AN05/ PPG01 I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, 7 blocked* * - Previous state - Hi-Z*6 kept - Input - Input blocked*2, *7 2, *7 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) - Hi-Z - Input enabled*3 (However, it does not function.) - Hi-Z - Input enabled*3 (However, it does not function.) (Continued) 170 DS702–00013–0v02-E MB95850K/860K/870K Series Pin name P46/SDA P47/SCL P60/EC1/ DIO00 P61/PPG20 P62/PPG21 Normal operation Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset I/O port/ peripheral function I/O - Previous state - Hi-Z kept - Input - Input blocked*2, *11 2, *11 blocked* - Previous state - Hi-Z kept - Input - Input blocked*2, *11 2, *11 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* - Previous state - Hi-Z*6 kept*5 - Input - Input blocked*2, *7 2, *7 blocked* - Hi-Z - Input enabled*3 (However, it does not function.) I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Hi-Z - Input - Previous state - Previous state - Hi-Z*6 - Hi-Z*6 enabled*3 kept kept 2 2 Input blocked* Input blocked* (However, it - Input blocked*2 - Input blocked*2 does not function.) I/O port/ touch input I/O port/ touch input - Previous state - Hi-Z*12 kept*12 - Input - Input blocked*2, *13 2, 13 blocked* * I/O port/ peripheral function I/O I/O port/ peripheral function I/O P63/AREF P64/S00 P65/S01 P66/S02 P67/S03 P70/S04 P71/S05 P72/S06 - Previous state - Hi-Z*12 kept*12 - Input - Input blocked*2, *13 2, 13 blocked* * - Hi-Z - Input blocked*2 P73/S07 P74/S08 P75/S09 P76/S10 P77/S11 SPL: Pin state setting bit in the standby control register (STBC:SPL) Hi-Z: High impedance *1: The pin stays at the state shown when configured as a general-purpose I/O port. *2: “Input blocked” means direct input gate operation from the pin is disabled. *3: “Input enabled” means that the input function is enabled. While the input function is enabled, a pull-up or pull-down operation has to be performed in order to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other ports. *4: The PF2/RST pin stays at the state shown when configured as a reset pin. *5: In stop mode and watch mode, the pin functions as a TS direct output pin only when the SPL bit is set to “0” and the TS direct output function is enabled. *6: The pull-up control setting is still effective. *7: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *8: Though input is blocked, an analog signal can be input to generate a comparator interrupt when the comparator interrupt is enabled. *9: In stop mode and watch mode, comparator input varies according to the register settings of the comparator, and the pin functions as a comparator output pin only when the SPL bit is set to “0” and the comparator output function is enabled. *10: In stop mode and watch mode, the pin functions as a beep output pin only when the SPL bit is set to “0” and the beep output function is enabled. *11: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled. For details of the MCU standby mode wakeup function, refer to “CHAPTER 21 I2C BUS INTERFACE” in the hardware manual of the MB95850K/860K/870K Series. (Continued) DS702–00013–0v02-E 171 MB95850K/860K/870K Series (Continued) *12: In stop mode and watch mode, the pin outputs SNCLK only when it is used as a TS touch input pin and the TS is in operation. *13: Though input is blocked, a touch signal can be input to generate a touch interrupt (TINT) when the TINT is enabled. 172 DS702–00013–0v02-E MB95850K/860K/870K Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage* 1 Output voltage* 1 Maximum clamp current Total maximum clamp current “L” level maximum output current Symbol Rating Min V VI VSS − 0.3 VSS + 6 V *2 VO VSS − 0.3 VSS + 6 V *2 ICLAMP −2 +2 mA Applicable to specific pins*3 Σ|ICLAMP| — 20 mA Applicable to specific pins*3 IOL — 15 mA 4 — IOLAV2 “H” level maximum output current mA 12 For pins other than P06, P07, P40 to P45 Average output current = operating current × operating ratio (1 pin) For P06, P07, P40 to P45 Average output current = operating current × operating ratio (1 pin) ΣIOL — 100 mA ΣIOLAV — 37 Total average output current = mA operating current × operating ratio (Total number of pins) IOH — −15 mA −4 IOHAV1 — “H” level average current mA −8 IOHAV2 “H” level total maximum output current Remarks VSS − 0.3 VSS + 6 “L” level average current “L” level total average output current Unit VCC IOLAV1 “L” level total maximum output current Max For pins other than P06, P07, P40 to P45 Average output current = operating current × operating ratio (1 pin) For P06, P07, P40 to P45 Average output current = operating current × operating ratio (1 pin) ΣIOH — −100 mA ΣIOHAV — −47 Total average output current = mA operating current × operating ratio (Total number of pins) Power consumption Pd — 320 mW Operating temperature TA −40 +85 °C Storage temperature Tstg −55 +150 °C Operating humidity Hopr 5 95 % Electrostatic discharge (human-body model) HBM — 8000 V “H” level total average output current For the TS touch input pins: S00 to S11 (Continued) DS702–00013–0v02-E 173 MB95850K/860K/870K Series (Continued) *1: These parameters are based on the condition that VSS is 0.0 V. *2: V1 and V0 must not exceed VCC + 0.3 V. V1 must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Specific pins: P00 to P07, P11 to P17, P40 to P45, P60 to P67, P70 to P77, PF0, PF1, PG1, PG2 • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit: • Input/Output equivalent circuit Protective diode VCC P-ch Limiting resistor HV(High Voltage) input (0 V to 16 V) N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 174 DS702–00013–0v02-E MB95850K/860K/870K Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Power supply voltage Value CS Operating temperature TA Remarks V When the device is powered on or in on-chip debug mode, or when the LVD reset circuit is enabled Max 2.88 5.5 2.4 5.5 When the LVD reset circuit is disabled 2.3 5.5 Hold condition in stop mode 0.022 1 −40 +85 +5 +35 VCC Decoupling capacitor Unit Min µF °C * Other than on-chip debug mode On-chip debug mode *: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG / RST / C pins connection diagram * DBG C RST Cs *: Connect the DBG pin to an external pull-up resistor of 2 kΩ or above.After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS702–00013–0v02-E 175 MB95850K/860K/870K Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol “H” level input voltage “L” level input voltage Open-drain output application voltage “H” level output voltage “L” level output voltage Input leak current (Hi-Z output leak current) Internal pull-up resistor Input capacitance Pin name Condition VIHI P13, P46, P47 VIHS Value Unit Remarks VCC + 0.3 V CMOS input level — VCC + 0.3 V Hysteresis input 0.8 VCC — VCC + 0.3 V Hysteresis input — VSS − 0.3 — 0.3 VCC V CMOS input level Other than P13, P46, P47, PF2 — VSS − 0.3 — 0.2 VCC V Hysteresis input PF2 — VSS − 0.3 — 0.2 VCC V Hysteresis input P10, P46, P47, PF2 — VSS − 0.3 — Vss + 5.5 V VOH1 Output pins other than P06, P07, P10, IOH = −4 mA P40 to P45, PF2 VCC − 0.5 — — V VOH2 P06, P07, P40 to P45 IOH = −8 mA VCC − 0.5 — — V VOL1 Output pins other than P06, P07, P40 to P45 IOL = 4 mA — — 0.4 V VOL2 P06, P07, P40 to P45 IOL = 12 mA — — 0.4 V All input pins 0.0 V < VI < VCC −5 — +5 When the internal µA pull-up resistor is disabled Other than P10, P46, P47, PF0, VI = 0 V PF1, PF2 25 50 100 When the internal kΩ pull-up resistor is enabled Other than VCC f = 1 MHz and VSS — 5 15 pF Min Typ Max — 0.7 VCC — Other than P13, P46, P47, PF2 — 0.8 VCC VIHM PF2 — VILI P13, P46, P47 VILS VILM VD ILI RPULL CIN (Continued) 176 DS702–00013–0v02-E MB95850K/860K/870K Series (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition Value Min — FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) ICC Typ*1 Max*2 4.7 Unit Remarks 5.8 Except during Flash memory mA programming and erasing — 8.6 13.8 During Flash memory mA programming and erasing — 6.1 9.1 mA At A/D conversion — 2.2 3 mA — 63 145 µA ICCLS FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = +25 °C — 11 16 µA In deep standby mode ICCT FCL = 32 kHz Watch mode Main stop mode TA = +25 °C — 8 13 µA In deep standby mode FMCRPLL = 16 MHz FMP = 16 MHz Main CR PLL clock mode (multiplied by 4) TA = +25 °C — 5.1 6.8 mA ICCMCR FCRH = 4 MHz FMP = 4 MHz Main CR clock mode — 1.4 4.6 mA ICCSCR Sub-CR clock mode (divided by 2) TA = +25 °C — 58.1 230 µA — 590 660 µA In deep standby mode — 8 13 µA In deep standby mode FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) ICCS ICCL VCC (External clock FCL = 32 kHz operation) FMPL = 16 kHz Subclock mode (divided by 2) TA = +25 °C Power supply current*3 ICCMPLL VCC ICCTS ICCH FCH = 32 MHz Time-base timer VCC mode (External clock TA = +25 °C operation) Substop mode TA = +25 °C (Continued) DS702–00013–0v02-E 177 MB95850K/860K/870K Series (Continued) Parameter (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition Value Min Typ*1 Max*2 Unit IV Current consumption of the comparator — 60 160 µA ILVD Current consumption of the low-voltage detection reset circuit — 4 7 µA ICRH Current consumption of the main CR oscillator — 240 320 µA ICRL Current consumption of the sub-CR oscillator oscillating at 100 kHz — 7 20 µA INSTBY Current consumption difference between normal standby mode and deep standby mode TA = +25 °C — 20 30 µA ITSC Current consumption difference between standby mode with the TS in operation and standby mode with the TS not in operation — 37 60 µA Power supply current*3 VCC Remarks *1: VCC = 5.0 V, TA = +25 °C *2: VCC = 5.5 V, TA = +85 °C (unless otherwise specified) *3: • The power supply current is determined by the external clock. When the low-voltage detection reset circuit is selected, the power supply current is the sum of adding the current consumption of the low-voltage detection reset circuit (ILVD) to one of the values from ICC to ICCH. In addition, when both the low-voltage detection reset circuit and a CR oscillator are selected, the power supply current is the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH or ICRL) and one of the values from ICC to ICCH. In on-chip debug mode, the main CR oscillator (ICRH) and the low-voltage detection reset circuit are always in operation, and current consumption therefore increases accordingly. • See “4. AC Characteristics (1) Clock Timing” for FCH, FCL, FCRH and FMCRPLL. • See “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL. • The power supply current value in standby mode is measured in deep standby mode. The current consumption in normal standby is higher than that in deep standby mode. The power supply current value in normal standby can be found by adding the current consumption difference between normal standby mode and deep standby mode (INSTBY) to the power supply current value in deep standby mode. For details of normal standby and deep standby mode, refer to “CHAPTER 3 CLOCK CONTROLLER” in the hardware manual of the MB95850K/860K/870K Series. 178 DS702–00013–0v02-E MB95850K/860K/870K Series 4. AC Characteristics (1) Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition X0, X1 FCH X0 X1: open X0, X1 FCRH — — * FCL FCRL — X0A, X1A — Max Unit Typ 1 — 1 — 12 1 — 32.5 3.92 4 4.08 Operating conditions MHz • The main CR clock is used. • 0 °C ≤ TA ≤ +70 °C 16.25 MHz When the main oscillation circuit is used MHz When the main external clock MHz is used 3.8 4 4.2 Operating conditions • The main CR clock is used. MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 7.84 8 8.16 Operating conditions MHz • PLL multiplier: 2 • 0 °C ≤ TA ≤ +70 °C 7.6 8 8.4 Operating conditions • PLL multiplier: 2 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 9.8 10 10.2 Operating conditions MHz • PLL multiplier: 2.5 • 0 °C ≤ TA ≤ +70 °C Operating conditions • PLL multiplier: 2.5 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 9.5 10 10.5 11.76 12 Operating conditions 12.24 MHz • PLL multiplier: 3 • 0 °C ≤ TA ≤ +70 °C — Operating conditions • PLL multiplier: 3 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 11.4 12 12.6 15.68 16 Operating conditions 16.32 MHz • PLL multiplier: 4 • 0 °C ≤ TA ≤ +70 °C Operating conditions • PLL multiplier: 4 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 15.2 16 16.8 — 32.768 — kHz When the sub-oscillation circuit is used — 32.768 — kHz When the sub-external clock is used 50 100 150 kHz When the sub-CR clock is used — — Remarks Min — Clock frequency FMCRPLL Value (Continued) DS702–00013–0v02-E 179 MB95850K/860K/870K Series (Continued) Parameter (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition X0, X1 Clock cycle time Input clock pulse width Input clock rise time and fall time CR oscillation start time tHCYL X0 tLCYL X0A, X1A tWH1 tWL1 X0 tWH2 tWL2 tCR tCF X0A X0 Max 61.5 — 1000 ns 83.4 — 1000 * 30.8 — 1000 ns When an external clock is ns used — — 30.5 — µs 33.4 — — ns * 12.4 — — ns — — 15.2 — µs — — 5 ns * — — 5 ns — X1: open X0, X1 Remarks Typ X1: open X0, X1 Unit Min X1: open X0, X1 Value When the main oscillation circuit is used When the subclock is used When an external clock is used, the duty ratio should range between 40% and 60%. When an external clock is used tCRHWK — — — — 50 µs When the main CR clock is used tCRLWK — — — — 30 µs When the sub-CR clock is used — — — — 100 µs When the main CR PLL clock is used PLL oscillation tMCRPLLWK start time *: The external clock signal is input to X0 and the inverted external clock signal to X1. 180 DS702–00013–0v02-E MB95850K/860K/870K Series • Input waveform generated when an external clock (main clock) is used tHCYL tWH1 tWL1 tCR tCF 0.8 VCC 0.8 VCC X0, X1 0.2 VCC 0.2 VCC 0.2 VCC • Figure of main clock input port external connection When a crystal oscillator or a ceramic oscillator is used X0 When an external clock is used When an external clock (X1 is open) is used X0 X1 X1 X0 X1 Open FCH FCH FCH • Input waveform generated when an external clock (subclock) is used tLCYL tWH2 tCR tWL2 tCF 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC • Figure of subclock input port external connection When a crystal oscillator or a ceramic oscillator is used X0A X1A When an external clock is used X0A X1A Open FCL FCL • Input waveform generated when an internal clock (main CR clock) is used tCRHWK 1/FCRH Main CR clock Oscillation starts DS702–00013–0v02-E Oscillation stabilizes 181 MB95850K/860K/870K Series • Input waveform generated when an internal clock (sub-CR clock) is used tCRLWK 1/FCRL Sub-CR clock Oscillation starts Oscillation stabilizes • Input waveform generated when an internal clock (main CR PLL clock) is used 1/FMCRPLL tMCRPLLWK Main CR PLL clock Oscillation starts 182 Oscillation stabilizes DS702–00013–0v02-E MB95850K/860K/870K Series (2) Source Clock/Machine Clock (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Source clock cycle time*1 Symbol tSCLK Pin name — FSP Source clock frequency — FSPL Machine clock cycle time*2 (minimum instruction execution time) tMCLK — FMPL Unit Remarks Min Typ Max 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 62.5 — 1000 ns When the main CR clock is used Min: FCRH = 4 MHz, multiplied by 4 Max: FCRH = 4 MHz, divided by 4 — 61 — µs When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 — 20 — µs When the sub-CR clock is used FCRL = 100 kHz, divided by 2 0.5 — 16.25 — 4 — MHz When the main CR clock is used — 16.384 — kHz When the sub-oscillation clock is used — 50 — kHz 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 250 — 4000 ns When the main CR clock is used Min: FSP = 4 MHz, no division Max: FSP = 4 MHz, divided by 16 61 — 976.5 µs When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 0.031 — 16.25 0.25 — 16 1.024 — 16.384 3.125 — 50 MHz When the main oscillation clock is used — FMP Machine clock frequency Value When the sub-CR clock is used FCRL = 100 kHz, divided by 2 MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz *1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following. • Main clock divided by 2 • PLL multiplication of main CR clock (Select a multiplier from 2, 2.5, 3 and 4.) • Main CR clock • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 DS702–00013–0v02-E 183 MB95850K/860K/870K Series • Schematic diagram of the clock generation block FCH (Main oscillation clock) Divided by 2 FMCRPLL (Main CR PLL clock) SCLK (Source clock) FCRH (Main CR clock) FCL (Suboscillation clock) Division circuit × 1 × 1/4 × 1/8 × 1/16 MCLK (Machine clock) Divided by 2 Machine clock divide ratio select bits (SYCC:DIV[1:0]) FCRL (Sub-CR clock) Divided by 2 Clock mode select bits (SYCC:SCS[2:0]) • Operating voltage - Operating frequency (TA = −40°C to +85°C) 5.5 Operating voltage (V) 5.0 A/D converter operation range 4.0 3.5 3.0 2.7 2.4 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) 184 DS702–00013–0v02-E MB95850K/860K/870K Series (3) External Reset (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter RST “L” level pulse width Symbol tRSTL Value Min Max 2 tMCLK* — Unit Remarks ns *: See “(2) Source Clock/Machine Clock” for tMCLK. tRSTL RST 0.2 VCC DS702–00013–0v02-E 0.2 VCC 185 MB95850K/860K/870K Series (4) Power-on reset (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Condition Power supply rising time tR Power supply cutoff time tOFF tR Value Unit Min Max — — 50 ms — 1 — ms Remarks Wait time until power-on tOFF 2.5 V VCC 0.2 V 0.2 V 0.2 V Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below. VCC 2.3 V Set the slope of rising to a value below 30 mV/ms. Hold condition in stop mode VSS 186 DS702–00013–0v02-E MB95850K/860K/870K Series (5) Peripheral Input Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL INT00 to INT09*1, EC0, EC1 tILIH INT00 to INT09*1, EC0, EC1 Value Pin name 0.8 VCC Unit Min Max 2 tMCLK*2 — ns MCLK 2 — ns 2t * tIHIL 0.8 VCC 0.2 VCC 0.2 VCC *1: On the MB95850K Series, only INT00, INT01, INT04, INT05, INT06 and INT07 are available. On the MB95860K Series, only INT00 to INT07 are available. On the MB95870K Series, INT00 to INT09 are available. *2: See “(2) Source Clock/Machine Clock” for tMCLK. DS702–00013–0v02-E 187 MB95850K/860K/870K Series (6) Low-voltage Detection (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Unit Remarks Min Typ Max 2.52 2.7 2.88 V 2.61 2.8 2.99 V 2.89 3.1 3.31 V 3.08 3.3 3.52 V 2.43 2.6 2.77 V 2.52 2.7 2.88 V 2.80 3 3.20 V 2.99 3.2 3.41 V VHYS — — 100 mV Power supply start voltage Voff — — 2.3 V Power supply end voltage Von 4.9 — — V Power supply voltage change time (at power supply rise) tr 650 — — µs Slope of power supply that the reset release signal generates within the rating (VDL+) Power supply voltage change time (at power supply fall) tf 650 — — µs Slope of power supply that the reset release signal generates within the rating (VDL-) Reset release delay time td1 — — 30 µs Reset detection delay time td2 — — 30 µs LVD reset threshold voltage transition stabilization time tstb 10 — — µs Release voltage* Detection voltage* Hysteresis width VDL+ VDL− At power supply rise At power supply fall *: After the LVD reset is enabled by the LVD reset circuit control register (LVDCC), the release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID register (LVDR) in the lowvoltage detection reset circuit. For details of the LVDCC register and the LVDR register, refer to “CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT” in the hardware manual of the MB95850K/860K/870K Series. (Continued) 188 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) VCC Von Voff time tf tr VDL+ VHYS VDL- Internal reset signal time td2 DS702–00013–0v02-E td1 189 MB95850K/860K/870K Series (7) I2C Bus Interface Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Value Parameter Standardmode Fast-mode Min Max Min Max 0 100 0 400 kHz SCL, SDA 4.0 — 0.6 — µs Symbol Pin name Condition SCL clock frequency fSCL (Repeated) START condition hold time SDA ↓ → SCL ↓ tHD;STA SCL Unit SCL clock “L” width tLOW SCL 4.7 — 1.3 — µs SCL clock “H” width tHIGH SCL 4.0 — 0.6 — µs 4.7 — 0.6 — µs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSU;STA SCL, SDA Data hold time SCL ↓ → SDA ↓↑ tHD;DAT SCL, SDA 0 3.45*2 0 0.9*3 µs Data setup time SDA ↓↑ → SCL ↑ tSU;DAT SCL, SDA 0.25 — 0.1 — µs STOP condition setup time SCL ↑ → SDA ↑ tSU;STO SCL, SDA 4 — 0.6 — µs tBUF SCL, SDA 4.7 — 1.3 — µs Bus free time between STOP condition and START condition R = 1.7 kΩ, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at “L” (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT ≥ 250 ns is fulfilled. tWAKEUP SDA tLOW tHD;DAT tHIGH tHD;STA tBUF SCL tHD;STA tSU;DAT fSCL tSU;STA tSU;STO (Continued) 190 DS702–00013–0v02-E MB95850K/860K/870K Series (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Pin Condition name Parameter Symbol Value*2 Min Max Unit Remarks SCL clock “L” width tLOW SCL (2 + nm/2)tMCLK − 20 — ns Master mode SCL clock “H” width tHIGH SCL (nm/2)tMCLK − 20 (nm/2)tMCLK + 20 ns Master mode Master mode Maximum value is applied when ns m, n = 1, 8. Otherwise, the minimum value is applied. START condition hold time tHD;STA SCL, SDA (-1 + nm/2)tMCLK − 20 (-1 + nm)tMCLK + 20 STOP condition setup time tSU;STO SCL, SDA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode START condition setup time tSU;STA SCL, SDA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode tBUF SCL, SDA (2 nm + 4) tMCLK − 20 — ns tHD;DAT SCL, SDA 3 tMCLK − 20 — ns Master mode Bus free time between STOP condition and START condition Data hold time Data setup time Setup time between clearing interrupt and SCL rising R = 1.7 kΩ, C = 50 pF*1 SCL, SDA Master mode It is assumed that “L” of SCL is not extended. The minimum value is (-2 + nm/2) tMCLK − 20 (-1 + nm/2) tMCLK + 20 ns applied to the first bit of continuous data. Otherwise, the maximum value is applied. tSU;INT SCL The minimum value is applied to the interrupt at the ninth SCL↓. (1 + nm/2) tMCLK + 20 ns The maximum value is applied to the interrupt at the eighth SCL↓. tSU;DAT (nm/2) tMCLK − 20 SCL clock “L” width tLOW SCL 4 tMCLK − 20 — ns At reception SCL clock “H” width tHIGH SCL 4 tMCLK − 20 — ns At reception (Continued) DS702–00013–0v02-E 191 MB95850K/860K/870K Series (Continued) Parameter START condition detection STOP condition detection RESTART condition detection condition (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin Condition name tHD;STA SCL, SDA tSU;STO SCL, SDA Value*2 Min Max Unit Remarks — No START condition is detected when 1 ns tMCLK is used at reception. — No STOP condition is detected when 1 ns tMCLK is used at reception. 2 tMCLK − 20 — No RESTART condition is ns detected when 1 tMCLK is used at reception. 2 tMCLK − 20 — ns At reception 2 tMCLK − 20 2 tMCLK − 20 tSU;STA SCL, SDA Bus free time tBUF SCL, SDA Data hold time tHD;DAT SCL, SDA 2 tMCLK − 20 — ns At slave transmission mode Data setup time tSU;DAT SCL, SDA tLOW − 3 tMCLK − 20 — ns At slave transmission mode Data hold time tHD;DAT SCL, SDA 0 — ns At reception Data setup time tSU;DAT SCL, SDA tMCLK − 20 — ns At reception SDA↓ → SCL↑ (with wakeup function in use) tWAKEUP SCL, SDA Oscillation stabilization wait time +2 tMCLK − 20 — ns R = 1.7 kΩ, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: • See “(2) Source Clock/Machine Clock” for tMCLK. • m represents the CS[4:3] bits in the I2C clock control register (ICCR0). • n represents the CS[2:0] bits in the I2C clock control register (ICCR0). • The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK) and the CS[4:0] bits in the ICCR0 register. • Standard-mode: m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 MHz < tMCLK ≤ 10 MHz (m, n) = (8, 22) : 0.9 MHz < tMCLK ≤ 16.25 MHz • Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 MHz < tMCLK ≤ 10 MHz (m, n) = (5, 8) : 3.3 MHz < tMCLK ≤ 16.25 MHz 192 DS702–00013–0v02-E MB95850K/860K/870K Series (8) UART/SIO, Serial I/O Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Value Condition Unit Min Max 4 tMCLK* — ns −190 +190 ns 2 tMCLK* — ns Serial clock cycle time tSCYC UCK0 UCK ↓ → UO time tSLOV UCK0, UO0 Valid UI → UCK ↑ tIVSH UCK0, UI0 UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 tMCLK* — ns Serial clock “H” pulse width tSHSL UCK0 4 tMCLK* — ns Serial clock “L” pulse width tSLSH UCK0 4 tMCLK* — ns UCK ↓ → UO time tSLOV UCK0, UO0 — 190 ns Valid UI → UCK ↑ tIVSH UCK0, UI0 2 tMCLK* — ns UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 tMCLK* — ns Internal clock operation External clock operation *: See “(2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC 0.8 VCC UCK0 0.2 VCC 0.2 VCC tSLOV 0.8 VCC UO0 0.2 VCC tIVSH tSHIX 0.7 VCC 0.7 VCC UI0 0.3 VCC 0.3 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC UCK0 0.2 VCC 0.2 VCC tSLOV 0.8 VCC UO0 0.2 VCC tIVSH tSHIX 0.7 VCC 0.7 VCC UI0 0.3 VCC 0.3 VCC DS702–00013–0v02-E 193 MB95850K/860K/870K Series (9) Comparator Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Pin name Value Min Typ Max Unit Remarks Voltage range CMP0_P, CMP0_N 0 — VCC − 1.3 V Offset voltage CMP0_P, CMP0_N −15 — +15 mV Delay time CMP0_O — 650 1200 ns Overdrive 5 mV — 140 420 ns Overdrive 50 mV Power down delay CMP0_O — — 1200 ns Power down recovery PD: 1 → 0 Power up CMP0_O stabilization wait time — — 1200 ns Output stabilization time at power up 194 DS702–00013–0v02-E MB95850K/860K/870K Series (10) BGR for Comparator (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Power up stabilization wait time Output voltage DS702–00013–0v02-E Value Unit Min Typ Max — — — 150 µs VBGR 1.1495 1.21 1.2705 V Remarks Load: 10 pF 195 MB95850K/860K/870K Series (11) TS (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Min — — — — Touch sensitivity — — Sensor clock 0.149 0.086 0.063 0.047 Max — — — — Unit Remarks pF The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b000”. pF The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b001”. pF The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b010”. pF The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b011”. pF The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b100”. pF The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b101”. pF The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b110”. The sensitivity of touch ch. n bits in a TS sensitivity select register x (RSELx:SnB[2:0])* have been set to “0b111”. Stch — Tuning capacitor in AREF and sensor pad Typ 0.040 0.033 0.030 — — — — 0.027 — pF Csi 0 — 15 pF FSNCLK 5 — 20 kHz Frequency of the sensor clock *: “n” represents the touch channel number and “x” a number from one to six. For details of the RSELx register, refer to “CHAPTER 26 TOUCH SENSOR” in the hardware manual of the MB95850K/860K/870K Series 196 DS702–00013–0v02-E MB95850K/860K/870K Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Unit Min Typ Max Resolution — — 10 bit Total error −3 — +3 LSB −2.5 — +2.5 LSB −1.9 — +1.9 LSB Linearity error — Differential linearity error Zero transition voltage V0T VSS − 7.2 LSB VSS + 0.5 LSB VSS + 8.2 LSB V Full-scale transition voltage VFST VCC − 6.2 LSB VCC − 1.5 LSB VCC + 9.2 LSB V Compare time — 3 — 10 µs 2.7 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC ≤ 5.5 V, with external impedance < 3.3 kΩ and external capacitance = 10 pF Sampling time — 0.941 — ∞ µs Analog input current IAIN −0.3 — +0.3 µA Analog input voltage VAIN VSS — VCC V DS702–00013–0v02-E Remarks 197 MB95850K/860K/870K Series (2) Notes on Using A/D Converter • External impedance of analog input and its sampling time The A/D converter of has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit Analog input Comparator R C During sampling: ON VCC R C 4.5 V ≤ VCC ≤ 5.5 V 1.45 kΩ (Max) 14.89 pF (Max) 2.7 V ≤ VCC < 4.5 V 2.7 kΩ (Max) 14.89 pF (Max) Note: The values are reference values. • Relationship between external impedance and minimum sampling time [External impedance = 0 kΩ to 100 kΩ] 100 External impedance [kΩ] 80 60 40 20 0 0 2 4 6 8 10 12 14 16 18 20 Minimum sampling time [μs] [External impedance = 0 kΩ to 20 kΩ] External impedance [kΩ] 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Minimum sampling time [μs] Note: External capacitance = 10 pF • A/D conversion error As |VCC − VSS| decreases, the A/D conversion error increases proportionately. 198 DS702–00013–0v02-E MB95850K/860K/870K Series (3) Definitions of A/D Converter Terms • Resolution It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“0000000000” ← → “0000000001”) of a device to the full-scale transition point (“1111111111” ← → “1111111110”) of the same device. • Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. • Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. Ideal I/O characteristics Total error VFST 0x3FF 0x3FF 2 LSB 0x3FD Digital output Digital output 0x004 0x003 Actual conversion characteristic 0x3FE 0x3FE 0x3FD V0T {1 LSB × (N − 1) + 0.5 LSB} 0x004 VNT 0x003 1 LSB 0x002 0x002 0x001 Actual conversion characteristic Ideal characteristic 0x001 0.5 LSB VSS Analog input 1 LSB = VCC VCC − VSS V 1024 N VSS Analog input Total error of digital output N = VCC VNT − {1 LSB × (N − 1) + 0.5 LSB} LSB 1 LSB : A/D converter digital output value VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN (Continued) DS702–00013–0v02-E 199 MB95850K/860K/870K Series (Continued) Zero transition error Full-scale transition error 0x004 Ideal characteristic Actual conversion characteristic 0x3FF Actual conversion characteristic 0x002 Ideal characteristic Digital output Digital output 0x003 Actual conversion characteristic 0x3FE VFST (measurement value) 0x3FD Actual conversion characteristic 0x001 0x3FC V0T (measurement value) VSS Analog input VCC VSS 0x3FE Ideal characteristic Actual conversion characteristic 0x(N+1) Actual conversion characteristic {1 LSB × N + V0T} VFST Digital output Digital output 0x3FD (measurement value) VNT 0x004 0x002 V(N+1)T 0xN VNT 0x(N−1) Actual conversion characteristic 0x003 VCC Differential linearity error Linearity error 0x3FF Analog input Ideal characteristic Actual conversion characteristic 0x(N−2) 0x001 V0T (measurement value) VSS Analog input VCC Linearity error of digital output N = VSS VCC VNT − {1 LSB × N + V0T} 1 LSB Differential linearity error of digital output N = N Analog input V(N+1)T − VNT − 1 1 LSB : A/D converter digital output value VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN V0T (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC − 2 LSB [V] 200 DS702–00013–0v02-E MB95850K/860K/870K Series 6. Flash Memory Program/Erase Characteristics Parameter Value Unit Remarks 1.6*2 s The time of writing “0x00” prior to erasure is excluded. 0.6*1 3.1*2 s The time of writing “0x00” prior to erasure is excluded. 17 272 µs System-level overhead is excluded. Program/erase cycle 100000 — — cycle Power supply voltage at program/erase 2.4 — 5.5 V 20*3 — — Average TA = +85 °C Number of program/erase cycles: 1000 or below 10*3 — — Average TA = +85 °C year Number of program/erase cycles: 1001 to 10000 inclusive 5*3 — — Min Typ Max Sector erase time (2 Kbyte sector) — 0.3*1 Sector erase time (32 Kbyte sector) — Byte writing time — Flash memory data retention time Average TA = +85 °C Number of program/erase cycles: 10001 or above *1: VCC = 5.5 V, TA = +25 °C, 0 cycle *2: VCC = 2.4 V, TA = +85 °C, 100000 cycles *3: These values were converted from the result of a technology reliability assessment. (These values were converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being +85 °C.) DS702–00013–0v02-E 201 MB95850K/860K/870K Series ■ ORDERING INFORMATION Part number Package MB95F856KPFT-G-SNE2 24-pin plastic TSSOP (FPT-24P-M10) MB95F856KPF-G-SNE2 24-pin plastic SOP (FPT-24P-M34) MB95F866KPMC-G-SNE2 32-pin plastic LQFP (FPT-32P-M30) MB95F876KPMC-G-SNE2 48-pin plastic LQFP (FPT-48P-M49) MB95F876KPMC1-G-SNE2 52-pin plastic LQFP (FPT-52P-M02) 202 DS702–00013–0v02-E MB95850K/860K/870K Series ■ PACKAGE DIMENSION 24-pin plastic TSSOP Lead pitch 0.65 mm Package width × package length 4.40 mm × 7.80 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm MAX Weight 0.10 g (FPT-24P-M10) 24-pin plastic TSSOP (FPT-24P-M10) Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) #: These dimensions do not include resin protrusion. # 7.80±0.10(.307±.004) +0.06 24 0.13 –0.03 +.002 .005 –.001 13 BTM E-MARK # 4.40±0.10 (.173±.004) INDEX Details of "A" part 6.40±0.20 (.252±.008) 1 12 0.65(.026) +0.07 0.22 –0.02 +.003 .008 –.001 1.20(.047) (Mounting height) MAX 0~8° "A" 0.10(.004) 0.60±0.15 (.024±.006) 0.10±0.05 (Stand off) (.004±.002) 0.10(.004) C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED F24033S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS702–00013–0v02-E 203 MB95850K/860K/870K Series 24-pin plastic SOP Lead pitch 1.27 mm Package width × package length 7.50 mm × 15.34 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 2.80 mm MAX Weight 0.44 g (FPT-24P-M34) 24-pin plastic SOP (FPT-24P-M34) Note 1) * : These dimensions do not include resin protrusion. *15.34±0.10(.604±.004) 24 0.27±0.07 (.011±.003) 13 10.20±0.40 (.402±.016) INDEX ø1.20±0.1 DEP0.20 ø.047±.004 DEP.008 +0.10 –0.05 +.004 –.002 7.50±0.10 (.295±.004) Details of "A" part 2.60 .102 +0.20 –0.25 +.008 –.010 0.25(.010) 1 1.27(.050) 12 0.42±0.07 (.017±.003) "A" 0~8° 0.25(.010) M 0.60±0.20 (.024±.008) +0.15 0.15 –0.10 .006 +.006 –.004 0.10(.004) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F24034S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 204 DS702–00013–0v02-E MB95850K/860K/870K Series 32-pin plastic LQFP Lead pitch 0.80 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.60 mm MAX (FPT-32P-M30) 32-pin plastic LQFP (FPT-32P-M30) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ +0.05 * 7.00±0.10(.276±.004)SQ 0.13 –0.00 +.002 24 .005 –.000 17 16 25 0.10(.004) Details of "A" part 1.60 MAX (Mounting height) (.063) MAX INDEX 0.25(.010) 9 32 0~7° 1 0.80(.031) 0.35 .014 C "A" 8 +0.08 –0.03 +.003 –.001 0.20(.008) 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) M 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS702–00013–0v02-E 205 MB95850K/860K/870K Series 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.17 g (FPT-48P-M49) 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ *7.00±0.10(.276±.004)SQ 36 0.145±0.055 (.006±.002) 25 24 37 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 13 48 "A" 0°~8° 1 0.50(.020) (Mounting height) .059 –.004 INDEX 0.10±0.10 (.004±.004) (Stand off) 12 0.22±0.05 (.008±.002) 0.08(.003) 0.25(.010) M 0.60±0.15 (.024±.006) C 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 206 DS702–00013–0v02-E MB95850K/860K/870K Series (Continued) 52-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 10.00 × 10.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g Code (Reference) P-LFQFP52-10× 10-0.65 (FPT-52P-M02) 52-pin plastic LQFP (FPT-52P-M02) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 39 0.145±0.055 (.006±.002) 27 Details of "A" part 40 26 +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 0.25(.010) INDEX 0.10(.004) 52 0~8˚ 14 "A" 0.50±0.20 (.020±.008) 1 13 0.65(.026) +0.065 0.30 –0.035 +.0026 0.13(.005) M 0.10±0.10 (.004±.004) (Stand off) 0.60±0.15 (.024±.006) .012 –.0014 C 2010 FUJITSU SEMICONDUCTOR LIMITED F52002Sc-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS702–00013–0v02-E 207 MB95850K/860K/870K Series ■ MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Details 11 ■ PIN FUNCTIONS (MB95850K SERIES) Revised the function of the AREF pin. TS reference input pin → TS reference impedance input pin 13 ■ PIN FUNCTIONS (MB95860K SERIES) Revised the function of the AREF pin. TS reference input pin → TS reference impedance input pin 17 ■ PIN FUNCTIONS (MB95870K SERIES) Revised the function of the AREF pin. TS reference input pin → TS reference impedance input pin 29 ■ PIN CONNECTION • DBG pin Revised details of “• DBG pin”. • RST pin Revised details of “• RST pin”. ■ I/O MAP (MB95850K SERIES) Revised the register name of the RSEL0 register. TS resistance select register 0 → TS sensitivity select register 0 40 Revised the register name of the RSEL1 register. TS resistance select register 1 → TS sensitivity select register 1 Revised the register name of the RSEL2 register. TS resistance select register 2 → TS sensitivity select register 2 Revised the register name of the RSEL3 register. TS resistance select register 3 → TS sensitivity select register 3 42 Corrected the initial value of the TOUCHH register. 0b00000XXX → 0b0000XXXX (Continued) 208 DS702–00013–0v02-E MB95850K/860K/870K Series Page 47 Section ■ I/O MAP (MB95860K SERIES) Details Revised the register name of the RSEL0 register. TS resistance select register 0 → TS sensitivity select register 0 Revised the register name of the RSEL1 register. TS resistance select register 1 → TS sensitivity select register 1 Revised the register name of the RSEL2 register. TS resistance select register 2 → TS sensitivity select register 2 Revised the register name of the RSEL3 register. TS resistance select register 3 → TS sensitivity select register 3 Revised the register name of the RSEL4 register. TS resistance select register 4 → TS sensitivity select register 4 49 54 Corrected the initial value of the TOUCHH register. 0b00000XXX → 0b0000XXXX ■ I/O MAP (MB95870K SERIES) Revised the register name of the RSEL0 register. TS resistance select register 0 → TS sensitivity select register 0 Revised the register name of the RSEL1 register. TS resistance select register 1 → TS sensitivity select register 1 Revised the register name of the RSEL2 register. TS resistance select register 2 → TS sensitivity select register 2 Revised the register name of the RSEL3 register. TS resistance select register 3 → TS sensitivity select register 3 Revised the register name of the RSEL4 register. TS resistance select register 4 → TS sensitivity select register 4 Revised the register name of the RSEL5 register. TS resistance select register 5 → TS sensitivity select register 5 Revised the register name of the RSEL6 register. TS resistance select register 6 → TS sensitivity select register 6 (Continued) DS702–00013–0v02-E 209 MB95850K/860K/870K Series (Continued) Page Section Details 57 ■ I/O MAP (MB95870K SERIES) 175 ■ ELECTRICAL CHARACTERISTICS Revised the remark in “• DBG/RST/C pins connection 2. Recommended Operating Conditions diagram”. 176 3. DC Characteristics Corrected the initial value of the TOUCHH register. 0b00000XXX → 0b0000XXXX Revised the remark of the parameter “Input leak current (Hi-Z output leak current)”. When pull-up resistance is disabled → When the internal pull-up resistor is disabled Rename the parameter “Pull-up resistance” to “Internal pull-up resistor”. Revised the remark of the parameter “Internal pull-up resistor”. When pull-up resistance is enabled → When the internal pull-up resistor is enabled 196 4. AC Characteristics (11)TS Revised all typical values of the parameter “Touch sensitivity”. 0.14 → 0.149 0.09 → 0.086 0.06 → 0.063 0.05 → 0.047 0.04 → 0.040 0.04 → 0.033 0.03 → 0.030 0.03 → 0.027 197 5. A/D Converter (1) A/D Converter Electrical Characteristics Corrected the symbol of the parameter “Zero transition voltage”. VOT → V0T 5. A/D Converter (3) Definitions of A/D Converter Terms Corrected the symbol of the zero transition voltage. VOT → V0T 199, 200 210 DS702–00013–0v02-E MB95850K/860K/870K Series MEMO DS702–00013–0v02-E 211 MB95850K/860K/870K Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 2/F, Green 18 Building, Hong Kong Science Park, Shatin, N.T., Hong Kong Tel : +852-2736-3232 Fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department