The following document contains information on Cypress products. CM26-10127-1ET1 Errata This errata sheet is for MB95350L Series Hardware Manual Rev. 1 (CM26-10127-1E). F2MC-8FX 8-BIT MICROCONTROLLER MB95350L Series HARDWARE MANUAL Date 2012/ 05/11 Page 80 2012.05.11 Section Description 6.12 “Table 6.12-1 Count Clock Sources Generated by Prescaler” should be corrected as indicated by the shading below. (Error) Table 6.12-1 Count Clock Sources Generated by Prescaler Count clock source frequency MCLK/2 MCLK/4 MCLK/8 MCLK/16 MCLK/32 7 FCH/2 8 FCH/2 Frequency (FCH = 10 MHz, MCLK = 10 MHz) MCLK/2 (5 MHz) MCLK/4 (2.5 MHz) MCLK/8 (1.25 MHz) MCLK/16 (0.625 MHz) MCLK/32 (0.3125 MHz) 7 FCH/2 (78 kHz) 8 FCH/2 (39 kHz) Frequency (FCH = 16 MHz, MCLK = 16 MHz) MCLK/2 (8 MHz) MCLK/4 (4 MHz) MCLK/8 (2 MHz) MCLK/16 (1 MHz) MCLK/32 (0.5 MHz) 7 FCH/2 (125 kHz) 8 FCH/2 (62.5 kHz) Frequency (FCH = 16.25 MHz, MCLK = 16.25 MHz) MCLK/2 (8.125 MHz) MCLK/4 (4.0625 MHz) MCLK/8 (2.0313 MHz) MCLK/16 (1.0156 MHz) MCLK/32 (0.5078 MHz) 7 FCH/2 (127 kHz) 8 FCH/2 (63.5 kHz) (Correct) Table 6.12-1 Count Clock Sources Generated by Prescaler (FCH) Count clock source frequency MCLK/2 MCLK/4 MCLK/8 MCLK/16 MCLK/32 7 FCH/2 8 FCH/2 2012/ 05/11 80 6.12 MCLK/2 MCLK/4 MCLK/8 MCLK/16 MCLK/32 6 FCRH/2 7 FCRH/2 203 14.5.1 Frequency (FCH = 32 MHz, MCLK = 16 MHz) 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 250 kHz 125 kHz Frequency (FCH = 32.5 MHz, MCLK = 16.25 MHz) 8.125 MHz 4.0625 MHz 2.0313 MHz 1.0156 MHz 0.5078 MHz 253.9 kHz 126.95 kHz “Table 6.12-2 Count Clock Sources Generated by Prescaler (FCRH)” should be added after “Table 6.12-1 Count Clock Sources Generated by Prescaler (FCH)”. Count clock source frequency 2012/ 05/11 Frequency (FCH = 20 MHz, MCLK = 10 MHz) 5 MHz 2.5 MHz 1.25 MHz 0.625 MHz 0.3125 MHz 156.25 kHz 78.125 kHz Frequency (FCRH = 1 MHz, MCLK = 1 MHz) 500 kHz 250 kHz 1.25 kHz 62.5 kHz 31.25 kHz 15.625 kHz 7.8125 kHz Frequency (FCRH = 8 MHz, MCLK = 8 MHz) 4 MHz 2 MHz 1 MHz 0.5 MHz 0.25 MHz 125 kHz 62.5 kHz Frequency (FCRH = 10 MHz, MCLK = 10 MHz) 5 MHz 2.5 MHz 1.25 MHz 0.625 MHz 0.3125 MHz 156.25 kHz 78.125 kHz Frequency (FCRH = 12.5 MHz, MCLK = 12.5 MHz) 6.25 MHz 3.125 MHz 1.5625 MHz 0.78125 MHz 0.390625 MHz 195.3125 kHz 97.65625 kHz The following statement should be added to details of the function of the IFE bit in “Table 14.5-1 Functions of Bits in 8/16-bit Composite Timer 00/01 Status Control Register 0 (T00CR0/T01CR0)”. During timer operation (T00CR1/T01CR1:STA = 1), the write access to this bit has no effect on operation. Ensure that the timer has stopped before modifying this bit. 1/3 Date 2012/ 05/11 2012/ 05/11 2012/ 05/11 Page 206 297 339 Section Description 14.5.2 The following statement should be added to details of the function of the IFE bit in “Table 14.5-2 Functions of Bits in 8/16-bit Composite Timer 10/11 Status Control Register 0 (T10CR0/T11CR0)”. 16.4.5 16.8 During timer operation (T10CR1/T11CR1:STA = 1), the write access to this bit has no effect on operation. Ensure that the timer has stopped before modifying this bit. The following statements should be added to details of the function of the SCES bit in “Table 16.4-4 Functions of Bits in LIN-UART Extended Status Control Register (ESCR)”. With this bit set to "1", executing a software reset is prohibited. Disable reception and transmission before modifying this bit. In “ Notes on Using LIN-UART”, the following content in “ Modifying operation settings” should be corrected as indicated by the shading below. (Error) After modifying operation settings such as the addition of start/stop and changing the data format, reset the LIN-UART. Even though the setting of the LIN-UART serial mode register (SMR) and the resetting of the LIN-UART (SMR:UPCL = 1) are executed simultaneously, that does not ensure that the operation settings are correct. Therefore, after setting the LIN-UART serial mode register (SMR), reset the LIN-UART again. 2012/ 05/11 339 16.8 (Correct) With the sampling clock edge select bit (ESCR:SCES) set to "0", before modifying any of the bits listed below, disable reception and transmission. After modifying them, reset the LINUART with a software reset. • Serial control register (SCR) Parity enable bit (PEN), stop bit length select bit (SBL), data length select bit (CL) • Serial mode register (SMR) Operating mode select bits (MD[1:0]) • Extended status control register (ESCR) Continuous clock output enable bit (CCO) • Extended communication control register (ECCR) Serial clock transmission/reception side select bit (MS), serial clock delay enable bit (SCDE), start/stop bits mode enable bit (SSM) To reset the LIN-UART with a software reset (SMR:UPCL = 1), finish modifying the settings of the SMR register first, and then access the register again. In the case of not following the above procedure to modify operating settings, proper operations of this device cannot be guaranteed. Though the transmission bit length of the LIN break field is variable, the detection bit length of the LIN break field is fixed at 11 bits. In “ Notes on Using LIN-UART”, a new section “ Modifying sampling clock edge select bit (ESCR:SCES)” should be added after “Modifying operation settings”. Modifying sampling clock edge select bit (ESCR:SCES) With the SCES bit set to "1", executing the LIN-UART software reset is prohibited. • To modify the SCES bit from "0" to "1" Disable reception and transmission, executing a LIN-UART software reset (SMR:UPCL = 1), then modify the SCES bit from "0" to "1". • To modify the SCES bit from "1" to "0" Disable reception and transmission, modify the SCES bit from "1" to "0", then executing a LIN-UART software reset (SMR:UPCL = 1). 2/3 Date 2012/ 05/11 2012/ 05/11 Page 340 340 Section Description 16.8 In “ Notes on Using LIN-UART”, a new section “ Handling framing errors” should be added after “ Synch break detection”. 16.8 Handling framing errors If a framing error occurs (stop bit: SIN = "0") and the next start bit (SIN = "0") immediately follows it, this start bit is recognized regardless of a falling edge for the start bit and reception is started. This sequence is used for detecting the continuous "L" state of the serial data input (SIN) when the next framing error is detected while the data stream is synchronized (See "When reception is always enabled (RXE=1)" in Figure 16.8-1). If this operation is not necessary, disable data reception temporarily after receiving a framing error (RXE = 1→0→1). Therefore, the falling edge of the serial data input (SIN) is detected, the start bit is recognized when "L" is detected at the reception sampling point, and the reception is started (See "When reception is temporarily disabled (RXE=1→0→1)" in Figure 16.8-1). The following diagram should be added as “Figure 16.8-1 UART Dominant Bus Operation” in “ Handling framing errors”. When reception is always enabled (RXE=1) SIN FRE CRE Framing error occurs Error is cleared Reception is ongoing regardress of no falling edge Next framing error occurs Falling edge is next start bit edge When reception is temporarily disabled (RXE=1→ 0 → 1) SIN FRE CRE RXE Reception is reset: Waitng for falling edge Error is cleared Framing error occurs Reception is ongoing regardress of no falling edge 3/3 No further errors Falling edge is next start bit edge