MB95350L Series

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07–12631–3E
8-bit Microcontrollers
CMOS
F2MC-8FX MB95350L Series
MB95F352E/F352L/F353E/F353L/F354E/F354L
■ DESCRIPTION
MB95350L is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction
set, the microcontrollers of this series contain a variety of peripheral resources.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Clock
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (1/8/10/12.5 MHz ±2%, maximum machine clock frequency: 12.5 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer × 2 channels
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
• UART/SIO × 1 channel (The channel can be used either as a UART/SIO channel or as an I2C channel.)
• Alternative selection of UART/SIO
• Full duplex double buffer
• Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer
(Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.8
MB95350L Series
(Continued)
• I2C × 2 channels (One of the two channels can be used either as an I2C channel or as a UART/SIO channel.)
• Supports Standard-mode and Fast-mode (400 kHz)
• Built-in wake-up function
• LIN-UART
• Full duplex double buffer
• Capable of clock-synchronous serial data transfer and clock-asynchronous serial data transfer
• External interrupt × 6 channels
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter × 6 channels
• 8-bit and 10-bit resolution can be chosen.
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F352L/F353L/F354L (maximum no. of I/O ports: 21)
General-purpose I/O ports (N-ch open drain)
:3
General-purpose I/O ports (CMOS I/O)
: 18
• MB95F352E/F353E/F354E (maximum no. of I/O ports: 22)
General-purpose I/O ports (N-ch open drain)
:3
General-purpose I/O ports (CMOS I/O)
: 18
General-purpose input port (CMOS input)
:1
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Low-voltage detection reset and interrupt circuit
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Programmable port input voltage level
• CMOS input level / hysteresis input level
• Dual operation Flash memory
• The erase/write operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
• Protects the content of the Flash memory
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DS07–12631–3E
MB95350L Series
■ PRODUCT LINE-UP
Part number
MB95F352E
MB95F353E
MB95F354E
MB95F352L
MB95F353L
MB95F354L
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Program ROM
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Low-voltage
Yes
No
detection reset
Reset input
Selected through software
Dedicated
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
CPU functions
Data bit length
: 1, 8 and 16 bits
Minimum instruction execution time : 61.5 ns (with machine clock = 16.25 MHz)
Interrupt processing time
: 0.6 µs (with machine clock = 16.25 MHz)
I/O ports (Max): 22
I/O ports (Max): 21
CMOS I/O: 18
GeneralCMOS I/O: 18
N-ch open drain: 3
purpose I/O
N-ch open drain: 3
CMOS input: 1
Time-base timer Interrupt cycle: 0.256 ms to 8.3 s (when external clock = 4 MHz)
Hardware/
Reset generation cycle
- Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
A wide range of communication speeds can be selected by a dedicated reload timer.
Clock-synchronous serial data transfer and clock-asynchronous serial data transfer is
LIN-UART
enabled.
The LIN function can be used as a LIN master or a LIN slave.
6 channels
8/10-bit A/D
converter
8-bit resolution and 10-bit resolution can be chosen.
2 channels
The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel".
8/16-bit
composite timer It has built-in timer function, PWC function, PWM function and input capture function.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
6 channels
External
Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
It can be used to wake up the device from different standby modes.
1-wire serial control
On-chip debug
It supports serial writing. (asynchronous mode)
(Continued)
DS07–12631–3E
3
MB95350L Series
(Continued)
Part number
MB95F352E
MB95F353E
MB95F354E
MB95F352L
MB95F353L
MB95F354L
Parameter
1 channel (The channel can be used either as a UART/SIO channel or as an I2C channel.)
Data transfer with UART/SIO is enabled.
It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
UART/SIO
It uses the NRZ type transfer format.
LSB-first data transfer and MSB-first data transfer are available to use.
Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
2 channels (One of the two channels can be used either as an I2C channel or as a UART/SIO
channel.)
Master/slave transmission and receiving
It has the following functions:
2C
• bus error function
I
• arbitration function
• transmission direction detection function
• wake-up function
• functions of generating and detecting repeated START conditions.
Watch prescaler Eight different time intervals can be selected.
It supports automatic programming, Embedded Algorithm,
write/erase/erase-suspend/erase-resume commands.
It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
Number of write/erase cycles: 100000
Data retention time: 20 years
Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
FPT-24P-M34
Package
FPT-24P-M10
LCC-32P-M19
4
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MB95350L Series
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F352E
MB95F353E
MB95F354E
MB95F352L
MB95F353L
MB95F354L
FPT-24P-M34
O
O
O
O
O
O
FPT-24P-M10
O
O
O
O
O
O
LCC-32P-M19
O
O
O
O
O
O
Package
O: Available
DS07–12631–3E
5
MB95350L Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool.
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DS07–12631–3E
MB95350L Series
■ PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
(TOP VIEW)
SOP24
FPT-24P-M34
TSSOP24
FPT-24P-M10
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
P64/EC1
P14/SDA0
P15/SCL0
32
31
30
29
28
27
26
25
X0/PF0
X1/PF1
NC
NC
NC
NC
P07/INT07
P12/EC0/DBG
X0/PF0
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
UCK/PG0
RST/PF2
UI/SCL1/P17
UO/SDA1/P16
TO10/P62
TO11/P63
DS07–12631–3E
(TOP VIEW)
13
14
15
16
NC
NC
SDA0/P14
SCL0/P15
QFN32
LCC-32P-M19
9
10
11
12
RST/PF2
UI/SCL1/P17
UO/SDA1/P16
1
2
3
4
5
6
7
8
TO11/P63
TO10/P62
NC
NC
Vss
X1A/PG2
X0A/PG1
Vcc
UCK/PG0
24
23
22
21
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
20
19
18
17
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
P64/EC1
7
MB95350L Series
■ PIN DESCRIPTION (24-pin MCU)
Pin no.
1
2
3
4
5
6
7
Pin name
PF0
X0
PF1
X1
VSS
PG2
X1A
PG1
X0A
VCC
PG0
UCK
I/O
circuit
type*
B
B
—
C
C
—
G
PF2
8
RST
10
11
SCL1
A
J
14
15
16
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
General-purpose I/O port
UART/SIO clock pin
Reset pin
Dedicated reset pin on MB95F352L/F353L/F354L
I2C ch. 1 clock I/O pin
UI
UART/SIO data input pin
P16
General-purpose I/O port
SDA1
J
I2C ch. 1 data I/O pin
UO
UART/SIO data output pin
P62
General-purpose I/O port
High-current pin
D
P63
8/16-bit composite timer ch. 1 output pin
D
TO11
13
Main clock input oscillation pin
General-purpose I/O port
TO10
12
General-purpose I/O port
General-purpose input port
P17
9
Function
P15
SCL0
P14
SDA0
P64
EC1
P00
AN00
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
I
I
D
E
General-purpose I/O port
I2C ch. 0 clock I/O pin
General-purpose I/O port
I2C ch. 0 data I/O pin
General-purpose I/O port
8/16-bit composite timer ch. 1 clock input pin
General-purpose I/O port
A/D converter analog input pin
(Continued)
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DS07–12631–3E
MB95350L Series
(Continued)
Pin no.
Pin name
17
P01
AN01
I/O
circuit
type*
E
P02
18
19
20
21
INT02
AN02
E
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
P03
General-purpose I/O port
INT03
AN03
E
External interrupt input pin
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
F
A/D converter analog input pin
SIN
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
E
External interrupt input pin
AN05
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
G
P07
INT07
EC0
DBG
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
G
P12
24
A/D converter analog input pin
SCK
TO01
23
General-purpose I/O port
General-purpose I/O port
P06
22
Function
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
H
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS07–12631–3E
9
MB95350L Series
■ PIN DESCRIPTION (32-pin MCU)
Pin no.
Pin name
I/O
circuit
type*
1
VSS
—
2
3
4
5
PG2
X1A
PG1
X0A
VCC
PG0
UCK
C
C
—
G
PF2
6
RST
8
9
SCL1
A
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
General-purpose I/O port
UART/SIO clock pin
Reset pin
Dedicated reset pin on MB95F352L/F353L/F354L
General-purpose I/O port
J
I2C ch. 1 clock I/O pin
UI
UART/SIO data input pin
P16
General-purpose I/O port
SDA1
J
I2C ch. 1 data I/O pin
UO
UART/SIO data output pin
P63
General-purpose I/O port
High-current pin
D
TO11
10
Power supply pin (GND)
General-purpose input port
P17
7
Function
P62
8/16-bit composite timer ch. 1 output pin
D
TO10
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
11
NC
—
It is an internally connected pin. Always leave it unconnected.
12
NC
—
It is an internally connected pin. Always leave it unconnected.
13
NC
—
It is an internally connected pin. Always leave it unconnected.
14
NC
—
It is an internally connected pin. Always leave it unconnected.
15
16
17
18
P14
SDA0
P15
SCL0
P64
EC1
P00
AN00
I
I
D
E
General-purpose I/O port
I2C ch. 0 data I/O pin
General-purpose I/O port
I2C ch. 0 clock I/O pin
General-purpose I/O port
8/16-bit composite timer ch. 1 clock input pin
General-purpose I/O port
A/D converter analog input pin
(Continued)
10
DS07–12631–3E
MB95350L Series
(Continued)
Pin no.
Pin name
19
P01
AN01
I/O
circuit
type*
E
P02
20
21
22
23
INT02
AN02
E
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
P03
General-purpose I/O port
INT03
AN03
E
External interrupt input pin
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
F
A/D converter analog input pin
SIN
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
E
External interrupt input pin
AN05
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
G
EC0
General-purpose I/O port
H
DBG
P07
INT07
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P12
26
A/D converter analog input pin
SCK
TO01
25
General-purpose I/O port
General-purpose I/O port
P06
24
Function
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
G
General-purpose I/O port
External interrupt input pin
27
NC
—
It is an internally connected pin. Always leave it unconnected.
28
NC
—
It is an internally connected pin. Always leave it unconnected.
29
NC
—
It is an internally connected pin. Always leave it unconnected.
30
NC
—
It is an internally connected pin. Always leave it unconnected.
31
32
PF1
X1
PF0
X0
B
B
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
Main clock input oscillation pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS07–12631–3E
11
MB95350L Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Reset input / Hysteresis input
B
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
• Hysteresis input
• Reset input
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
Pull-up control
P-ch
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx.10 MΩ
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
• Pull-up control available
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
(Continued)
12
DS07–12631–3E
MB95350L Series
Type
Circuit
D
Remarks
P-ch
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
CMOS input
G
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
H
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
(Continued)
DS07–12631–3E
13
MB95350L Series
(Continued)
Type
Circuit
Remarks
I
N-ch
Digital output
• N-ch open drain output
• Hysteresis input
• CMOS input
CMOS input
Hysteresis input
Standby control
J
I2C mode control
Digital output
P-ch
N-ch
•
•
•
•
CMOS output
Hysteresis input
CMOS input
N-ch open drain output in I2C mode
Digital output
CMOS input
Standby control
14
Hysteresis input
DS07–12631–3E
MB95350L Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The PF2/RST pin functions as the reset input pin after power-on. The RSTEN bit in the SYSC register is
used to switch the pin functions, the reset input function and the general-purpose I/O port function, of the
PF2/RST pin. However, only on MB95F352E/F353E/F354E can the pin functions be changed.
DS07–12631–3E
15
MB95350L Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
PF2/RST*2
Reset with LVD
Flash with security function
PF1/X1*2
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
CR
oscillator
RAM (496/240 bytes)
PG1/X0A*2
Interrupt controller
Clock control
(P05*3/TO00)
(P12*1/DBG)
On-chip debug
8/16-bit composite timer ch. 0
(P06*3/TO01)
P02/INT02 to P07/INT07
*3
(P00/AN00 to P05 /AN05)
External interrupt
Internal bus
P12*1/EC0, (P04/EC0)
Wild register
P62*3/TO10
8/16-bit composite timer ch. 1
P64/EC1
8/10-bit A/D converter
I2C ch. 0
I2C ch. 1
(P02/SCK)
(P03/SOT)
P63*3/TO11
P14*1/SDA0
P15*1/SCL0
(P16/SDA1)
(P17/SCL1)
PG0/UCK
LIN-UART
UART/SIO
(P04/SIN)
P16/UO
P17/UI
Port
Vcc
*1: P12, P14 and P15 are N-ch open drain pins.
Vss
*2: Software option
Port
*3: P05, P06, P62 and P63 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
16
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MB95350L Series
■ CPU CORE
• Memory Space
The memory space of the MB95350L Series is 64 Kbyte in size, and consists of an I/O area, a data area,
and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95350L Series are shown below.
• Memory Maps
MB95F352E/F352L
0000H
MB95F353E/F353L
I/O
0080H
0090H
0100H
Access prohibited
RAM 240 bytes
I/O
0080H
0090H
0100H
Register
0180H
MB95F354E/F354L
0000H
0000H
Access prohibited
RAM 496 bytes
I/O
0080H
0090H
0100H
Register
0200H
Access prohibited
RAM 496 bytes
Register
0200H
0280H
0280H
Access prohibited
Access prohibited
0F80H
0F80H
Extended I/O
1000H
B000H
1000H
Flash 4 Kbyte
Access prohibited
F000H
FFFFH
DS07–12631–3E
0F80H
Flash 4 Kbyte
Extended I/O
Extended I/O
Access prohibited
C000H
Access prohibited
1000H
Access prohibited
Access prohibited
B000H
C000H
Flash 4 Kbyte
B000H
Access prohibited
Flash 20 Kbyte
E000H
Flash 8 Kbyte
FFFFH
FFFFH
17
MB95350L Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
R/W
11111111B
0006H
—
—
—
0007H
SYCC
System clock control register
R/W
0000X011B
00000XXXB
(Disabled)
Oscillation stabilization wait time setting register
(Disabled)
0008H
STBC
Standby control register
R/W
0009H
RSRR
Reset source register
R/W XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH
to
0015H
—
—
—
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0034H
—
—
—
(Disabled)
(Disabled)
(Disabled)
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
T11CR1
8/16-bit composite timer 11 status control register 1 ch. 1
R/W
00000000B
0039H
T10CR1
8/16-bit composite timer 10 status control register 1 ch. 1
R/W
00000000B
003AH
to
0048H
—
—
—
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
(Disabled)
(Continued)
18
DS07–12631–3E
MB95350L Series
Address
Register
abbreviation
Register name
004CH,
004DH
—
(Disabled)
004EH
LVDR
004FH
R/W Initial value
—
—
LVD reset voltage selection ID register
R/W
00000000B
LVDC
LVD interrupt control register
R/W
X000000XB
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART receive/transmit data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch. 0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch. 0
R/W
00100000B
0058H
SSR0
UART/SIO serial status and data register ch. 0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch. 0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch. 0
R
00000000B
005BH
to
005FH
—
—
—
0060H
IBCR00
0061H
IBCR10
(Disabled)
I2C bus control register 0 ch. 0
R/W
00000000B
2
R/W
00000000B
2
R
00000000B
I C bus control register 1 ch. 0
0062H
IBSR0
I C bus status register ch. 0
0063H
IDDR0
I2C data register ch. 0
R/W
00000000B
0064H
IAAR0
I2C address register ch. 0
0065H
ICCR0
R/W
00000000B
2
R/W
00000000B
2
I C clock control register ch. 0
0066H
IBCR01
I C bus control register 0 ch. 1
R/W
00000000B
0067H
IBCR11
I2C bus control register 1 ch. 1
R/W
00000000B
0068H
IBSR1
0069H
IDDR1
I2C bus status register ch. 1
R
00000000B
2
R/W
00000000B
2
I C data register ch. 1
006AH
IAAR1
I C address register ch. 1
R/W
00000000B
006BH
ICCR1
I2C clock control register ch. 1
R/W
00000000B
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower)
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
R
00000000B
(Disabled)
Flash memory status register 3
(Continued)
DS07–12631–3E
19
MB95350L Series
Address
Register
abbreviation
Register name
0075H
—
(Disabled)
0076H
WREN
0077H
WROR
0078H
—
0079H
ILR0
007AH
R/W Initial value
—
—
Wild register address compare enable register
R/W
00000000B
Wild register data test setting register
R/W
00000000B
—
—
Interrupt level setting register 0
R/W
11111111B
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
R/W
00000000B
0F97H
T11CR0
8/16-bit composite timer 11 status control register 0 ch. 1
R/W
00000000B
0F98H
T10CR0
8/16-bit composite timer 10 status control register 0 ch. 1
R/W
00000000B
0F99H
T11DR
8/16-bit composite timer 11 data register ch. 1
R/W
00000000B
0F9AH
T10DR
8/16-bit composite timer 10 data register ch. 1
R/W
00000000B
0F9BH
TMCR1
8/16-bit composite timer 10/11 timer mode control register
ch. 1
R/W
00000000B
0F9CH
to
0FBBH
—
—
—
Mirror of register bank pointer (RP) and
mirror of direct bank pointer (DP)
(Disabled)
(Disabled)
(Disabled)
(Continued)
20
DS07–12631–3E
MB95350L Series
(Continued)
Address
Register
abbreviation
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator prescaler select
register ch. 0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
R/W
00000000B
0FC0H
to
0FC2H
—
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H
to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 0XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 00XXXXXXB
0FE6H,
0FE7H
—
0FE8H
SYSC
0FE9H
Register name
(Disabled)
A/D input disable register (lower)
(Disabled)
(Disabled)
R/W Initial value
—
—
System configuration register
R/W
11000001B
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
0FEDH
—
—
—
0FEEH
ILSR
R/W
00000000B
0FEFH
to
0FFFH
—
—
—
(Disabled)
Input level select register
(Disabled)
• R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS07–12631–3E
21
MB95350L Series
■ INTERRUPT SOURCE TABLE
Vector table address
Priority order of
interrupt
Bit name of
sources of the
interrupt level
same level
setting register
(occurring
simultaneously)
Interrupt
request
number
Upper
Lower
External interrupt ch. 4
IRQ00
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 5
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ08
FFEAH
FFEBH
L08 [1:0]
IRQ09
FFE8H
FFE9H
L09 [1:0]
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
IRQ14
FFDEH
FFDFH
L14 [1:0]
IRQ15
FFDCH
FFDDH
L15 [1:0]
IRQ16
FFDAH
FFDBH
L16 [1:0]
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
IRQ21
FFD0H
FFD1H
L21 [1:0]
8/16-bit composite timer ch. 1
(lower)
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
LVD interrupt
UART/SIO ch. 0
—
I2C ch. 1
8/16-bit composite timer ch. 1
(upper)
—
2
I C ch. 0
—
—
22
High
Low
DS07–12631–3E
MB95350L Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
VSS − 0.3
VSS + 4.0
V
VI1
VSS − 0.3
VSS + 4.0
V
Other than P14 and P15*2
VI2
VSS − 0.3
VSS + 6.0
V
P14 and P15*2
VO
VSS − 0.3
VSS + 4.0
V
*2
ICLAMP
−2
+2
mA
Applicable to specific pins*3
Σ|ICLAMP|
—
20
mA
Applicable to specific pins*3
IOL1
IOL2
—
mA
12
ΣIOL
—
100
mA
ΣIOLAV
—
50
mA
IOH1
IOH2
—
“H” level average
current
−15
−15
mA
−4
IOHAV1
—
mA
−8
IOHAV2
“H” level total maximum
output current
15
mA
4
IOLAV2
“H” level maximum
output current
15
—
“L” level average current
“L” level total average
output current
ΣIOH
—
−100
mA
ΣIOHAV
—
−50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
−40
+85
°C
Storage temperature
Tstg
−55
+150
°C
“H” level total average
output current
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Other than P05, P06, P62 and P63
P05, P06, P62 and P63
Other than P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1 pin)
P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
Other than P05, P06, P62 and P63
P05, P06, P62 and P63
Other than P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1 pin)
P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
(Continued)
DS07–12631–3E
23
MB95350L Series
(Continued)
*1: The parameter is based on VSS = 0.0 V.
*2: VI1, VI2 and VO must not exceed VCC + 0.3 V. VI1 and VI2 must not exceed the rated voltage. However, if the
maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used
instead of the VI1 and VI2 ratings.
*3: Applicable to the following pins: P00 to P07, P15, P16, P62 to P64, PF0, PF1, PG0 to PG2
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the
current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin,
affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit
• Input/Output equivalent circuit
Protective diode
VCC
HV(High Voltage) input (0 V to 16 V)
P-ch
Limiting
resistor
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
24
DS07–12631–3E
MB95350L Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Power supply
voltage
Operating
temperature
Value
Remarks
Max
1.8*1*2*3
3.6
In normal operation,
TA = −10°C to +85°C
2.0
3.6
In normal operation,
TA = −40°C to +85°C
1.5
3.6
Hold condition in stop mode
2.7
3.6
In normal operation
1.5
3.6
Hold condition in stop mode
−40
+85
+5
+35
V
VCC
TA
Unit
Min
°C
Other than on-chip debug
mode
On-chip debug mode
Other than on-chip debug mode
On-chip debug mode
*1: This value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: This value is initially 2.03 V when the low-voltage detection reset is used.
*3: The threshold voltage can be set to 2.03 V, 2.55 V or 3.10 V by using the software.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07–12631–3E
25
MB95350L Series
3. DC Characteristics
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter Symbol
"H" level
input
voltage
“L” level
input
voltage
Open-drain
output
application
voltage
“H” level
output
voltage
“L” level
output
voltage
Input leak
current (Hi-Z
output leak
current)
Pull-up
resistance
Input
capacitance
Pin name
Condition
VIHI1
P04, P16, P17
VIHI2
Value
Unit
Remarks
VCC + 0.3
V
When CMOS input
level is selected
—
VSS + 5.5
V
When CMOS input
level is selected
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
*1
0.8 VCC
—
VSS + 5.5
V
Hysteresis input
PF2
—
0.7 VCC
—
VCC + 0.3
V
Hysteresis input
VIL
P04,
P14 to P17
*1
VSS − 0.3
—
0.3 VCC
V
When CMOS input
level is selected
VILS
P00 to P07,
P12, P14 to
P17, P62 to
P64, PF0, PF1,
PG0 to PG2
*1
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VILM
PF2
—
VSS − 0.3
—
0.3 VCC
V
Hysteresis input
VD1
P12
—
VSS − 0.3
—
VSS + 5.5
V
VD2
P14, P15
—
VSS − 0.3
—
VSS + 5.5
V
VD3
P16, P17
—
VSS − 0.3
—
VSS + 3.6
V
VOH1
Output pins
other than P05,
IOH = −4 mA
P06, P12, P62,
P63
VCC − 0.5
—
—
V
VOH2
P05, P06, P62
IOH = −8 mA
and P63
VCC − 0.5
—
—
V
VOL1
Output pins
other than P05, IOL = 4 mA
P06, P62, P63
—
—
0.4
V
VOL2
P05, P06, P62,
IOL = 12 mA
P63
—
—
0.4
V
ILI
All input pins
0.0 V < VI < VCC
−5
—
+5
When pull-up
µA resistance is
disabled
RPULL
P00 to P07,
PG1, PG2
VI = 0 V
25
50
100
When pull-up
kΩ resistance is
enabled
—
5
15
pF
Min
Typ
Max
*1
0.7 VCC
—
P14, P15
*1
0.7 VCC
VIHS1
P00 to P07,
P12, P16, P17,
P60 to P64,
PF0, PF1,
PG0 to PG2
*1
VIHS2
P14, P15
VIHM
CIN
Other than VCC
f = 1 MHz
and VSS
In I2C mode
(Continued)
26
DS07–12631–3E
MB95350L Series
(VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Pin name
Value
Min
Typ*3
Max
Unit
Remarks
—
11.2
20
Flash memory
product (except
mA
writing and
erasing)
—
26.2
38
Flash memory
mA product (at writing
and erasing)
—
13.3
23.4
mA At A/D conversion
—
5.2
9.6
mA
ICCL
VCC
(External clock FCL = 32 kHz
FMPL = 16 kHz
operation)
Subclock mode
(divided by 2)
TA = +25°C
—
15
35
µA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
—
5
15
µA
ICCT
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
—
1
10
µA
ICCMCR
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock
mode
—
9
15
mA
Sub-CR clock
mode
(divided by 2)
TA = +25°C
—
77
160
µA
—
1.1
3
mA
—
0.1
5
µA
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
ICCS
Power
supply
current*2
Condition
VCC
ICCSCR
ICCTS
ICCH
FCH = 32 MHz
Time-base
timer
VCC
mode
(External clock
operation)
Substop mode
TA = +25°C
(Continued)
DS07–12631–3E
27
MB95350L Series
(Continued)
Parameter
Power
supply
current*2
Symbol
Pin name
(VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Condition
Unit
Remarks
Min Typ*3 Max
ILVD
Current
consumption for
low-voltage
detection circuit
only
—
6.4
32
µA
ICRH
Current
consumption for
the main CR
oscillator
—
0.25
0.6
mA
Current
consumption for
the sub-CR
oscillator oscillating
at 100 kHz
—
20
72
µA
VCC
ICRL
*1: The input levels of P04 and P14 to P17 can be switched between “CMOS input level” and “hysteresis input
level”. The input level selection register (ILSR) is used to switch between the two input levels.
*2: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL.
*3: VCC = 3.0 V, TA = +25°C
28
DS07–12631–3E
MB95350L Series
4. AC Characteristics
(1) Clock Timing
(VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Pin name
X0, X1
FCH
X0
X0, X1
—
Clock
frequency
—
1
—
16.25
X1: open
1
—
12
*
1
—
32.5
MHz When the main external
MHz clock is used
12.25
12.5
12.75
MHz
9.8
10
10.2
7.84
8
8.16
0.98
1
1.02
MHz When the main CR clock
is used
MHz TA = − 10 °C to + 85 °C
MHz
12.1875
12.5
9.75
10
10.25
7.8
8
8.2
0.975
1
1.025
—
—
Unit
Remarks
MHz
When the main oscillation
circuit is used
12.8125 MHz
MHz When the main CR clock
is used
MHz TA = − 40 °C to − 10 °C
MHz
When the sub-oscillation
kHz circuit or the sub-external
clock is used
—
—
32.768
—
FCRL
—
—
50
100
200
kHz
When the sub-CR clock is
used
—
61.5
—
1000
ns
When the main oscillation
circuit is used
X1: open
83.4
—
1000
ns
*
30.8
—
1000
ns
—
—
30.5
—
µs
X1: open
33.4
—
—
ns
*
12.4
—
—
ns
—
—
15.2
—
µs
X1: open
—
—
5
ns
*
—
—
5
ns
Clock cycle
time
X0
X0, X1
tLCYL X0A, X1A
CR
oscillation
start time
Max
X0A, X1A
tHCYL
Input clock
rise time and
fall time
Typ
FCL
X0, X1
Input clock
pulse width
Min
FCRH
—
Value
Condition
tWH1 X0
tWL1 X0, X1
tWH2
X0A
tWL2
tCR
tCF
X0
X0, X1
When the main external
clock is used
When the sub-oscillation
circuit or the sub-external
clock is used
When the external clock
is used, the duty ratio
should range between
40% and 60%.
When the external clock
is used
tCRHWK
—
—
—
—
250
µs
When the main CR clock
is used
tCRLWK
—
—
—
—
10
µs
When the sub-CR clock is
used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
DS07–12631–3E
29
MB95350L Series
• Input waveform generated when an external clock (main clock) is used
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0, X1
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When the external clock is used When the external clock
(X1 is open)
is used
X0
X1
X1
X0
X1
Open
FCH
FCH
FCH
• Input waveform generated when an external clock (subclock) is used
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When the external clock
is used
X0A
X1A
Open
FCL
30
DS07–12631–3E
MB95350L Series
(2) Source Clock/Machine Clock
Parameter
Symbol
Source clock
cycle time*1
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
FMPL
Unit
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
80
—
1000
ns
When the main CR clock is used
Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
—
61
—
µs
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.5
—
16.25
MHz When the main oscillation clock is used
1
—
12.5
MHz When the main CR clock is used
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
80
—
16000
ns
When the main CR clock is used
Min: FSP = 12.5 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
µs
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
MHz When the main oscillation clock is used
0.0625
—
12.5
MHz When the main CR clock is used
1.024
—
16.384
3.125
—
50
—
FMP
Machine clock
frequency
Value
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
kHz When the sub-oscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio
selection bits (SYCC:DIV1, DIV0]). This source clock is divided to become a machine clock according to the
division ratio set by the machine clock division ratio selection bits (SYCC:DIV1, DIV0]). In addition, a source
clock can be selected from the following.
• Main clock divided by 2
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS07–12631–3E
31
MB95350L Series
• Schematic diagram of the clock generation block
Divided
by 2
FCH
(Main oscillation)
FCRH
(Main CR clock)
FCL
(Sub-oscillation)
FCRL
(Sub-CR clock)
FSP/FSPL
(Source clock)
Divided
by 2
Divided
by 2
Clock mode select bits
(SYCC2: RCS1, RCS0)
Division
circuit
× 1
× 1/4
× 1/8
×1/16
FMP/FMPL
(Machine clock)
Machine clock divide ratio select bits
(SYCC:DIV1, DIV0)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
Without the on-chip debug function
Operating voltage (V)
3.6
2.7
2.0
~
16 kHz
7.5 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
32
DS07–12631–3E
MB95350L Series
• Operating voltage - Operating frequency (When TA = −10°C to +85°C)
Without the on-chip debug function
Operating voltage (V)
3.6
2.7
1.8
~
16 kHz
5 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
With the on-chip debug function
Operating voltage (V)
3.6
2.7
~
16 kHz
5 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
DS07–12631–3E
33
MB95350L Series
(3) External Reset
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
RST “L” level
pulse width
Symbol
tRSTL
Value
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the
oscillator*2 + 100
—
µs
In stop mode, subclock mode,
sub-sleep mode, watch mode,
and power-on
100
—
µs
In time-base timer mode
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
tRSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
Oscillation
time of
oscillator
Internal reset
34
100 μs
Oscillation stabilization wait time
Execute instruction
DS07–12631–3E
MB95350L Series
(4) Power-on Reset
(VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
1.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 20 mV/ms as
shown below.
VCC
1.5 V
Set the slope of rising to
a value below 20 mV/ms.
Hold condition in stop mode
VSS
DS07–12631–3E
35
MB95350L Series
(5) Peripheral Input Timing
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
Value
Pin name
INT02 to INT07, EC0, EC1
Unit
Min
Max
2 tMCLK*
—
ns
2 tMCLK*
—
ns
*: See “(2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT02 to INT07,
EC0, EC1
0.8 VCC
tIHIL
0.8 VCC
0.2 VCC
36
0.2 VCC
DS07–12631–3E
MB95350L Series
(6) LIN-UART Timing
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
SCK, SOT Internal clock
−95
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
tMCLK*3 + 190
SCK, SIN
0
Serial clock “L” pulse width
tSLSH
SCK
3t
* − tR
—
ns
Serial clock “H” pulse width
tSHSL
SCK
tMCLK*3 + 95
—
ns
SCK ↓ → SOT delay time
tSLOVE
SCK, SOT
—
2 tMCLK*3 + 95
ns
Valid SIN → SCK ↑
tIVSHE
SCK, SIN
190
—
ns
* + 95
—
ns
SCK ↑ → valid SIN hold time
tSHIXE
SCK, SIN
MCLK 3
External clock
operation output pin:
CL = 80 pF + 1 TTL
t
MCLK 3
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
DS07–12631–3E
37
MB95350L Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tF
0.2 VCC
tR
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
tSHIXE
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
38
DS07–12631–3E
MB95350L Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0)
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SOT Internal clock
−95
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
tMCLK*3 + 190
SCK, SIN
0
Serial clock “H” pulse width
tSHSL
SCK
3t
* − tR
—
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
—
ns
SCK ↑ → SOT delay time
tSHOVE
SCK, SOT
—
2 tMCLK*3 + 95
ns
Valid SIN → SCK ↓
tIVSLE
SCK, SIN
190
—
ns
* + 95
—
ns
SCK ↓ → valid SIN hold time
tSLIXE
SCK, SIN
MCLK 3
External clock
operation output pin:
CL = 80 pF + 1 TTL
t
MCLK 3
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
DS07–12631–3E
39
MB95350L Series
• Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
tR
tF
0.2 VCC
0.2 VCC
tSHOVE
2.4 V
SOT
0.8 V
tIVSLE
tSLIXE
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
40
DS07–12631–3E
MB95350L Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1)
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
4 tMCLK*3
ns
−95
Internal clock
operation output pin: tMCLK*3 + 190
CL = 80 pF + 1 TTL
0
—
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
DS07–12631–3E
0.8 V
tSHOVI
tSOVLI
tSLIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
41
MB95350L Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1)
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SOT delay time
tSLOVI
SCK, SOT
Valid SIN → SCK ↑
tIVSHI
SCK, SIN
SCK ↑ → valid SIN hold time
tSHIXI
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
−95
Internal clock
operation output pin: tMCLK*3 + 190
CL = 80 pF + 1 TTL
0
SCK, SOT
MCLK 3
—
4t
*
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
42
tSLOVI
2.4 V
tSHIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
DS07–12631–3E
MB95350L Series
(7) Low-voltage Detection
(VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = −40°C to +85°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
Power release voltage 0
VPDL0+
1.83
1.93
2.03
V
At power supply rise
Power detection voltage 0
VPDL0-
1.80
1.90
2.00
V
At power supply fall
Power release voltage 1
VPDL1+
2.25
2.40
2.55
V
At power supply rise
Power detection voltage 1
VPDL1-
2.20
2.35
2.50
V
At power supply fall
Power release voltage 2
VPDL2+
2.80
2.95
3.10
V
At power supply rise
Power detection voltage 2
VPDL2-
2.70
2.85
3.00
V
At power supply fall
Interrupt release voltage 0
VIDL0+
2.03
2.18
2.33
V
At power supply rise
Interrupt detection voltage 0
VIDL0-
2.00
2.15
2.30
V
At power supply fall
Interrupt release voltage 1
VIDL1+
2.25
2.40
2.55
V
At power supply rise
Interrupt detection voltage 1
VIDL1-
2.20
2.35
2.50
V
At power supply fall
Interrupt release voltage 2
VIDL2+
2.46
2.61
2.76
V
At power supply rise
Interrupt detection voltage 2
VIDL2-
2.40
2.55
2.70
V
At power supply fall
Interrupt release voltage 3
VIDL3+
2.67
2.82
2.97
V
At power supply rise
Interrupt detection voltage 3
VIDL3-
2.60
2.75
2.90
V
At power supply fall
Interrupt release voltage 4
VIDL4+
2.90
3.10
3.30
V
At power supply rise
Interrupt detection voltage 4
VIDL4-
2.80
3.00
3.20
V
At power supply fall
Power supply start voltage
Voff
—
—
1.8
V
Power supply end voltage
Von
3.3
—
—
V
tr
3000
—
—
µs
Power supply voltage
change time
(at power supply rise)
Slope of power supply that the reset
release signal generates within the
rating (VPDL+/VIDL+)
(Continued)
DS07–12631–3E
43
MB95350L Series
(Continued)
(VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = −40°C to +85°C)
Parameter
Value
Symbol
Unit
Remarks
—
µs
Slope of power supply that the reset
detection signal generates within
the rating (VPDL-/VIDL-)
—
300
µs
—
—
150
µs
tdi1
10
—
200
µs
tdi2
—
—
150
µs
Min
Typ
Max
tf
3000
—
Power reset release delay
time
tdp1
10
Power reset detection delay
time
tdp2
Interrupt reset release delay
time
Interrupt reset detection
delay time
Power supply voltage
change time
(at power supply fall)
VCC
Von
Voff
time
VCC
tf
tr
VPDL+/VIDL+
VPDL-/VIDL-
Reset/Interrupt
time
tdp2/tdi2
44
tdp1/tdi1
DS07–12631–3E
MB95350L Series
(8) I2C Timing
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name Condition
SCL clock frequency
fSCL
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHD;STA
SCL clock “L” width
tLOW
SCL clock “H” width
tHIGH
(Repeated) START condition hold time
SCL ↑ → SDA ↓
tSU;STA
Data hold time
SCL ↓ → SDA ↓↑
tHD;DAT
Data setup time
SDA ↓↑ → SCL ↑
tSU;DAT
STOP condition setup time
SCL ↑ → SDA ↑
tSU;STO
Bus free time between STOP condition
and START condition
tBUF
SCL0,
SCL1
SCL0,
SCL1,
SDA0,
SDA1
SCL0,
SCL1
SCL0,
SCL1
SCL0,
SCL1,
SDA0,
SDA1
SCL0,
SCL1,
SDA0,
SDA1
SCL0,
SCL1,
SDA0,
SDA1
SCL0,
SCL1,
SDA0,
SDA1
SCL0,
SCL1,
SDA0,
SDA1
R = 1.7 kΩ,
C = 50 pF*1
Value
StandardFast-mode Unit
mode
Min Max Min Max
0
100
0
400
kHz
4.0
—
0.6
—
µs
4.7
—
1.3
—
µs
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
0
3.45*2
0
0.9*3
µs
0.25
—
0.1
—
µs
4
—
0.6
—
µs
4.7
—
1.3
—
µs
*1: R represents the pull-up resistor of the SCL0/1 and SDA0/1 lines, and C the load capacitor of the SCL0/1
and SDA0/1 lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT ≥ 250 ns is fulfilled.
tWAKEUP
SDA0,
SDA1
tLOW
SCL0,
SCL1
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
fSCL
tHD;STA
tSU;STA
tBUF
tSU;STO
(Continued)
DS07–12631–3E
45
MB95350L Series
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
SCL clock “L”
width
SCL clock “H”
width
Sym- Pin
Condition
bol name
tLOW
tHIGH
SCL0,
SCL1
SCL0,
SCL1
tSU;STO
START
condition
setup time
tSU;STA
Bus free time
between
STOP
condition and
START
condition
Data hold
time
Data setup
time
tBUF
tHD;DAT
tSU;DAT
Unit
Remarks
Min
Max
(2 + nm/2)tMCLK − 20
—
ns
Master mode
(nm/2)tMCLK − 20
(nm/2)tMCLK + 20
ns
Master mode
(−1 + nm/2)tMCLK − 20
(−1 + nm)tMCLK + 20
ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value
is applied.
(1 + nm/2)tMCLK − 20
(1 + nm/2)tMCLK + 20
ns
Master mode
(1 + nm/2)tMCLK − 20
(1 + nm/2)tMCLK + 20
ns
Master mode
SCL0,
SCL1,
(2 nm + 4)tMCLK − 20
SDA0, R = 1.7 kΩ,
SDA1 C = 50 pF*1
—
ns
SCL0,
SCL1,
SDA0,
SDA1
—
ns
SCL0,
START
SCL1,
condition hold tHD;STA
SDA0,
time
SDA1
STOP
condition
setup time
Value*2
SCL0,
SCL1,
SDA0,
SDA1
SCL0,
SCL1,
SDA0,
SDA1
SCL0,
SCL1,
SDA0,
SDA1
Setup time
between
SCL0,
clearing inter- tSU;INT
SCL1
rupt and SCL
rising
3 tMCLK − 20
(−2 + nm/2)tMCLK − 20 (−1 + nm/2)tMCLK + 20
(nm/2)tMCLK − 20
(1 + nm/2)tMCLK + 20
ns
ns
Master mode
Master mode
When assuming
that “L” of SCL is
not extended,
the minimum
value is applied
to first bit of
continuous data.
Otherwise, the
maximum value
is applied.
Minimum value
is applied to
interrupt at 9th
SCL↓. Maximum
value is applied
to the interrupt at
the 8th SCL↓.
(Continued)
46
DS07–12631–3E
MB95350L Series
(Continued)
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Value*2
Unit
Remarks
Condition
Min
Max
Parameter
Symbol
Pin name
SCL clock “L” width
tLOW
SCL0, SCL1
4 tMCLK − 20
—
ns
At reception
SCL clock “H” width
tHIGH
SCL0, SCL1
4 tMCLK − 20
—
ns
At reception
START condition
detection
tHD;STA
SCL0, SCL1,
SDA0, SDA1
2 tMCLK − 20
—
ns
Undetected when 1
tMCLK is used at
reception
STOP condition
detection
tSU;STO
SCL0, SCL1,
SDA0, SDA1
2 tMCLK − 20
—
ns
Undetected when 1
tMCLK is used at
reception
SCL0, SCL1,
RESTART condition
tSU;STA
SDA0, SDA1
detection condition
2 tMCLK − 20
—
ns
Undetected when 1
tMCLK is used at
reception
2 tMCLK − 20
—
ns
At reception
2 tMCLK − 20
—
ns
At slave
transmission mode
SCL0, SCL1, R = 1.7 kΩ,
SDA0, SDA1 C = 50 pF*1
SCL0, SCL1,
SDA0, SDA1
Bus free time
tBUF
Data hold time
tHD;DAT
Data setup time
tSU;DAT
SCL0, SCL1,
SDA0, SDA1
tLOW − 3 tMCLK − 20
—
ns
At slave
transmission mode
Data hold time
tHD;DAT
SCL0, SCL1,
SDA0, SDA1
0
—
ns
At reception
Data setup time
tSU;DAT
SCL0, SCL1,
SDA0, SDA1
tMCLK − 20
—
ns
At reception
Oscillation
stabilization wait
time
+2 tMCLK − 20
—
ns
SCL0, SCL1,
SDA↓ → SCL↑
tWAKEUP
SDA0, SDA1
(at wakeup function)
*1: R represents the pull-up resistor of the SCL0/1 and SDA0/1 lines, and C the load capacitor of the SCL0/1
and SDA0/1 lines.
See “(2) Source Clock/Machine Clock” for tMCLK.
m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
*2: •
•
•
•
DS07–12631–3E
47
MB95350L Series
(9) UART/SIO, Serial I/O Timing
Parameter
(VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Pin name
Condition
Unit
Min
Max
Symbol
Serial clock cycle time
tSCYC
UCK
UCK ↓ → UO time
tSLOV
UCK, UO
Valid UI → UCK ↑
tIVSH
UCK, UI
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Serial clock “L” pulse width
4 tMCLK*
—
ns
−190
+190
ns
2 tMCLK*
—
ns
UCK, UI
2 tMCLK*
—
ns
tSHSL
UCK
4 tMCLK*
—
ns
tSLSH
UCK
4 tMCLK*
—
ns
—
190
ns
Internal clock
operation
External clock
operation
UCK ↓ → UO time
tSLOV
UCK, UO
Valid UI → UCK ↑
tIVSH
UCK, UI
2 tMCLK*
—
ns
UCK ↑ → valid UI hold time
tSHIX
UCK, UI
2 tMCLK*
—
ns
*: See “(2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK
0.8 V
0.8 V
tSLOV
2.4 V
UO
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
UI
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
UCK
0.2 VCC
0.2 VCC
tSLOV
2.4 V
UO
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
UI
0.2 VCC 0.2 VCC
48
DS07–12631–3E
MB95350L Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Resolution
Total error
Linearity error
—
Differential linear
error
Zero transition
voltage
VOT
Full-scale transition
voltage
VFST
Compare time
Sampling time
—
Value
Unit
Min
Typ
Max
—
—
10
bit
−3
—
+3
LSB
−2.5
—
+2.5
LSB
−1.9
—
+1.9
LSB
VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB
V
2.7 V ≤ VCC ≤ 3.6 V
VSS − 0.5 LSB VSS + 1.5 LSB VSS + 3.5 LSB
V
1.8 V ≤ VCC < 2.7 V
VCC − 3.5 LSB VCC − 1.5 LSB VCC + 0.5 LSB
V
2.7 V ≤ VCC ≤ 3.6 V
VCC − 2.5 LSB VCC − 0.5 LSB VCC + 1.5 LSB
V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 3.6 V
1.3
—
140
20
—
140
0.4
—
—
µs
2.7 V ≤ VCC ≤ 3.6 V,
with external
impedance < 1.8 kΩ
30
—
—
µs
1.8 V ≤ VCC < 2.7 V,
with external
impedance < 14.8 kΩ
µs
—
Analog input current
IAIN
−0.3
—
+0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
DS07–12631–3E
Remarks
1.8 V ≤ VCC < 2.7 V
49
MB95350L Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
2.7 V ≤ VCC ≤ 3.6 V
1.7 kΩ (Max)
1.8 V ≤ VCC < 2.7 V
84 kΩ (Max)
14.5 pF (Max)
25.2 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
20
External impedance [kΩ]
External impedance [kΩ]
100
90
80
70
(VCC ≥ 2.7 V)
60
50
(VCC ≥ 1.8 V)
40
30
20
10
18
16
14
(VCC ≥ 2.7 V)
12
10
8
6
4
2
0
0
0
5
10
15
20
25
30
Minimum sampling time [μs]
35
40
0
1
2
3
4
Minimum sampling time [μs]
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
50
DS07–12631–3E
MB95350L Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
2 LSB
3FDH
Digital output
Digital output
3FDH
004H
003H
Actual conversion
characteristic
3FEH
3FEH
VOT
{1 LSB × (N-1) + 0.5 LSB}
004H
VNT
003H
1 LSB
002H
002H
001H
Actual conversion
characteristic
Ideal characteristic
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC - VSS
(V)
1024
N
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
DS07–12631–3E
51
MB95350L Series
(Continued)
Zero transition error
Full-scale transition error
004H
Ideal characteristic
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
002H
Digital output
Digital output
003H
Actual conversion
characteristic
Ideal
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
VSS
Analog input
VCC
VSS
3FEH
Ideal characteristic
Actual conversion
characteristic
(N+1)H
Actual conversion
characteristic
{1 LSB × N + VOT}
VFST
(measurement
value)
VNT
004H
002H
Digital output
Digital output
3FDH
V(N+1)T
NH
VNT
(N-1)H
Actual conversion
characteristic
003H
VCC
Differential linearity error
Linearity error
3FFH
Analog input
Ideal
characteristic
Actual conversion
characteristic
(N-2)H
001H
VOT (measurement value)
VSS
Analog input
VCC
VNT - {1 LSB × N + VOT}
Linearity error
=
of digital output N
1 LSB
N
VSS
Analog input
VCC
V(N+1)T - VNT
Differential linear error
=
- 1
of digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
52
DS07–12631–3E
MB95350L Series
6. Flash Memory Write/Erase Characteristics
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.2*1
0.5*2
s
The time of writing 00H prior to
erasure is excluded.
Sector erase time
(16 Kbyte sector)
—
0.5*1
7.5*2
s
The time of writing 00H prior to
erasure is excluded.
Byte writing time
—
21
6100*2
µs
System-level overhead is excluded.
Erase/write cycle
100000
—
—
cycle
Power supply voltage at erase/
write
2.7
3.0
3.6
V
Flash memory data retention
time
20*3
—
—
year Average TA = +85°C
*1: TA = +25°C, VCC = 3.0 V, 100000 cycles
*2: TA = +85°C, VCC = 2.7 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being +85°C).
DS07–12631–3E
53
MB95350L Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC − TA
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
15
15
FMP = 16 MHz
ICC [mA]
Icc [mA]
FMP = 16 MHz
10
FMP = 10 MHz
10
FMP = 8 MHz
5
FMP = 10 MHz
FMP = 4 MHz
5
FMP = 2 MHz
0
1
2
3
4
0
−50
5
0
Vcc [V]
ICCS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
+100
+150
ICCS − TA
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
20
20
15
15
ICCS [mA]
Iccs [mA]
+50
TA [°C]
10
10
FMP = 16 MHz
FMP = 16 MHz
5
5
FMP = 10 MHz
FMP = 8 MHz
FMP = 10 MHz
FMP = 4 MHz
FMP = 2 MHz
0
−50
0
1
2
3
4
5
0
ICCL − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
+100
+150
ICCL − TA
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
40
40
30
30
ICCL [μA]
IccL [μA]
+50
TA [°C]
Vcc [V]
20
20
10
10
0
1
2
3
Vcc [V]
4
5
0
−50
0
+50
+100
+150
TA [°C]
(Continued)
54
DS07–12631–3E
MB95350L Series
ICCLS − TA
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
15
15
12
12
9
9
IccLS [μA]
IccLS [μA]
ICCLS − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
6
6
3
3
0
−50
0
1
2
3
4
5
0
ICCT − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
10.0
7.5
7.5
IccT [μA]
10.0
IccT [μA]
+100
+150
ICCT − TA
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
5.0
5.0
2.5
2.5
0.0
−50
0.0
1
2
3
4
5
0
+50
+100
+150
TA [°C]
Vcc [V]
ICCTS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
ICCTS − TA
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
2.0
2.0
1.5
1.6
FMP = 16 MHz
1.2
IccTS [mA]
IccTS [mA]
+50
TA [°C]
Vcc [V]
FMP = 10 MHz
FMP = 8 MHz
0.8
FMP = 4 MHz
0.4
1.2
FMP = 16 MHz
0.8
FMP = 10 MHz
0.4
FMP = 2 MHz
0.0
1
2
3
Vcc [V]
4
5
0.0
−50
0
+50
+100
+150
TA [°C]
(Continued)
DS07–12631–3E
55
MB95350L Series
(Continued)
ICCH − VCC
TA = +25°C, FMPL = (stop)
Substop mode with the external clock stopping
ICCH − TA
VCC = 3.0 V, FMPL = (stop)
Substop mode with the external clock stopping
3.0
2.4
2.4
1.8
1.8
IccH [μA]
IccH [μA]
3.0
1.2
1.2
0.6
0.6
0.0
−50
0.0
1
2
3
4
5
0
20
20
15
15
FMP = 12.5 MHz
FMP = 10 MHz
FMP = 8 MHz
10
FMP = 12.5 MHz
5
FMP = 1 MHz
FMP = 1 MHz
0
−50
0
1
2
3
4
5
0
Vcc [V]
+50
+100
+150
TA [°C]
ICCSCR − VCC
TA = +25°C, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
ICCSCR − TA
VCC = 3.0 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
200
200
150
150
ICCSCR [μA]
ICCSCR [μA]
+150
FMP = 10 MHz
FMP = 8 MHz
5
100
100
50
50
0
1
2
3
Vcc [V]
56
+100
ICCMCR − TA
VCC = 3.0 V, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
ICCMCR [mA]
ICCMCR [mA]
ICCMCR − VCC
TA = +25°C, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
10
+50
TA [°C]
Vcc [V]
4
5
0
−50
0
+50
+100
+150
TA [°C]
DS07–12631–3E
MB95350L Series
• Input voltage characteristics
VIHI2 − VCC and VIL − VCC
TA = +25°C
4
4
3
3
VIHI2/VIL [V]
VIHI1/VIL [V]
VIHI1 − VCC and VIL − VCC
TA = +25°C
VIHI1
2
VIL
VIHI2
2
VIL
1
1
0
0
1
2
3
4
1
5
2
VIHS1 − VCC and VILS − VCC
TA = +25°C
4
5
VIHS2 − VCC and VILS − VCC
TA = +25°C
4
4
3
3
VIHS2/VILS [V]
VIHS1/VILS [V]
3
Vcc [V]
Vcc [V]
VIHS1
2
VILS
1
VIHS2
2
VILS
1
0
0
1
2
3
4
5
1
2
Vcc [V]
3
4
5
Vcc [V]
VIHM − VCC and VILM − VCC
TA = +25°C
4
VIHM/VILM [V]
3
2
VIHM
VILM
1
0
1
2
3
4
5
Vcc [V]
DS07–12631–3E
57
MB95350L Series
• Output voltage characteristics
(VCC − VOH2) − IOH
TA = +25°C
1.0
1.0
0.8
0.8
VCC − VOH2 [V]
VCC − VOH1 [V]
(VCC − VOH1) − IOH
TA = +25°C
0.6
0.4
0.2
0.6
0.4
0.2
0
0
−2
−6
−4
−8
0
−10
−2
0
−4
−6
IOH [mA]
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
−12
VOL2 − IOL
TA = +25°C
1.0
1.0
0.8
0.8
0.6
0.6
VOL2 [V]
VOL1 [V]
−10
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VOL1 − IOL
TA = +25°C
0.4
0.4
0.2
0.2
0
0
0
2
6
4
IOL [mA]
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
58
−8
IOH [mA]
8
10
0
2
4
6
8
10
12
14
16
IOL [mA]
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
DS07–12631–3E
MB95350L Series
• Pull-up characteristics
RPULL − VCC
TA = +25°C
250
RPULL [kΩ]
200
150
100
50
0
1
2
3
4
5
Vcc [V]
DS07–12631–3E
59
MB95350L Series
■ MASK OPTIONS
No.
Part Number
MB95F352E
MB95F353E
MB95F354E
Selectable/Fixed
60
MB95F352L
MB95F353L
MB95F354L
Fixed
1
Low-voltage detection reset With low-voltage detection reset
Without low-voltage detection reset
2
Reset
With dedicated reset input
Without dedicated reset input
DS07–12631–3E
MB95350L Series
■ ORDERING INFORMATION
Part Number
MB95F352EPF-G-SNE2
MB95F352LPF-G-SNE2
MB95F353EPF-G-SNE2
MB95F353LPF-G-SNE2
MB95F354EPF-G-SNE2
MB95F354LPF-G-SNE2
MB95F352EPFT-G-SNE2
MB95F352LPFT-G-SNE2
MB95F353EPFT-G-SNE2
MB95F353LPFT-G-SNE2
MB95F354EPFT-G-SNE2
MB95F354LPFT-G-SNE2
MB95F352EWQN-G-SNE1
MB95F352EWQN-G-SNERE1
MB95F352LWQN-G-SNE1
MB95F352LWQN-G-SNERE1
MB95F353EWQN-G-SNE1
MB95F353EWQN-G-SNERE1
MB95F353LWQN-G-SNE1
MB95F353LWQN-G-SNERE1
MB95F354EWQN-G-SNE1
MB95F354EWQN-G-SNERE1
MB95F354LWQN-G-SNE1
MB95F354LWQN-G-SNERE1
DS07–12631–3E
Package
24-pin plastic SOP
(FPT-24P-M34)
24-pin plastic TSSOP
(FPT-24P-M10)
32-pin plastic QFN
(LCC-32P-M19)
61
MB95350L Series
■ PACKAGE DIMENSION
24-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
7.50 mm × 15.34 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.80 mm MAX
Weight
0.44 g
(FPT-24P-M34)
24-pin plastic SOP
(FPT-24P-M34)
Note 1) * : These dimensions do not include resin protrusion.
*15.34±0.10(.604±.004)
24
0.27±0.07
(.011±.003)
13
10.20±0.40
(.402±.016)
INDEX ø1.20±0.1 DEP0.20
ø.047±.004 DEP.008
+0.10
–0.05
+.004
–.002
7.50±0.10
(.295±.004)
Details of "A" part
2.60
.102
+0.20
–0.25
+.008
–.010
0.25(.010)
1
1.27(.050)
12
0.42±0.07
(.017±.003)
"A"
0~8°
0.25(.010)
M
0.60±0.20
(.024±.008)
+0.15
0.15 –0.10
.006 +.006
–.004
0.10(.004)
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F24034S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
62
DS07–12631–3E
MB95350L Series
T
24-pin plastic TSSOP
Lead pitch
0.65 mm
Package width ×
package length
4.40 mm × 7.80 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm MAX
Weight
0.10 g
(FPT-24P-M10)
24-pin plastic TSSOP
(FPT-24P-M10)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
# 7.80±0.10(.307±.004)
+0.06
24
0.13 –0.03
+.002
.005 –.001
13
BTM E-MARK
# 4.40±0.10
(.173±.004)
INDEX
Details of "A" part
6.40±0.20
(.252±.008)
1
12
0.65(.026)
+0.07
0.22 –0.02
+.003
.008 –.001
1.20(.047)
(Mounting height)
MAX
0~8°
"A"
0.10(.004)
0.60±0.15
(.024±.006)
0.10±0.05
(Stand off)
(.004±.002)
0.10(.004)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F24033S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07–12631–3E
63
MB95350L Series
(Continued)
32-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
5.00 mm × 5.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.06 g
(LCC-32P-M19)
32-pin plastic QFN
(LCC-32P-M19)
3.50±0.10
(.138±.004)
5.00±0.10
(.197±.004)
5.00±0.10
(.197±.004)
3.50±0.10
(.138±.004)
INDEX AREA
0.25
(.010
(3-R0.20)
((3-R.008))
0.50(.020)
+0.05
–0.07
+.002
–.003
)
0.40±0.05
(.016±.002)
1PIN CORNER
(C0.30(C.012))
(TYP)
0.75±0.05
(.030±.002)
0.02
(.001
C
+0.03
–0.02
+.001
–.001
(0.20(.008))
)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
64
DS07–12631–3E
MB95350L Series
■ MAJOR CHANGES IN THIS EDITION
Page
Section
Details
7
■ PIN ASSIGNMENT
Deleted the HCLK1 pin and the HCLK2 pin.
9
■ PIN DESCRIPTION (24-pin MCU)
Deleted the HCLK1 pin and the HCLK2 pin.
11
■ PIN DESCRIPTION (32-pin MCU)
Deleted the HCLK1 pin and the HCLK2 pin.
16
■ BLOCK DIAGRAM
Deleted the HCLK1 pin and the HCLK2 pin.
26
■ ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Changed the value of VCC in the operating conditions.
3.0 V to 3.6 V → 2.7 V to 3.6 V
27
Changed the value of VCC in the operating conditions.
3.6 V → 1.8 V to 3.6 V
Changed the typical (Typ) values and the maximum
(Max) values of ICC.
Value
Unit
Remarks
22.4
mA
Flash memory product
(except writing and erasing)
38.1
44.9
mA
Flash memory product (at
writing and erasing)
15.1
24.6
mA At A/D conversion
Min
Typ
Max
—
13.6
—
—
→
Value
Min
Typ*3 Max
Unit
Remarks
—
11.2
20
mA
Flash memory product
(except writing and erasing)
—
26.2
38
mA
Flash memory product (at
writing and erasing)
—
13.3
23.4
mA At A/D conversion
Changed the Typ value of ICCS.
6.3 → 5.2
Changed the Typ value and the Max value of ICCL.
Typ : 20 → 15
Max : 45 → 35
Changed the Typ value and the Max value of ICCLS.
Typ : 6.3 → 5
Max : 30 → 15
Changed the Typ value and the Max value of ICCT.
Typ : 2 → 1
Max : 22 → 10
(Continued)
DS07–12631–3E
65
MB95350L Series
(Continued)
Page
27
Section
■ ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Details
Changed the Typ value of ICCMCR.
11 → 9
Changed the Typ value of ICCSCR.
110 → 77
Changed the Typ value of ICCTS.
1.8 → 1.1
Changed the Typ value of ICCH.
1 → 0.1
Changed the Typ value of ILVD.
8 → 6.4
28
Changed the Typ value of ICRH.
0.5 → 0.25
Added the following note:
*3: VCC = 3.0 V, TA = +25°C
29
30
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1) Clock Timing
Deleted all information about the HCLK1 pin and the
HCLK2 pin in the table.
Deleted HCLK1 and HCLK2 in the “• Input waveform
generated when an external clock (main clock) is used”.
Deleted the external connection diagram for the HCLK1
pin and HCLK2 pin in “• Figure of main clock input port
external connection”.
43
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(7) Low-voltage Detection
Deleted VPHYS/VIHYS from the diagram.
44
54 to 59 ■ SAMPLE CHARACTERISTICS
61
Deleted the following parameters:
Power hysteresis width 0,
Power hysteresis width 1,
Power hysteresis width 2,
Interrupt hysteresis width 0,
Interrupt hysteresis width 1,
Interrupt hysteresis width 2,
Interrupt hysteresis width 3,
Interrupt hysteresis width 4
■ ORDERING INFORMATION
Added diagrams showing sample characteristics.
Added the following part numbers for the 32-pin plastic
QFN package (LCC-32P-M19):
MB95F352EWQN-G-SNE1
MB95F352LWQN-G-SNE1
MB95F353EWQN-G-SNE1
MB95F353LWQN-G-SNE1
MB95F354EWQN-G-SNE1
MB95F354LWQN-G-SNE1
The vertical lines marked on the left side of the page indicate the changes.
66
DS07–12631–3E
MB95350L Series
MEMO
DS07–12631–3E
67
MB95350L Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department