UCN5890 and UCN5891: BiMOS II 8-Bit Serial-Input Latched Source Drivers

Data Sheet
26182.12C
5890 AND
5891
BIMOS II 8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
16
SERIAL
DATA OUT
GROUND
1
CLOCK
2
SERIAL
DATA IN
3
STROBE
4
OUT 1
5
12
OUT 8
OUT 2
6
11
OUT 7
OUT 3
7
10
OUT 6
OUT 4
8
9
OUT 5
CLK
SHIFT
REGISTER
VDD 15
14
OUTPUT
ENABLE
VBB 13
LOAD
SUPPLY
OE
ST
LATCHES
LOGIC
SUPPLY
Dwg. PP-026-2A
Note the suffix ‘A’ devices (DIP) and the suffix
‘LW’ devices (SOIC) are electrically identical and
share a common terminal number assignment.
Frequently applied in non-impact printer systems, the UCN5890A,
UCN5890LW, UCN5891A, and UCN5891LW are BiMOS II serial-input,
latched source (high-side) drivers. The octal, high-current smart-power ICs
merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS
control logic (strobe and output enable) with sourcing power Darlington
outputs. Typical applications include multiplexed LED and incandescent
displays, relays, solenoids, and similar peripheral loads to a maximum of
-500 mA per output.
T
C
U
D
O
R
y
l
P On
Except for output voltage ratings, these smart high-side driver ICs are
equivalent. The UCN5890A/LW are rated for operation with load supply
voltages of 20 V to 80 V and a minimum output sustaining voltage of 50 V.
The UCN5891A/LW are optimized for operation with supply voltages of 5 V
to 50 V (35 V sustaining).
BiMOS II devices have higher data-input rates than the original BiMOS
circuits. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V,
higher speeds are possible. The CMOS inputs are compatible with standard
CMOS and NMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors to ensure a proper input-logic high. A CMOS serial data
output, allows cascading these devices in multiple drive-line applications
required by many dot matrix, alphanumeric, and bar graph displays.
D
e
E
c
U
n
N ere
I
T
f
e
N
R
O
r
C
o
S F
I
D
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Output Voltage, VOUT
(UCN5890A & UCN5890LW) ......... 80 V
(UCN5891A & UCN5891LW) ......... 50 V
Logic Supply Voltage Range,
VDD .................................... 4.5 V to 15 V
Driver Supply Voltage Range, VBB
(UCN5890A/LW) ................ 20 V to 80 V
(UCN5891A/LW) ............... 5.0 V to 50 V
Input Voltage Range,
VIN ........................ -0.3 V to VDD + 0.3 V
Continuous Output Current,
IOUT ........................................... -500 mA
Allowable Package Power Dissipation,
PD ......................................... See Graph
Operating Temperature Range,
TA .................................. -20°C to +85°C
Storage Temperature Range,
TS ................................ -55°C to +150°C
Caution: CMOS devices have input static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
Suffix ‘A’ devices are supplied in a standard dual in-line plastic package
with copper lead frame for enhanced package power dissipation characteristics. Suffix ‘LW’ devices are supplied in a standard wide-body SOIC package
for surface-mount applications. Similar driver, featuring reduced output
saturation voltage, are the UCN5895A and A5895SLW. Complementary,
8-bit serial-input, latched sink drivers are the Series UCN5820A.
FEATURES
■
■
■
■
■
50 V or 80 V Source Outputs
Output Current to -500 mA
Output Transient-Suppression Diodes
To 3.3 MHz Data-lnput Rate
Low-Power CMOS Logic and Latches
Always order by complete part number, e.g., UCN5891LW .
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FUNCTIONAL BLOCK DIAGRAM
2.5
CLOCK
2.0
SUFFIX 'A', R θJA = 60°C/W
SERIAL
DATA IN
8-BIT SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
1.5
SERIAL
DATA OUT
VDD
GROUND
OUTPUT
ENABLE
1.0
MOS
BIPOLAR
SUFFIX 'LW', R
0.5
0
25
θJA
= 94°C/W
VBB
50
75
100
125
AMBIENT TEMPERATURE IN °C
150
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Dwg. No. A-12,654
Dwg. GP-018C
TYPICAL INPUT CIRCUIT
VDD
IN
Number of
Outputs On at
UCN5890/91A Max. Allowable Duty Cycle
at TA of
IOUT = -200 mA
50°C
60°C
70°C
8
7
6
5
4
3
2
1
53%
60%
70%
83%
100%
100%
100%
100%
47%
54%
64%
75%
94%
100%
100%
100%
41%
48%
56%
67%
84%
100%
100%
100%
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
V BB
Number of
Outputs On at
OUT
Dwg. No. A-12,648
UCN5890/91LW Max. Allowable Duty Cycle
at TA of
IOUT = -200 mA
50°C
60°C
70°C
8
7
6
5
4
3
2
1
40%
45%
53%
62%
80%
100%
100%
100%
35%
41%
48%
56%
71%
96%
100%
100%
31%
36%
42%
50%
62%
84%
100%
100%
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2003 Allegro MicroSystems, Inc.
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 80 V (UCN5890A/LW) or 50 V
(UCN5891A/LW), VDD = 5 V and 12 V (unless otherwise noted).
Characteristic
Output Leakage Current
Output Saturation Voltage
Output Sustaining Voltage
Input Voltage
Input Current
Input lmpedance
Max. Clock Frequency
Symbol
VBB
ICEX
Max.
VCE(SAT)
VCE(sus)
VIN(1)
50 V
Max.
50 V
Min.
Limits
Max.
Units
TA = +25°C
—
-50
µA
TA = +70°C
—
-100
µA
IOUT = -100 mA
—
1.8
V
IOUT = -225 mA
—
1.9
V
IOUT = -350 mA
—
2.0
V
IOUT = -350 mA, L = 2 mH, UCN5891A/LW
35
—
V
IOUT = -350 mA, L = 2 mH, UCN5890A/LW
50
—
V
VDD = 5.0 V
3.5
5.3
V
VDD = 12 V
10.5
12.3
V
Test Conditions
VIN(0)
50 V
VDD = 5 V to 12 V
-0.3
+0.8
V
IIN(1)
50 V
VDD = VIN = 5.0 V
—
50
µA
VDD = VIN = 12 V
—
240
µA
VDD = 5.0 V
100
—
kΩ
VDD = 12 V
50
—
kΩ
3.3*
—
MHz
VDD = 5.0 V
—
20
kΩ
VDD = 12 V
—
6.0
kΩ
ZIN
50 V
fc
50 V
Serial Data Output
Resistance
ROUT
50 V
Turn-On Delay
tPLH
50 V
Output Enable to Output, IOUT = -350 mA
—
2.0
µs
Turn-Off Delay
tPHL
50 V
Output Enable to Output, IOUT = -350 mA
—
10
µs
Supply Current
IBB
50 V
All outputs on, All outputs open
—
10
mA
All outputs off
—
200
µA
VDD = 5 V, All outputs off, Inputs = 0 V
—
100
µA
VDD = 12 V, All outputs off, Inputs = 0 V
—
200
µA
VDD = 5 V, One output on, All Inputs = 0 V
—
1.0
mA
VDD = 12 V, One output on, All Inputs = 0 V
—
3.0
mA
TA = +25°C
—
50
µA
TA = +70°C
—
100
µA
IF = 350 mA
—
2.0
V
lDD
Diode Leakage Current
Diode Forward Voltage
IR
VF
50 V
Max.
Open
NOTES: Turn-off delay is influenced by load conditions. Systems applications well below the specified output loading may require
timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem
pole configuration.
Positive (negative) current is defined as going into (coming out of) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
CLOCK
A
B
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
D
DATA IN
E
F
C
STROBE
BLANKING
G
OUTN
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
Information present at any register is transferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high,
all of the output buffers are disabled (off) without
affecting the information stored in the latches or
shift register. With the OUTPUT ENABLE input
low, the outputs are controlled by the state of
their respective latches.
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
X
H
X
P1 P2 P3 ...
... X X H
PN-1 PN
L
L
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
X
H = High Logic Level
X = Irrelevant
P = Present State
Output
Enable
I1 I2 I3 ... IN-1 IN
L
L
P1 P2 P3 ... PN-1 PN
... L
L
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TYPICAL APPLICATION
SOLENOID OR RELAY DRIVER
+5V
+48V
UCN5890A
1
CLOCK
2
DATA IN
3
STROBE
4
16
SHIFT
REGISTER
LATCHES
DATA OUT
VDD 15
OE
14
VBB
13
5
12
6
11
7
10
8
9
OUTPUT ENABLE
(ACTIVE LOW)
Dwg. No. A-12,548
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5890A and UCN5891A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
9
16
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
0.775
0.735
8
0.005
BSC
MIN
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
9
16
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
19.68
18.67
BSC
8
0.13
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
NOTES: 1.
2.
3.
4.
Dwg. MA-001-16A mm
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 25 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5890LW and UCN5891LW
Dimensions in Inches
(for reference only)
16
9
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.4133
0.3977
0.0926
0.1043
Dwg. MA-008-16A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
16
9
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
10.50
10.10
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
Dwg. MA-008-16A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 47 devices or add “TR” to part number for tape and reel.
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