I2C Controller for Serial EPROMs March 2014 Reference Design RD1006 Introduction The I2C bus provides a simple two-wire means of communication. This protocol supports multi-masters and provides a low-speed connection between intelligent control devices, such as microprocessors, and general-purpose circuits, such as memories. This reference design documents an I2C controller designed to interface with serial EEPROM devices. The design can be used with a microprocessor to read the configuration data from a serial EEPROM that supports an I2C protocol. It is intended to be a simple I2C master using 7-bit addresses and providing random reads cycles only. Typically, serial EEPROMs are programmed at the time of board assembly. They store configuration information which is read by a microprocessor during power-up. This design is implemented in Verilog and VHDL. Lattice design tools are used for synthesis, place and route and simulation. The design can be targeted to multiple Lattice device families. Its small size makes it portable across different FPGA/CPLD architectures. This design assumes the user has experience with I2C controllers. Information available in the documents listed below is not repeated in this document. References • National Semiconductor NM24C16 16,384-Bit Serial EEPROM • Philips I2C Specification • Lattice Semiconductor Data Sheets Theory of Operation Overview This I2C controller provides an interface between standard microprocessors and I2C serial EEPROM devices. It acts as an I2C master to support random read cycles from the serial EEPROM. The design consists of the following modules: • I2c Top-level module • I2c_clk Clock generation module • I2c_rreg Read register module • I2c_st State machine module • I2c_wreg Write register module Figure 1 provides a top-level block diagram for the I2C controller reference design. © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 rd1006_02.6 I2C Controller for Serial EEPROMs Figure 1. I2C Controller Top-Level Block Diagram I2C Controller clock rst_l i2c_clk reg_clk_in addr[1:0] ack_l scl_pin i2c_wreg Tri-state Buffer Control i2c_st reg_clk_out I2C Interface rd_wr_l Microprocessor Interface cs_l sda_pin i2c_rreg data[7:0] Top-Level Signal Descriptions Table 1 provides descriptions of the input/output signals of the I2C controller. Signals ending with “_L” indicate an active low signal. This convention is used throughout the design. The chip select signal is assumed synchronous to the clock. Address, data and the read/write signals are assumed valid at the assertion of the chip select. Table 1. I2C Signal Descriptions Interface Signal I2C Interface Description I2C chip select from microprocessor RD_WR_L Input Write pulse from microprocessor ADDR[1:0] Input Address bus from microprocessor DATA[7:0] Microprocessor Interface Type Input CS_L I/O CLK Microprocessor data bus Input Input clock from microprocessor, 50MHz RST_L Input Asynchronous reset REG_CLK_IN Input Clock used to latch word address ACK_L Output Microprocessor cycle acknowledge REG_CLK_OUT Output Generated clock to latch word address SCL_PIN Output I2C clock pin SDA_PIN I/O I2C data pin Register Descriptions Table 2 lists the I2C controller registers. Table 2. I2C Registers Register Address Type Word Address 00 Read/Write Data 01 Read Status 10 Read 2 I2C Controller for Serial EEPROMs Design Module Description I2C_CLK Module The I2C_CLK module provides a one-microprocessor clock tick wide pulse every 5µsec. This is used to control the state machine. The 8-bit counter in this module can be adjusted to meet the needs of any design. If a faster microprocessor clock is used, a bigger counter will be needed. If it is desired to run the I2C bus at a faster speed, the counter can be smaller. This design assumes a microprocessor clock frequency of 50MHz. I2C_RREG Module The I2C_RREG module provides a multiplexor for reading data back to the CPU. The word address, the data read from the I2C device and status information can be read back. The status register bits are defined in Table 3. Table 3. Status Register Bits Bit Signal 7 ready 6 ack_err 0 Active Description 2 The I C device has responded back with read data. The I2C device did not acknowledge the current read cycle. An I2C cycle is in progress. I2C_ST Module The state machine used in this module is shown in Figure 2. It starts from the IDLE state and waits for the i2c_go signal from the I2C_WREG module. Once i2c_go is asserted, the state machine goes through various i2c states to ensure proper address/data transfers. The ACK signals are inserted by the serial EPROM, which is the slave I2C device in this design. The I2C_st module provides: • A state machine to control the I2C cycles • A bit counter to count the bit phases • I2C clock generation • I2C data generation • Ready generation • Error generation 3 I2C Controller for Serial EEPROMs Figure 2. State Machine !scl_tick !scl_tick !scl_tick ack4 stop1 start2 scl & scl_tick scl_tick dev_ add2 !scl_tick !scl_tick scl_tick ack2 start1 scl & scl_tick !scl_tick dis_ clk1 !scl_tick scl_tick scl & scl_tick scl & scl_tick cntr_done & scl_tick wait scl_tick cntr_done & scl_tick en_clk cntr_done & scl_tick i2c_go !scl_tick !scl_tick data scl & scl_tick Idle !scl_tick !i2c_go dev_ add1 !scl_tick cntr_done & scl_tick ack3 scl & scl_tick ack1 !scl_tick w_add !scl_tick !scl_tick I2C_WREG Module The I2C_WREG module provides the word address register. When this register is written to, an i2c_go signal is generated. This causes the state machine to start a random read cycle to the address stored in this register. A clock, reg_clk_out, is generated in this module to allow the use of input registers for the word address register in certain CPLD/FPGA architectures. In order to use the input registers, this clock signal must be routed to a dedicated clock input pin on the board. Please refer to the device data sheet for architectural details. A microprocessor acknowledge signal is provided in this module. This is the chip select signal delayed by one clock tick. This signal can be omitted from the design if the function is not needed or is performed elsewhere. I2C Module The I2C module provides the top-level logic for the design. It links together the individual modules and tri-state buffer for the microprocessor data. It also provides the open drain outputs for the I2C clock and data signals. Test Bench Description The test bench for this design includes the following modules: • CLK_RST • I2C_SLAVE • I2C_TB • MICRO 4 I2C Controller for Serial EEPROMs CLK_RST Module The CLK_RST module provides the clock and reset signals to the test bench. Editing the CLK_PERIOD parameter changes the clock frequency. Editing the RESET_TIME parameter changes the duration of reset. The reset_recovery parameter delays the clock until a fixed time, allowing all registers to recover from reset. I2C_SLAVE Module The I2C_SLAVE module provides a model of a I2C memory device which features 256 memory locations. The slave module is able to detect START and STOP commands from the I2C controller. It generates ACK after the word address cycle and leaves the I2C bus tristated after data read. The data stored in the memory is the same as its address. This provides a convenient way to check the data by comparing “Slave Data Receive on Write” and “Slave Data Transmitted on Read” messages during simulation. I2C_TB Module The I2C_TB module is the top-level test bench for the design. It instantiates the I2C controller as well as the modules in the test bench. MICRO Module The MICRO module provides the microprocessor stimulus to the I2C controller. This module provides tasks to simulate write and read cycles to the I2C controller. It also performs error checking on the data read back from the I2C controller. Design Flow Lattice design tools are used for synthesis, place and route and simulation. In addition to the place and route/fitter engine, the Lattice ispLEVER® design tool includes Synplify®/SynplifyPro® from Synplicity®, and Active-HDL® from Aldec®. The details of the design flow can be found in the README.txt file that comes with the reference design. Timing Diagrams The following timing diagrams show the major timing milestones in the simulation. Microprocessor Write Cycle The microprocessor writes a “55” to the word address register. This causes the I2C controller state machine to start a random read cycle to the I2C device. Figure 3. Microprocessor Write Cycle Timing Diagram Microprocessor Read Cycle The microprocessor reads the status register. Bit 1 is set indicating an I2C cycle is in progress. Bits 6 and 7 are cleared. This indicates the cycle has not completed and that an error has not been detected. 5 I2C Controller for Serial EEPROMs Figure 4. Microprocessor Read Cycle Timing Diagram I2C Device Address Write Cycle An I2C cycle starts, followed by the device address and an acknowledge from the I2C device. Figure 5. I2C Device Address Write Cycle Timing Diagram I2C Word Address Cycle The word address cycle starts, followed by an acknowledge from the I2C device. Figure 6. I2C Word Address Cycle Timing Diagram 6 I2C Controller for Serial EEPROMs I2C Device Address Read Cycle The second device address cycle, this time requesting a read. Figure 7. I2C Device Address Read Cycle Timing Diagram I2C Read Data Cycle The data is read from the I2C device. This cycle is done without an acknowledge. A stop is asserted by the controller. Figure 8. I2C Read Data Cycle Timing Diagram 7 I2C Controller for Serial EEPROMs Microprocessor Read Status Cycle The status register is read indicating the I2C cycle has completed. Figure 9. Microprocessor Read Status Cycle Timing Diagram Microprocessor Read Data Cycle The I2C data is read by the microprocessor. Figure 10. Microprocessor Read Data Cycle Timing Diagram 8 I2C Controller for Serial EEPROMs Implementation This design is implemented in Verilog and VHDL. When using this design in a different device, density, speed, or grade, performance and utilization may vary. Default settings are used during the fitting of the design. Table 3. Performance and Resource Utilization Device Family ECP5™ 6 LatticeECP3™ 3 MachXO3L™ 7 MachXO2™ 1 MachXO™ 2 LatticeXP2™ 4 ispMACH® 4000ZE5 Language Speed Grade Utilization Fmax(MHz) I/Os Architecture Resources Verilog -6 85 LUTs >50 18 N/A VHDL -6 85 LUTs >50 18 N/A Verilog -6 96 LUTs >50 18 N/A VHDL -6 94 LUTs >50 18 N/A Verilog-LSE -6 85 LUTs >50 18 N/A Verilog-Syn -6 85 LUTs >50 18 N/A VHDL-LSE -6 84 LUTs >50 18 N/A VHDL-Syn -6 86 LUTs >50 18 N/A Verilog -6 86 LUTs >50 18 N/A VHDL -6 85 LUTs >50 18 N/A Verilog -3 82 LUTs >50 18 N/A VHDL -3 82 LUTs >50 18 N/A Verilog -5 89 LUTs >50 18 N/A VHDL -5 90 LUTs >50 18 N/A Verilog -5ns 64 Macrocells >50 18 N/A VHDL -5ns 64 Macrocells >50 18 N/A 1. Performance and utilization characteristics are generated using LCMXO2-1200HC-6TG144C with Lattice Diamond® 3.1 design software with LSE (Lattice Synthesis Engine). 2. Performance and utilization characteristics are generated using LCMXO256E-3T100C with Lattice Diamond 3.1 design software with LSE. 3. Performance and utilization characteristics are generated using LFE3-17EA-6FTN256C with Lattice Diamond 3.1 design software. 4. Performance and utilization characteristics are generated using LFXP2-5E-5M132C with Lattice Diamond 3.1 design software. 5. Performance and utilization characteristics are generated using LC4256ZE-5TN100C with Lattice Diamond 3.1 design software. 6. Performance and utilization characteristics are generated using LFE5U-45F-6MG285C with Lattice Diamond 3.1 design software with LSE. 7. Performance and utilization characteristics are generated using LCMXO3L-4300C-6BG256C with Lattice Diamond 3.1 design software with LSE and Synplify Pro. Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com 9 I2C Controller for Serial EEPROMs Revision History Date Version — — Change Summary February 2009 02.1 Design updated to include MachXO support. Document updates to reflect the design/tool change. September 2009 02.2 Design updated to include ispMACH 4000ZE support. Added VHDL source file and testbench. December 2009 02.3 Previous Lattice releases. Added support for LatticeXP2 device family. Updated for ispLEVER 8.0. November 2010 02.4 Added support for the MachXO2 device family. Updated to support Lattice Diamond 1.1 design software. Updated to support ispLEVER 8.1 SP1 design software. April 2011 02.5 Added support for LatticeECP3 device family. March 2014 02.6 Updated Table 3, Performance and Resource Utilization. Updated to support Lattice Diamond 1.2 design software. - Added support for ECP5 device family. - Added support for MachXO3L device family. - Added support for Lattice Diamond 3.1 design software. Updated corporate logo. Updated Technical Support Assistance information. 10