I2C Slave Peripheral Using the Embedded Function Block February 2014 Reference Design RD1124 Introduction Microprocessors often have a limited number of general purpose I/O (GPIO) ports that reduce pin count and shrink package size, but limit the number of I/Os to which a microprocessor can be connected. To allow more I/Os to be connected to microprocessors, I/O expanders or port expanders are used to provide I/O expansion capability. Most generic GPIO expanders use low pin count protocols, such as I2C or SPI, as the interface to the master. They allow designers to save the GPIO ports on the microprocessor for other critical tasks. The I2C GPIO Memory Interface reference design provides a programmable solution for serial expansion of GPIOs. It uses an Inter IC Communication (I2C) interface between the microprocessor and the GPIOs. The design provides additional control and monitoring capabilities for a microprocessor when it does not have sufficient GPIOs to do the job. Apart from the GPIO expander, this design also provides a memory interface to the microprocessor. This memory is accessible via the I2C interface. The I2C memory command interface is similar to those commonly found in discrete I2C memory devices. This reference design is intended to provide a familiar and intuitive interface extension to the MachXO2™ Embedded Function Block (EFB). The EFB I2C module supports the major features listed in the I2C specification. Users can take advantage of the MachXO2 hardened I2C port to access user-defined internal registers or provide a memory extension. The user is spared from learning operational details of the I2C protocol, the WISHBONE bus or the EFB block. Interface Figure 1. I2C to GPIO Memory Interface SDA GPI_0[7:0] SCL GPI_1[7:0] INTQ GPI_2[7:0] RST_N GPI_3[7:0] CLK MEM_ADDR[7:0] GPO_0[7:0] I2C – GPIO Memory Interface GPO_1[7:0] MEM_WD[7:0] GPO_2[7:0] MEM_RD[7:0] GPO_3[7:0] MEM_WR Enable MEM_CLK IRQ[3:0] © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 rd1124_01.2 I2C Slave Peripheral Using the Embedded Function Block Functional Description This design provides eight bytes of I/O port and memory interface, which is controlled through the I2C slave interface. There are four single-byte input ports and four single-byte output ports. The interrupt generation block generates an interrupt signal to the master when at least one of the interrupt pins is active high. This design interfaces with an embedded memory block. The memory read and write operations are controller by the I2C commands. The operation of the design will be activated only when an enable command is received by the I2C slave. The state machine in the design is designed according to TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices. It responds to the commands issued by an I2C master. In normal situations, the I2C slave acknowledges the successful receipt of an address or data by issuing an Ack command. In the case of an erroneous transfer, the state machine will respond with a Nack command. The state machine is capable of handling error conditions such as invalid commands, unexpected or wrong operands, abrupt stop, etc. The detailed state machine flow for read and write commands is shown in Figures 6, 7 and 8. Figure 6 shows the common steps to be followed for a read and write operation. Figure 7 show the steps to be followed for a read operation and Figure 8 shows the steps to be followed for a write operation. Figure 2. Functional Block Diagram IRQ[3:0] I2C GPIO Memory Interface INTQ Interrupt Generation GPO0 GPO1 GPO2 I2C Master GPO3 SCL SDA GPIO Port State Machine and Command Decoding EFB I2C Port WISHBONE Bus GPI0 GPI1 GPI2 Memory Interface CLK RST_N GPI3 Enable EBR Memory 2 I2C Slave Peripheral Using the Embedded Function Block Figure 3. State Machine Flow for Common Operations State 0: Idle State 1: Enable I2C Interface State 2: Clock Disable State 3: Wait for Not Busy State 4: Discard Data 1 State 5: Discard Data 2 State 2 If Stop State 7: Wait for TRRDY State 8: Store I2C Command Information Interrupt Read Command State 9: Check for Valid/Invalid Command Enable Command/ Error Command State 17 Other Valid Commands State 10: Wait for TRRDY If Stop Interrupt Command State 11: Store Operand State 2 State 17 GPIO & Memory Command State 12: Wait for TRRDY 3 If Stop State 2 I2C Slave Peripheral Using the Embedded Function Block Figure 4. State Machine Flow for Read Operations State 12: Wait for TRRDY Read Operation State 14: Read Data Read More Data Read Done State 19: Wait for TRRDY Read Done State 16: Send NACK for Extra Data State 17: Wait for Stop State 2 Figure 5. State Machine Flow for Write Operations State 12: Wait for TRRDY Write Operation State 2 State 13: Check for SRW Bit State 19: Wait for TRRDY State 15: Send Data to Master Send More Data State 18: Wait for TRRDY State 16: Send NACK for Extra Data State 17: Wait for Stop State 2 4 Read Done I2C Slave Peripheral Using the Embedded Function Block Table 1. I2C GPIO Expander I/O Interface Descriptions Signal I/O Description I2C Master Interface SCL Inout Serial clock SDA Inout Serial Data in INTQ Output External interrupt, asserted low. Asserted low when any IRQ status register bit is set (open drain output). GPO_0[7:0] Output General purpose output byte port GPO_1[7:0] Output General purpose output byte port GPO_2[7:0] Output General purpose output byte port GPO_3[7:0] Output GPI_0[7:0] Input General purpose input byte port GPI_1[7:0] Input General purpose input byte port GPI_2[7:0] Input General purpose input byte port GPI_0[7:0] Input General purpose input byte port IRQ[3:0] Input Input interrupt Input Master clock RST_N Input Active low reset Enable Output General purpose enable signal MEM_CLK Output Clock port for memory MEM_WR Output Memory write signal MEM_ADDR[7:0] Output Memory address MEM_WD[7:0] Output Memory write data MEM_RD[7:0] Input Memory read data GPIO Interface General purpose output byte port General Signals CLK Memory Interface 5 I2C Slave Peripheral Using the Embedded Function Block I2C Slave Interface The I2C GPIO Memory Interface design has a 7-bit I2C slave address format. This address is defined by the user while instantiating an EFB block from the IPexpress™ tool. In this design the I2C slave address is set as '0001001B'. The first seven bits of the first byte sent by the I2C master after a start condition are the I2C slave address. The eighth bit determines the direction of the message. A '0' in the least significant position of the first byte indicates a write operation from the I2C master to the I2C slave. A '1' in this position indicates a read operation on the I2C bus. Figure 6. I2C Slave Address Start Parameter I2C Slave Address R/W A typical I2C write and read command sequence is shown in the figures below. Figure 7. I2C Write Operation Start Slave Address Output Data From Master W Ack Command Ack Output Data Ack Ack Stop From Slave Figure 8. I2C Read Operation Start Slave Address Repeat Input Data From Master Slave Address Nack W Ack R Ack Stop From Slave 6 Register Ack Input Data Ack I2C Slave Peripheral Using the Embedded Function Block HDL Parameter Descriptions This design uses a number of parameters to control various aspects of the design. This allows the user to specify the interfaces to meet custom requirements without modifying the underlying Verilog RTL code. Table 2 provides descriptions of the parameters used in the design. Table 2. Parameter Descriptions Operation Description Value GPI_PORT_NUM Specifies the number of general purpose input ports 1|7 GPI_DATA_WIDTH Specifies the width of general purpose input ports 1|8 GPO_PORT_NUM Specifies the number of general purpose output ports 1|7 GPO_DATA_WIDTH Specifies the width of general purpose output ports 1|8 MEM_ADDR_WIDTH Specifies the width of memory address 1|8 IRQ_NUM Specifies the number of input interrupt pin MAX_MEM_BURST_NUM Specifies the burst width for memory operation 1|8 INTQ_OPENDRAIN Specify whether INTQ output will be open drain or not 1|255 ON/OFF Commands Table 3. Commands Operation Command Operands Number of Bytes in Command Data Enable 0x06 Nil Nil Disable 0x04 Nil Nil 1 byte IRQ Enable Write 0x66 Nil 1 byte bitwise enable IRQ Status 0x65 Nil 1 byte bitwise interrupt source IRQ Clear 0x61 Nil 1 byte bitwise interrupt clear IRQ Enable Read 0x6A Nil 1 byte bitwise enable read Write GPO 0x01 Port # (0 to 3) 1 byte write data Read GPI 0x05 Port # (0 to 3) 1 byte read data Write Memory 0x02 1-byte address 8 bytes write data Read Memory 0x0B 1-byte address 8 bytes read data 2 bytes 3 bytes 10 bytes Enable/Disable Command The Enable command sets the Enable pin of the design. This signal is used to activate the custom logic or memory interface. Figure 9 shows the enable command operation. The Disable command has the same structure except for the command value. Figure 9. Enable Command Operation SCL SDA A6 A5 A4 A3 A2 0 1 Start By Master W 0 0 0 0 0 1 ACK By MachXO2 Frame 1 I2C Slave Addres s Byte 0 ACK By MachXO2 Frame 2 CMD Byte 7 1 Stop By Master I2C Slave Peripheral Using the Embedded Function Block Interrupt Commands This design supports four input interrupts and based upon their status and enable bit it will generate an output interrupt, INTQ. These inputs can be enabled/disabled by the I2C master. The interrupt output signal is activated (active low) when one of the interrupt signals is set and the corresponding interrupt enable bit is also set. The I2C master can read the status of these interrupts and its enable settings by issuing a read command. The design maintains two registers to hold the values of the interrupt enable and interrupt status. The interrupt enable register will hold the values of enables set by the I2C master. The I2C master can perform a read operation on this register. The interrupt status register will hold the status of the interrupt input when it has changed from '0' to '1'. The status register will be cleared by the I2C master only by sending IRQ clear command. Figure 3 shows the structure of the interrupt enable and status register. Table 4. Interrupt Enable and Status Register Register Interrupt Enable Interrupt Status Width 8 8 Access R/W R/W Reset Value Bit Definition 0x00 [7-4] – Reserved for future use 3 – Enable IRQ[3] signal 2 – Enable IRQ[2] signal 1 – Enable IRQ[1] signal 0 – Enable IRQ[0] signal 0x00 [7-4] – Reserved for future use 3 – Set when IRQ[3] goes from 0 to 1 2 – Set when IRQ[2] goes from 0 to 1 1 – Set when IRQ[1] goes from 0 to 1 0 – Set when IRQ[0] goes from 0 to 1 [3-0] will be reset when I2C master sends IRQ Clear. The corresponding bit will be cleared in the status register. Figure 10. Interrupt: Set, Status, Clear 8 I2C Slave Peripheral Using the Embedded Function Block GPIO Commands Four single-byte input and output ports can be controlled by the I2C master. All the GPIO commands are three-byte commands. The first byte contains the I2C address and the second byte contains the GPIO port address. Depending upon the read/write operation, the third byte is written or read by the I2C master. GPIO commands are shown in Figure 11. Figure 11. Write GPO Transaction SCL ... SDA A6 A5 A4 A3 A2 0 1 W Start By Master 0 0 0 0 0 0 0 1 ACK By MachXO2 0 0 0 0 0 0 P1 ACK By MachXO2 Frame 1 I2C Slave Address Byte P0 ... ACK By MachXO2 Frame 2 CMD Byte Frame 3 Operand (Port) SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D0 ACK By MachXO2 Stop By Master Frame 4 GPO Data Byte Figure 12. Read GPI Transaction SCL ... SDA A6 A5 A4 A3 A2 0 1 Start By Master W 0 0 0 0 0 1 0 ACK By MachXO2 Frame 1 I2C Slave Address Byte 1 0 0 0 A6 A5 A4 A3 A2 0 1 Frame 2 CMD Byte R Frame 4 I2C Slave Address Byte 0 P1 Frame 3 Operand (Port) NACK By Master Frame 5 GPI Data Byte 9 P0 ACK By MachXO2 D7 D6 D5 D4 D3 D2 D1 D0 ACK By MachXO2 Restart By Master 0 ACK By MachXO2 SCL (continued) SDA (continued) 0 Stop By Master ... I2C Slave Peripheral Using the Embedded Function Block Memory Commands An EBR-based memory is interfaced to this design. All memory operations are controlled by the I2C master. The intermediate commands, such as address or write/read, will be generated by the state machine inside the design. A burst of eight bytes are read/written into memory every time. This make the size of the I2C transfer 10 bytes. The enable command will activate the memory block. The memory commands will be similar to the GPIO commands except that they are 10-byte commands. The timing diagram for the memory interface is shown in Figure 13. Figure 13. Memory Interface Timing Diagram Erroneous Commands This design is capable of detecting error transfers such as incorrect commands, too many bytes, too few bytes etc. The design can respond to different error scenarios. In the case of an incorrect command sent to the design, the design will issue a NACK. If there are more than the required number of bytes present in the transfer, the design will consider the relevant bytes and ignore the extra bytes sent by the master. When there are fewer bytes provided by the master, the slave design will ignore the command and discard the data. Please note that this design does not support stand-alone read operation. 10 I2C Slave Peripheral Using the Embedded Function Block Test Bench Description The I2C GPIO Memory Interface design is simulated with the aide of I2C Master Bus Functional modules. The test bench for this design consists of the following functional blocks, as shown in Figure 15. • I2C master bus functional model • EBR-based memory module • Design under test (I2C slave) • Back-end interface (clock and reset generation) Figure 14. Test Bench Architecture GPIO Back End Interface CLK_MEM INTQ I2C Master Model SDA SCL I2C GPIO Memory Interface (DUT) MEM_ADDR MEM_WD MEM_RD EBR-Based Memory MEM_WR The following timing diagrams show the major timing milestones in the simulation. Figure 15. Enable Command 11 I2C Slave Peripheral Using the Embedded Function Block Figure 16. Set Interrupt Command Figure 17. Writing GPO Command Figure 18. Writing into Memory Command Figure 19. Reading from Memory Command 12 I2C Slave Peripheral Using the Embedded Function Block Implementation Table 5. Performance and Resource Utilization Family Language Speed Grade Utilization fmax (MHZ) I/Os Architecture Resources Verilog -3 193 LUTs >45 100 EFB MachXO21 MachXO3L2 VHDL -3 216 LUTs >45 100 EFB Verilog-LSE -6 193 LUTs >45 100 EFB Verilog-Syn -6 182 LUTs >45 100 EFB VHDL-LSE -6 216 LUTs >45 100 EFB VHDL-Syn -6 199 LUTs >45 100 EFB 1. Performance and utilization characteristics are generated using LCMOX02-1200ZE-3MG132C with Lattice DiamondTM 3.1 design software with LSE. 2. Performance and utilization characteristics are generated using LCMXO3L-4300C-6BG256C with Lattice Diamond 3.1 design software with LSE and Synplify Pro®. References • I2C Specification from Freescale Semiconductor, Inc. • TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary April 2012 01.0 Initial release. September 2013 01.1 Updated for VHDL implementation. Added HDL Parameter Descriptions section. Updated Figure 3 and Verilog and VHDL code to remove clock stretching support per PCN#10A-13. Updated Technical Support Assistance information. February 2014 01.2 Updated I2C Slave Interface section. Changed I2C slave address. Updated Table 5, Performance and Resource Utilization. - Modified Utilization data for Verilog implementation Added VHDL implementation. - Changed device and Lattice Diamond software version in footnote. Added support for MachXO3L device family. 13