The following document contains information on Cypress products. CM71-10133-1ET3 Errata FR Family 32-BIT MICROCONTROLLER MB91461/MB91F467R HARDWARE MANUAL Date 2008/ 5/30 Page 6 Item 1.3 2009.4.1 Description "Figure 1.3-1 Package Dimensions of MB91461/F467R" was corrected as indicated by the shading below. (Error) (Correct) [mcu_doc0749] 1/3 Date 2009/ 4/1 Page 38 Item 3.1 Description Table 3.1-1 was corrected as indicated by the shading below. MB91F467R Built-in ROM external bus mode The address of built-in FLASH is added. 0004 0000H The address of Reset/mode vector is changed. 0010 4000H → 0010 0000H MB91F467R External ROM external bus mode The address of built-in FLASH is added. 0004 0000H The address of Reset/mode vector is changed. 0010 4000H → 0010 0000H 2008/ 7/1 108 3.11.6 [mcu_doc0770] "Figure 3.11-3 The Structure of the Standby Control Register" was corrected as indicated by the shading below. (Error) STCR bit 7 6 STOP SLEEP 5 HIZ 4 SRST 3 OS1 2 OS0 1 0 Reserved OSCD1 bit 7 6 STOP SLEEP 5 HIZ 4 SRST 3 OS1 2 OS0 1 0 OSCD2 OSCD1 Address:000481H (Correct) STCR Address:000481H 2008/ 7/1 110 3.11.6 [mcu_doc0823] The following description of "[bit1] Reserved bit" in "* STCR: Standby Control Register" was corrected as indicated by the shading below. (Error) [bit1] Reserved bit This bit is reserved. (Correct) [bit1] OSCD2 (sub-clock oscillation stop bit) (MB91F467R Only) Controls the oscillation stop of the sub-clock oscillation circuit at the stop mode. Operation of sub-clock at OSCD2 STOP mode Value Function 0 Does not stop the sub-clock oscillation at the stop mode. 1 Stops the sub-clock oscillation at the stop mode. It is initialized to “1” by reset (INIT). It is readable and writable Note: It is a reserve bit for MB91461. [mcu_doc0823] 2/3 Date 2009/ 4/1 Page 301 Item 10.4 Description "Figure 10.4-16 Configuration of Control Register (Port 19)" was corrected as indicated by the shading below. (Error) 2009/ 4/1 301 10.4 Address bit7 6 5 4 PFR19 000D93H − PFR19_6 PFR19_5 PFR19_4 EPFR19 000DD3H − EPFR19_6 R/W R/W R/W − 3 2 1 0 Initial value − PFR19_2 PFR19_1 PFR19_0 -000-000B − EPFR19_2 EPFR19_1 EPFR19_0 -0---0---B R/W R/W R/W − (Correct) Address bit7 6 5 4 PFR19 000D93H − PFR19_6 PFR19_5 PFR19_4 EPFR19 000DD3H − EPFR19_6 R/W R/W R/W − 3 2 1 − PFR19_2 PFR19_1 − EPFR19_2 − R/W R/W − 0 Initial value PFR19_0 -000-000B -0---0---B − R/W [mcu_doc0856] "Table 10.4-16 Function of Control Register (Port 19)" was corrected as indicated by the shading below. (Error) Bit name Value Function X0B 10B 11B P19_2: External pin is used as a general-purpose port (P19_2). SCK4: Used as SCK of LIN-UART4. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. * Setting is disabled. Value Function 0XB 10B P19_2: External pin is used as a general-purpose port (P19_2). SCK4: Used as SCK of LIN-UART4. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. * Setting is disabled. PFR19_2/EPFR19_2 (Correct) Bit name PFR19_2/EPFR19_2 11B 2009/ 4/1 540 17.3.1 [mcu_doc0856] The following description of "[bit10] CRE: Reception error flag clear bit" in "■ Serial Control Register (SCR)" was added as indicated by the shading below. [bit10] CRE: Reception error flag clear bit Reception error clear Write Read 0 Invalid [Initial value] Read value is always "0" Clears all reception errors 1 (PE, FRE, ORE). This bit clears the PE, FRE, and ORE flags of the serial status register (SSR). It also clears a reception error interrupt factor. Writing "1" to this bit clears the error flags. Writing "0" is invalid. Reading this bit always returns "0". Note: When the reception error flag is cleared without disabling the reception, the reception is interrupted once at that timing and then it restarts. Therefore, when the reception is restarted, Incorrect data might be received. CRE [mcu_doc:0806] 3/3