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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10158-1E
FR80
32-BIT MICROCONTROLLER
MB91665 Series
HARDWARE MANUAL
FR80
32-BIT MICROCONTROLLER
MB91665 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU SEMICONDUCTOR LIMITED
MB91665 Series
Preface
Thank you for your continued use of Fujitsu Semiconductor products.
Read this manual and "Data Sheet" thoroughly before using products in the MB91665 series.
■ Purpose of this manual and intended readers
This manual explains the functions and operations of the MB91665 series and describes how it is used.
The manual is intended for engineers engaged in the actual development of products using the MB91665
series.
Note: FR is an abbreviation for the FUJITSU RISC controller, which is a product of Fujitsu
Semiconductor Limited.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
■ Sample programs and development environment
Fujitsu Semiconductor offers sample programs free of charge for using the peripheral functions of the
FR80 family. Fujitsu Semiconductor also makes available descriptions of the development environment
required for the MB91665 series. Feel free to use them to verify the operational specifications and usage
of this Fujitsu Semiconductor microcontroller.
• Microcontroller support information:
http://edevice.fujitsu.com/micom/en-support/
* Note that the sample programs are subject to change without notice. Since they are offered as a way to
demonstrate standard operations and usage, evaluate them sufficiently before running them on your
system.
Fujitsu Semiconductor assumes no responsibility for any damage that may occur as a result of using a
sample program.
CM71-10158-1E
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•
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for
the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for
any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is
secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or
other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e.,
submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.
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FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
MB91665 Series
Manuals That Make Up the Manuals for This Series
The manuals used for this series are listed below. See the manual appropriate to the applicable
conditions.
The contents of these manuals are subject to change without notice. Contact us to check the latest
versions available.
■ Hardware manual
• FR80 FAMILY MB91665 SERIES HARDWARE MANUAL (CM71-10158) (this manual)
■ Data sheet
• MICROCONTROLLER 32-bit ORIGINAL FR80 FAMILY MB91665 SERIES DATA SHEET
(DS07-16916)
■ Programming manual
• FR80 FAMILY PROGRAMMING MANUAL (CM71-00104)
This manual explains a programming model and instructions for the FR80 family CPUs.
■ Hardware tool-related manual
• DSU-FR EMULATOR MB2198-01 HARDWARE MANUAL (CM71-00413)
This manual explains emulator handling and specifications, and it explains how to connect and operate
the emulator.
■ Software tool-related manuals
• SOFTUNETM WORKBENCH OPERATION MANUAL for V6 (CM71-00328)
This manual explains how to operate the integrated development environment called SOFTUNE and
the development procedures.
• SOFTUNETM WORKBENCH USER'S MANUAL for V6 (CM71-00329)
This manual explains the basic functions and dependent functions of SOFTUNE Workbench.
• SOFTUNETM WORKBENCH COMMAND REFERENCE MANUAL for V6 (CM71-00330)
This manual explains the commands and built-in variables/functions of SOFTUNE Workbench.
• FR FAMILY 32-BIT MICROCONTROLLER EMBEDDED C PROGRAMMING MANUAL FOR
APPLICATION (CM71-00324)
This manual describes the know-how for creating built-in systems using the C compiler fcc911 for the
FR family. The manual explains how to create efficient C programs using the architecture of the FR
family and provides the notes.
• FR FAMILY SOFTUNE C/C++ COMPILER MANUAL for V6 (CM81-00206)
Refer to this manual when using SOFTUNE C/C++ compiler to create/develop application programs in
C and C++.
• FR FAMILY SOFTUNETM ASSEMBLER MANUAL for V6 (CM71-00203)
This manual explains the functions of Fujitsu SOFTUNETM Assembler operating in Windows 98,
Windows Me, Windows 2000, or Windows XP and how to use it.
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
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MB91665 Series
• SOFTUNETM LINKAGE KIT MANUAL for V6 (CM71-00327)
This manual explains the functions of Fujitsu SOFTUNETM Linkage Kit operating in Windows 98,
Windows Me, Windows 2000, or Windows XP and how to use it.
See the manual when developing an application program.
• FR Family ABSOLUTE ASSEMBLY LIST GENERATOR TOOL MANUAL (CM71-00305)
This manual explains absolute assemble lists.
• FR-V/FR FAMILY SOFTUNE C/C++ ANALYZER MANUAL for V5 (CM81-00309)
This manual explains the functions of C/C++ Analyzer and how to use it.
• FR-V/FR FAMILY SOFTUNE C/C++ CHECKER MANUAL for V5 (CM81-00310)
This manual explains the functions of C/C++ Checker and how to use it.
■ REALOS-related manuals
● REALOS μITRON3.0-related manuals
• FR/F2MC FAMILY IN CONFORMANCE WITH μITRON SPECIFICATIONS SOFTUNETM
REALOSTM/FR/907/896 CONFIGURATOR MANUAL (CM71-00322)
This manual explains the functions and operations of SOFTUNE REALOS Configurator.
• FR-V/FR/F2MC FAMILY IN CONFORMANCE WITH μITRON SPECIFICATIONS SOFTUNETM
REALOSTM/ANALYZER MANUAL (CM81-00315)
This manual explains the functions provided by SOFTUNE REALOS Analyzer and how to utilize the
functions.
• FR FAMILY IN CONFORMANCE WITH μITRON 3.0 SPECIFICATIONS SOFTUNE REALOS/
FR USER'S GUIDE (CM71-00320)
This manual explains the configuration/activation of REALOS/FR application systems.
See the manual when performing comprehensive work for an entire system.
• FR FAMILY IN CONFORMANCE WITH μITRON 3.0 SPECIFICATIONS SOFTUNE REALOS/
FR KERNEL MANUAL (CM71-00321)
This manual explains the functions provided by SOFTUNE REALOS/FR and how to utilize the
functions.
See the manual when creating an application system or user program.
● REALOS μITRON4.0-related manuals
• FR FAMILY IN CONFORMANCE WITH μITRON 4.0 SPECIFICATIONS SOFTUNETM
REALOSTM/FR Spec.4 PROGRAMMING MANUAL (CM81-00316)
This manual explains the functions provided by SOFTUNE REALOS/FR Spec.4 and how to utilize the
functions.
• FR-V/FR FAMILY IN CONFORMANCE WITH μITRON 4.0 SPECIFICATIONS SOFTUNETM
REALOSTM KERNEL MANUAL (CM81-00312)
This manual explains the functions provided by SOFTUNE REALOS/FRV/FR Spec.4 and how to
utilize the functions.
• FR-V/FR FAMILY IN CONFORMANCE WITH μITRON 4.0 SPECIFICATIONS SOFTUNETM
REALOSTM CONFIGURATOR MANUAL (CM81-00311)
This manual explains the functions provided by SOFTUNE REALOS Configurator (GUI) and how to
utilize the functions.
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FUJITSU SEMICONDUCTOR LIMITED
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MB91665 Series
• FR-V/FR /F2MC FAMILY IN CONFORMANCE WITH μITRON SPECIFICATIONS SOFTUNE
REALOSTM ANALYZER MANUAL (CM81-00315)
This manual explains the functions provided by SOFTUNE REALOS Analyzer and how to utilize the
functions.
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
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How to Use This Manual
■ Finding a function
The following methods can be used to search for the explanation of a desired function in this manual:
• Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
• Search from the register list
The register list lists all the registers of this device. You can look up the name of a desired register on
the list to find the address of its location or the page that explains it.
The address where each register is located is not described in the text. To verify the address of a
register, see "APPENDIX A I/O Map", and "APPENDIX B List of Registers".
• Search from the index
You can look up the keyword such as the name of a peripheral function in the index to find the
explanation of the function.
■ About the chapters
Basically, this manual explains 1 peripheral function per chapter.
■ Terminology
This manual uses the following terminology.
Term
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Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
MB91665 Series
CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
CHAPTER 2
2.1
2.2
2.3
2.4
Overview ........................................................................................................1
MB91665 Series Overview .....................................................................................................................2
MB91665 Series Product Configuration .................................................................................................7
MB91665 Series Block Diagram .............................................................................................................9
Package Dimensions ............................................................................................................................10
Pins of the MB91665 Series .......................................................................13
Pin Assignment Diagram ......................................................................................................................14
Pin Functions ........................................................................................................................................16
I/O Circuit Types ...................................................................................................................................29
Setting Method for Pins ........................................................................................................................33
CHAPTER 3
CPU ..............................................................................................................63
3.1 Memory Space ......................................................................................................................................64
3.2 Features of the Internal Architecture ....................................................................................................66
3.3 Operation Modes ..................................................................................................................................67
3.4 Pipeline .................................................................................................................................................68
3.5 Overview of Instructions .......................................................................................................................70
3.5.1 Arithmetic Operation ........................................................................................................................70
3.5.2 Load and Store ................................................................................................................................70
3.5.3 Branch .............................................................................................................................................71
3.5.4 Logical Operation and Bit Operation ...............................................................................................71
3.5.5 Direct Addressing ............................................................................................................................71
3.5.6 Bit Search ........................................................................................................................................71
3.5.7 Other ................................................................................................................................................71
3.6 Basic Programming Model ....................................................................................................................72
3.7 Registers ...............................................................................................................................................73
3.7.1 General-purpose Registers (R0 to R15) ..........................................................................................73
3.7.2 Program Status Register (PS) .........................................................................................................74
3.7.3 Program Counter (PC) .....................................................................................................................79
3.7.4 Table Base Register (TBR) .............................................................................................................80
3.7.5 Return Pointer (RP) .........................................................................................................................81
3.7.6 System Stack Pointer (SSP) ............................................................................................................82
3.7.7 User Stack Pointer (USP) ................................................................................................................83
3.7.8 Multiply & Divide Registers ..............................................................................................................84
3.8 Data Configuration ................................................................................................................................85
3.8.1 Bit Ordering .....................................................................................................................................85
3.8.2 Byte Ordering ..................................................................................................................................86
3.8.3 Word Alignment ...............................................................................................................................87
3.9 Addressing ............................................................................................................................................88
3.9.1 Direct Addressing Areas ..................................................................................................................88
3.9.2 20-bit Addressing Area ....................................................................................................................89
3.9.3 32-bit Addressing Area ....................................................................................................................89
3.9.4 Vector Table Initial Area ..................................................................................................................89
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3.10 Branch Instructions .............................................................................................................................. 90
3.10.1 Operation with Delay Slots ............................................................................................................. 90
3.10.2 Operation without Delay Slots ........................................................................................................ 92
3.11 EIT (Exception, Interrupt, Trap) ........................................................................................................... 93
3.11.1 EIT Sources .................................................................................................................................... 93
3.11.2 Return from EIT .............................................................................................................................. 93
3.11.3 Interrupt Level ................................................................................................................................. 94
3.11.4 I Flag ............................................................................................................................................... 95
3.11.5 Interrupt Level Mask Register (ILM) ............................................................................................... 96
3.11.6 Level Mask for Interrupts ................................................................................................................ 96
3.11.7 Interrupt Control Register (ICR) ...................................................................................................... 97
3.11.8 System Stack Pointer (SSP) ........................................................................................................... 97
3.11.9 Interrupt Stack ................................................................................................................................ 97
3.11.10 Table Base Register (TBR) ............................................................................................................. 98
3.11.11 EIT Vector Table ............................................................................................................................. 98
3.11.12 Multi-EIT Processing ....................................................................................................................... 99
3.11.13 Operation ...................................................................................................................................... 100
3.11.14 INT Instruction Operation .............................................................................................................. 101
3.11.15 INTE Instruction Operation ........................................................................................................... 102
3.11.16 Step Trace Trap Operation ........................................................................................................... 102
3.11.17 Undefined Instruction Exception Operation .................................................................................. 103
3.11.18 RETI Instruction Operation ........................................................................................................... 103
3.11.19 Delay Slots and EIT ...................................................................................................................... 103
CHAPTER 4
Clock Generating Parts ............................................................................ 105
4.1 Overview ............................................................................................................................................ 106
4.2 Configuration ..................................................................................................................................... 107
4.2.1 Clock Generating Parts ................................................................................................................. 107
4.2.2 Source Clock (SRCCLK) Selection Block ..................................................................................... 110
4.3 Pins .................................................................................................................................................... 111
4.4 Registers ............................................................................................................................................ 112
4.4.1 Clock Source Select Register (CSELR) ........................................................................................ 113
4.4.2 Clock Source Monitor Register (CMONR) .................................................................................... 117
4.4.3 Clock Stabilization Time Select Register (CSTBR) ...................................................................... 120
4.4.4 PLL Configuration Register (PLLCR) ............................................................................................ 123
4.5 Explanation of Operations ................................................................................................................. 127
4.5.1 Explanation of Clock Source Operations ...................................................................................... 127
4.5.2 Switching the Source Clock (SRCCLK) ....................................................................................... 130
4.5.3 Multiple Rate for Generating the PLL Clock (PLLCLK) ................................................................. 133
CHAPTER 5
Clock Division Control Part ..................................................................... 135
5.1 Overview ............................................................................................................................................ 136
5.2 Internal Clocks ................................................................................................................................... 137
5.3 Configuration ..................................................................................................................................... 139
5.4 Registers ............................................................................................................................................ 140
5.4.1 Divide Clock Configuration Register 0 (DIVR0) ............................................................................ 141
5.4.2 Divide Clock Configuration Register 1 (DIVR1) ............................................................................ 142
5.4.3 Divide Clock Configuration Register 2 (DIVR2) ............................................................................ 144
5.5 Division Rate ...................................................................................................................................... 146
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5.6
Notes on Use ......................................................................................................................................148
CHAPTER 6
Main Timer .................................................................................................149
6.1 Overview .............................................................................................................................................150
6.2 Configuration ......................................................................................................................................151
6.3 Registers .............................................................................................................................................152
6.3.1 Main Timer Control Register (MTMCR) .........................................................................................153
6.4 Interrupts ............................................................................................................................................157
6.5 An Explanation of Operations and Setting Procedure Examples .......................................................158
6.5.1 Main Timer Operation ....................................................................................................................158
6.5.2 Transition to Stop Mode ................................................................................................................160
CHAPTER 7
Sub Timer ..................................................................................................161
7.1 Overview .............................................................................................................................................162
7.2 Configuration ......................................................................................................................................163
7.3 Registers .............................................................................................................................................164
7.3.1 Sub Timer Control Register (STMCR) ...........................................................................................165
7.4 Interrupts ............................................................................................................................................169
7.5 An Explanation of Operations and Setting Procedure Examples .......................................................170
7.5.1 Sub timer operation .......................................................................................................................170
7.5.2 Transition to Stop Mode, and Watch Mode ...................................................................................172
CHAPTER 8
Low-power Dissipation Mode ..................................................................173
8.1 Overview .............................................................................................................................................174
8.2 Configuration ......................................................................................................................................175
8.3 Registers .............................................................................................................................................177
8.3.1 Standby Mode Control Register (STBCR) .....................................................................................178
8.3.2 Sleep Rate Configuration Register (SLPRR) .................................................................................181
8.4 An Explanation of Operations and Setting Procedure Examples .......................................................183
8.4.1 Operation When Clock Control Is Set ............................................................................................184
8.4.2 Operation in Doze Mode ................................................................................................................186
8.4.3 Operation in Sleep Mode ...............................................................................................................187
8.4.4 Operation in Main Timer Mode ......................................................................................................190
8.4.5 Operation in Watch Mode ..............................................................................................................192
8.4.6 Operation in Stop Mode .................................................................................................................194
8.5 Notes on Use ......................................................................................................................................197
CHAPTER 9
Reset ..........................................................................................................199
9.1 Overview .............................................................................................................................................200
9.2 Configuration ......................................................................................................................................201
9.3 Pins .....................................................................................................................................................203
9.4 Registers .............................................................................................................................................204
9.4.1 Reset Result Register (RSTRR) ....................................................................................................205
9.4.2 Reset Control Register (RSTCR) ..................................................................................................207
9.5 Explanation of Operations ..................................................................................................................209
9.5.1 Reset Types ..................................................................................................................................209
9.5.2 Reset Resource .............................................................................................................................210
9.5.3 Operation of Reset ........................................................................................................................212
9.5.4 Irregular reset ................................................................................................................................217
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9.6
Operating State and Transition .......................................................................................................... 218
CHAPTER 10 Interrupt Controller .................................................................................. 223
10.1 Overview ............................................................................................................................................ 224
10.2 Configuration ..................................................................................................................................... 225
10.3 Registers ............................................................................................................................................ 226
10.3.1 Interrupt Control Register (ICR00 to ICR47) ................................................................................. 227
10.4 An Explanation of Operations and Setting Procedure Examples ....................................................... 229
10.4.1 Explanation of Operations of Interrupt Controller ......................................................................... 229
10.5 Notes on Use ..................................................................................................................................... 231
CHAPTER 11 Interrupt Request Batch-Read Function ................................................ 233
11.1 Overview ............................................................................................................................................ 234
11.2 Configuration ..................................................................................................................................... 235
11.3 Registers ............................................................................................................................................ 236
11.3.1 Interrupt Request Batch-Read Register 0 Upper (IRPR0H) ......................................................... 237
11.3.2 Interrupt Request Batch-Read Register 2 Lower (IRPR2L) .......................................................... 239
11.3.3 Interrupt Request Batch-Read Register 3 Upper (IRPR3H) ......................................................... 240
11.3.4 Interrupt Request Batch-Read Register 3 Lower (IRPR3L) .......................................................... 241
11.3.5 Interrupt Request Batch-Read Register 4 Upper (IRPR4H) ......................................................... 242
11.3.6 Interrupt Request Batch-Read Register 4 Lower (IRPR4L) .......................................................... 243
11.4 Notes on Use ..................................................................................................................................... 244
CHAPTER 12 Delay Interrupt .......................................................................................... 245
12.1 Overview ............................................................................................................................................ 246
12.2 Configuration ..................................................................................................................................... 247
12.3 Registers ............................................................................................................................................ 248
12.3.1 Delayed Interrupt Control Register (DICR) ................................................................................... 249
12.4 An Explanation of Operations and Setting Procedure Examples ....................................................... 250
12.4.1 Explanation of Delay Interrupt Operations .................................................................................... 250
12.5 Notes on Use ..................................................................................................................................... 251
CHAPTER 13 External Bus Interface ............................................................................. 253
13.1 Overview ............................................................................................................................................ 254
13.2 Configuration ..................................................................................................................................... 257
13.3 Pins .................................................................................................................................................... 259
13.4 Registers ............................................................................................................................................ 261
13.4.1 Area Setting Registers (ASR0 to ASR3) ....................................................................................... 262
13.4.2 Area Configuration Registers (ACR0 to ACR3) ............................................................................ 265
13.4.3 Area Wait Registers (AWR0 to AWR3) ......................................................................................... 268
13.5 Protocols ............................................................................................................................................ 277
13.5.1 Address Data Split Bus Protocol ................................................................................................... 277
13.5.2 Address Data Multiplex Bus Protocol ........................................................................................... 283
13.6 Timing Settings .................................................................................................................................. 289
13.6.1 Read Access Automatic Wait ....................................................................................................... 290
13.6.2 Write Access Automatic Wait ........................................................................................................ 293
13.6.3 Read Access Idle Cycle ................................................................................................................ 296
13.6.4 Write Recovery Cycle ................................................................................................................... 299
13.6.5 Read Access Setup Cycle ............................................................................................................ 302
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13.6.6 Read Access Hold Cycle ...............................................................................................................304
13.6.7 Write Access Setup Cycle .............................................................................................................307
13.6.8 Write Access Hold Cycle ...............................................................................................................309
13.6.9 Chip Select Delay Cycle ................................................................................................................311
13.6.10 Address Output Extension Cycle ...................................................................................................314
13.6.11 Address Strobe Output Extension Cycle .......................................................................................316
13.7 Access Cycle Extension Using the RDY Pin ......................................................................................319
13.8 Number of Access Cycles ...................................................................................................................322
13.9 Address Information and Address Alignment .....................................................................................324
13.9.1 Address Information ......................................................................................................................324
13.9.2 Address Alignment ........................................................................................................................325
13.10 Data Alignment ...................................................................................................................................326
13.10.1 Big Endian .....................................................................................................................................328
13.10.2 Little Endian ...................................................................................................................................332
13.11 CS Area Setting Procedure ................................................................................................................336
CHAPTER 14 I/O Ports .....................................................................................................341
14.1 Overview .............................................................................................................................................342
14.2 Configuration ......................................................................................................................................344
14.3 Pins .....................................................................................................................................................348
14.4 Registers .............................................................................................................................................349
14.4.1 Port Data Direction Registers (DDR0 to DDRK) ............................................................................351
14.4.2 Port Function Registers (PFR0 to PFRH) ......................................................................................354
14.4.3 Extended Port Function Registers (EPFR0 to EPFR35) ...............................................................357
14.4.4 Port Data Registers (PDR0 to PDRK) ...........................................................................................376
14.4.5 Pull-up Resistor Control Registers (PCR0 to PCR8) .....................................................................378
14.4.6 A/D Channel Enable Register (ADCHE) ........................................................................................379
14.4.7 N-ch Open Drain Control Register (NDE0, NDE1) ........................................................................380
14.4.8 External Bus Address Select Register (EXBS) ..............................................................................382
14.4.9 FR Identification Data Register (FRID) ..........................................................................................383
14.5 Notes on Use ......................................................................................................................................384
CHAPTER 15 External Interrupt Controllers ..................................................................387
15.1 Overview .............................................................................................................................................388
15.2 Configuration ......................................................................................................................................389
15.3 Pins .....................................................................................................................................................391
15.4 Registers .............................................................................................................................................392
15.4.1 External Interrupt Request Level Registers (ELVR0, ELVR2) .......................................................393
15.4.2 External Interrupt Request Registers (EIRR0, EIRR2) ..................................................................395
15.4.3 Enable Interrupt Request Registers (ENIR0, ENIR2) ....................................................................397
15.5 Explanation of Operations and Setting Procedure Examples .............................................................398
15.5.1 Operations of the External Interrupt Controllers ............................................................................398
15.5.2 Return from Standby Mode ...........................................................................................................401
15.5.3 Return from Sleep Mode ...............................................................................................................403
CHAPTER 16 Watchdog Timer ........................................................................................405
16.1 Overview .............................................................................................................................................406
16.2 Configuration ......................................................................................................................................407
16.3 Registers .............................................................................................................................................409
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16.3.1 Watchdog Timer Control Register 0 (WDTCR0) ........................................................................... 410
16.3.2 Watchdog Timer Clear Pattern Register 0 (WDTCPR0) ............................................................... 413
16.4 Explanation of Operations and Setting Procedure Examples ............................................................ 414
16.4.1 Operations of the Watchdog Timer ............................................................................................... 414
CHAPTER 17 Watch Counter .......................................................................................... 417
17.1 Overview ............................................................................................................................................ 418
17.2 Configuration ..................................................................................................................................... 419
17.3 Registers ............................................................................................................................................ 421
17.3.1 Watch Counter Reload Register (WCRL) ..................................................................................... 422
17.3.2 Watch Counter Control Register (WCCR) .................................................................................... 423
17.3.3 Watch Counter Read Register (WCRD) ....................................................................................... 426
17.4 Interrupts ............................................................................................................................................ 427
17.5 Explanation of Operations and Setting Procedure Examples ............................................................ 428
17.5.1 Operations of the Watch Counter ................................................................................................. 428
17.6 Notes on Use ..................................................................................................................................... 430
CHAPTER 18 32-bit Free-Run Timer .............................................................................. 431
18.1 Overview ............................................................................................................................................ 432
18.2 Configuration ..................................................................................................................................... 433
18.3 Pins .................................................................................................................................................... 437
18.4 Registers ............................................................................................................................................ 438
18.4.1 Free-Run Timer Select Register (FRTSEL) .................................................................................. 439
18.4.2 Compare Clear Register (CPCLR0, CPCLR1) ............................................................................. 440
18.4.3 Timer Data Register (TCDT0, TCDT1) ......................................................................................... 441
18.4.4 Timer Status Control Register Upper/Lower (TCCSH0/TCCSL0, TCCSH1/TCCSL1) ................. 442
18.5 Interrupts ............................................................................................................................................ 446
18.6 An Explanation of Operations and Setting Procedure Examples ....................................................... 447
18.6.1 Operation When an Internal Clock (Peripheral Clock) Is Selected ............................................... 448
18.6.2 Operation When an External Clock Is Selected ............................................................................ 449
CHAPTER 19 32-bit Input Capture ................................................................................. 451
19.1 Overview ............................................................................................................................................ 452
19.2 Configuration ..................................................................................................................................... 453
19.3 Pins .................................................................................................................................................... 455
19.4 Registers ............................................................................................................................................ 456
19.4.1 Input Capture Status Control Registers (ICS01 to ICS67) ............................................................ 457
19.4.2 Input Capture Data Register (IPCP0 to IPCP7) ............................................................................ 461
19.5 Interrupts ............................................................................................................................................ 462
19.6 An Explanation of Operations and Setting Procedure Examples ....................................................... 463
19.6.1 Explanation of 32-bit Input Capture Operation ............................................................................. 463
CHAPTER 20 32-bit Output Compare ............................................................................ 467
20.1 Overview ............................................................................................................................................ 468
20.2 Configuration ..................................................................................................................................... 469
20.3 Pins .................................................................................................................................................... 471
20.4 Registers ............................................................................................................................................ 472
20.4.1 Output Compare Register (OCCP0 to OCCP7) ............................................................................ 473
20.4.2 Compare Control Register Upper (OCSH1, OCSH3, OCSH5, OCSH7) ...................................... 474
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20.4.3 Compare Control Register Lower (OCSL0, OCSL2, OCSL4, OCSL6) .........................................478
20.5 Interrupts ............................................................................................................................................481
20.6 An Explanation of Operations and Setting Procedure Examples .......................................................482
20.6.1 When the 2 Channels Are Used Independently of Each Other .....................................................482
20.6.2 When the 2 Channels Are Used as a Pair .....................................................................................484
CHAPTER 21 16-bit Reload Timer ..................................................................................487
21.1 Overview .............................................................................................................................................488
21.2 Configuration ......................................................................................................................................489
21.3 Pins .....................................................................................................................................................491
21.4 Registers .............................................................................................................................................492
21.4.1 Timer Control Status Register (TMCSR0 to TMCSR2) .................................................................493
21.4.2 16-bit Timer Reload Register A/B (TMRLRA0 to TMRLRA2/TMRLRB0 to TMRLRB2) ................500
21.4.3 16-bit Timer Register (TMR0 to TMR2) .........................................................................................502
21.5 Interrupts ............................................................................................................................................503
21.6 An Explanation of Operations and Setting Procedure Examples .......................................................504
21.6.1 Operation in Interval Timer Mode ..................................................................................................506
21.6.2 Operations in Event Counter Mode ...............................................................................................524
21.6.3 Operation in Cascade Mode ..........................................................................................................539
21.7 Notes on Use ......................................................................................................................................541
CHAPTER 22 Base Timer I/O Select Function ...............................................................543
22.1 Overview .............................................................................................................................................544
22.2 Configuration ......................................................................................................................................545
22.3 Pins .....................................................................................................................................................546
22.4 Registers .............................................................................................................................................548
22.4.1 Base Timer IO Select Register for Ch.0/1/2/3 (BTSEL0123) ........................................................549
22.4.2 Base Timer Same Time Soft Start Register (BTSSSR) .................................................................552
22.5 I/O Mode .............................................................................................................................................554
22.5.1 I/O Mode 0 (16-bit Timer Standard Mode) .....................................................................................554
22.5.2 I/O Mode 1 (Timer Full Mode) .......................................................................................................556
22.5.3 I/O Mode 2 (External Trigger Shared Mode) .................................................................................558
22.5.4 I/O Mode 3 (Other Channel Trigger Shared Mode) .......................................................................560
22.5.5 Operations in I/O Mode 4 (Timer Activation/Stop Mode) ...............................................................562
22.5.6 Operations in I/O Mode 5 (Same Time Software Activation Mode) ...............................................565
22.5.7 Operations in I/O Mode 6 (Software Activation Timer Activation/Stop Mode) ...............................567
22.5.8 Operations in I/O Mode 7 (Timer Activation Mode) .......................................................................569
22.5.9 Operations in I/O Mode 8 (Other Channel Trigger Shared Timer Activation/Stop Mode) .............571
CHAPTER 23 Base Timer ................................................................................................573
23.1 Overview of the Base Timer ...............................................................................................................574
23.2 Block Diagrams of the Base Timer .....................................................................................................576
23.3 Base Timer's Registers .......................................................................................................................584
23.4 Operations of the Base Timer .............................................................................................................588
23.5 32-bit Mode Operations ......................................................................................................................590
23.6 Notes of Using the Base Timer ...........................................................................................................592
23.7 Base Timer Interrupts .........................................................................................................................594
23.8 Base Timer Description by Function Mode .........................................................................................595
23.8.1 PWM Function ...............................................................................................................................596
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23.8.2 PPG Function ............................................................................................................................... 610
23.8.3 Reload Timer Function ................................................................................................................. 625
23.8.4 PWC Function ............................................................................................................................... 637
CHAPTER 24 Up/Down Counter ..................................................................................... 653
24.1 Overview ............................................................................................................................................ 654
24.2 Configuration ..................................................................................................................................... 656
24.3 Pins .................................................................................................................................................... 658
24.4 Registers ............................................................................................................................................ 659
24.4.1 Reload Compare Register (RCR1) ............................................................................................... 660
24.4.2 Up-Down Count Register (UDCR1) .............................................................................................. 662
24.4.3 Counter Control Register (CCR1) ................................................................................................. 663
24.4.4 Counter Status Register (CSR1) .................................................................................................. 668
24.5 Interrupt ............................................................................................................................................. 671
24.6 An Explanation of Operations and Setting Procedure Examples ....................................................... 673
24.6.1 Operation in Timer Mode .............................................................................................................. 677
24.6.2 Operations in Up/Down Count Mode ............................................................................................ 679
24.6.3 Operations in Phase Difference Count Mode (Multiplied by 2) ..................................................... 682
24.6.4 Operations in Phase Difference Count Mode (Multiplied by 4) ..................................................... 684
CHAPTER 25 10-Bit A/D Converter ................................................................................ 687
25.1 Overview ............................................................................................................................................ 688
25.2 Configuration ..................................................................................................................................... 689
25.3 Pins .................................................................................................................................................... 691
25.4 Registers ............................................................................................................................................ 693
25.4.1 A/DC Control Registers (ADCR0) ................................................................................................. 694
25.4.2 A/DC Status Registers (ADSR0) .................................................................................................. 697
25.4.3 Scan Conversion Control Registers (SCCR0) .............................................................................. 701
25.4.4 Scan Conversion FIFO Number Setting Register (SFNS0) .......................................................... 705
25.4.5 Scan Conversion FIFO Data Registers (SCFD0) ......................................................................... 707
25.4.6 Scan Conversion Input Select Registers (SCIS20 to SCIS00) ..................................................... 711
25.4.7 Priority Conversion Control Registers (PCCR0) ........................................................................... 713
25.4.8 Priority Conversion FIFO Number Setting Registers (PFNS0) ..................................................... 717
25.4.9 Priority Conversion FIFO Data Registers (PCFD0) ...................................................................... 719
25.4.10 Priority Conversion Input Select Registers (PCIS0) ..................................................................... 723
25.4.11 A/D Comparison Data Setting Registers (CMPD0) ...................................................................... 726
25.4.12 A/D Comparison Control Registers (CMPCR0) ............................................................................ 727
25.4.13 Sampling Time Setting Registers (ADST00, ADST10) ................................................................. 731
25.4.14 Sampling Time Select Registers (ADSS20 to ADSS00) ............................................................... 734
25.4.15 Compare Time Setting Registers (ADCT0) .................................................................................. 736
25.5 Interrupts ............................................................................................................................................ 738
25.6 Explanation of Operations and Setting Procedure Examples ............................................................ 740
25.6.1 Operation of A/D Scan Conversion ............................................................................................... 750
25.6.2 Operation of A/D Priority Conversion ............................................................................................ 753
25.6.3 FIFO Operations ........................................................................................................................... 756
25.6.4 Activating the DMA Controller (DMAC) ......................................................................................... 762
CHAPTER 26 Multi-function Serial Interface ................................................................. 765
26.1 Characteristics of Multi-function Serial Interface ................................................................................ 766
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26.2 UART (Asynchronous Serial Interface) ...............................................................................................767
26.3 Overview of UART (Asynchronous Serial Interface) ...........................................................................768
26.4 Registers of UART (Asynchronous Serial Interface) ..........................................................................769
26.4.1 Serial Control Register (SCR) .......................................................................................................771
26.4.2 Serial Mode Register (SMR) ..........................................................................................................773
26.4.3 Serial Status Register (SSR) .........................................................................................................776
26.4.4 Extended Serial Control Register (ESCR) .....................................................................................779
26.4.5 Reception Data Register / Transmission Data Register (RDR/TDR) ............................................781
26.4.6 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ....................................................................783
26.5 Interrupts of UART ..............................................................................................................................785
26.5.1 Occurrence of Reception Interrupts and Flag Set Timing .............................................................786
26.5.2 Occurrence of Transmission Interrupts and Flag Set Timing ........................................................787
26.6 Operation of UART .............................................................................................................................788
26.7 Dedicated Baud Rate Generator ........................................................................................................792
26.7.1 Setting Baud Rate .........................................................................................................................793
26.8 Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode) ...............797
26.9 Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multi-processor Mode) ..798
26.10 Notes on UART Mode .........................................................................................................................801
26.11 CSIO (Clock Synchronous Serial Interface) .......................................................................................802
26.12 Overview of CSIO (Clock Synchronous Serial Interface) ...................................................................803
26.13 Registers of CSIO (Clock Synchronous Serial Interface) ...................................................................804
26.13.1 Serial Control Register (SCR) .......................................................................................................806
26.13.2 Serial Mode Register (SMR) ..........................................................................................................809
26.13.3 Serial Status Register (SSR) .........................................................................................................812
26.13.4 Extended Serial Control Register (ESCR) .....................................................................................814
26.13.5 Reception Data Register / Transmission Data Register (RDR/TDR) ............................................816
26.13.6 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ....................................................................818
26.14 Interrupts of CSIO (Clock Synchronous Serial Interface) ...................................................................819
26.14.1 Occurrence of Reception Interrupts and Flag Set Timing .............................................................820
26.14.2 Occurrence of Transmission Interrupts and Flag Set Timing ........................................................821
26.15 Operation of CSIO (Clock Synchronous Serial Interface) ...................................................................822
26.16 Dedicated Baud Rate Generator ........................................................................................................839
26.16.1 Setting Baud Rate .........................................................................................................................840
26.17 Setup Procedure and Program Flow for CSIO (Clock Synchronous Serial Interface) ........................843
26.18 Notes on CSIO Mode ..........................................................................................................................844
26.19 I2C Interface .......................................................................................................................................845
26.20 Overview of I2C Interface ....................................................................................................................846
26.21 Registers of I2C Interface ...................................................................................................................847
26.21.1 I2C Bus Control Register (IBCR) ...................................................................................................849
26.21.2 Serial Mode Register (SMR) ..........................................................................................................854
26.21.3 I2C Bus Status Register (IBSR) .....................................................................................................856
26.21.4 Serial Status Register (SSR) .........................................................................................................860
26.21.5 Reception Data Register / Transmission Data Register (RDR/TDR) ............................................862
26.21.6 7-bit Slave Address Mask Register (ISMK) ...................................................................................864
26.21.7 7-bit Slave Address Register (ISBA) .............................................................................................865
26.21.8 Baud Rate Generator Registers 1, 0 (BGR1, BGR0) ....................................................................866
26.22 Interrupts of I2C Interface ...................................................................................................................867
26.22.1 Operation of I2C Interface Communication ....................................................................................869
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26.22.2 Master Mode ................................................................................................................................. 870
26.22.3 Slave Mode ................................................................................................................................... 882
26.22.4 Bus Error ....................................................................................................................................... 885
26.23 Dedicated Baud Rate Generator ....................................................................................................... 886
26.24 Notes on I2C Mode ............................................................................................................................ 888
CHAPTER 27 USB Clock Generating Part ..................................................................... 891
27.1 Overview ............................................................................................................................................ 892
27.2 Configuration ..................................................................................................................................... 893
27.3 Registers ............................................................................................................................................ 894
27.3.1 USB Clock Configuration Register (UCCR) .................................................................................. 895
27.4 Explanation of Operations and Setting Procedure Examples ............................................................ 897
CHAPTER 28 DMA Transfer Request Selector ............................................................. 899
28.1 Overview ............................................................................................................................................ 900
28.2 Configuration ..................................................................................................................................... 901
28.3 Registers ............................................................................................................................................ 902
28.3.1 DREQ Select Register (DREQSEL) ............................................................................................. 903
CHAPTER 29 USB Function ............................................................................................ 905
29.1 Overview ............................................................................................................................................ 906
29.2 Configuration ..................................................................................................................................... 907
29.3 Registers ............................................................................................................................................ 908
29.3.1 USB Selection Register (USBSEL) ............................................................................................... 910
29.3.2 USB Enable Register (USBEN) .................................................................................................... 911
29.3.3 UDC Control Register (UDCC) ..................................................................................................... 913
29.3.4 EP0 Control Register (EP0C) ....................................................................................................... 917
29.3.5 EP1 to EP3 Control Registers (EP1C to EP3C) ........................................................................... 920
29.3.6 Time Stamp Register (TMSP) ....................................................................................................... 925
29.3.7 UDC Status Register (UDCS) ....................................................................................................... 926
29.3.8 UDC Enable Interrupt Request Register (UDCIE) ........................................................................ 930
29.3.9 EP0I Status Register (EP0IS) ....................................................................................................... 932
29.3.10 EP0O Status Register (EP0OS) ................................................................................................... 934
29.3.11 EP1 to EP3 Status Registers (EP1S to EP3S) ............................................................................. 937
29.3.12 EP0 to EP3 Data Registers (EP0DTH to EP3DTH/EP0DTL to EP3DTL) .................................... 941
29.4 Explanation of Operations and Setting Procedure Examples ............................................................ 945
29.4.1 Detection of Connections and Disconnections ............................................................................. 948
29.4.2 Register Operation for a Command Response ............................................................................. 951
29.4.3 STALL Response and Release .................................................................................................... 953
29.4.4 Suspend Function ......................................................................................................................... 959
29.4.5 Wakeup Function .......................................................................................................................... 960
29.4.6 DMA Transfer Function ................................................................................................................. 962
29.4.7 NULL Transfer Function ............................................................................................................... 968
29.4.8 Software Control Examples .......................................................................................................... 969
CHAPTER 30 USB HOST ................................................................................................. 977
30.1 Overview ............................................................................................................................................ 978
30.2 Configuration ..................................................................................................................................... 980
30.3 Registers ............................................................................................................................................ 982
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30.3.1 Host Control Register 0, 1 (HCNT) ................................................................................................984
30.3.2 Host Interrupt Register (HIRQ) ......................................................................................................989
30.3.3 Host Error Status Register (HERR) ...............................................................................................993
30.3.4 Host Status Register (HSTATE) ....................................................................................................997
30.3.5 SOF Interrupt FRAME comparison register (HFCOMP) ..............................................................1000
30.3.6 Retry Timer Setting Register (HRTIMER) ...................................................................................1001
30.3.7 Host Address Register (HADR) ...................................................................................................1003
30.3.8 EOF Setting Register (HEOF) .....................................................................................................1004
30.3.9 FRAME Setting Register (HFRAME) ...........................................................................................1006
30.3.10 Host Token Endpoint Register (HTOKEN) ..................................................................................1008
30.4 Explanation of Operations and Setting Procedure Examples ...........................................................1010
30.4.1 Connecting a USB Device ...........................................................................................................1010
30.4.2 Resetting the USB Bus ................................................................................................................1012
30.4.3 Token Packets .............................................................................................................................1013
30.4.4 Data Packets ...............................................................................................................................1014
30.4.5 Operation of a Handshake Packet ...............................................................................................1015
30.4.6 Retry Function .............................................................................................................................1015
30.4.7 SOF Interrupts .............................................................................................................................1017
30.4.8 Error Status .................................................................................................................................1019
30.4.9 Packet End ..................................................................................................................................1020
30.4.10 Suspend and Resume .................................................................................................................1021
30.4.11 Disconnecting a USB Device .......................................................................................................1023
30.4.12 Flowcharts for tokens in operation with USB HOST ....................................................................1024
CHAPTER 31 DMA Controller (DMAC) .........................................................................1029
31.1 Overview ...........................................................................................................................................1030
31.2 Configuration ....................................................................................................................................1033
31.3 Registers ...........................................................................................................................................1035
31.3.1 DMA Control Register (DMACR) .................................................................................................1036
31.3.2 DMA Source Address Registers (DSAR0 to DSAR3) .................................................................1039
31.3.3 DMA Destination Address Registers (DDAR0 to DDAR3) ..........................................................1040
31.3.4 DMA Transfer Count Registers (DTCR0 to DTCR3) ...................................................................1041
31.3.5 DMA Channel Control Registers (DCCR0 to DCCR3) ................................................................1042
31.3.6 DMA Channel Status Registers (DCSR0 to DCSR3) ..................................................................1052
31.3.7 DMA-Halt by Interrupt Level Register (DILVR) ............................................................................1055
31.4 Interrupts ..........................................................................................................................................1057
31.5 An Explanation of Operations and Setting Procedure Examples .....................................................1058
31.5.1 Transfer Settings .........................................................................................................................1058
31.5.2 Transfer Operations .....................................................................................................................1061
31.5.3 Transfer Suspension ...................................................................................................................1071
31.5.4 Operation at the End of Transfer .................................................................................................1073
31.5.5 Post-transfer Operation ...............................................................................................................1074
31.5.6 DMA Transfer Halt .......................................................................................................................1078
CHAPTER 32 Select Function for DMA Transfer Request Generation/Clear by a
Peripheral Function ................................................................................1079
32.1 Overview ...........................................................................................................................................1080
32.2 Configuration ....................................................................................................................................1081
32.3 Registers ...........................................................................................................................................1083
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32.3.1 IO-Data Request Registers (IORR0 to IORR3) .......................................................................... 1085
32.3.2 Select Register 0 for DMA Transfer Request Clear by a Peripheral Function (ICSEL0) ............ 1089
32.3.3 Select Register 2 for DMA Transfer Request Clear by a Peripheral Function (ICSEL2) ............ 1091
32.3.4 Select Register 4 for DMA Transfer Request Clear by a Peripheral Function (ICSEL4) ............ 1093
32.3.5 Select Register 6 for DMA Transfer Request Clear by a Peripheral Function (ICSEL6) ............ 1095
32.3.6 Select Register 7 for DMA Transfer Request Clear by a Peripheral Function (ICSEL7) ............ 1097
32.3.7 Select Register 8 for DMA Transfer Request Clear by a Peripheral Function (ICSEL8) ............ 1099
32.3.8 Select Register 9 for DMA Transfer Request Clear by a Peripheral Function (ICSEL9) ............ 1101
32.3.9 Select Register 10 for DMA Transfer Request Clear by a Peripheral Function (ICSEL10) ........ 1103
32.4 An Explanation of Operations and Setting Procedure Examples ..................................................... 1107
32.4.1 Operations upon a DMA Transfer ............................................................................................... 1107
CHAPTER 33 Control of Built-in Program Memory .................................................... 1109
33.1 Overview of Built-in Program Memory Controller ............................................................................. 1110
33.2 Register for Built-in Program Memory Controller ............................................................................. 1111
33.2.1 FLASH Control Register (FCTLR) .............................................................................................. 1112
CHAPTER 34 Flash Memory ......................................................................................... 1115
34.1 Overview of Flash Memory .............................................................................................................. 1116
34.2 Flash Memory Configuration ............................................................................................................ 1117
34.3 Flash Memory Registers .................................................................................................................. 1119
34.3.1 FLASH Status Register (FSTR) .................................................................................................. 1120
34.3.2 FLASH Control Register (FCTLR) .............................................................................................. 1121
34.4 Flash Memory Access Mode ........................................................................................................... 1122
34.5 Automatic Algorithm ......................................................................................................................... 1123
34.5.1 Command Sequence .................................................................................................................. 1123
34.5.2 Execution State of Automatic Algorithm ..................................................................................... 1126
34.6 Explanation of Flash Memory Operation ......................................................................................... 1131
34.6.1 Reset Operation .......................................................................................................................... 1131
34.6.2 Data Write Operation .................................................................................................................. 1132
34.6.3 Chip Erase .................................................................................................................................. 1135
34.6.4 Sector Erase ............................................................................................................................... 1135
34.6.5 Sector Erase Suspending ........................................................................................................... 1137
34.6.6 Sector Erase Restarting .............................................................................................................. 1139
34.7 Restrictions on Data Polling Flag (DQ7) and How to Avoid Problems ............................................. 1140
34.8 Notes on Using Flash Memory ........................................................................................................ 1143
CHAPTER 35 Wild Register .......................................................................................... 1145
35.1 Overview of Wild Register ............................................................................................................... 1146
35.2 Configuration of Wild Register ......................................................................................................... 1147
35.3 Registers of Wild Register ............................................................................................................... 1148
35.3.1 Wild Register Address Register (WRAR00 to WRAR15) ........................................................... 1150
35.3.2 Wild Register Data Register (WRDR00 to WRDR15) ................................................................. 1151
35.3.3 Wild Register Enable Register (WREN) ..................................................................................... 1152
35.4 Explanation of Operations and Setting Procedure Examples of the Wild Register .......................... 1153
35.4.1 Wild Register Operation .............................................................................................................. 1153
35.5 Notes on Using the Wild Register .................................................................................................... 1154
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CHAPTER 36 Serial Programming Connection ...........................................................1157
36.1 Fujitsu Semiconductor Serial Programmer .......................................................................................1158
36.1.1 Pins Used ....................................................................................................................................1165
CHAPTER 37 Handling the Device ...............................................................................1167
37.1 Notes on Handling the Device ..........................................................................................................1168
APPENDIX A I/O Map .....................................................................................................1176
APPENDIX B List of Registers ......................................................................................1194
APPENDIX C Interrupt Vectors .....................................................................................1211
APPENDIX D Pin State in Each CPU State ..................................................................1215
APPENDIX E
E.1
E.2
E.3
Lists of Instructions ...............................................................................1222
Instruction List ...................................................................................................................................1222
Instruction Tables .............................................................................................................................1226
List of Instructions That Can Be Specified for Delay Slots ...............................................................1239
Index of Pins .....................................................................................................................1241
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Main changes in this edition
Page
-
Changes (For details, refer to main body.)
First edition
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xxii
CHAPTER 1 Overview
This chapter explains the features and basic specifications
of the MB91665 series.
1.1
1.2
1.3
1.4
CM71-10158-1E
MB91665 Series Overview
MB91665 Series Product Configuration
MB91665 Series Block Diagram
Package Dimensions
FUJITSU SEMICONDUCTOR LIMITED
1
CHAPTER 1 Overview
1.1
1.1
MB91665 Series
MB91665 Series Overview
The MB91665 series, a microcontroller that uses 32-bit RISC CPUs, has built-in peripheral control
functions for embedded control which requires high-performance/high-speed CPU processing.
This series is based on the FR80 family CPUs and is implemented in a single-chip.
■ FR80 family CPUs
•
32-bit RISC, load/store architecture, 5-stage pipeline
•
16 general-purpose 32-bit registers
•
16-bit fixed-length instructions (basic instructions), 1 instruction per cycle
•
Instructions suitable for embedded applications
-
Instructions for memory-to-memory transfer, bit processing, barrel shift, etc.
-
High-level language support instructions
-
Bit search instruction
Function entry/exit instructions and multi-load/store instructions for register contents
1 detection, 0 detection, and transition point detection
-
Branch instruction with delay slot(s)
-
Register interlock function
Reduced overhead time in branch executions
Efficient assembly language coding
-
Support for multipliers at the built-in function/instruction level
Signed 32-bit multiplication - 5 cycles
Signed 16-bit multiplication - 3 cycles
-
Interrupt (Save PC and PS)
High-speed response at a minimum of 6 cycles, 16 levels of priority
•
2
-
Simultaneous access to a program and data enabled by Harvard architecture
-
The prefetch function for instructions using the 4-word instruction queue in the CPU
Basic instruction compatibility with the FR family CPUs
-
Addition of the bit search instruction
-
No resource instruction and coprocessor instruction provided
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CHAPTER 1 Overview
1.1
MB91665 Series
■ Maximum operating frequency
CPU
33 MHz
Peripheral
33 MHz
External bus
33 MHz
■ External bus interface
•
Maximum operating frequency: 33 MHz
•
MB91F669 (64 pins)
24 addresses, 8/16-bit data I/O (multiplex bus)
8 addresses, 8/16-bit data I/O (split bus)
•
MB91F668 (48 pins)*
16 addresses, 8-bit data I/O (multiplex bus)
No address, 8-bit data I/O (split bus)
*There are no RDY, SYSCLK, WR1, CS1, CS2, and CS3.
•
A programmable auto wait cycle for each area occurs.
■ DMA controller (DMAC)
•
Number of channels: 4
•
Address space: 32 bits (4 GB)
•
Transfer mode: Block transfer/Burst transfer/Demand transfer
•
Address update: Increment/Decrement/Fix (increment/decrement value fixed to 1, 2, or 4)
•
Transfer size: 8 bits, 16 bits, and 32 bits
•
Block size: 1 to 16
•
Transfer count: 1 to 65,535 times
•
Transfer request:
-
Request by software
-
Interrupt request of a built-in peripheral function (a shared interrupt request or external interrupt
request)
•
Reload function: Reloading of all channels can be specified.
•
Level of priority: Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ...), or round robin
•
Interrupt request: Occurrence of a normal end interrupt request, abnormal end interrupt request, or
transfer suspension interrupt request
CM71-10158-1E
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CHAPTER 1 Overview
1.1
MB91665 Series
■ Multifunction serial interface
•
Any of the following uses can be selected for each channel:
-
UART
-
CSIO
-
I2C
[Features of UART]
-
Full-duplex double buffer
-
Selection with or without parity supported
-
Built-in dedicated baud rate generator
-
External clock available as a serial clock
-
Various error detection functions available (parity errors, framing errors, and overrun errors)
[Features of CSIO]
-
Full-duplex double buffer
-
Built-in dedicated baud rate generator
-
Overrun error detection function available
[Features of I2C]
-
Standard mode (maximum: 100 kbps)/High-speed mode (maximum: 400 kbps) supported
-
5V tolerance supported for some channels
■ Interrupts
•
Total of 16 external interrupts (5V tolerance supported for some pins)
•
Interrupt from an internal peripheral function
•
Programmable setting of interrupt levels (16 levels)
•
Return from stop mode or sleep mode supported
■ A/D converter
4
•
MB91F669 (64 pins): 12 channels, 1 unit
•
MB91F668 (48 pins): 10 channels, 1 unit
•
10-bit resolution
•
Successive comparison type Conversion time: Approximately 1.2 μs (PCLK=33 MHz)
•
Priority A/D conversion available (2 levels)
•
Conversion mode (one shot conversion mode, scanning conversion mode)
•
Activation trigger (software/external trigger/base timer)
•
FIFO for storing conversion data available (scanning conversion: 16 levels; priority conversion: 4
levels)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 1 Overview
1.1
MB91665 Series
■ Base timer
•
•
•
•
•
Number of channels: 4 built-in channels
Any of the following uses can be selected for each channel:
- 16/32-bit reload timer
- 16-bit PWM timer
- 16/32-bit PWC timer
- 16-bit PPG timer
32-bit timer available by connecting 2 channels in cascade
Function for activating multiple channels simultaneously available
I/O select function available
■ 16-bit reload timer
•
•
•
Number of channels: 3 (including a channel for REALOS)
Interval timer function
Function for selecting count clock (Peripheral clock (PCLK) divided by a value ranging from 2 to 64)
■ Compare timer
•
•
•
32-bit input capture: 8 built-in channels
32-bit output compare: 8 built-in channels
32-bit free-run timer: 2 built-in channels
■ Other interval timers
•
•
•
Up/Down counter: 1 built-in channel
Watch counter: 1 built-in channel
Watchdog timer: 1 built-in channel
■ USB function/HOST
•
•
•
•
Number of channels: 1
USB2.0 Full-Speed supported
The USB function and USB HOST are the switch types (USB I/O multiplexed)
Support of DMA transfer
[USB Function]
•
•
Support of up to four endpoints
- Endpoint 0 is provided for the fixed use of control transfers
- Bulk or interrupt transfer can be selected for endpoint 1 to 3
Double buffer structure for endpoint 1 to 3
[USB HOST]
•
•
•
•
•
CM71-10158-1E
Support control transfer, bulk transfer, interrupt transfer, and isochronous transfer
Automatic detection of connection/disconnection of USB devices
Automatic processing of a handshake packet for IN/OUT token processing
Support of a maximum packet length of up to 256 bytes
Support for a wakeup function
FUJITSU SEMICONDUCTOR LIMITED
5
CHAPTER 1 Overview
1.1
MB91665 Series
■ Main timer
•
Number of channels: 1
•
Count of the oscillation stabilization wait time of the main clock (MCLK).
•
Count of the oscillation stabilization wait time of the PLL clock (PLLCLK).
•
Interval timer when the oscillation of the main clock (MCLK) is stable.
■ Sub timer
•
Number of channels: 1
•
Count of the oscillation stabilization wait time of the sub clock (SBCLK).
•
Interval timer when the oscillation of the sub clock (SBCLK) is stable.
■ Clock generation
•
Main clock (MCLK) oscillation
•
Sub clock (SBCLK) oscillation
•
PLL clock (PLLCLK) oscillation
■ Low-power dissipation mode
•
Stop mode
•
Watch mode
•
Sleep mode
•
Doze mode
•
Clock division function
■ Other features
•
I/O port
•
INIT pin available as a reset pin.
•
Watchdog timer reset and software reset available
•
Delay interrupt
•
Power supply
-
6
Single power supply (When USB not used: 2.7 V to 3.6 V, When USB used: 3.0 V to 3.6 V)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 1 Overview
1.2
MB91665 Series
1.2
MB91665 Series Product Configuration
This section explains the products in the MB91665 series.
Table 1.2-1 MB91665 series product configuration (1 / 2)
Part number
MB91F669
MB91F668
Parameter
Product type
Flash memory product
Built-in program
memory capacity
128 Kbytes
(Flash)
Built-in RAM capacity
16 Kbytes
External bus
interface
multi
Address: 24 bits
Data: 16/8 bits
Address: 16 bits
Data: 8 bits
split
Address: 8 bits
Data: 16/8 bits
No address
Data: 8 bits
DMA controller
(DMAC)
Base timer
Multifunction serial
interface
4 channels
4 channels
(Reload timer/ PWM/ PPG/ PWC modes can be switched)
4 channels (UART/ SPI/ I2C modes can be switched)
External interrupt
10-bit A/D converter
16
12 channels
(1 unit)
16-bit reload timer
3 channels
Compare timer
32-bit input capture: 8 channels
32-bit output compare: 8 channels
32-bit free-run timer: 2 channels
Up/Down counter
1 channel
Watch counter
1 channel
I/O port
USB function/HOST
50
34
1 channel (function/ host modes can be switched)
Main timer
1 channel
Sub timer
1 channel
Wild register
Debug function
CM71-10158-1E
10 channels
(1 unit)
16 channels
-
FUJITSU SEMICONDUCTOR LIMITED
7
CHAPTER 1 Overview
1.2
MB91665 Series
Table 1.2-1 MB91665 series product configuration (2 / 2)
Part number
MB91F669
MB91F668
Type: LQFP-64
Package code: FPT-64P-M24
Pin pitch: 0.5 mm
Size: 10 mm × 10 mm
Type: LQFP-48
Package code: FPT-48P-M26
Pin pitch: 0.5 mm
Size: 7 mm × 7 mm
Parameter
Package
8
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 1 Overview
1.3
MB91665 Series
1.3
MB91665 Series Block Diagram
Figure 1.3-1 is the block diagrams of the MB91665 series.
Figure 1.3-1 MB91665 series block diagram
Step-down regulator
FR80
CPU
Built-in program
memory
Flash memory
Cross bar
switch
RAM
On-chip bus
DMAC
4 channels
Peripheral bus
bridge
Watchdog timer
Interrupt controller
Delay interrupt
Port
External interrupt
16 channels
16 -bit peripheral bus
Clock control
32 -bit peripheral bus
External bus I/F
USB function/
HOST
Clock generation
USB clock
generation
Watch counter
16 -bit reload timer
3 channels
32-bit free-run timer
2channels
Base timer
4 channels
Up/down counter
1 channel
32-bit output compare
8 channels
A/D converter
12/10 channels (1 unit)*
Port
32-bit input capture
8 channels
Multi-function serial interface
4 channels
* MB91F669 (64 pins): 12 channels
MB91F668 (48 pins): 10 channels
Port
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
9
CHAPTER 1 Overview
1.4
1.4
MB91665 Series
Package Dimensions
The dimensions of the packages used for the MB91665 series are shown below.
Figure 1.4-1 Package dimensions (FPT-48P-M26)
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 mm × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0°~8°
LEAD No.
0.50(.020)
1
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F48040S-c-2-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
For the latest specifications of package dimensions, refer to the following URL.
http://edevice.fujitsu.com/package/en-search/
10
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 1 Overview
1.4
MB91665 Series
Figure 1.4-2 Package dimensions (FPT-64P-M24)
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 mm × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
Details of "A" part
*10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
0.15(.006)
MAX
0.40(.016)
MAX
32
0.08(.003)
Details of "B" part
11.00(.433)
NOM.
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
"A"
64
LEAD No.
1
0.20±0.05
(.008±.002)
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-1c(D)-1-3
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
"B"
16
0.50(.020)
C
0~8°
17
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
For the latest specifications of package dimensions, refer to the following URL.
http://edevice.fujitsu.com/package/en-search/
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
11
CHAPTER 1 Overview
1.4
12
MB91665 Series
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
This chapter explains the pins and multiplexed pin settings
of the MB91665 series.
2.1
2.2
2.3
2.4
CM71-10158-1E
Pin Assignment Diagram
Pin Functions
I/O Circuit Types
Setting Method for Pins
FUJITSU SEMICONDUCTOR LIMITED
13
CHAPTER 2 Pins of the MB91665 Series
2.1
2.1
MB91665 Series
Pin Assignment Diagram
2 types of package are available for the MB91665 series.
■ LQFP-64 (MB91F669)
Figure 2.1-1 Pin assignment diagram in the LQFP-64 series
P10/D08/SOUT2/INT0 (5V tolerance,OD)
P61/SYSCLK/TIOB1_1/SIN2_1
P60/RDY/TIOA1_1/SOUT2_1
P83/AN11/IN3_1
P82/AN10/IN2_1
P81/AN9/IN1_1/TMI1_1
P80/AN8/IN0_1/TMI0_1
P77/AN7/SCK0/TMI2/OUT7_1/INT23
P76/AN6/SIN0/TMI1/OUT6_1/INT22
P75/AN5/SOUT0/TMI0/OUT5_1/INT21
P74/AN4/TMO2/OUT4_1/INT20
P73/AN3/TMO1/OUT3_1/INT19
P72/AN2/TMO0/OUT2_1/INT18
P71/AN1/OUT1_1/INT17
P70/AN0/OUT0_1/INT16
AVcc
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
P11/D09/SIN2/INT1 (5V tolerance)
1
48
AVss
P12/D10/SCK2/INT2 (5V tolerance,OD)
2
47
P57/WR1/TIOB3_1/TMI2_1
P13/D11/INT3
3
46
P56/WR0/ZIN1_1/FRCK0/SCK6
P14/D12/AIN1/INT4/OUT4
4
45
P55/RD/BIN1_1/ADTRG0/SIN6
P15/D13/BIN1/INT5/OUT5
5
44
P54/AS/AIN1_1/SOUT6
P16/D14/ZIN1/INT6/OUT6
6
43
P53/CS3/FRCK1/TIOA3_1/SCK1_1
P17/D15/INT7/OUT7
7
42
P52/CS2/TIOB2_1/SIN1_1
PH3/INT3_1 (5V tolerance)
8
41
P51/CS1/TIOA2_1/SOUT1_1
Vcc
9
40
P50/CS0/TMO0_1
UDM
10
39
P07/D07/TIOB3/IN7
UDP
11
38
P06/D06/TIOA3/SCK1/IN6 (5V tolerance,OD)
Vss
12
37
P05/D05/TIOB2/SIN1/IN5 (5V tolerance)
P20/A00/TMO1_1/A16 (5V tolerance,OD)
13
36
P04/D04/TIOA2/SOUT1/IN4 (5V tolerance,OD)
LQFP-64
21
22
23
24
25
26
27
28
29
30
31
32
PH2/SCK2_1/INT2_1 (5V tolerance)
P00/D00/TIOA0/SOUT0_1/IN0 (5V tolerance,OD)
P01/D01/TIOB0/SIN0_1/IN1
INIT
X0A/PK1
X1A/PK0
C
MD1
MD0
X0
X1
Vss
Vcc
20
33
P27/A07/OUT3/A23 (5V tolerance,OD)
16
19
P23/A03/TIOB0_1/A19 (5V tolerance)
P26/A06/OUT2/A22 (5V tolerance,OD)
P02/D02/TIOA1/SCK0_1/IN2 (5V tolerance,OD)
18
P03/D03/TIOB1/IN3
34
17
35
15
P25/A05/OUT1/A21 (5V tolerance,OD)
14
P24/A04/OUT0/A20 (5V tolerance,OD)
P21/A01/TMO2_1/A17 (5V tolerance,OD)
P22/A02/TIOA0_1/A18 (5V tolerance,OD)
* Explanation of ( )
5V tolerance: 5V tolerant pin
OD: Open drain control pin
(FPT-64P-M24)
Note : The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the port number.
For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port
function register (EPFR) to select the pin.
14
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.1
MB91665 Series
■ LQFP-48 (MB91F668)
Figure 2.1-2 Pin assignment diagram in the LQFP-48 series
P10/D08/SOUT2/INT0 (5V tolerance,OD)
P81/AN9/IN1_1/TMI1_1
P80/AN8/IN0_1/TMI0_1
P77/AN7/SCK0/TMI2/OUT7_1/INT23
P76/AN6/SIN0/TMI1/OUT6_1/INT22
P75/AN5/SOUT0/TMI0/OUT5_1/INT21
P74/AN4/TMO2/OUT4_1/INT20
P73/AN3/TMO1/OUT3_1/INT19
P72/AN2/TMO0/OUT2_1/INT18
P71/AN1/OUT1_1/INT17
P70/AN0/OUT0_1/INT16
AVcc
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
P11/D09/SIN2/INT1 (5V tolerance)
1
36
AVss
P12/D10/SCK2/INT2 (5V tolerance,OD)
2
35
P56/WR0/ZIN1_1/FRCK0/SCK6
P13/D11/INT3
3
34
P55/RD/BIN1_1/ADTRG0/SIN6
P14/D12/AIN1/INT4/OUT4
4
33
P54/AS/AIN1_1/SOUT6
P15/D13/BIN1/INT5/OUT5
5
P16/D14/ZIN1/INT6/OUT6
6
LQFP-48
32
P50/CS0/TMO0_1
31
P07/D07/TIOB3/IN7
30
P06/D06/TIOA3/SCK1/IN6 (5V tolerance,OD)
20
21
22
23
24
MD0
X0
X1
Vss
Vcc
MD1
25
19
12
C
P02/D02/TIOA1/SCK0_1/IN2 (5V tolerance,OD)
Vss
18
P03/D03/TIOB1/IN3
26
X1A/PK0
27
11
17
10
UDP
X0A/PK1
UDM
16
P04/D04/TIOA2/SOUT1/IN4 (5V tolerance,OD)
INIT
28
15
9
P01/D01/TIOB0/SIN0_1/IN1
P05/D05/TIOB2/SIN1/IN5 (5V tolerance)
Vcc
14
29
13
8
PH2/SCK2_1/INT2_1 (5V tolerance)
7
P00/D00/TIOA0/SOUT0_1/IN0 (5V tolerance,OD)
P17/D15/INT7/OUT7
PH3/INT3_1 (5V tolerance)
* Explanation of ( )
5V tolerance: 5V tolerant pin
OD: Open drain control pin
(FPT-48P-M26)
Note : The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the port number.
For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port
function register (EPFR) to select the pin.
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
15
CHAPTER 2 Pins of the MB91665 Series
2.2
2.2
MB91665 Series
Pin Functions
Table 2.2-1 lists the pin functions of the MB91665 series.
In a pin that includes an underscore (_), such as XXX_1 and XXX_2, the number following the
underscore represents a port number. For details of the port numbers, see "2.4 Setting Method for
Pins".
■ Pin function list
Table 2.2-1 Pin functions (1 / 13)
Pin Number
64
pin
1
2
3
4
16
48
pin
1
2
3
4
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
D09
External bus interface data bus bit9
❍
-
SIN2
Multifunction serial interface ch.2
input pin
-
❍
INT1
External interrupt request 1 input pin
-
❍
General-purpose I/O port
-
❍
D10
External bus interface data bus bit10
❍
-
SCK2
(SCL2)
Multifunction serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL2 when it is
used in an I2C (operation mode 4).
-
❍
INT2
External interrupt request 2 input pin
-
❍
General-purpose I/O port
-
❍
D11
External bus interface data bus bit11
❍
-
INT3
External interrupt request 3 input pin
-
❍
General-purpose I/O port
-
❍
D12
External bus interface data bus bit12
❍
-
AIN1
Up/Down counter ch.1 AIN input pin
-
❍
INT4
External interrupt request 4 input pin
-
❍
OUT4
32-bit output compare ch.4 output pin
-
-
P11
Q*2
P12
Q*2
P13
B
P14
B
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (2 / 13)
Pin Number
48
pin
64
pin
5
6
7
8
5
6
7
8
Pin
Name
I/O
Circuit
Type*1
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
D13
External bus interface data bus bit13
❍
-
BIN1
Up/Down counter ch.1 BIN input pin
-
❍
INT5
External interrupt request 5 input pin
-
❍
OUT5
32-bit output compare ch.5 output pin
-
❍
General-purpose I/O port
-
❍
D14
External bus interface data bus bit14
❍
-
ZIN1
Up/Down counter ch.1 ZIN input pin
-
❍
INT6
External interrupt request 6 input pin
-
❍
OUT6
32-bit output compare ch.6 output pin
-
❍
General-purpose I/O port
-
❍
D15
External bus interface data bus bit15
❍
-
INT7
External interrupt request 7 input pin
-
❍
OUT7
32-bit output compare ch.7 output pin
-
❍
General-purpose I/O port
-
❍
External interrupt request 3 input pin
(Port 1)
-
❍
Power pin
-
-
P15
B
P16
B
P17
B
D*2
PH3
INT3_1
CM71-10158-1E
Function
9
9
VCC
-
10
10
UDM
USB
D- pin of USB function/HOST
-
-
11
11
UDP
USB
D+ pin of USB function/HOST
-
-
12
12
VSS
-
GND pin
-
-
13
-
P20
Q*2
General-purpose I/O port
-
❍
A00
External bus interface address bus
bit0
-
-
TMO1_1
16-bit reload timer ch.1 output pin
(Port 1)
-
❍
A16
External bus interface address bus
bit16
-
-
FUJITSU SEMICONDUCTOR LIMITED
17
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (3 / 13)
Pin Number
48
pin
64
pin
14
15
16
17
18
18
-
-
-
-
-
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
A01
External bus interface address bus
bit1
-
-
TMO2_1
16-bit reload timer ch.2 output pin
(Port 1)
-
❍
A17
External bus interface address bus
bit17
-
-
General-purpose I/O port
-
❍
A02
External bus interface address bus
bit2
-
-
TIOA0_1
Base timer ch.0 TIOA pin (Port 1)
-
❍
A18
External bus interface address bus
bit18
-
-
General-purpose I/O port
-
❍
A03
External bus interface address bus
bit3
-
-
TIOB0_1
Base timer ch.0 TIOB pin (Port 1)
-
❍
A19
External bus interface address bus
bit19
❍
-
General-purpose I/O port
-
❍
A04
External bus interface address bus
bit4
-
-
OUT0
32-bit output compare ch.0 output pin
-
-
A20
External bus interface address bus
bit20
-
-
General-purpose I/O port
-
❍
A05
External bus interface address bus
bit5
-
-
OUT1
32-bit output compare ch.1 output pin
-
-
A21
External bus interface address bus
bit21
-
-
P21
Q*2
P22
Q*2
Q*2
P23
P24
Q*2
P25
Q*2
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (4 / 13)
Pin Number
48
pin
64
pin
19
20
21
22
CM71-10158-1E
-
-
13
14
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
A06
External bus interface address bus
bit6
-
-
OUT2
32-bit output compare ch.2 output pin
-
-
A22
External bus interface address bus
bit22
-
-
General-purpose I/O port
-
❍
A07
External bus interface address bus
bit7
-
-
OUT3
32-bit output compare ch.3 output pin
-
-
A23
External bus interface address bus
bit23
-
-
General-purpose I/O port
-
❍
SCK2_1
(SCL2_1)
Multifunction serial interface ch.2
clock I/O pin (Port 1).
This pin operates as SCK2_1 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL2_1 when it
is used in an I2C (operation mode 4).
-
❍
INT2_1
External interrupt request 2 input pin
(Port 1)
-
❍
General-purpose I/O port
-
❍
D00
External bus interface data bus bit0
❍
-
TIOA0
Base timer ch.0 TIOA pin
-
-
SOUT0_1
(SDA0_1)
Multifunction serial interface ch.0
output pin (Port 1).
This pin operates as SOUT0_1 when
it is used in a UART/CSIO (operation
modes 0 to 2) and as SDA0_1 when it
is used in an I2C (operation mode 4).
-
-
IN0
32-bit input capture ch.0 input pin
-
❍
P26
Q*2
P27
Q*2
D*2
PH2
P00
Q*2
FUJITSU SEMICONDUCTOR LIMITED
19
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (5 / 13)
Pin Number
64
pin
23
Pin
Name
48
pin
15
I/O
Circuit
Type*1
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
D01
External bus interface data bus bit1
❍
-
TIOB0
Base timer ch.0 TIOB pin
-
❍
SIN0_1
Multifunction serial interface ch.0
input pin (Port 1)
-
❍
IN1
32-bit input capture ch.1 input pin
-
❍
P01
B
24
16
INIT
P
External reset input pin. A reset is
valid when INIT=L.
The I/O circuit type for the flash
memory products is P.
-
❍
25
17
PK1
I
General-purpose I/O port
-
❍
Sub clock (oscillation) input pin
-
❍
General-purpose I/O port
-
❍
Sub clock (oscillation) I/O pin
-
-
X0A
26
18
PK0
I
X1A
20
Function
27
19
C
-
Power stabilization capacity pin
-
-
28
20
MD1
P
Mode 1 pin. Input must always be at
the "L" level.
The I/O circuit type for the flash
memory products is P.
-
❍
29
21
MD0
P
Mode 0 pin.
The I/O circuit type for the flash
memory products is P.
During normal operation, MD0=L
must be input. During serial
programming to flash memory,
MD0=H must be input.
-
❍
30
22
X0
A
Main clock (oscillation) input pin
-
❍
31
23
X1
A
Main clock (oscillation) I/O pin
-
-
32
24
VSS
-
GND pin
-
-
33
25
VCC
-
Power pin
-
-
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (6 / 13)
Pin Number
64
pin
34
35
36
37
CM71-10158-1E
48
pin
26
27
28
29
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
D02
External bus interface data bus bit2
❍
-
TIOA1
Base timer ch.1 TIOA pin
-
❍
SCK0_1
(SCL0_1)
Multifunction serial interface ch.0
clock I/O pin (Port 1).
This pin operates as SCK0_1 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL0_1 when it
is used in an I2C (operation mode 4).
-
❍
IN2
32-bit input capture ch.2 input pin
-
❍
General-purpose I/O port
-
❍
D03
External bus interface data bus bit3
❍
-
TIOB1
Base timer ch.1 TIOB pin
-
❍
IN3
32-bit input capture ch.3 input pin
-
❍
General-purpose I/O port
-
❍
D04
External bus interface data bus bit4
❍
-
TIOA2
Base timer ch.2 TIOA pin
-
-
SOUT1
(SDA1)
Multifunction serial interface ch.1
output pin.
This pin operates as SOUT1 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SDA1 when it is
used in an I2C (operation mode 4).
-
❍
IN4
32-bit input capture ch.4 input pin
-
❍
General-purpose I/O port
-
❍
D05
External bus interface data bus bit5
❍
-
TIOB2
Base timer ch.2 TIOB pin
-
❍
SIN1
Multifunction serial interface ch.1
input pin
-
❍
IN5
32-bit input capture ch.5 input pin
-
❍
P02
Q*2
P03
B
P04
Q*2
Q*2
P05
FUJITSU SEMICONDUCTOR LIMITED
21
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (7 / 13)
Pin Number
48
pin
64
pin
38
39
40
41
42
22
30
31
32
-
-
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
D06
External bus interface data bus bit6
❍
-
TIOA3
Base timer ch.3 TIOA pin
-
❍
SCK1
(SCL1)
Multifunction serial interface ch.1
clock I/O pin.
This pin operates as SCK1 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL1 when it is
used in an I2C (operation mode 4).
-
❍
IN6
32-bit input capture ch.6 input pin
-
❍
General-purpose I/O port
-
❍
D07
External bus interface data bus bit7
❍
-
TIOB3
Base timer ch.3 TIOB pin
-
❍
IN7
32-bit input capture ch.7 input pin
-
❍
General-purpose I/O port
-
❍
CS0
External bus interface chip select 0
output pin
-
-
TMO0_1
16-bit reload timer ch.0 output pin
(Port 1)
-
-
General-purpose I/O port
-
❍
CS1
External bus interface chip select 1
output pin
-
-
TIOA2_1
Base timer ch.2 TIOA pin (Port 1)
-
-
SOUT1_1
(SDA1_1)
Multifunction serial interface ch.1
output pin (Port 1).
This pin operates as SOUT1_1 when
it is used in a UART/CSIO (operation
modes 0 to 2) and as SDA1_1 when it
is used in an I2C (operation mode 4).
-
❍
General-purpose I/O port
-
❍
CS2
External bus interface chip select 2
output pin
-
-
TIOB2_1
Base timer ch.2 TIOB pin (Port 1)
-
❍
SIN1_1
Multifunction serial interface ch.1
input pin (Port 1)
-
❍
P06
Q*2
P07
B
P50
C
P51
C
P52
C
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (8 / 13)
Pin Number
48
pin
64
pin
43
44
45
CM71-10158-1E
-
33
34
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
CS3
External bus interface chip select 3
output pin
-
-
FRCK1
32-bit free-run timer ch.1 external
clock input pin
-
❍
TIOA3_1
Base timer ch.3 TIOA pin (Port 1)
-
❍
SCK1_1
(SCL1_1)
Multifunction serial interface ch.1
clock I/O pin (Port 1).
This pin operates as SCK1_1 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL1_1 when it
is used in an I2C (operation mode 4).
-
❍
General-purpose I/O port
-
❍
AS
External bus interface address strobe
output pin
-
-
AIN1_1
Up/Down counter ch.1 AIN input pin
(Port 1)
-
❍
SOUT6
(SDA6)
Multifunction serial interface ch.6
output pin.
This pin operates as SOUT6 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SDA6 when it is
used in an I2C (operation mode 4).
-
❍
General-purpose I/O port
-
❍
RD
External bus interface read strobe
output pin
-
-
BIN1_1
Up/Down counter ch.1 BIN input pin
(Port 1)
-
❍
ADTRG0
10-bit A/D converter external trigger
input pin
-
❍
SIN6
Multifunction serial interface ch.6
input pin
-
❍
P53
C
P54
C
P55
C
FUJITSU SEMICONDUCTOR LIMITED
23
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (9 / 13)
Pin Number
48
pin
64
pin
46
47
-
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
WR0
External bus interface write strobe 0
output pin
-
-
ZIN1_1
Up/Down counter ch.1 ZIN input pin
(Port 1)
-
❍
FRCK0
32-bit free-run timer ch.0 external
clock input pin
-
❍
SCK6
(SCL6)
Multifunction serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL6 when it is
used in an I2C (operation mode 4).
-
❍
General-purpose I/O port
-
❍
WR1
External bus interface write strobe 1
output pin
-
-
TIOB3_1
Base timer ch.3 TIOB pin (Port 1)
-
❍
TMI2_1
16-bit reload timer ch.2 input pin
(Port 1)
-
❍
P56
C
P57
C
48
36
AVSS
-
10-bit A/D converter GND pin
-
-
49
37
AVCC
-
10-bit A/D converter analog power
pin
-
-
50
38
P70
E
General-purpose I/O port
-
❍
AN0
10-bit A/D converter ch.0 analog
input pin
-
-
OUT0_1
32-bit output compare ch.0 output pin
(Port 1)
-
-
INT16
External interrupt request 16 input
pin
-
❍
General-purpose I/O port
-
❍
AN1
10-bit A/D converter ch.1 analog
input pin
-
-
OUT1_1
32-bit output compare ch.1 output pin
(Port 1)
-
-
INT17
External interrupt request 17 input
pin
-
❍
51
24
35
Pin
Name
39
P71
E
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (10 / 13)
Pin Number
64
pin
52
53
54
CM71-10158-1E
48
pin
40
41
42
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
AN2
10-bit A/D converter ch.2 analog
input pin
-
-
TMO0
16-bit reload timer ch.0 output pin
-
-
OUT2_1
32-bit output compare ch.2 output pin
(Port 1)
-
-
INT18
External interrupt request 18 input
pin
-
❍
General-purpose I/O port
-
❍
AN3
10-bit A/D converter ch.3 analog
input pin
-
-
TMO1
16-bit reload timer ch.1 output pin
-
-
OUT3_1
32-bit output compare ch.3 output pin
(Port 1)
-
-
INT19
External interrupt request 19 input
pin
-
❍
General-purpose I/O port
-
❍
AN4
10-bit A/D converter ch.4 analog
input pin
-
-
TMO2
16-bit reload timer ch.2 output pin
-
-
OUT4_1
32-bit output compare ch.4 output pin
(Port 1)
-
-
INT20
External interrupt request 20 input
pin
-
❍
P72
E
P73
E
P74
E
FUJITSU SEMICONDUCTOR LIMITED
25
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (11 / 13)
Pin Number
64
pin
55
56
57
26
48
pin
43
44
45
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
AN5
10-bit A/D converter ch.5 analog
input pin
-
-
SOUT0
(SDA0)
Multifunction serial interface ch.0
output pin.
This pin operates as SOUT0 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SDA0 when it is
used in an I2C (operation mode 4).
-
-
TMI0
16-bit reload timer ch.0 input pin
-
❍
OUT5_1
32-bit output compare ch.5 output pin
(Port 1)
-
-
INT21
External interrupt request 21 input
pin
-
❍
General-purpose I/O port
-
❍
AN6
10-bit A/D converter ch.6 analog
input pin
-
-
SIN0
Multifunction serial interface ch.0
input pin
-
❍
TMI1
16-bit reload timer ch.1 input pin
-
❍
OUT6_1
32-bit output compare ch.6 output pin
(Port 1)
-
-
INT22
External interrupt request 22 input
pin
-
❍
General-purpose I/O port
-
❍
AN7
10-bit A/D converter ch.7 analog
input pin
-
-
SCK0
(SCL0)
Multifunction serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL0 when it is
used in an I2C (operation mode 4).
-
❍
TMI2
16-bit reload timer ch.2 input pin
-
❍
OUT7_1
32-bit output compare ch.7 output pin
(Port 1)
-
-
INT23
External interrupt request 23 input
pin
-
❍
P75
E
P76
E
P77
E
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (12 / 13)
Pin Number
48
pin
64
pin
58
59
60
61
62
CM71-10158-1E
46
47
-
-
-
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
AN8
10-bit A/D converter ch.8 analog
input pin
-
-
IN0_1
32-bit input capture ch.0 input pin
(Port 1)
-
❍
TMI0_1
16-bit reload timer ch.0 input pin
(Port 1)
-
❍
General-purpose I/O port
-
❍
AN9
10-bit A/D converter ch.9 analog
input pin
-
-
IN1_1
32-bit input capture ch.1 input pin
(Port 1)
-
❍
TMI1_1
16-bit reload timer ch.1 input pin
(Port 1)
-
❍
General-purpose I/O port
-
❍
AN10
10-bit A/D converter ch.10 analog
input pin
-
-
IN2_1
32-bit input capture ch.2 input pin
(Port 1)
-
❍
General-purpose I/O port
-
❍
AN11
10-bit A/D converter ch.11 analog
input pin
-
-
IN3_1
32-bit input capture ch.3 input pin
(Port 1)
-
❍
General-purpose I/O port
-
❍
RDY
External bus interface ready input pin
❍
-
TIOA1_1
Base timer ch.1 TIOA pin (Port 1)
-
❍
SOUT2_1
(SDA2_1)
Multifunction serial interface ch.2
output pin (Port 1).
This pin operates as SOUT2_1 when
it is used in a UART/CSIO (operation
modes 0 to 2) and as SDA2_1 when it
is used in an I2C (operation mode 4).
-
❍
P80
E
P81
E
P82
E
P83
E
P60
B
FUJITSU SEMICONDUCTOR LIMITED
27
CHAPTER 2 Pins of the MB91665 Series
2.2
MB91665 Series
Table 2.2-1 Pin functions (13 / 13)
Pin Number
48
pin
64
pin
63
64
-
48
Pin
Name
I/O
Circuit
Type*1
Function
CMOS CMOS level
level hysteresis
input
input
General-purpose I/O port
-
❍
SYSCLK
External bus interface bus clock
output pin
-
-
TIOB1_1
Base timer ch.1 TIOB pin (Port 1)
-
❍
SIN2_1
Multifunction serial interface ch.2
input pin (Port 1)
-
❍
General-purpose I/O port
-
❍
D08
External bus interface data bus bit8
❍
-
SOUT2
(SDA2)
Multifunction serial interface ch.2
output pin.
This pin operates as SOUT2 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SDA2 when it is
used in an I2C (operation mode 4).
-
❍
INT0
External interrupt request 0 input pin
-
❍
P61
C
P10
Q
* 1 : Refer to "2.3 I/O Circuit Types" for details on the I/O circuit types.
* 2 : 5 V tolerant pin
28
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.3
MB91665 Series
2.3
I/O Circuit Types
Table 2.3-1 lists the I/O circuit types for the MB91665 series.
■ I/O circuit types
Table 2.3-1 I/O circuit types (1 / 4)
Type
A
Circuit
X1
Remarks
Clock input
- Oscillation feedback resistor:
Approximately 1MΩ
- With standby mode control
X0
Standby mode control
B
- CMOS level output
- CMOS level input
- CMOS level hysteresis input
- With pull-up resistor control
- With standby mode control
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up resistor
control
Digital input
Standby mode
control
Digital input
Standby mode
control
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
*: CMOS level input when
input data, RDY pin of
external bus interface.
Input other than above
situations, CMOS level
hysteresis input.
*: When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off.
*: When this pin is used as a
N-ch open drain control pin,
the digital output P-ch
transistor is always off.
29
CHAPTER 2 Pins of the MB91665 Series
2.3
MB91665 Series
Table 2.3-1 I/O circuit types (2 / 4)
Type
Circuit
Remarks
C
- CMOS level output
- CMOS level hysteresis input
- With pull-up resistor control
- With standby mode control
P-ch
R
P-ch
Digital output
N-ch
Digital output
* When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off.
Pull-up resistor
control
Digital input
Standby mode
control
D
P-ch
N-ch
Digital output
- CMOS level output
- CMOS level hysteresis input
- 5V tolerant input
- With standby mode control
Digital output
* When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off.
R
Digital input
Standby mode
control
30
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.3
MB91665 Series
Table 2.3-1 I/O circuit types (3 / 4)
Type
Circuit
Remarks
E
P-ch
P-ch
N-ch
Digital output
- CMOS level output
- CMOS level hysteresis input
- With input control
- Analog input
- With pull-up resistor control
- With standby mode control
Digital output
*: When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off.
Pull-up resistor
control
R
Digital input
Standby mode
control
Analog input
Input control
I
X1A
P-ch
Digital output
N-ch
Digital output
- Oscillation feedback resistor:
Approximately 10MΩ
- CMOS level output
- CMOS level hysteresis input
- With standby mode control
R
Digital input
Standby mode
control
Clock input
R
Standby mode
control
Digital input
Standby mode
control
X0A
CM71-10158-1E
P-ch
Digital output
N-ch
Digital output
FUJITSU SEMICONDUCTOR LIMITED
31
CHAPTER 2 Pins of the MB91665 Series
2.3
MB91665 Series
Table 2.3-1 I/O circuit types (4 / 4)
Type
Circuit
Remarks
P
- Flash memory products only
- CMOS level hysteresis input
- With high-voltage control for
flash memory tests
N-ch
N-ch
Control pin
N-ch
N-ch
Mode input
N-ch
R
Q
P-ch
N-ch
Digital output
Digital output
R
- CMOS level output
- CMOS level input
- CMOS level hysteresis input
- 5 V tolerant input
- With standby control
*: When this pin is used as a
N-ch open drain control pin,
the digital output P-ch
transistor is always off.
Digital input
Standby control
Digital input
Standby control
USB
- USB I/O pin
UDP(+)
output
UDP(+)
UDP(+) input
Differential
UDM(-)
Differential
input
UDM(-) input
UDM(-)
output
Direction
32
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
2.4
Setting Method for Pins
This section explains how to set registers for the multiplexed pins.
More than one function has been assigned to the multiplexed pins. The tables below list the register
setting values used to assign each of these functions to the pins, as categorized by peripheral function.
The register names appearing in these tables are abbreviated names.
- EPFR: Extended port function register
- PFR: Port function register
- DDR: Port data direction register
For details of these registers, see "CHAPTER 14 I/O Ports".
Other abbreviated register names are explained in the notes under each table. For details, see the
respective chapters.
■ Ports
Pin Name
Register Name
Bit Name
Written
Value
P00 to P07
PFR0
PFR00 to PFR07
0
P10 to P17
PFR1
PFR10 to PFR17
0
P20 to P27
PFR2
PFR20 to PFR27
0
-
PFR3
PFR30 to PFR37
0
-
PFR4
PFR40 to PFR47
0
P50 to P57
PFR5
PFR50 to PFR57
0
P60, P61
PFR6*
PFR60, PFR61
0
P70 to P77
PFR7
PFR70 to PFR77
0
P80 to P83
PFR8
PFR80 to PFR83
0
-
PFRA
PFRA0 to PFRA7
0
-
PFRG
PFRG0 to PFRG7
0
PFRH*
PFRH2, PFRH3
0
PH2, PH3
*:
The PFR register settings for P60 and PH3 are not required.
<Note>
For details of the settings of the port data direction register (DDR) see "CHAPTER 14 I/O Ports".
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
33
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
■ Clocks
Pin Name
Register Name
X0A, X1A
Bit Name
Written
Value
DDRK
DDRK1, DDRK0
00
EPFR19
XAE
1
CSELR
SCEN
1
CSELR: Clock source select register
■ External interrupt controllers
One of either of the INTx or INTx_1 pins can be selected for use with each channel (Not all of the
channels can be used.).
To use the INT pin, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the external interrupt controller (For details, see "CHAPTER 15 External
Interrupt Controllers").
For details of the basic settings, see the following table.
Channel
0 to 3
Port
Number
Port 0
Port 1
4 to 7
16 to 19
Port 0
Port 0
Pin Name
INT0 to INT3
INT2_1 to INT3_1
INT4 to INT7
INT16 to INT19
Register
Name
Bit Name
Written
Value
DDR1
DDR10 to DDR13
0
PFR1
PFR10 to PFR13
0
EPFR28
INT0E to INT3E
0
DDRH
DDRH0 to DDRH3
0
PFRH
*
0
EPFR28
INT0E to INT3E
1
DDR1
DDR14 to DDR17
0
PFR1
PFR14 to PFR17
0
EPFR28
INT4E to INT7E
0
DDR3
DDR34 to DDR37
0
PFR3
PFR34 to PFR37
0
DDR7
DDR70 to DDR73
0
PFR7
PFR70 to PFR73
0
EPFR30
INT16E to INT19E
0
ADCHE
ADE0 to ADE3
0
*: INT2_1:PFRH2, INT3_1: no PFR
34
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
Channel
20
21
22
23
CM71-10158-1E
Port
Number
Port 0
Port 0
Port 0
Port 0
Pin Name
INT20
INT21
INT22
INT23
Register
Name
Bit Name
Written
Value
DDR7
DDR74
0
PFR7
PFR74
0
EPFR31
INT20E
0
ADCHE
ADE4
0
DDR7
DDR75
0
PFR7
PFR75
0
EPFR31
INT21E1, INT21E0
00
ADCHE
ADE5
0
DDR7
DDR76
0
PFR7
PFR76
0
EPFR31
INT22E1, INT22E0
00
ADCHE
ADE6
0
DDR7
DDR77
0
PFR7
PFR77
0
EPFR31
INT23E1, INT23E0
00
ADCHE
ADE7
0
FUJITSU SEMICONDUCTOR LIMITED
35
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
■ 32-bit free-run timer
To use the FRCK pin, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the 32-bit free-run timer (For details, see "CHAPTER 18 32-bit Free-Run
Timer").
For details of the basic settings, see the following table.
Channel
0
1
Port
Number
Port 0
Port 0
Pin Name
FRCK0
FRCK1*
Register
Name
Bit Name
Written
Value
DDR5
DDR56
0
PFR5
PFR56
0
EPFR34
FRCK0E1, FRCK0E0
00
DDR3
DDR32
0
PFR3
PFR32
0
DDR5
DDR53
0
PFR5
PFR53
0
EPFR34
FRCK1E1, FRCK1E0
00
DDRG
DDRG6
0
PFRG
PFRG6
0
* For MB91F668 (48 pins), there is no FRCK1 pin.
36
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
■ 32-bit input capture
The 32-bit input capture provides 2 IN pins for use with each channel (Not all of the channels can be
used.).
One of each of the pins can be selected for use with each channel.
To use the IN pin, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the 32-bit input capture (For details, see "CHAPTER 19 32-bit Input
Capture").
For details of the basic settings, see the following table.
Channel
0
Port
Number
Port 0
Port 1
1
Port 0
Port 1
CM71-10158-1E
Pin Name
IN0
IN0_1
IN1
IN1_1
Register
Name
Bit Name
Written
Value
DDR0
DDR00
0
PFR0
PFR00
0
EPFR4
IN0E1, IN0E0
00
DDR8
DDR80
0
PFR8
PFR80
0
EPFR4
IN0E1, IN0E0
01
ADCHE
ADE8
0
DDRA
DDRA5
0
ADCHE
ADE21
1
DDR0
DDR01
0
PFR0
PFR01
0
EPFR4
IN1E1, IN1E0
00
DDR8
DDR81
0
PFR8
PFR81
0
EPFR4
IN1E1, IN1E0
01
ADCHE
ADE9
0
DDRA
DDRA6
0
PFRA
PFRA6
0
ADCHE
ADE22
1
FUJITSU SEMICONDUCTOR LIMITED
37
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel
2
Port
Number
Port 0
Port 1
3
Port 0
Port 1
4
5
6
7
38
Port 0
Port 0
Port 0
Port 0
MB91665 Series
Pin Name
IN2
IN2_1
IN3
IN3_1
IN4
IN5
IN6
IN7
Register
Name
Bit Name
Written
Value
DDR0
DDR02
0
PFR0
PFR02
0
EPFR4
IN2E1, IN2E0
00
DDR8
DDR82
0
PFR8
PFR82
0
EPFR4
IN2E1, IN2E0
01
ADCHE
ADE10
0
DDR0
DDR03
0
PFR0
PFR03
0
EPFR4
IN3E1, IN3E0
00
DDR8
DDR83
0
PFR8
PFR83
0
EPFR4
IN3E1, IN3E0
01
ADCHE
ADE11
0
DDR0
DDR04
0
PFR0
PFR04
0
EPFR5
IN4E1, IN4E0
00
DDR0
DDR05
0
PFR0
PFR05
0
EPFR5
IN5E1, IN5E0
00
DDR0
DDR06
0
PFR0
PFR06
0
EPFR5
IN6E1, IN6E0
00
DDR0
DDR07
0
PFR0
PFR07
0
EPFR5
IN7E1, IN7E0
00
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
■ 32-bit output compare
The 32-bit output compare provides 2 OUT pins for use with each channel.
One of each of the pins can be selected for use with each channel.
To use the OUT pin, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register.
(For details of the multiplexed pins, see the pin assignment diagram.)
3. Select a pin (port number) to be used on the EPFR register.
4. Set peripheral functions on the PFR register (PFR=1).
For details of the basic settings, see the following table.
Channel
0
Port
Number
Port 0
Port 1
1
Port 0
Port 1
2
Port 0
Port 1
CM71-10158-1E
Pin Name
Register
Name
OUT0
PFR2
PFR24
1
EPFR0
OUT0E2 to OUT0E0
001
DDR4
DDR44
0
PFR4
PFR44
0
PFR7
PFR70
1
EPFR0
OUT0E2 to OUT0E0
010
ADCHE
ADE0
0
PFR2
PFR25
1
EPFR0
OUT1E2 to OUT1E0
001
DDR4
DDR45
0
PFR4
PFR45
0
PFR7
PFR71
1
EPFR0
OUT1E2 to OUT1E0
010
ADCHE
ADE1
0
PFR2
PFR26
1
EPFR1
OUT2E2 to OUT2E0
001
DDR4
DDR46
0
PFR4
PFR46
0
PFR7
PFR72
1
EPFR1
OUT2E2 to OUT2E0
010
EPFR33
TMO0E1, TMO0E0
Other than 01*
ADCHE
ADE2
0
OUT0_1
OUT1
OUT1_1
OUT2
OUT2_1
Bit Name
FUJITSU SEMICONDUCTOR LIMITED
Written Value
39
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel
3
Port
Number
Port 0
Port 1
4
Port 0
Port 1
5
Port 0
Port 1
6
Port 0
Port 1
40
MB91665 Series
Pin Name
Register
Name
OUT3
PFR2
PFR27
1
EPFR1
OUT3E2 to OUT3E0
001
DDR4
DDR47
0
PFR4
PFR47
0
PFR7
PFR73
1
EPFR1
OUT3E2 to OUT3E0
010
EPFR33
TMO1E1, TMO1E0
Other than 01*
ADCHE
ADE3
0
PFR3
PFR34
1
EPFR2
OUT4E2 to OUT4E0
001
DDR1
DDR14
0
PFR1
PFR14
0
PFR7
PFR74
1
EPFR2
OUT4E2 to OUT4E0
010
EPFR34
TMO2E1, TMO2E0
Other than 01*
ADCHE
ADE4
0
PFR3
PFR35
1
EPFR2
OUT5E2 to OUT5E0
001
DDR1
DDR15
0
PFR1
PFR15
0
PFR7
PFR75
1
EPFR2
OUT5E2 to OUT5E0
010
EPFR6
SOUT0E2 to SOUT0E0
Other than 001*
ADCHE
ADE5
0
PFR3
PFR36
1
EPFR3
OUT6E2 to OUT6E0
001
DDR1
DDR16
0
PFR1
PFR16
0
PFR7
PFR76
1
EPFR3
OUT6E2 to OUT6E0
010
ADCHE
ADE6
0
OUT3_1
OUT4
OUT4_1
OUT5
OUT5_1
OUT6
OUT6_1
Bit Name
FUJITSU SEMICONDUCTOR LIMITED
Written Value
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
Channel
7
Port
Number
Port 0
Port 1
Pin Name
Register
Name
OUT7
PFR3
PFR37
1
EPFR3
OUT7E2 to OUT7E0
001
DDR1
DDR17
0
PFR1
PFR17
0
PFR7
PFR77
1
EPFR3
OUT7E2 to OUT7E0
010
EPFR6
SCK0E2 to SCK0E0
Other than 001*
ADCHE
ADE7
0
OUT7_1
Bit Name
Written Value
* : Do not write a setting prohibited value. For details, see "CHAPTER 14 I/O Ports".
■ 16-bit reload timer
The 16-bit reload timer provides 2 of each of the TMI/TMO pins for use with each channel.
One of each of the TMI/TMO pins can be selected for use with each channel. However, to use pins for the
same channel, the pins must be assigned to the same port number.
To use the TMI pin, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the 16-bit reload timer (For details, see "CHAPTER 21 16-bit Reload
Timer").
To use the TMO pin, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register.
(For details of the multiplexed pins, see the pin assignment diagram.)
3. Select a pin (port number) to be used on the EPFR register.
4. Set peripheral functions on the PFR register (PFR=1).
For details of the basic settings, see the following table.
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
41
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel
0
Port
Number
Port 0
MB91665 Series
Pin Name
TMI0
TMO0
Port 1
TMI0_1
TMO0_1
42
Register
Name
Bit Name
Written
Value
DDR7
DDR75
0
PFR7
PFR75
0
EPFR33
TMI0E
0
ADCHE
ADE5
0
PFR7
PFR72
1
EPFR33
TMO0E1, TMO0E0
01
ADCHE
ADE2
0
DDRA
DDRA5
0
EPFR33
TMI0E
1
ADCHE
ADE21
0
DDR8
DDR80
0
PFR8
PFR80
0
ADCHE
ADE8
1
PFRA
PFRA2
1
EPFR33
TMO0E1, TMO0E0
10
ADCHE
ADE18
0
DDR5
DDR50
0
PFR5
PFR50
0
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
Channel
1
Port
Number
Port 0
Pin Name
TMI1
TMO1
Port 1
TMI1_1
TMO1_1
CM71-10158-1E
Register
Name
Bit Name
Written
Value
DDR7
DDR76
0
PFR7
PFR76
0
EPFR33
TMI1E
0
ADCHE
ADE6
0
PFR7
PFR73
1
EPFR33
TMO1E1, TMO1E0
01
ADCHE
ADE3
0
DDRA
DDRA6
0
PFRA
PFRA6
0
EPFR33
TMI1E
1
ADCHE
ADE22
0
DDR8
DDR81
0
PFR8
PFR81
0
ADCHE
ADE9
1
PFRA
PFRA3
1
EPFR33
TMO1E1, TMO1E0
10
ADCHE
ADE19
0
DDR2
DDR20
0
PFR2
PFR20
0
DDR4
DDR40
0
PFR4
PFR40
0
FUJITSU SEMICONDUCTOR LIMITED
43
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel
2
Port
Number
Port 0
MB91665 Series
Pin Name
TMI2
TMO2
Port 1
TMI2_1
TMO2_1
44
Register
Name
Bit Name
Written
Value
DDR7
DDR77
0
PFR7
PFR77
0
EPFR34
TMI2E
0
ADCHE
ADE7
0
PFR7
PFR74
1
EPFR34
TMO2E1, TMO2E0
01
ADCHE
ADE4
0
DDRA
DDRA7
0
PFRA
PFRA7
0
EPFR34
TMI2E
1
ADCHE
ADE23
0
DDR5
DDR57
0
PFR5
PFR57
0
DDRG
DDRG7
0
PFRA
PFRA4
1
EPFR34
TMO2E1, TMO2E0
10
ADCHE
ADE20
0
DDR2
DDR21
0
PFR2
PFR21
0
DDR4
DDR41
0
PFR4
PFR41
0
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
■ Base timer
The base timer provides 2 TIOA/TIOB pins for use with channels 0 to 3 and 1 TIOA/TIOB pin for use
with channels 6 to 15.
One of each of the TIOA/TIOB pins can be selected for use with channels 0 to 5. However, to use pins
for the same channel, the pins must be assigned to the same port number.
To use the TIOA/TIOB pins for input, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the base timer (For details, see "CHAPTER 23 Base Timer").
To use the TIOA pin for output, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register.
(For details of the multiplexed pins, see the pin assignment diagram.)
3. Select a pin (port number) to be used on the EPFR register.
4. Set peripheral functions on the PFR register (PFR=1).
For details of the basic settings, see the following table.
Channel
0
Port
Number
Port 0
Pin Name
Register
Name
TIOA0
PFR0
PFR00
1
EPFR20
TIOA0E1, TIOA0E0
01
EPFR6
SOUT0E2 to SOUT0E0
Other than 010 *
PFR0
PFR01
0
DDR0
DDR01
0
EPFR20
TIOB0E
0
PFRG
PFRG0
1
EPFR20
TIOA0E1, TIOA0E0
10
DDR2
DDR22
0
PFR2
PFR22
0
DDR4
DDR42
0
PFR4
PFR42
0
PFRG
PFRG1
0
DDRG
DDRG1
0
EPFR20
TIOB0E
1
DDR2
DDR23
0
PFR2
PFR23
0
DDR4
DDR43
0
PFR4
PFR43
0
TIOB0
Port 1
TIOA0_1
TIOB0_1
CM71-10158-1E
Bit Name
FUJITSU SEMICONDUCTOR LIMITED
Written Value
45
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel
1
Port
Number
Port 0
Pin Name
Register
Name
TIOA1
PFR0
PFR02
At input: 0
At output: 1
DDR0
DDR02
0 (only at input)
EPFR20
TIOA1E1, TIOA1E0
01
EPFR6
SCK0E2 to SCK0E0
Other than 010 *
PFR0
PFR03
0
DDR0
DDR03
0
EPFR20
TIOB1E
0
PFRG
PFRG2
At input: 0
At output: 1
DDRG
DDRG2
0 (only at input)
EPFR20
TIOA1E1, TIOA1E0
10
DDR6
DDR60
0
PFR6
PFR60
0
DDRH
DDRH0
0
PFRH
PFRH0
0
DDRG
DDRG3
0
EPFR20
TIOB1E
1
DDR6
DDR61
0
PFR6
PFR61
0
DDRH
DDRH1
0
TIOB1
Port 1
TIOA1_1
TIOB1_1
46
MB91665 Series
Bit Name
FUJITSU SEMICONDUCTOR LIMITED
Written Value
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
Channel
2
Port
Number
Port 0
Pin Name
Register
Name
TIOA2
PFR0
PFR04
1
EPFR21
TIOA2E1, TIOA2E0
01
EPFR7
SOUT1E1, SOUT1E0
Other than 01 *
PFR0
PFR05
0
DDR0
DDR05
0
EPFR21
TIOB2E
0
PFRG
PFRG4
1
EPFR21
TIOA2E1, TIOA2E0
10
EPFR7
SOUT1E1, SOUT1E0
Other than 10 *
DDR5
DDR51
0
PFR5
PFR51
0
PFRG
PFRG5
0
DDRG
DDRG5
0
EPFR21
TIOB2E
1
DDR5
DDR52
0
PFR5
PFR52
0
TIOB2
Port 1
TIOA2_1
TIOB2_1
CM71-10158-1E
Bit Name
FUJITSU SEMICONDUCTOR LIMITED
Written Value
47
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel
3
Port
Number
Port 0
Pin Name
Register
Name
TIOA3
PFR0
PFR06
At input: 0
At output: 1
DDR0
DDR06
0 (only at input)
EPFR21
TIOA3E1, TIOA3E0
01
EPFR7
SCK1E1, SCK1E0
Other than 01 *
PFR0
PFR07
0
DDR0
DDR07
0
EPFR21
TIOB3E
0
PFRG
PFRG6
At input: 0
At output: 1
DDRG
DDRG6
0 (only at input)
EPFR21
TIOA3E1, TIOA3E0
10
EPFR7
SCK1E1, SCK1E0
Other than 10 *
DDR5
DDR53
0
PFR5
PFR53
0
DDRG
DDRG7
0
EPFR21
TIOB3E
1
DDR5
DDR57
0
PFR5
PFR57
0
DDRA
DDRA7
0
PFRH
PFRA7
0
TIOB3
Port 1
MB91665 Series
TIOA3_1
TIOB3_1
Bit Name
Written Value
* : Do not write a setting prohibited value. For details, see "CHAPTER 14 I/O Ports".
■ Up/Down counter
The up/down counter provides 2 AIN/BIN/ZIN pins.
One of each of the AIN/BIN/ZIN pins can be selected for use with each channel. However, the pins must
be assigned to the same port number.
To use the AIN/BIN/ZIN pins, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the up/down counter (For details, see "CHAPTER 24 Up/Down Counter").
48
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
For details of the basic settings, see the following table.
Channel
1
Port
Number
Port 0
Pin Name
AIN1
BIN1
ZIN1
Port 1
AIN1_1
BIN1_1
ZIN1_1
CM71-10158-1E
Register
Name
Bit Name
Written
Value
DDR1
DDR14
0
PFR1
PFR14
0
EPFR18
UDIN1E1, UDIN1E0
00
DDR3
DDR34
0
PFR3
PFR34
0
DDR1
DDR15
0
PFR1
PFR15
0
EPFR18
UDIN1E1, UDIN1E0
00
DDR3
DDR35
0
PFR3
PFR35
0
DDR1
DDR16
0
PFR1
PFR16
0
EPFR18
UDIN1E1, UDIN1E0
00
DDR3
DDR36
0
PFR3
PFR36
0
DDR5
DDR54
0
PFR5
PFR54
0
EPFR18
UDIN1E1, UDIN1E0
01
DDR3
DDR30
0
PFR3
PFR30
0
DDR5
DDR55
0
PFR5
PFR55
0
EPFR18
UDIN1E1, UDIN1E0
01
DDR3
DDR31
0
PFR3
PFR31
0
DDR5
DDR56
0
PFR5
PFR56
0
EPFR18
UDIN1E1, UDIN1E0
01
DDR3
DDR32
0
PFR3
PFR32
0
FUJITSU SEMICONDUCTOR LIMITED
49
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
■ 10-bit A/D converter
•
AN pins
Pin Name
Register Name
Bit Name
Written
Value
AN0 to AN7
ADCHE
ADE0 to ADE7
1
AN8 to AN11
ADCHE
ADE8 to ADE11
1
* For MB91F668 (48 pins), there is no AN10 and AN11 pins.
ADCHE: A/D channel enable register
•
ADTRG0 pins
The 10-bit A/D converter provides 1 ADTRG0 pin.
One of each of the pins can be selected for use with each channel.
To use the ADTRG0 pin, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the 10-bit A/D converter (For details, see "CHAPTER 25 10-Bit A/D
Converter").
For details of the basic settings, see the following table.
Port Number
Port 0
Pin Name
ADTRG0
Register
Name
Bit Name
Written
Value
DDR5
DDR55
0
PFR5
PFR55
0
EPFR19
ADTRG0E2 to ADTRG0E0
000
DDR3
DDR31
0
PFR3
PFR31
0
■ Multifunction serial interface
The multifunction serial interface provides multiple SCK pins , SIN pins, and SOUT pins for use with one
channel.
One of each of the SCK/SIN/SOUT pins can be selected for use with each channel. However, to use pins
for the same channel, the pins must be assigned to the same port number.
To use the SIN/SCK pins for input, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Select a pin (port number) to be used on the EPFR register.
3. Enable the operation of the multifunction serial interface (For details, see "CHAPTER 26 Multifunction Serial Interface").
To use the SOUT/SCK pins for output, the following settings are required.
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register.
(For details of the multiplexed pins, see the pin assignment diagram.)
3. Select a pin (port number) to be used on the EPFR register.
4. Set peripheral functions on the PFR register (PFR=1).
50
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
For details of the basic settings, see the following table.
Channel Port Number
0
Port 0
Pin Name
SCK0
(SCL0)
SIN0
SOUT0
(SDA0)
Port 1
SCK0_1
(SCL0_1)
SIN0_1
SOUT0_1
(SDA0_1)
CM71-10158-1E
Register Name
Bit Name
Written Value
PFR7
PFR77
At SCK input: 0
At SCK output: 1
DDR7
DDR77
0 (only at SCK input)
EPFR6
SCK0E2 to SCK0E0
001
SMR0
SCKE
Input enable: 0
Output enable: 1
ADCHE
ADE7
0
DDR7
DDR76
0
PFR7
PFR76
0
EPFR6
SIN0E1, SIN0E0
00
ADCHE
ADE6
0
PFR7
PFR75
1
EPFR6
SOUT0E2 to SOUT0E0
001
SMR0
SOE
1
ADCHE
ADE5
0
PFR0
PFR02
At SCK input: 0
At SCK output: 1
DDR0
DDR02
0 (only at SCK input)
EPFR6
SCK0E2 to SCK0E0
010
SMR0
SCKE
Input enable: 0
Output enable: 1
DDR0
DDR01
0
PFR0
PFR01
0
EPFR6
SIN0E1, SIN0E0
01
PFR0
PFR00
1
EPFR6
SOUT0E2 to SOUT0E0
010
SMR0
SOE
1
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51
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel Port Number
1
Port 0
Pin Name
SCK1 (SCL1)
SIN1
SOUT1
(SDA1)
Port 1
SCK1_1
(SCL1_1)
SIN1_1
SOUT1_1
(SDA1_1)
52
MB91665 Series
Register Name
Bit Name
Written Value
PFR0
PFR06
At SCK input:0
At SCK output or SCL:1
DDR0
DDR06
0 (only at SCK input)
EPFR7
SCK1E1, SCK1E0
01
SMR1
SCKE
Input enable:0
Output enable:1
(only at SCK)
DDR0
DDR05
0
PFR0
PFR05
0
EPFR7
SIN1E
0
PFR0
PFR04
1
EPFR7
SOUT1E1, SOUT1E0
01
SMR1
SOE
1
PFRG
PFRG6
At SCK input:0
At SCK output or SCL:1
DDRG
DDRG6
0 (only at SCK input)
EPFR7
SCK1E1, SCK1E0
10
SMR1
SCKE
Input enable:0
Output enable:1
(only at SCK)
DDR5
DDR53
0
PFR5
PFR53
0
DDRG
DDRG5
0
PFRG
PFRG5
0
EPFR7
SIN1E
1
DDR5
DDR52
0
PFR5
PFR52
0
PFRG
PFRG4
1
EPFR7
SOUT1E1, SOUT1E0
10
SMR1
SOE
1
DDR5
DDR51
0
PFR5
PFR51
0
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
Channel Port Number
2
Port 0
Pin Name
SCK2 (SCL2)
SIN2
SOUT2
(SDA2)
Port 1
SCK2_1
(SCL2_1)
SIN2_1
SOUT2_1
(SDA2_1)
CM71-10158-1E
Register Name
Bit Name
Written Value
PFR1
PFR12
At SCK input:0
At SCK output or SCL:1
DDR1
DDR12
0 (only at SCK input)
EPFR8
SCK2E1, SCK2E0
01
SMR2
SCKE
Input enable:0
Output enable:1
(only at SCK)
DDR1
DDR11
0
PFR1
PFR11
0
EPFR8
SIN2E
0
PFR1
PFR10
1
EPFR8
SOUT2E1, SOUT2E0
01
SMR2
SOE
1
PFRH
PFRH2
At SCK input:0
At SCK output or SCL:1
DDRH
DDRH2
0 (only at SCK input)
EPFR8
SCK2E1, SCK2E0
10
SMR2
SCKE
Input enable:0
Output enable:1
(only at SCK)
DDRH
DDRH1
0
EPFR8
SIN2E
1
DDR6
DDR61
0
PFR6
PFR61
0
DDRG
DDRG3
0
PFRH
PFRH0
1
EPFR8
SOUT2E1, SOUT2E0
10
SMR2
SOE
1
DDR6
DDR60
0
PFR6
PFR60
0
DDRG
DDRG2
0
PFRG
PFRG2
0
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53
CHAPTER 2 Pins of the MB91665 Series
2.4
Channel Port Number
6
Port 0
Pin Name
SCK6 (SCL6)
SIN6
SOUT6
(SDA6)
MB91665 Series
Register Name
Bit Name
Written Value
PFR3
PFR32
At SCK input:0
At SCK output or SCL:1
DDR3
DDR32
0 (only at SCK input)
EPFR12
SCK6E1, SCK6E0
01
SMR6
SCKE
Input enable:0
Output enable:1
(only at SCK)
DDR5
DDR56
0
PFR5
PFR56
0
DDR3
DDR31
0
PFR3
PFR31
0
EPFR12
SIN6E
0
DDR5
DDR55
0
PFR5
PFR55
0
PFR3
PFR30
1
EPFR12
SOUT6E1, SOUT6E0
01
SMR6
SOE
1
DDR5
DDR54
0
PFR5
PFR54
0
SMR: Serial mode register
<Note>
Different pins are enabled depending on the operation mode. For details, see "CHAPTER 26
Multi-function Serial Interface".
54
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
■ External bus interface
To assign an external bus interface pin, disable all the other pin settings assigned to the pin.
•
A pins
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register (For details of the
multiplexed pins, see the pin assignment diagram).
3. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
4. Set peripheral functions on the PFR register (PFR=1).
Pin Name
A00
A01
A02
A03
CM71-10158-1E
Register Name
Bit Name
Written Value
PFR2
PFR20
1
DDR4
DDR40
0
PFR4
PFR40
0
DDRA
DDRA3
0
PFRA
PFRA3
0
ADCHE
ADE19
1
EXBS
MSS
0
PFR2
PFR21
1
DDR4
DDR41
0
PFR4
PFR41
0
DDRA
DDRA4
0
PFRA
PFRA4
0
ADCHE
ADE20
1
EXBS
MSS
0
PFR2
PFR22
1
DDR4
DDR42
0
PFR4
PFR42
0
DDRG
DDRG0
0
PFRG
PFRG0
0
EXBS
MSS
0
PFR2
PFR23
1
DDR4
DDR43
0
PFR4
PFR43
0
DDRG
DDRG1
0
PFRG
PFRG1
0
EXBS
MSS
0
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55
CHAPTER 2 Pins of the MB91665 Series
2.4
Pin Name
A04
A05
A06
A07
A16
56
MB91665 Series
Register Name
Bit Name
Written Value
PFR2
PFR24
1
EPFR0
OUT0E2 to OUT0E0
Other than 001 *
DDR4
DDR44
0
PFR4
PFR44
0
EXBS
MSS
0
PFR2
PFR25
1
EPFR0
OUT1E2 to OUT1E0
Other than 001 *
DDR4
DDR45
0
PFR4
PFR45
0
EXBS
MSS
0
PFR2
PFR26
1
EPFR1
OUT2E2 to OUT2E0
Other than 001 *
DDR4
DDR46
0
PFR4
PFR46
0
EXBS
MSS
0
PFR2
PFR27
1
EPFR1
OUT3E2 to OUT3E0
Other than 001 *
DDR4
DDR47
0
PFR4
PFR47
0
EXBS
MSS
0
PFR4
PFR40
1
DDR2
DDR20
0
PFR2
PFR20
0
DDRA
DDRA3
0
PFRA
PFRA3
0
ADCHE
ADE19
1
EXBS
MSS
1
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
Pin Name
A17
A18
A19
A20
A21
A22
CM71-10158-1E
Register Name
Bit Name
Written Value
PFR4
PFR41
1
DDR2
DDR21
0
PFR2
PFR21
0
DDRA
DDRA4
0
PFRA
PFRA4
0
ADCHE
ADE20
1
EXBS
MSS
1
PFR4
PFR42
1
DDR2
DDR22
0
PFR2
PFR22
0
DDRG
DDRG0
0
PFRG
PFRG0
0
EXBS
MSS
1
PFR4
PFR43
1
DDR2
DDR23
0
PFR2
PFR23
0
DDRG
DDRG1
0
PFRG
PFRG1
0
EXBS
MSS
1
PFR4
PFR44
1
DDR2
DDR24
0
PFR2
PFR24
0
EXBS
MSS
1
PFR4
PFR45
1
DDR2
DDR25
0
PFR2
PFR25
0
EXBS
MSS
1
PFR4
PFR46
1
DDR2
DDR26
0
PFR2
PFR26
0
EXBS
MSS
1
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CHAPTER 2 Pins of the MB91665 Series
2.4
Pin Name
A23
MB91665 Series
Register Name
Bit Name
Written Value
PFR4
PFR47
1
DDR2
DDR27
0
PFR2
PFR27
0
EXBS
MSS
1
* : Do not write a setting prohibited value. For details, see "CHAPTER 14 I/O Ports".
•
AS pin
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register (For details of the
multiplexed pins, see the pin assignment diagram).
3. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
4. Set peripheral functions on the PFR register (PFR=1).
Pin Name
AS
•
Register Name
Bit Name
Written Value
PFR5
PFR54
1
DDR3
DDR30
0
PFR3
PFR30
0
CS pins
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register (For details of the
multiplexed pins, see the pin assignment diagram).
3. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
4. Set peripheral functions on the PFR register (PFR=1).
Pin Name
CS0
CS1
CS2
58
Register Name
Bit Name
Written Value
PFR5
PFR50
1
DDRA
DDRA2
0
PFRA
PFRA2
0
ADCHE
ADE18
1
PFR5
PFR51
1
DDRG
DDRG4
0
PFRG
PFRG4
0
PFR5
PFR52
1
EPFR16
bit-2:1
Other than 01 *
DDRG
DDRG5
0
PFRG
PFRG5
0
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
CS3
PFR5
PFR53
1
DDRG
DDRG6
0
PFRG
PFRG6
0
* : Do not write a setting prohibited value. For details, see "CHAPTER 14 I/O Ports".
•
D pins
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register (For details of the
multiplexed pins, see the pin assignment diagram).
3. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
4. Set peripheral functions on the PFR register (PFR=1).
Pin Name
D00
Register Name
Bit Name
Written Value
PFR0
PFR00
1
EPFR6
SOUT0E2 to SOUT0E0
Other than 010*
EPFR20
TIOA0E1, TIOA0E0
Other than 01 *
D01
PFR0
PFR01
1
D02
PFR0
PFR02
1
EPFR6
SCK0E2 to SCK0E0
Other than 010
*
EPFR20
TIOA1E1, TIOA1E0
Other than 01 *
D03
PFR0
PFR03
1
D04
PFR0
PFR04
1
EPFR7
SOUT1E1, SOUT1E0
Other than 01 *
EPFR21
TIOA2E1, TIOA2E0
Other than 01 *
D05
PFR0
PFR05
1
D06
PFR0
PFR06
1
EPFR7
SCK1E1, SCK1E0
Other than 01 *
EPFR21
TIOA3E1, TIOA3E0
Other than 01 *
D07
PFR0
PFR07
1
D08
PFR1
PFR10
1
EPFR8
SOUT2E1, SOUT2E0
Other than 01 *
D09
PFR1
PFR11
1
D10
PFR1
PFR12
1
EPFR8
SCK2E1, SCK2E0
Other than 01 *
PFR1
PFR13
1
D11
CM71-10158-1E
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CHAPTER 2 Pins of the MB91665 Series
2.4
Pin Name
D12
D13
D14
D15
MB91665 Series
Register Name
Bit Name
Written Value
PFR1
PFR14
1
DDR3
DDR34
0
PFR3
PFR34
0
PFR1
PFR15
1
DDR3
DDR35
0
PFR3
PFR35
0
PFR1
PFR16
1
DDR3
DDR36
0
PFR3
PFR36
0
PFR1
PFR17
1
DDR3
DDR37
0
PFR3
PFR37
0
* : Do not write a setting prohibited value. For details, see "CHAPTER 14 I/O Ports".
•
RD pin
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
3. Set peripheral functions on the PFR register (PFR=1).
Pin Name
RD
•
Register Name
Bit Name
Written
Value
PFR5
PFR55
1
DDR3
DDR31
0
PFR3
PFR31
0
RDY pin
1. Set the port inputs on the DDR register (DDR=0).
2. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
Pin Name
RDY
60
Register Name
Bit Name
Written
Value
DDR6
DDR60
0
DDRG
DDRG2
0
PFRG
PFRG2
0
DDRH
DDRH0
0
PFRH
PFRH0
0
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 2 Pins of the MB91665 Series
2.4
MB91665 Series
•
SYSCLK pin
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
3. Set peripheral functions on the PFR register (PFR=1).
Pin Name
SYSCLK
•
Register Name
Bit Name
Written
Value
PFR6
PFR61
1
DDRG
DDRG3
0
DDRH
DDRH1
0
WR0 and WR1 pins
1. Set the port inputs on the DDR register and the PFR register (DDR=0, PFR=0).
2. Disable the output of peripheral functions that share this pin with the EPFR register (For details of the
multiplexed pins, see the pin assignment diagram).
3. Set an external bus interface (For details, see "CHAPTER 13 External Bus Interface").
4. Set peripheral functions on the PFR register (PFR=1).
Pin Name
WR0
WR1
Register Name
Bit Name
Written
Value
PFR5
PFR56
1
DDR3
DDR32
0
PFR3
PFR32
0
PFR5
PFR57
1
DDRG
DDRG7
0
DDRA
DDRA7
0
PFRA
PFRA7
0
ADCHE
ADE23
1
<Note>
Complete all the settings of the registers above before access the external bus.
If accessing is performed before completion of the settings, unintended waveform may be output.
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 2 Pins of the MB91665 Series
2.4
62
FUJITSU SEMICONDUCTOR LIMITED
MB91665 Series
CM71-10158-1E
CHAPTER 3 CPU
This chapter explains the basics of the FR80 family CPUs,
including its architecture, specifications, and instructions, to
provide a better understanding of the CPU functions.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
CM71-10158-1E
Memory Space
Features of the Internal Architecture
Operation Modes
Pipeline
Overview of Instructions
Basic Programming Model
Registers
Data Configuration
Addressing
Branch Instructions
EIT (Exception, Interrupt, Trap)
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 3 CPU
3.1
3.1
MB91665 Series
Memory Space
The logical address space of the FR80 family CPUs is 4 GB (232 locations), and the CPUs can
linearly access it.
■ Direct addressing areas
The address spaces 0000 0000H to 0000 03FFH are called the direct addressing areas.
These areas allow operands to be specified directly in instructions.
The direct addressing areas vary as follows depending on the size of the data accessed:
64
•
Byte data access: 0000 0000H to 0000 00FFH
•
Half word data access: 0000 0000H to 0000 01FFH
•
Word data access: 0000 0000H to 0000 03FFH
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 3 CPU
3.1
MB91665 Series
■ Memory map
Figure 3.1-1 shows a memory map of the MB91665 series.
Figure 3.1-1 Memory map
MB91F668/F669
Flash 128 Kbytes
RAM 16 Kbytes
0000 0000H
I/O area
(Direct addressing)
0000 0400H
I/O area
0001 0000H
Reserved
0003 C000H
Internal RAM area
16 Kbytes
0004 0000H
Reserved
000E 0000H
Flash area 128 Kbytes
0010 0000H
Reserved
0024 0000H
External bus area
FFFF FFFFH
<Notes>
•
For details of the small-sector area in flash memory, see "CHAPTER 34 Flash Memory".
The small-sector area concerns only the flash memory products.
•
Do not access the reserved areas.
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
65
CHAPTER 3 CPU
3.2
3.2
MB91665 Series
Features of the Internal Architecture
The FR80 family CPUs have a high-performance core based on the RISC architecture with high-level
functions and instructions included for embedded applications.
•
Adoption of the RISC architecture
Basic instructions: 1 instruction/1 cycle
•
32-bit architecture
16 general-purpose 32-bit registers
•
Linearly accessed 4-GB memory space
•
Built-in multipliers
•
-
32-bit × 32-bit multiplication: 5 cycles
-
16-bit × 16-bit multiplication: 3 cycles
Enhanced interrupt processing functions
-
•
•
High-speed response (6 cycles)
-
Multi-interrupt support
-
Level mask function (16 levels)
Enhanced instructions for I/O operations
-
Memory-to-memory transfer instruction
-
Bit processing instruction
High code efficiency
-
Basic instruction word length: 16 bits
•
Compatibility of basic instructions with the FR60 family
•
Addition of the following instructions to the instructions of the FR60 family:
-
•
•
Bit search instructions (SRCH0, SRCH1, and SRCHC)
Deletion of the following instructions from the instructions of the FR60 family:
-
Coprocessor instructions (COPOP, COPLD, COPST, and COPSV)
-
Resource instructions (LDRES and STRES)
Non-blocking load
Up to 4 load instructions can be issued in advance.
66
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 3 CPU
3.3
MB91665 Series
3.3
Operation Modes
This section explains the operation modes of this series.
This series provides the operation modes below. At an activation of the device, one of these operation
modes can be selected.
•
User single-chip mode
•
Serial programming mode
Table 3.3-1 lists the operation modes of this series.
Table 3.3-1 Operation modes
MD Pin
MD1
0
CM71-10158-1E
Control Pin
MD0
Operation Mode
P75
0
X
User single-chip mode
1
1
Serial programming mode
FUJITSU SEMICONDUCTOR LIMITED
67
CHAPTER 3 CPU
3.4
3.4
MB91665 Series
Pipeline
The FR architecture of the FR80 family CPUs is a compact 32-bit RISC architecture.
It has not only the normal instruction execution pipeline but also an additional pipeline for loading
memory, which can reduce pipeline hazards during load instruction execution.
A five-stage instruction pipeline method is used in executing 1 instruction per cycle. The pipeline
consists of the following stages:
•
Instruction fetch (IF) stage: Fetches the instruction at the output address.
•
Instruction decode (ID) stage: Decodes the fetched instruction. It also reads a register.
•
Execution (EX) stage: Executes the decoded instruction.
•
Memory access (MA) stage: Accesses the target memory.
•
Register writing (WB) stage: Writes the operation results (or loaded memory data) to a register.
The pipeline for loading memory has been added so that the MA and WB stages of the instruction, which
does not access memory, can overlap the MA and WB stages of an LD instruction.
As a rule, 1 instruction is executed per cycle. However, more than one cycle is required for execution of
a load/store instruction with memory wait, a branch instruction without a delay slot, or a multi-cycle
instruction. In addition, the instruction execution speed is slower when there is a delay in supplying an
instruction.
Example 1:
CLK
(1)
LD
@R10,R1
(2)
LDI:8
#0x02,R2
(3)
CMP
R1, R2
(4)
BNE:D
Label_G
(5)
ADD
#0x1,R1
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
Example 1: The instructions are executed in sequence because the data that uses R1 to write the (1) LD
instruction is returned in the (3) CMP instruction within 1 cycle.
In the load operation, the MA stage is extended until reading of the loaded data is completed.
However, if the register used for loading will not be used for the subsequent instructions, the instruction is
executed as is.
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Example 2:
CLK
(1)
LD
@R10,R1
(2)
LDI:8
#0x02,R2
(3)
CMP
R1, R2
(4)
BNE:D
Label_G
(5)
ADD
#0x1,R1
IF
ID
EX
MA
MA
MA
WB
IF
ID
EX
MA
WB
IF
ID
ID
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
Example 2: The data that uses R1 to write the (1) LD instruction is not returned within 1 cycle in the (3) CMP
instruction, resulting in execution only up to the (2) LDI:8 instruction and keeping the CMP
instruction waiting in the ID stage because of a register conflict.
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3.5
MB91665 Series
Overview of Instructions
In addition to the general RISC instruction set, the FR80 family CPUs support the logical operations
optimized for embedded applications, bit operation instructions, and direct addressing instructions.
Each instruction has a length of 16 bits (some instructions have a length of 32 or 48 bits) and provides
superior performance in memory usage efficiency.
The instruction sets can be divided into the following function groups:
3.5.1
•
Arithmetic operation
•
Load and store
•
Branch
•
Logical operation and bit operation
•
Direct addressing
•
Bit search
•
Other
Arithmetic Operation
These instructions are standard arithmetic instructions (addition, subtraction, and comparison) and shift
instructions (logical shift and arithmetic operation shift). The arithmetic operations of addition and
subtraction can include operations with a carry used in individual operations with a multi-word length
(operation for 32 or more bits of data) and operations suitable for address calculation in which flag values
are not changed.
Also included in these instructions are the 32-bit × 32-bit multiplication instruction, 16-bit × 16-bit
multiplication instruction, and 32-bit / 32-bit step division instruction.
The immediate transfer instruction that sets immediate data in a register and the register-to-register
transfer instruction are also included.
All the operations of arithmetic operation instructions use the general-purpose registers and Multiply &
Divide registers in the CPUs.
3.5.2
Load and Store
Load and store are instructions for reading and writing external memory. They are also used for reading
and writing by the internal peripheral functions of the chip.
The access lengths of load and store are in any of 3 units: byte, half word, and word. In addition to
general-purpose register indirect memory addressing, some load and store instructions can use register
indirect memory addressing with either displacement or register increment/decrement operations.
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3.5.3
Branch
Branch instructions include branch, call, interrupt, and return instructions. The branch instructions
consist of instructions with delay slots and instructions without delay slots, and they can be optimized as
required. For details of the branch instructions, see "3.10 Branch Instructions".
3.5.4
Logical Operation and Bit Operation
Logical operation instructions can perform the AND, OR, and EOR logical operations between generalpurpose registers or between a general-purpose register and memory (and I/O). Also, bit operation
instructions can directly manipulate data on memory (and of I/O).
Memory addressing is general-purpose register indirect memory addressing.
3.5.5
Direct Addressing
Direct addressing instructions are instructions used for access between I/O and a general-purpose register
or between I/O and memory. Specifying an I/O address directly in an instruction instead of using register
indirect addressing enables highly efficient high-speed access. Also, some direct addressing instructions
can perform register indirect memory addressing with register increment/decrement operations.
3.5.6
Bit Search
A bit search instruction searches 32-bit data beginning from the MSB to obtain the bit location of the first
"1" or "0" found in the register. A bit search instruction can also make a comparison with the MSB value
and obtain the bit location of a value different from the first MSB found in a register.
3.5.7
Other
Other available instructions include those for setting flags in the PS register, performing stack operations,
and making a carry/zero extension. Also included in these instructions are function entry/exit instructions
supporting high-level languages and multi-load/store instructions for registers.
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Basic Programming Model
Figure 3.6-1 shows the basic programming model.
Figure 3.6-1 Basic programming model
32 bits
Initial value
General-purpose
registers
R0
XXXX XXXXH
R1
XXXX XXXXH
R2
XXXX XXXXH
R3
XXXX XXXXH
R4
XXXX XXXXH
R5
XXXX XXXXH
R6
XXXX XXXXH
R7
XXXX XXXXH
R8
XXXX XXXXH
R9
XXXX XXXXH
R10
XXXX XXXXH
R11
XXXX XXXXH
R12
XXXX XXXXH
R13
AC
XXXX XXXXH
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter (PC)
XXXX XXXXH
Program status (PS)
72
-
ILM
-
SCR
CCR
Table base register (TBR)
000F FC00H
Return pointer (RP)
XXXX XXXXH
System stack pointer (SSP)
0000 0000H
User stack pointer (USP)
XXXX XXXXH
Multiply &
Divide
register
(MDH)
XXXX XXXXH
(MDL)
XXXX XXXXH
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3.7
Registers
The register configuration consists of general-purpose registers and dedicated registers for specific
purposes.
3.7.1
General-purpose Registers (R0 to R15)
Registers R0 to R15 are general-purpose registers. They are used as accumulators and memory
access pointers in a variety of operations.
Figure 3.7-1 shows the bit configuration of the general-purpose registers (R0 to R15).
Figure 3.7-1 Bit configuration of the general-purpose registers (R0 to R15)
32 bits
Initial value
R0
XXXX XXXXH
R1
XXXX XXXXH
R2
XXXX XXXXH
R3
XXXX XXXXH
R4
XXXX XXXXH
R5
XXXX XXXXH
R6
XXXX XXXXH
R7
XXXX XXXXH
R8
XXXX XXXXH
R9
XXXX XXXXH
R10
XXXX XXXXH
R11
XXXX XXXXH
R12
XXXX XXXXH
R13
AC
XXXX XXXXH
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Of the 16 registers, the following registers are assumed to have specific purposes, and certain instructions
have therefore been enhanced. For details of the initial values at the reset time, see Figure 3.7-1.
•
R13: Virtual accumulator (AC)
•
R14: Frame pointer (FP)
•
R15: Stack pointer (SP)
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3.7.2
MB91665 Series
Program Status Register (PS)
This register retains the program status, and it is divided into 3 parts: interrupt level mask register
(ILM), system condition code register (SCR), and condition code register (CCR).
Figure 3.7-2 shows the bit configuration of the program status register (PS).
Figure 3.7-2 Bit configuration of the program status register (PS)
bit
31
21 20
Undefined
16 15
ILM
11 10
Undefined
8
SCR
7
0
CCR
[bit31 to bit21, bit15 to bit11]: Undefined bits
In case of writing
Ignored
In case of reading
"0" is always read.
[bit20 to bit16] Interrupt level mask register (ILM)
See "■ Interrupt level mask register (ILM)".
[bit10 to bit8] System condition code register (SCR)
See "■ System condition register (SCR)".
[bit7 to bit0] Condition code register (CCR)
See "■ Condition code register (CCR)".
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■ Condition code register (CCR)
Figure 3.7-3 shows the bit configuration of the condition code register (CCR).
Figure 3.7-3 Bit configuration of the condition code register (CCR)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
S
I
N
Z
V
C
Attribute
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Initial
value
0
0
0
0
X
X
X
X
R/W: Read/Write
-: Undefined
X: Undefined
[bit7, bit6]: Undefined bits
In case of writing
Ignored
In case of reading
"0" is always read.
[bit5]: S (Stack flag)
This bit specifies a stack pointer operating as general-purpose register 15 (R15).
S
Explanation
0
The system stack pointer (SSP) is operating as general-purpose register 15 (R15).
The bit is automatically cleared to "0" when EIT occurs.
(However, the value before the bit is cleared is saved to the stack.)
1
The user stack pointer (USP) is operating as general-purpose register 15 (R15).
This bit is cleared to "0" when the system is reset.
"0" must be written when the RETI instruction is executed.
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[bit4]: I (Interrupt enable flag)
This bit controls enabling/disabling of user interrupt requests.
I
Explanation
0
Disables user interrupt requests.
The bit is automatically cleared to "0" when the INT instruction is executed.
(However, the value before the bit is cleared is saved to the stack.)
1
Enables user interrupt requests.
The mask processing of user interrupt requests is controlled with the value
retained by the interrupt level mask register (ILM).
This bit is cleared to "0" when the system is reset.
[bit3]: N (Negative flag)
This bit indicates a carry for an operation result recognized as an integer represented by a 2's complement.
N
Explanation
0
Indicates that the operation result is a positive value.
1
Indicates that the operation result is a negative value.
The initial state set by a reset is undefined.
[bit2]: Z (Zero flag)
This bit indicates whether the result of an operation is "0".
Z
Explanation
0
Indicates that the operation result is not "0".
1
Indicates that the operation result is "0".
The initial state set by a reset is undefined.
[bit1]: V (Overflow flag)
This bit indicates whether an overflow occurred as a result of an operation by interpreting each operand
used for the operation as integers represented by 2's complements.
V
Explanation
0
No overflow occurred as a result of the operation.
1
An overflow occurred as a result of the operation.
The initial state set by a reset is undefined.
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[bit0]: C (Carry flag)
This bit indicates whether a carry or borrow from the most significant bit occurred as a result of an
operation.
C
Explanation
0
No carry or borrow occurred.
1
A carry or borrow occurred.
The initial state set by a reset is undefined.
■ System condition register (SCR)
Figure 3.7-4 shows the bit configuration of the system condition register (SCR).
Figure 3.7-4 Bit configuration of the system condition register (SCR)
bit
Attribute
Initial
value
10
9
8
D1
D0
T
R/W
R/W
R/W
X
X
0
R/W: Read/Write
X: Undefined
[bit10, bit9]: D1, D0 (Step division flag)
These bits retain in-process data during step division execution.
Do not change these bits while division processing is being executed.
To execute any other processing during step division, save and return the value of the program status
register (PS). Doing so ensures a restart of step division.
The initial state set by a reset is undefined.
<Notes>
•
The bits are set with the reference of the dividend and divisor by execution of the DIV0S
instruction.
•
They are forcibly cleared by execution of the DIV0U instruction.
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[bit8]: T (Step trace trap flag)
This bit specifies whether the step trace trap is enabled.
T
Explanation
0
The step trace trap is disabled.
1
The step trace trap is enabled.
All user interrupt requests are disabled.
This bit is cleared to "0" when the system is reset.
Emulators use the step trace trap function. The step trace trap cannot be used in a user program together
with an emulator.
■ Interrupt level mask register (ILM)
This register retains the interrupt level mask value. The value retained by the register is used for the level
mask.
Figure 3.7-5 shows the bit configuration of the interrupt level mask register (ILM).
Figure 3.7-5 Bit configuration of the interrupt level mask register (ILM)
bit
Attribute
Initial
value
20
19
18
17
16
ILM4
ILM3
ILM2
ILM1
ILM0
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
R/W: Read/Write
An interrupt request that is input to the CPU is accepted only if the corresponding interrupt level is higher
than the level specified by this register.
The highest level is "0" (00000B), and the lowest is "31" (11111B).
A limited range of values can be set from programs.
•
Original value in a range of 16 to 31: A value ranging from 16 to 31 can be specified as a new value. If
a value ranging from 0 to 15 is set for an instruction, (specified-value + 16) is transferred when the
instruction is executed.
•
Original value in a range of 0 to 15: Any value ranging from 0 to 31 can be specified.
These bits are initialized to "15" (01111B) by a reset.
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3.7.3
Program Counter (PC)
This register is the program counter (PC) indicating the address of the instruction being executed.
Figure 3.7-6 shows the bit configuration of the program counter (PC).
Figure 3.7-6 Bit configuration of the program counter (PC)
bit
31
0
Initial value
XXXX XXXXH
bit0 is set to "0" when an instruction that entails a PC update is executed.
It is prohibited to specify an odd-numbered location as the branch destination address, and to set bit0 to
"1".
The instruction would have to be located at an address that is a multiple of 2.
The initial value following a reset is undefined, and the program start address is set by a reset vector
fetch.
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3.7.4
MB91665 Series
Table Base Register (TBR)
This register retains the start address of the vector table used for EIT processing.
Figure 3.7-7 shows the bit configuration of the table base register (TBR).
Figure 3.7-7 Bit configuration of the table base register (TBR)
bit
31
0
Initial value
000F FC00H
The initial value following a reset is "000F FC00H".
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3.7.5
Return Pointer (RP)
This pointer retains the return destination address when returning from a subroutine.
Figure 3.7-8 shows the bit configuration of the return pointer (RP).
Figure 3.7-8 Bit configuration of the return pointer (RP)
bit
31
0
Initial value
XXXX XXXXH
The value of the program counter (PC) is transferred to this register when the CALL instruction is
executed.
The register contents are transferred to the program counter (PC) when the RET instruction is executed.
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3.7.6
MB91665 Series
System Stack Pointer (SSP)
This pointer operates as R15 when the S flag of the condition code register (CCR) is "0".
Also, the system stack pointer (SSP) can be specified explicitly.
It can be used as a stack pointer specifying the stack for saving the program status register (PS) and
the program counter (PC) when EIT occurs.
Figure 3.7-9 shows the bit configuration of the system stack pointer (SSP).
Figure 3.7-9 Bit configuration of the system stack pointer (SSP)
bit
31
0
Initial value
0000 0000H
The initial value following a reset is "0000 0000H".
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3.7.7
User Stack Pointer (USP)
This pointer operates as R15 when the S flag of the condition code register (CCR) is "1".
Also, the user stack pointer (USP) can be specified explicitly.
Figure 3.7-10 shows the bit configuration of the user stack pointer (USP).
Figure 3.7-10 Bit configuration of the user stack pointer (USP)
bit
31
0
Initial value
XXXX XXXXH
The initial value following a reset is undefined.
This pointer cannot be used in the RETI instruction.
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3.7.8
MB91665 Series
Multiply & Divide Registers
These registers are used for multiplication and division, and each register has a length of 32 bits.
Figure 3.7-11 Bit configuration of the Multiply & Divide registers
bit
31
0
Initial value
MDH
XXXX XXXXH
MDL
XXXX XXXXH
The initial value following a reset is undefined.
● In multiplication
In multiplication of 32 bits × 32 bits, the result of an operation with a length of 64 bits is stored in the
Multiply & Divide registers at the following locations:
•
MDH: Upper 32 bits
•
MDL: Lower 32 bits
In multiplication of 16 bits × 16 bits, the result is stored as follows:
•
MDH: Undefined
•
MDL: 32-bit result
● In division
The dividend is stored in MDL at the start of calculation.
In division according to the DIV0S, DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction, the result is
stored in MDH and MDL:
84
•
MDH: Remainder
•
MDL: Quotient
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3.8
Data Configuration
Data is arranged in the FR80 family CPUs in the following two ways:
• Bit Ordering
• Byte Ordering
3.8.1
Bit Ordering
The FR80 family CPUs use little endian for bit ordering.
Figure 3.8-1 shows the bit ordering.
Figure 3.8-1 Bit ordering
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
MSB
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5
4
3
2
1
0
LSB
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3.8.2
MB91665 Series
Byte Ordering
The FR80 family CPUs use big endian for byte ordering.
Figure 3.8-2 shows the byte ordering.
Figure 3.8-2 Byte ordering
MSB
LSB
bit31
10101010
bit23
bit15
11001100
bit7
11111111
bit0
00010001
bit
7
86
0
Location n
10101010
Location (n+1)
11001100
Location (n+2)
11111111
Location (n+3)
00010001
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3.8.3
Word Alignment
■ Program access
Programs for the FR80 family CPUs must be located at addresses that are multiples of 2. bit0 of the
program counter (PC) is set to "0" when an instruction that entails the program counter (PC) update is
executed. It is prohibited to specify an odd-numbered location as the branch destination address, and to
set bit0 to "1".
The instruction would have to be located at an address that is a multiple of 2.
There is no odd-numbered address exception.
■ Data access
For an accessing of data in the FR80 family, set the address depending on the size of the data accessed as
shown below. (The address is not aligned by the hardware.)
Word access: The address is a multiple of 4 (the lowest 2 bits are set to "00").
Half word access: The address is a multiple of 2 (the lowest bit is set to "0").
Byte access: ---During a word or half word data access, set the above address for the result from a calculation of the
effective address.
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Addressing
The memory space consists of linear 32-bit addresses.
Figure 3.9-1 shows the memory space.
Figure 3.9-1 Memory Space
0000 0000H
Byte data
0000 0100H
Direct addressing
areas
Half word data
0000 0200H
Word data
0000 0400H
TBR
20-bit addressing
area
000F FC00H
Vector table
000F FFFFH
32-bit addressing area
FFFF FFFFH
3.9.1
Direct Addressing Areas
The memory space areas listed below are areas for I/O. Direct addressing enables these areas to be
specified directly as operand addresses in instructions.
The size of an address area that can be specified by a direct address varies depending on the data length.
88
•
Byte data (8 bits): 0 to 0x0FF
•
Half word data (16 bits): 0 to 0x1FF
•
Word data (32 bits): 0 to 0x3FF
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3.9.2
20-bit Addressing Area
20-bit addressing area: 0 to 0xFFFFF
If all the program and data areas are located in the 20-bit addressing area, programs will be more compact
and therefore have high performance after compilation.
An example of expansion of a normal 20-bit branch macro instruction is shown below.
BRA20
label20,Ri
↓
Code size
LDI:20
#label20,Ri
; 4 bytes
JMP
@Ri
; 2 bytes
Total: 6 bytes
For details, see the "FR FAMILY SOFTUNE C/C++ COMPILER MANUAL for V6".
3.9.3
32-bit Addressing Area
32-bit addressing area: 0 to 0xFFFFFFFF
If the program and data areas are located beyond the 20-bit addressing area, the code sizes of programs
will be larger than those of programs created in the 20-bit addressing area.
An example of expansion of a normal 32-bit branch macro instruction is shown below.
BRA32
label32,Ri
↓
Code size
LDI:32
#label32,Ri
; 6 bytes
JMP
@Ri
; 2 bytes
Total: 8 bytes
For details, see the "FR FAMILY SOFTUNE C/C++ COMPILER MANUAL for V6".
3.9.4
Vector Table Initial Area
The area from 000F FC00H to 000F FFFFH is the EIT vector table initial area.
The vector table used for EIT processing can be placed at an arbitrary address by changing the table base
register (TBR) accordingly, but the initial address following a reset is the above address.
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3.10 Branch Instructions
Operation with delay slots and operation without delay slots can be specified for branch instructions in
the FR80 family CPUs.
3.10.1
Operation with Delay Slots
■ Instructions
The following instructions perform branch operations with delay slots:
JMP:D
@Ri
/
CALL:D
label12
/
CALL:D
@Ri
/
RET:D
BRA:D
label9
/
BNO:D
label9
/
BEQ:D
label9
/
BNE:D
label9
BC:D
label9
/
BNC:D
label9
/
BN:D
label9
/
BP:D
label9
BV:D
label9
/
BNV:D
label9
/
BLT:D
label9
/
BGE:D
label9
BLE:D
label9
/
BGT:D
label9
/
BLS:D
label9
/
BHI:D
label9
■ Explanation of operation
The instruction that is located immediately following a branch instruction (the location is called a "delay
slot") is executed before branching, and an instruction at the branch destination is executed after that.
Because the instruction in the delay slot is executed before the branch operation, the apparent execution
speed is 1 cycle. Such being the case, if no valid instruction can be entered in the delay slot, the NOP
instruction must be placed there instead.
Example:
;
Order of instructions
ADD
R1, R2;
BRA:D
LABEL
; Branch instruction
MOV
R2, R3
; Delay slot
R3, @R4
; Branch destination
...... Executed before branching
...
LABEL:
ST
The conditional branch instruction that is located in the delay slot is executed whether the branch
condition is satisfied or not.
Although the sequence of execution of some instructions seems to be inverted for delay branch
instructions, the sequence is inverted only when the program counter (PC) is updated. Any other
operations, such as updating or referencing a register, are executed in the sequence described.
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Concrete explanations are given below.
1. Ri referenced by the JMP:D @Ri / CALL:D @Ri instruction is not affected even when updated by the
instruction in a delay slot.
Example:
LDI:32
#Label, R0
JMP:D
@R0
; Branching to Label
LDI:8
#0, R0
; The branch destination address is not affected.
...
2. The return pointer (RP) referenced by the RET:D instruction is not affected even when the instruction
in a delay slot updates the return pointer (RP).
Example:
RET:D
; Branching to the address indicated by the RP
specified beforehand
MOV
R8, RP
; The return operation is not affected.
...
3. The flag referenced by the Bcc:D rel instruction is not affected by the instruction in a delay slot either.
Example:
ADD
#1, R0
; Flag change
BC:D
Overflow
; Branching according to the execution result of the
above instruction
ANDCCR
#0
; This flag update is not referenced in the above
branch instruction.
...
4. When the RP is referenced in an instruction in the delay slot of the CALL:D instruction, the updated
contents are read by the CALL:D instruction.
Example:
CALL:D
Label
; RP update and branching
MOV
RP, R0
; Transfer of the RP of the execution result for the
above CALL:D
...
■ Instructions that can be placed in delay slots
Only instructions that satisfy the following conditions can be executed in delay slots:
•
1-cycle instruction
•
Not a branch instruction
•
Instruction that does not affect operations even if the order of execution is changed
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■ Step trace trap
No step trace trap occurs between execution of a branch instruction with a delay slot and the delay slot.
■ Interrupts
No interrupt is accepted between execution of a branch instruction with a delay slot and the delay slot.
■ Undefined instruction exception
If the instruction except for BNO:D instruction in a delay slot is undefined, no undefined instruction
exception occurs. In such cases, the undefined instruction operates as the NOP instruction.
<Note>
Do not place an undefined instruction in a delay slot of BNO:D instruction.
3.10.2
Operation without Delay Slots
■ Instructions
The following instruction performs branch operations without delay slots:
JMP
@Ri
/
CALL
label12
/
CALL
@Ri
/
RET
BRA
label9
/
BNO
label9
/
BEQ
label9
/
BNE
label9
BC
label9
/
BNC
label9
/
BN
label9
/
BP
label9
BV
label9
/
BNV
label9
/
BLT
label9
/
BGE
label9
BLE
label9
/
BGT
label9
/
BLS
label9
/
BHI
label9
■ Explanation of operation
Instructions are executed in the order they are listed. No instruction that is coded immediately following a
branch instruction is executed before branching.
Example:
;
Order of instructions
ADD
R1, R2
;
BRA
LABEL
; Branch instruction (without a delay slot)
MOV
R2, R3
; Not executed
R3, @R4
; Branch destination
...
LABEL
ST
The number of execution cycles of a branch instruction without a delay slot is 2 cycles if there is
branching and 1 cycle if there is no branching.
Such operation increases the instruction code efficiency compared with that of branch instructions with
delay slots in which NOP is clearly written because appropriate instructions cannot be placed in the delay
slots.
If valid instructions can be placed in delay slots, select operation with delay slots; otherwise, select
operation without delay slots. Doing so can balance execution speed with code efficiency.
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3.11 EIT (Exception, Interrupt, Trap)
EIT stands for Exception, Interrupt, and Trap. It indicates that the event that occurred results in
suspension of execution of the current program, and the execution of another program.
An exception is an event that occurs in connection with the context being executed. The processing is
reexecuted beginning with the instruction that causes an exception.
An interrupt is an event that occurs independently of the context being executed. The source of events
is hardware.
A trap is an event that occurs in connection with the context being executed. Some traps occur as
instructed in programs such as a system call. The instruction following the instruction that generates a
trap is reexecuted first.
■ Features
3.11.1
•
Multi-EIT support
•
Level mask function for interrupts (A user can use 15 levels.)
•
Trap instructions (INT/INTE)
•
EIT for emulator activation (hardware/software)
EIT Sources
EIT sources include the following:
3.11.2
•
Reset
•
User interrupt (peripheral functions, external interrupts)
•
Delay interrupt
•
Undefined instruction exception
•
Trap instruction (INT)
•
Trap instruction (INTE)
•
Step trace trap
Return from EIT
The return from each EIT is through the RETI instruction.
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3.11.3
MB91665 Series
Interrupt Level
The interrupt levels are 0 to 31, and they are controlled in units of 5 bits.
Table 3.11-1 lists the assignment of each level.
Table 3.11-1 Interrupt level assignment table
Level
Interrupt Type
Binary
number
Decimal
number
00000
0
(Reserved for system)
...
...
...
...
...
...
00011
3
(Reserved for system)
00100
4
INTE instruction
Step trace trap
00101
5
(Reserved for system)
...
...
...
...
...
...
01100
14
(Reserved for system)
01101
15
(Reserved for system)
10000
16
Interrupt request
10001
17
Interrupt request
...
...
...
...
...
...
11110
30
Interrupt request
11111
31
-
Remarks
If the original value of the interrupt level mask
register (ILM) is in a range of 16 to 31, no
value in this range can be specified for the
interrupt level mask register (ILM) from the
program.
When the interrupt level mask register (ILM)
is set, user interrupts must be disabled.
If the interrupt control register (ICR) is set,
interrupts are disabled.
The operations are enabled only if the level is in a range of 16 to 31.
The interrupt level does not affect undefined instruction exceptions and the INT instruction. It does not
change the interrupt level mask register (ILM) either.
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3.11.4
I Flag
This flag specifies whether interrupts are enabled or disabled. It is provided as bit4 of the condition code
register (CCR) in the program status register (PS).
I
Explanation
0
The bit is automatically cleared to "0" when the INT instruction is executed.
(However, the value that is saved to the stack is that immediately before the bit is
cleared.)
1
The mask processing of user interrupt requests is controlled with the value retained by
the interrupt level mask register (ILM).
<Note>
After an instruction changes the value of the I flag, interrupt requests can be accepted beginning
from the instruction after the next instruction.
Therefore, to operate interrupts properly, NOP must be placed after the instruction that changes
the I flag value.
•
Enabling interrupts (I flag = 1)
Instruction
execution
↓
•
I flag
Interrupts
ORCCR #set_iflag
0
Disabled
NOP
1
Disabled
Instruction A
1
Enabled
I flag
Interrupts
ANDCCR #clear_iflag
1
Enabled
NOP
0
Enabled
Instruction A
0
Disabled
↑
Starts enabling interrupts
Disabling interrupts (I flag = 0)
Instruction
execution
↓
↑
Starts disabling interrupts
If an interrupt is received while executing an instruction to set I flag to "0", there is a delay for 1 cycle
from execution of an instruction for I flag and ILM to change. Therefore, I flag becomes "0" although
processing moves to the interrupt processing routine.
At this time, if multiple interrupts are generated, I flag can not receive any interrupt because it is "0", and
processing of multiple interrupts is not performed.
I flag itself is updated when executing an instruction. Therefore, a value of I flag after update is saved to
the stack, and when the value of the stack is returned, the value of I flag after update is reflected to PS
register.
To receive a new interrupt within the interrupt routine, it is required to set software to make I flag to "1"
at the beginning of the interrupt routine.
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3.11.5
MB91665 Series
Interrupt Level Mask Register (ILM)
This register retains the interrupt level mask value. The register is provided as bit20 to bit16 of the
program status register (PS).
An interrupt request that is input to a CPU in the FR80 family CPUs is accepted only if the corresponding
interrupt level is higher than the level specified by the interrupt level mask register (ILM).
The highest level is "0" (00000), and the lowest is "31" (11111).
A limited range of values can be set from programs. If the original value is in a range of 16 to 31, a value
ranging from 16 to 31 can be specified as a new value. If a value ranging from 0 to 15 is set for an
instruction, (specified-value + 16) is transferred when the instruction is executed.
If the original value is in a range of 0 to 15, any value ranging from 0 to 31 can be specified. Use the
STILM instruction for this setting.
<Note>
After an instruction changes the value of the interrupt level mask register (ILM), interrupt requests
can be accepted beginning from the instruction after the next instruction.
Therefore, to operate interrupts properly, NOP must be placed after the instruction that changes
the interrupt level mask register (ILM).
ILM
Instruction
execution
↓
3.11.6
Interrupt
Accepted
SETILM #set_ILM_B
A
A
NOP
B
A
Instruction C
B
B
↑
Instruction D
B
B
Starts enabling ILM=B.
Level Mask for Interrupts
When an interrupt request is generated, the interrupt level of the interrupt source is compared with the
level mask value retained by the interrupt level mask register (ILM). Then, if the following condition is
satisfied, the source is masked and the request is not accepted:
Interrupt level of source ≥ Level mask value
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3.11.7
Interrupt Control Register (ICR)
See "CHAPTER 10 Interrupt Controller".
3.11.8
System Stack Pointer (SSP)
This pointer indicates the stack used for saving or restoring data, when EIT has been received or the
return operation is performed.
Figure 3.11-1 shows the bit configuration of the system stack pointer (SSP).
Figure 3.11-1 Bit configuration of the system stack pointer (SSP)
bit
31
0
Initial value
0000 0000H
"8" is subtracted during EIT processing, and "8" is added at the time of return from EIT with the RETI
instruction executed.
The initial value following a reset is "0000 0000H".
This pointer operates as general-purpose register R15 when the S flag of the condition code register
(CCR) is "0".
3.11.9
Interrupt Stack
The interrupt stack is the area specified by the system stack pointer (SSP). It saves and restores the
values of the program counter (PC) and the program status register (PS). After an interrupt, the value
of the program counter (PC) is stored in the address specified by the system stack pointer (SSP), and
the value of the program status register (PS) is stored in the address specified by the system stack
pointer (SSP) plus 4.
Figure 3.11-2 shows the interrupt stack.
Figure 3.11-2 Interrupt stack
Before an interrupt
SSP
8000 0000H
After an interrupt
SSP
Memory
7FFF FFF8H
Memory
8000 0000H
8000 0000H
7FFF FFFCH
7FFF FFFCH
PS
7FFF FFF8H
7FFF FFF8H
PC
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3.11.10
MB91665 Series
Table Base Register (TBR)
This register indicates the start address of the vector table used for EIT processing.
Figure 3.11-3 shows the bit configuration of the table base register (TBR).
Figure 3.11-3 Bit configuration of the table base register (TBR)
bit
31
0
Initial value
000F FC00H
A vector address is the table base register (TBR) value plus the offset value assigned to each EIT source.
The initial value following a reset is "000F FC00H".
3.11.11
EIT Vector Table
The vector area for EIT processing is the 1-KB area from the address specified by the table base
register (TBR).
The size of 1 vector is 4 bytes, and the relationship between interrupt vector numbers and vector
addresses is expressed as follows:
vctadr
= TBR + vctofs
= TBR + (0x3FC - 4 × vct)
vctadr: Vector address vctofs: Vector offset vct: Interrupt vector number
TBR: Table base register
The lowest 2 bits of the addition result are always handled as "00".
The initial area of the vector table following a reset is the area from 000F FC00H to 000F FFFFH.
Specific functions are assigned to part of the vectors.
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3.11.12
Multi-EIT Processing
If multiple EIT sources occur at one time, the CPU selectively selects and accepts 1 EIT source, executes
the EIT sequence, detects EIT sources again, and then repeats these actions. When no more detected EIT
sources can be accepted, the CPU executes the handler instruction of the last EIT source accepted.
Therefore, if multiple EIT sources occur at one time, the sequence in which the handler of each source is
executed depends on the following:
1. Priority in which EIT sources are accepted
2. The mask applied to other sources after a source is accepted
The sequence of execution depends on the above 2 elements.
The priority in which EIT sources are accepted is the order of selection of the source whose EIT sequence
will be executed. In the EIT sequence, the program status register (PS) and the program counter (PC) are
saved, the program counter (PC) is updated, and the other sources are masked as required. The handler of
a source accepted earlier is not necessarily executed earlier.
Table 3.11-2 outlines the priority in which EIT sources are accepted.
Table 3.11-2 Priority in which EIT sources are accepted and masking of other sources
Priority of
Acceptance
Source
Masking of Other Sources
ILM
1
Reset
The other sources are abandoned.
15
2
Other than undefined
instructions
All sources of lower priority
-
3
INT instruction
I flag = 0
-
4
INTE instruction
All sources of lower priority
4
5
User interrupt
ILM = Level of accepted source
ICR
6
Step trace trap
All sources of lower priority
4
With additional consideration given to the masking of other sources after an EIT source is accepted, the
sequence of execution of the handlers of EIT sources that occur at one time is as shown below.
Table 3.11-3 lists the sequence of execution.
Table 3.11-3 Sequence of EIT handler execution
Priority of
Acceptance
CM71-10158-1E
Source
1
Reset
2
Other than undefined instructions
3
INTE instruction
4
Step trace trap
5
INT instruction
6
User interrupt
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Figure 3.11-4 shows multi-EIT processing.
Figure 3.11-4 Multi-EIT processing
Main routine
INTE instruction
handler
INT instruction handler
Priority
Executed
first
(High) INT instruction
execution
(Low) INTE
instruction execution
3.11.13
Operation
In the explanations in this section, the PC of the transfer source indicates the address of the instruction
that detects each EIT source.
"Next instruction address" indicates the value corresponding to the case where each of the instructions
below that detects EIT satisfies the respective condition shown:
•
For LDI:32 instruction: PC + 6
•
For LDI:20 instruction: PC + 4
•
For other instructions: PC + 2
■ User interrupt operation
The sequence in which a generated user interrupt request is determined as accepted or not is shown
below.
User interrupt requests are generated from peripheral functions, and an interrupt level is set for every
interrupt request.
● Acceptance of interrupt requests
1. The levels of interrupt requests generated simultaneously are compared, and the interrupt with the
highest level (with the lowest numerical value) is selected.
The value retained by the corresponding interrupt control register (ICR) is used for this comparison.
2. If multiple interrupt requests generated at one time have the same interrupt level, the interrupt request
with the lowest interrupt number is selected.
3. An interrupt request with an interrupt level greater than or equal to the level mask value is masked and
not accepted.
If the level mask value is greater than the interrupt level, go to 4.
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4. In cases where the selected interrupt request can be masked, if the I flag is "0", the interrupt request is
masked and not accepted. If the I flag is "1", the interrupt request is accepted.
Under the above conditions, the interrupt request will be accepted when one instruction processing is
completed.
When an instruction that changes the I flag or interrupt level mask register (ILM) is executed, EIT control
with the new acceptance condition becomes effective after 2 instructions.
If an EIT request is detected at the same time that a user interrupt request is accepted, the CPU operates as
follows using the interrupt number corresponding to the accepted interrupt request.
* The parentheses () in "● Operation" below indicate the address that a register points to.
● Operation
1
(TBR + vector offset of the accepted interrupt request)
→ TMP
2
SSP - 4
→ SSP
3
PS
→ (SSP)
4
SSP - 4
→ SSP
5
Next instruction address
→ (SSP)
6
Interrupt level of the accepted request
→ ILM
7
"0"
→ S flag
8
TMP
→ PC
After the interrupt sequence is completed, detection of any new EIT is performed before the first
instruction of the handler is executed. If any EIT that occurred can be accepted at this point, the CPU
switches to the EIT processing sequence.
3.11.14
INT Instruction Operation
The INT #u8 instruction generates a trap in software.
It generates a trap with the interrupt number specified in the operand.
● Operation
CM71-10158-1E
1
(TBR + 0x3FC - 4 × u8)
→ TMP
2
SSP - 4
→ SSP
3
PS
→ (SSP)
4
SSP - 4
→ SSP
5
PC + 2
→ (SSP)
6
"0"
→ I flag
7
"0"
→ S flag
8
TMP
→ PC
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3.11.15
MB91665 Series
INTE Instruction Operation
The INTE instruction generates a trap in software for debugging.
● Operation
3.11.16
1
(TBR + 0x3D8)
→TMP
2
SSP - 4
→SSP
3
PS
→(SSP)
4
SSP - 4
→SSP
5
PC + 2
→(SSP)
6
"00100B"
→ILM
7
"0"
→S flag
8
TMP
→PC
Step Trace Trap Operation
The step trace trap is a trap for debugging, and it is generated for each single instruction execution by
setting the T flag of the program status register (PS). No step trace trap is generated immediately after
execution of a branch instruction during execution of a delay branch instruction. It is generated after
the instruction in the delay slot is executed.
● Step trace trap detection conditions
1. T flag of the program status register (PS) = 1
2. The instruction being executed is not a delay branch instruction.
3. The CPU is in user mode.
If the above conditions are satisfied, a break is set when one instruction operation processing is
completed.
● Operation
1
(TBR + 0x3C4)
→TMP
2
SSP - 4
→SSP
3
PS
→(SSP)
4
SSP - 4
→SSP
5
Next instruction address
→(SSP)
6
"00100B"
→ILM
7
"0"
→S flag
8
TMP
→PC
If the T flag = 1, user interrupts are disabled.
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3.11.17
Undefined Instruction Exception Operation
When the instruction being decoded is detected as being undefined, an undefined instruction
exception is generated.
● Undefined instruction exception detection conditions
1. The instruction being decoded is detected as being undefined.
2. The instruction is not in a delay slot (i.e., it does not immediately follow a delay branch instruction).
If the above conditions are satisfied, an undefined instruction exception is generated and a break is set.
● Operation
1
(TBR + 0x3C4)
→TMP
2
SSP - 4
→SSP
3
PS
→(SSP)
4
SSP - 4
→SSP
5
PC
→(SSP)
6
"0"
→S flag
7
TMP
→PC
The address of the instruction that detects an undefined instruction exception is saved as the program
counter (PC).
3.11.18
RETI Instruction Operation
The RETI is an instruction to return from the EIT processing routine.
● Operation
1
(R15)
→PC
2
R15 + 4
→R15
3
(R15)
→PS
4
R15 + 4
→R15
The S flag must be "0" when the RETI instruction is executed.
3.11.19
Delay Slots and EIT
The delay slots of branch instructions have the following restrictions concerning EIT.
● Interrupts, traps
No interrupt or trap occurs between execution of a branch instruction with a delay slot and the delay slot.
● Exceptions
If the instruction in a delay slot is undefined, no undefined instruction exception occurs. In such cases, the
undefined instruction operates as the NOP instruction.
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CHAPTER 4 Clock Generating Parts
This chapter explains the clock generating parts that
generate the source clock (SRCCLK), which is the source
of all internal clocks in this device.
4.1
4.2
4.3
4.4
4.5
CM71-10158-1E
Overview
Configuration
Pins
Registers
Explanation of Operations
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4.1
4.1
MB91665 Series
Overview
The source clock (SRCCLK) is generated as the source of internal clocks used in operating this
device.
This section explains generation and oscillation control of the source clock (SRCCLK) and selection of
a clock as the source clock (SRCCLK).
■ Overview
This device operates with various internal clocks. The various internal clocks are generated by dividing
the source clock (SRCCLK).
The following 3 clocks can be selected for the source clock (SRCCLK):
•
Main clock (MCLK)
•
PLL clock (PLLCLK)
•
Sub clock (SBCLK)
The clock generating parts control the following:
•
•
•
•
Main clock (MCLK) generation
-
Controls the oscillation of the main clock (MCLK).
-
Sets the oscillation stabilization wait time of the main clock (MCLK).
-
Controls the main timer or generation of main timer interrupt requests.
Sub clock (SBCLK) generation
-
Controls the oscillation of the sub clock (SBCLK).
-
Sets the oscillation stabilization wait time of the sub clock (SBCLK).
-
Controls the sub timer or generation of sub timer interrupt requests.
PLL clock (PLLCLK) generation
-
Controls the oscillation of the PLL clock (PLLCLK).
-
Sets the oscillation stabilization wait time of the PLL clock (PLLCLK).
-
Sets the PLL multiple rate (the main clock (MCLK) multiple rate for generating the PLL clock
(PLLCLK)).
The multiple rate can be set only for the main clock (MCLK), but not for the subclock (SBCLK).
Source clock (SRCCLK) selection
Selects one of 3 clocks for use as the source clock (SRCCLK).
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4.2
MB91665 Series
4.2
Configuration
The clock generating parts consist of the clock generating parts themselves and the source clock
(SRCCLK) selection block.
4.2.1
Clock Generating Parts
There are 3 clock generating parts. Any of the clocks generated by the clock generating parts can be
selected for the source clock (SRCCLK).
■ Main clock (MCLK) generating part
This part uses inputs from the X0 pin and X1 pin (main oscillator) to generate the main clock (MCLK).
The main clock (MCLK) is used to generate the PLL clock (PLLCLK).
Figure 4.2-1 shows a block diagram of the main clock (MCLK) generating part.
Figure 4.2-1 Block diagram of the main clock (MCLK) generating part
Main clock (MCLK) generating part
MTE
MTC
MOSW
MTS
MTIE
Main timer
interrupt
request
Main
timer
MTIF
X1
Main clock ready
flag
MCRDY
MCEN
X0
•
Main clock
(MCLK)
Main timer
The main timer operates with the main clock (MCLK). For details, see "CHAPTER 6 Main Timer".
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■ PLL clock (PLLCLK) generating part
This part multiplies the main clock (MCLK) to generate the PLL clock (PLLCLK).
Figure 4.2-2 shows a block diagram of the PLL clock (PLLCLK) generating part.
Figure 4.2-2 Block diagram of the PLL clock (PLLCLK) generating part
PLL macro
oscillation
clock
PLL clock (PLLCLK) generating part
PLL input
clock
PLL input clock
divider (divides
by value from 1
to 16)
Main clock
(MCLK)
To USB clock
generating part
PLL macro
oscillation clock
divider (divides
by value from 1
to 4)
PLL
PLL clock
(PLLCLK)
PLL feedback clock
PDS
ODS
PLL feedback
clock divider
(multiplies by
value from 1 to 16)
PTS
PCEN
PCRDY
Main timer
•
PMS
PLL clock
ready flag
PLL
Clock multiplication circuit
•
PLL input clock divider
•
PLL feedback clock divider
This divider divides the main clock (MCLK) to generate the PLL input clock.
This divider divides the PLL clock (PLLCLK) generated by dividing the PLL macro oscillation clock
in order to generate the PLL feedback clock.
•
PLL macro oscillation clock divider
This divider divides the PLL macro oscillation clock to generate the PLL clock (PLLCLK).
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4.2
MB91665 Series
■ Sub clock (SBCLK) generating part
This part uses inputs from the X0A pin and X1A pin (sub oscillator) to generate the sub clock (SBCLK).
The sub clock (SBCLK) is the oscillation output as is.
Figure 4.2-3 shows a block diagram of the sub clock (SBCLK) generating part.
Figure 4.2-3 Block diagram of the sub clock (SBCLK) generating part
Sub clock (SBCLK) generating part
STE
STC
SOSW
STS
STIE
Sub timer
interrupt
Sub timer
Request
STIF
X1A
Sub clock ready
flag
SCRDY
SCEN
X0A
•
Sub clock
(SBCLK)
Sub timer
The sub timer operates with the sub clock (SBCLK). For details, see "CHAPTER 7 Sub Timer".
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CHAPTER 4 Clock Generating Parts
4.2
4.2.2
MB91665 Series
Source Clock (SRCCLK) Selection Block
This section explains selection of the source clock (SRCCLK). The source clock (SRCCLK) is
selected from the following 3 clock sources:
• Main clock (MCLK) divided by 2
• PLL clock (PLLCLK)
• Sub clock (SBCLK)
When an initialization reset (INIT) is generated, the settings of the source clock (SRCCLK) are
initialized, and the main clock (MCLK) divided by 2 is set for the source clock (SRCCLK).
Change it to an arbitrary source clock (SRCCLK) with the setting of the clock source select register
(CSELR) after the start of program operation.
■ Block diagram of the source clock (SRCCLK) selection block
Figure 4.2-4 shows a block diagram of the source clock (SRCCLK) selection block.
Figure 4.2-4 Block diagram of the source clock (SRCCLK) selection block
Source clock (SRCCLK) selection block
Main clock (MCLK)
Main clock divider
(divides by 2)
Source clock
Sub clock (SBCLK)
SRCCLK
PLL clock (PLLCLK)
CKS [0]
•
CKS [1]
Main clock divider (divides by 2)
The divider divides the main clock (MCLK) by 2 and sets the resultant value for the source clock
(SRCCLK).
•
CKS1 and CKS0 bits
These bits are the source clock (SRCCLK) selection bits in the clock source select register (CSELR).
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CHAPTER 4 Clock Generating Parts
4.3
MB91665 Series
4.3
Pins
This section explains the pins of the clock generating parts.
■ Overview
•
X0 and X1 pins
These pins are used to generate the main clock (MCLK).
•
X0A and X1A pins
These pins are used to generate the sub clock (SBCLK).
They are used to connect the oscillator to an external unit.
The pins are multiplexed pins. For details of using the X0A and X1A pins of the sub clock (SBCLK),
see "2.4 Setting Method for Pins".
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4.4
4.4
MB91665 Series
Registers
This section explains the configuration and functions of registers of the clock generating parts.
■ Registers of the clock generating parts
Table 4.4-1 lists the registers of the clock generating parts.
Table 4.4-1 Registers of the clock generating parts
Abbreviated
Register Name
112
Register Name
Reference
CSELR
Clock source select register
4.4.1
CMONR
Clock source monitor register
4.4.2
CSTBR
Clock stabilization time select register
4.4.3
PLLCR
PLL configuration register
4.4.4
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CHAPTER 4 Clock Generating Parts
4.4
MB91665 Series
4.4.1
Clock Source Select Register (CSELR)
This register controls the clock source and selects the source clock (SRCCLK).
Figure 4.4-1 shows the bit configuration of the clock source select register (CSELR).
Figure 4.4-1 Bit configuration of the clock source select register (CSELR)
bit
7
6
5
4
3
2
1
0
SCEN
PCEN
MCEN
Reserved
Reserved
Reserved
CKS1
CKS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (at INIT)
0
0
1
0
0
0
0
0
Initial value (at RST)
*
*
*
0
0
0
*
*
Attribute
R/W: Read/Write
*: Uninitialized bit
<Notes>
•
When this register is read, the actual setting value is not necessarily read. To verify that the
value specified for this register has actually been made effective, read the clock source monitor
register (CMONR).
•
Before changing this register, verify that the value specified for this register is the same as the
value of the clock source monitor register (CMONR).
•
Writing of this register is ignored during switching of the clocks (CKS1, CKS0
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[bit7]: SCEN (Sub clock oscillation enable bit)
This bit controls the oscillation of the sub clock (SBCLK).
Written Value
Explanation
Remarks
0
The oscillation of the sub clock
(SBCLK) is stopped.
The X0A or X1A pin can be used as
a port (PK0, PK1).
1
The sub clock (SBCLK) starts
oscillating.
The X0A and X1A pins are used to
generate the sub clock (SBCLK).
<Notes>
•
If the sub clock (SBCLK) is selected with the CKS1 and CKS0 bits (CKS1, CKS0=11) as the
source clock (SRCCLK), this bit cannot be changed.
•
The sub timer is cleared when "0" is written to the bit.
•
In stop mode, the oscillation of the sub clock (SBCLK) is stopped regardless of the value of the
bit.
[bit6]: PCEN (PLL clock oscillation enable bit)
This bit controls the oscillation of the PLL clock (PLLCLK).
Written Value
Explanation
0
The oscillation of the PLL clock (PLLCLK) is stopped.
1
The PLL clock (PLLCLK) starts oscillating.
<Notes>
•
Write "0" to this bit to stop the oscillation of the PLL clock (PLLCLK) before entering stop mode.
•
The bit cannot be changed under any of the following conditions:
- When the PLL clock (PLLCLK) is selected with the CKS1 and CKS0 bits (CKS1, CKS0 = 10)
as the source clock (SRCCLK)
- When the oscillation of the main clock (MCLK) is stopped, or the oscillation stabilization wait
time is in effect
(MCRDY bit = 0 in the clock source monitor register (CMONR))
•
This bit is changed to "0" when the MCEN bit (MCEN = 0) is specified to stop the oscillation of
the main clock (MCLK).
•
Do not change this bit from "0" to "1" while the main timer is being cleared (MTC bit = 1 in the
main timer control register (MTMCR)).
•
If this bit is changed from "0" to "1" to enable the oscillation of the PLL clock (PLLCLK), the main
timer is cleared.
In such cases, "1" is read from the MTC bit in the main timer control register (MTMCR).
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CHAPTER 4 Clock Generating Parts
4.4
MB91665 Series
[bit5]: MCEN (Main clock oscillation enable bit)
This bit controls the oscillation of the main clock (MCLK).
Written Value
Explanation
0
The oscillation of the main clock (MCLK) is stopped.
1
The main clock (MCLK) starts oscillating.
<Notes>
•
If any of the following is selected with the CKS1 or CKS0 bit as the source clock (SRCCLK), this
bit cannot be changed.
- The main clock (MCLK) is selected (CKS1, CKS0 = 00 or 01).
- The PLL clock (PLLCLK) is selected (CKS1, CKS0 = 10).
•
The main timer is cleared when "0" is written to this bit.
•
In stop mode, the oscillation of the main clock (MCLK) is stopped regardless of the value of the
bit.
[bit4 to bit2]: Reserved bits
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
[bit1, bit0]: CKS1, CKS0 (Source clock select bits)
These bits select the source clock (SRCCLK).
CKS1
CKS0
Explanation
0
0
0
1
1
0
PLL clock (PLLCLK)
1
1
Sub clock (SBCLK)
Main clock (MCLK) divided by 2
A clock whose oscillation is stopped or that has entered the oscillation stabilization wait time cannot be
selected as the source clock (SRCCLK).
Furthermore, no switching from the PLL clock (PLLCLK) to the sub clock (SBCLK) or from the sub
clock (SBCLK) to the PLL clock (PLLCLK) is possible.
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MB91665 Series
Table 4.4-2 lists the conditions for changes of this bit.
Table 4.4-2 CKS1 and CKS0 bit change conditions
Value before
Change
CKS1
CKS0
0
0
0
1
1
1
0
1
Changeable
Value
[CKS1:CKS0]
Change Condition Bit
Clock Source Monitor Register
(CMONR)
00, 01
MCRDY = 1
10
PCRDY = 1
00, 01
MCRDY = 1
11
SCRDY = 1
00
MCRDY = 1
10
PCRDY = 1
01
MCRDY = 1
11
SCRDY = 1
Unchangeable
Value
[CKS1:CKS0]
11
10
01, 11
00, 10
Do not write the unchangeable values listed in Table 4.4-2. For the procedures for switching the source
clock (SRCCLK), see "4.5.2 Switching the Source Clock (SRCCLK)".
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CHAPTER 4 Clock Generating Parts
4.4
MB91665 Series
4.4.2
Clock Source Monitor Register (CMONR)
This register displays the clock source and state of the source clock (SRCCLK).
The value specified for the clock source select register (CSELR) can be verified by reading this register to
verify whether it is actually effective.
Figure 4.4-2 shows the bit configuration of the clock source monitor register (CMONR).
Figure 4.4-2 Bit configuration of the clock source monitor register (CMONR)
bit
7
6
5
4
3
2
1
0
SCRDY
PCRDY
MCRDY
Reserved
Reserved
Reserved
CKM1
CKM0
Attribute
R
R
R
R
R
R
R
R
Initial value (at INIT)
0
0
1
0
0
0
0
0
Initial value (at RST)
*
*
*
0
0
0
*
*
R: Read only
*: Uninitialized bit
<Notes>
•
When changing a set value of the clock source select register (CSELR), be sure to read this
register and verify that the read value is the same as the set value of the clock source select
register (CSELR).
•
Do not change the clock source select register (CSELR) unless the set value of the clock source
select register (CSELR) matches the register value.
[bit7]: SCRDY (Sub clock ready bit)
This bit displays the sub clock (SBCLK) state.
Read Value
Explanation
0
The oscillation is stopped, or the oscillation stabilization wait time is in effect.
1
The oscillation stabilization is in effect.
This clock can be used as the source clock (SRCCLK).
<Notes>
•
If this bit is "0", the sub clock (SBCLK) cannot be selected as the source clock (SRCCLK).
•
After the SCEN bit in the clock source select register (CSELR) is changed from "1" to "0", this
bit may be read as having a value of "1".
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MB91665 Series
[bit6]: PCRDY (PLL clock ready bit)
This bit displays the PLL clock (PLLCLK) state.
Read Value
Explanation
0
The oscillation is stopped, or the oscillation stabilization wait time is in effect.
1
The oscillation stabilization is in effect.
This clock can be used as the source clock (SRCCLK).
<Notes>
•
If this bit is "0", the PLL clock (PLLCLK) cannot be selected as the source clock (SRCCLK).
•
After the PCEN bit in the clock source select register (CSELR) is changed from "1" to "0", this
bit may be read as having a value of "1".
[bit5]: MCRDY (Main clock ready bit)
This bit displays the main clock (MCLK) state.
Read Value
Explanation
0
The oscillation is stopped, or the oscillation stabilization wait time is in effect.
1
The oscillation stabilization is in effect.
This clock can be used as the source clock (SRCCLK).
<Notes>
•
If this bit is "0", neither the main clock (MCLK) nor the PLL clock (PLLCLK) can be selected as
the source clock (SRCCLK).
•
After the MCEN bit in the clock source select register (CSELR) is changed from "1" to "0", this
bit may be read as having a value of "1".
[bit4 to bit2]: Reserved bits
In case of reading
118
"0" is read.
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CHAPTER 4 Clock Generating Parts
4.4
MB91665 Series
[bit1, bit0]: CKM1, CKM0 (Source clock display bits)
These bits display the clock selected as the source clock (SRCCLK).
CM71-10158-1E
CKM1
CKM0
Explanation
0
0
0
1
1
0
The PLL clock (PLLCLK) is selected.
1
1
The sub clock (SBCLK) is selected.
The main clock (MCLK) divided by 2 is selected.
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4.4
4.4.3
MB91665 Series
Clock Stabilization Time Select Register (CSTBR)
This register sets the oscillation stabilization wait time of the clock source.
The oscillation stabilization wait time set in this register is used under the following conditions with the
ready bit being "1" for the relevant clock:
•
When returning from stop mode or watch mode
•
When the main oscillation is stopped and an initialize reset (INIT) is generated
•
When clock oscillation is enabled after being stopped
The ready bits are as follows:
-
Sub clock: SCRDY bit
-
PLL clock: PCRDY bit
-
Main clock: MCRDY bit
Figure 4.4-3 shows the bit configuration of the clock stabilization select register (CSTBR).
Figure 4.4-3 Bit configuration of the clock stabilization time select register (CSTBR)
bit
7
6
5
4
3
2
1
0
Reserved
SOSW2
SOSW1
SOSW0
MOSW3
MOSW2
MOSW1
MOSW0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INIT pin = "L" level
0
0
0
0
0
0
0
0
Initial value (at INIT)
0
0
0
0
*
*
*
*
Initial value (at RST)
0
*
*
*
*
*
*
*
Attribute
R/W: Read/Write
*: Uninitialized bit
<Note>
When the main oscillation is stopped and an initialize reset (INIT) is generated the main oscillation
stabilization wait time after operation is restarted is the initial value of this register.
[bit7]: Reserved bit
120
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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CHAPTER 4 Clock Generating Parts
4.4
MB91665 Series
[bit6 to bit4]: SOSW2 to SOSW0 (Sub clock oscillation stabilization wait select bits)
These bits select the oscillation stabilization wait time of the sub clock (SBCLK).
SOSW2
SOSW1
SOSW0
Sub Clock (SBCLK)
Oscillation Stabilization Wait Time
At 32.768 kHz
0
0
0
28 × Sub clock (SBCLK) period
About 7.8 ms
0
0
1
29 × Sub clock (SBCLK) period
About 15.6 ms
0
1
0
210 × Sub clock (SBCLK) period
About 31.3 ms
0
1
1
211 × Sub clock (SBCLK) period
62.5 ms
1
0
0
212 × Sub clock (SBCLK) period
125.0 ms
1
0
1
213 × Sub clock (SBCLK) period
250.0 ms
1
1
0
214 × Sub clock (SBCLK) period
500.0 ms
1
1
1
215 × Sub clock (SBCLK) period
1s
<Notes>
•
The times listed in the table are calculated values. Use these values only as a guide because
the actual times may include some errors depending on the oscillation state.
•
Writing to this bit is ignored when the following conditions are satisfied (in the oscillation
stabilization wait time of the sub clock (SBCLK)):
- SCRDY bit = 0 in the clock source monitor register (CMONR)
- SCEN bit = 1 in the clock source select register (CSELR)
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MB91665 Series
[bit3 to bit0]: MOSW3 to MOSW0 (Main clock oscillation stabilization select bits)
These bits select the oscillation stabilization wait time of the main clock (MCLK).
MOSW3 MOSW2 MOSW1 MOSW0
Main Clock (MCLK)
Oscillation Stabilization Wait
Time
At 4 MHz
At 8 MHz
At 48 MHz
0
0
0
0
21 × Main clock (MCLK) period
500 ns
250 ns
About 42 ns
0
0
0
1
25 × Main clock (MCLK) period
8 μs
4 μs
About 667 ns
0
0
1
0
26 × Main clock (MCLK) period
16 μs
8 μs
About 1 μs
0
0
1
1
27 × Main clock (MCLK) period
32 μs
16 μs
About 3 μs
0
1
0
0
28 × Main clock (MCLK) period
64 μs
32 μs
About 5 μs
0
1
0
1
29 × Main clock (MCLK) period
128 μs
64 μs
About 11 μs
0
1
1
0
210 × Main clock (MCLK) period
256 μs
128 μs
About 21 μs
0
1
1
1
211 × Main clock (MCLK) period
512 μs
256 μs
About 43 μs
1
0
0
0
212 × Main clock (MCLK) period
About 1 ms
512 μs
About 85 μs
1
0
0
1
213 × Main clock (MCLK) period
About 2 ms
About 1 ms
About 171 μs
1
0
1
0
214 × Main clock (MCLK) period
About 4 ms
About 2 ms
About 341 μs
1
0
1
1
215 × Main clock (MCLK) period
About 8 ms
About 4 ms
About 683 μs
1
1
0
0
217 × Main clock (MCLK) period
About 33 ms
About 16 ms
About 3 ms
1
1
0
1
219 × Main clock (MCLK) period
About 131 ms
About 66 ms
About 11 ms
1
1
1
0
221 × Main clock (MCLK) period
About 524 ms
About 262 ms
About 44 ms
1
1
1
1
223 × Main clock (MCLK) period
About 2 s
About 1 s
About 175 ms
<Notes>
•
The times listed in the table are calculated values. Use these values only as a guide because
the actual times may include some errors depending on the oscillation state.
•
Specify an oscillation stabilization wait time as 25μs or longer for a product equipped with a
regulator.
•
Writing to this bit is ignored when the following conditions are satisfied (in the oscillation
stabilization wait time of the main clock (MCLK)):
- MCRDY bit = 0 in the clock source monitor register (CMONR)
- MCEN bit = 1 in the clock source select register (CSELR)
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CHAPTER 4 Clock Generating Parts
4.4
MB91665 Series
4.4.4
PLL Configuration Register (PLLCR)
This register sets the multiple rate for generating the PLL clock (PLLCLK) from the main clock
(MCLK).
For the calculation of the clock frequency and the multiple rate related to generating the PLL clock
(PLLCLK), see "4.5.3 Multiple Rate for Generating the PLL Clock (PLLCLK)".
Figure 4.4-4 shows the bit configuration of the PLL configuration register (PLLCR).
Figure 4.4-4 Bit configuration of the PLL configuration register (PLLCR)
bit
15
14
13
12
11
10
9
8
Reserved
Reserved
ODS1
ODS0
PMS3
PMS2
PMS1
PMS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (at INIT)
0
0
0
0
0
0
0
0
Initial value (at RST)
0
0
*
*
*
*
*
*
bit
7
6
5
4
3
2
1
0
PTS3
PTS2
PTS1
PTS0
PDS3
PDS2
PDS1
PDS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (at INIT)
1
1
1
1
0
0
0
0
Initial value (at RST)
*
*
*
*
*
*
*
*
Attribute
Attribute
R/W: Read/Write
*: Uninitialized bit
<Note>
Writing to this bit is ignored when the oscillation of the PLL clock (PLLCLK) is enabled (PCEN = 1
in the clock source select register (CSELR)).
[bit15, bit14]: Reserved bits
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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MB91665 Series
[bit13, bit12]: ODS1, ODS0 (PLL macro oscillation clock division rate select bits)
These bits select the division rate from the PLL macro oscillation clock to the PLL clock (PLLCLK).
ODS1
ODS0
Explanation
0
0
PLL clock (PLLCLK) = PLL macro oscillation clock / 1
0
1
PLL clock (PLLCLK) = PLL macro oscillation clock / 2
1
0
PLL clock (PLLCLK) = PLL macro oscillation clock / 3
1
1
PLL clock (PLLCLK) = PLL macro oscillation clock / 4
[bit11 to bit8]: PMS3 to PMS0 (PLL clock multiple rate select bits)
These bits select the multiple rate from the PLL input clock to the PLL clock (PLLCLK).
124
PMS3
PMS2
PMS1
PMS0
PLL Clock (PLLCLK) Multiple Rate
0
0
0
0
PLL clock (PLLCLK) = PLL input clock × 1
0
0
0
1
PLL clock (PLLCLK) = PLL input clock × 2
0
0
1
0
PLL clock (PLLCLK) = PLL input clock × 3
0
0
1
1
PLL clock (PLLCLK) = PLL input clock × 4
0
1
0
0
PLL clock (PLLCLK) = PLL input clock × 5
0
1
0
1
PLL clock (PLLCLK) = PLL input clock × 6
0
1
1
0
PLL clock (PLLCLK) = PLL input clock × 7
0
1
1
1
PLL clock (PLLCLK) = PLL input clock × 8
1
0
0
0
PLL clock (PLLCLK) = PLL input clock × 9
1
0
0
1
PLL clock (PLLCLK) = PLL input clock × 10
1
0
1
0
PLL clock (PLLCLK) = PLL input clock × 11
1
0
1
1
PLL clock (PLLCLK) = PLL input clock × 12
1
1
0
0
PLL clock (PLLCLK) = PLL input clock × 13
1
1
0
1
PLL clock (PLLCLK) = PLL input clock × 14
1
1
1
0
PLL clock (PLLCLK) = PLL input clock × 15
1
1
1
1
PLL clock (PLLCLK) = PLL input clock × 16
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CHAPTER 4 Clock Generating Parts
4.4
MB91665 Series
[bit7 to bit4]: PTS3 to PTS0 (PLL clock oscillation stabilization wait time select bits)
These bits select the oscillation stabilization wait time of the PLL clock (PLLCLK).
PTS3
PTS2
PTS1
PTS0
PLL Clock (PLLCLK) Oscillation
Stabilization Wait Time
1
0
0
0
29 × Main clock (MCLK) period
1
0
0
1
210 × Main clock (MCLK) period
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
211 × Main clock (MCLK) period
212 × Main clock (MCLK) period
213 × Main clock (MCLK) period
214 × Main clock (MCLK) period
215 × Main clock (MCLK) period
216 × Main clock (MCLK) period
At 4 MHz
At 8 MHz
At 48 MHz
128.0 μs
64.0 μs
About 10.7 μs
256.0 μs
128.0 μs
About
21.3 μs
512.0 μs
256.0 μs
About
42.7 μs
About 1 ms
512.0 μs
About
85.3 μs
About 2 ms
About 1 ms
About
170.7 μs
About 4 ms
About 2 ms
About
341.3 μs
About 8 ms
About 4 ms
About
682.7 μs
About
16.4 ms
About 8 ms
About 1.4 ms
<Notes>
•
The times listed in the table are calculated values. Use these values only as a guide because
the actual times may include some errors depending on the oscillation state.
•
Always write "1" to the PTS3 bit.
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MB91665 Series
[bit3 to bit0]: PDS3 to PDS0 (PLL input clock division select bits)
These bits select the main clock (MCLK) division rate for generating the PLL input clock.
126
PDS3
PDS2
PDS1
PDS0
PLL Input Clock Division Selection
0
0
0
0
PLL input clock = Main clock (MCLK) / 1
0
0
0
1
PLL input clock = Main clock (MCLK) / 2
0
0
1
0
PLL input clock = Main clock (MCLK) / 3
0
0
1
1
PLL input clock = Main clock (MCLK) / 4
0
1
0
0
PLL input clock = Main clock (MCLK) / 5
0
1
0
1
PLL input clock = Main clock (MCLK) / 6
0
1
1
0
PLL input clock = Main clock (MCLK) / 7
0
1
1
1
PLL input clock = Main clock (MCLK) / 8
1
0
0
0
PLL input clock = Main clock (MCLK) / 9
1
0
0
1
PLL input clock = Main clock (MCLK) / 10
1
0
1
0
PLL input clock = Main clock (MCLK) / 11
1
0
1
1
PLL input clock = Main clock (MCLK) / 12
1
1
0
0
PLL input clock = Main clock (MCLK) / 13
1
1
0
1
PLL input clock = Main clock (MCLK) / 14
1
1
1
0
PLL input clock = Main clock (MCLK) / 15
1
1
1
1
PLL input clock = Main clock (MCLK) / 16
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CM71-10158-1E
CHAPTER 4 Clock Generating Parts
4.5
MB91665 Series
4.5
Explanation of Operations
This section explains the operations of the clock generating parts.
This section explains the operations of each clock source and how the source clocks are switched.
4.5.1
Explanation of Clock Source Operations
This section explains mainly oscillation control of the clock sources.
■ Main clock (MCLK)
This clock is generated with inputs from the X0 pin and X1 pin (main oscillator). It is used to generate
the PLL clock.
The main clock is used in operating the main timer. (See "CHAPTER 6 Main Timer".)
● Conditions for stopping oscillation
The oscillation of the main clock (MCLK) stops under any of the following conditions:
•
When stop mode is in effect
•
When the sub clock (SBCLK) is selected for the source clock (SRCCLK) and the oscillation of the
main clock (MCLK) is stopped (that is, when the following conditions are satisfied):
-
CKS1 or CKS0 bit in the clock source select register (CSELR) = 11
-
MCEN bit in the clock source select register (CSELR) = 0
Supplying of the main clock (MCLK) starts after all the above oscillation stop conditions are cleared and
the oscillation stabilization wait time specified by the MOSW3 to MOSW0 bits in the clock stabilization
time select register (CSTBR) has elapsed.
● Selecting the oscillation stabilization wait time
Supplying of the main clock (MCLK) starts after a wait for the oscillation of the main clock to stabilize
once the oscillation has been enabled.
The MOSW3 to MOSW0 bits in the clock stabilization time select register (CSTBR) specify the
oscillation stabilization wait time of the main clock (MCLK).
Input at the "L" level to the INIT pin initializes the MOSW3 to MOSW0 bits, returning the oscillation
stabilization wait time to its initial value. In such cases, the initial value is 21 × Main clock (MCLK)
period.
The MOSW3 to MOSW0 bits are not initialized by any other reset that occurs.
<Note>
Specify an oscillation stabilization wait time as 25μs or longer for products equipped with
regulators.
● End of the oscillation stabilization wait time
The main clock (MCLK) is supplied at the end of the oscillation stabilization wait time.
Checking the following values enables you to verify whether the main clock (MCLK) has entered the
oscillation stabilization wait time while operation of the main clock (MCLK) is enabled.
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MB91665 Series
Oscillation Stabilization Wait State Display
Oscillation Stabilization State Display
MCRDY = 0 in the clock source monitor register
(CMONR)
MCRDY = 1 in the clock source monitor register
(CMONR)
■ PLL clock (PLLCLK)
This high-performance clock multiplies and generates the main clock (MCLK).
● Conditions for stopping oscillation
The oscillation of the PLL clock (PLLCLK) stops under any of the following conditions:
•
When the oscillation of the main clock (MCLK) is stopped, or the oscillation stabilization wait time is
in effect
•
When the following conditions are satisfied and a clock other than the PLL clock (PLLCLK) is selected
for the source clock (SRCCLK):
(PCEN bit = 0 in the clock source select register (CSELR))
-
CKS1 or CKS0 bit in the clock source select register (CSELR) = a value other than 10
-
PCEN bit in the clock source select register (CSELR) = 0
Supplying of the PLL clock (PLLCLK) starts after all the above oscillation stop conditions are cleared
and the oscillation stabilization wait time specified by the PTS3 to PTS0 bits in the PLL configuration
register (PLLCR) has elapsed.
Input at the "L" level to the INIT pin or a return from an initialization reset (INIT) initializes the PCEN
bit in the clock source select register (CSELR) to "0" and stops the oscillation of the PLL clock
(PLLCLK). (To start the oscillation after such initialization, set the PCEN bit in the clock source select
register (CSELR) to "1".)
● Selecting an oscillation stabilization wait time
Supplying of the PLL clock (PLLCLK) starts after a wait for the oscillation of the PLL clock to stabilize
once the oscillation has been enabled.
The PTS3 to PTS0 bits in the PLL configuration register (PLLCR) specify the oscillation stabilization
wait time of the PLL clock (PLLCLK).
Input at the "L" level to the INIT pin or a return from an initialization reset (INIT) initializes the PTS3 to
PTS0 bits, returning the oscillation stabilization wait time to its initial value. In such cases, the initial
value is 216 × Main clock (MCLK) period.
To change the oscillation stabilization wait time, set the PTS3 to PTS0 bits, and then write "1" to the
PCEN bit in the clock source select register (CSELR).
● End of the oscillation stabilization wait time
The PLL clock (PLLCLK) is supplied at the end of the oscillation stabilization wait time.
Checking the following values enables you to verify whether the PLL clock (PLLCLK) has entered the
oscillation stabilization wait time while operation of the PLL clock (PLLCLK) is enabled.
Oscillation stabilization wait state display
PCRDY = 0 in the clock source monitor register
(CMONR)
128
Oscillation stabilization state display
PCRDY = 1 in the clock source monitor
register (CMONR)
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CHAPTER 4 Clock Generating Parts
4.5
MB91665 Series
■ Sub clock (SBCLK)
This clock is generated with inputs from the X0A pin and X1A pin (sub oscillator). The sub clock
(SBCLK) is the oscillation output as is.
The sub clock is used in operating the sub timer (See "CHAPTER 7 Sub Timer").
● Conditions for stopping oscillation
The oscillation of the sub clock (SBCLK) stops under any of the following conditions:
•
When input to the INIT pin is at the "L" level
•
When stop mode is in effect
•
When any clock other than the sub clock (SBCLK) is selected for the source clock (SRCCLK) and the
oscillation of the sub clock (SBCLK) is stopped (that is, when the following conditions are satisfied):
•
-
CKS1 or CKS0 bit in the clock source select register (CSELR) = a value other than 11
-
SCEN bit in the clock source select register (CSELR) = 0
The pins are set to use ports (the pins are multiplexed for the sub clock (SBCLK) generating part and
the ports).
Supplying of the sub clock (SBCLK) starts after all the above oscillation stop conditions are cleared and
the oscillation stabilization wait time specified by the SOSW2 to SOSW0 bits in the clock stabilization
time select register (CSTBR) has elapsed.
Input at the "L" level to the INIT pin or a return from an initialization reset (INIT) initializes the SCEN
bit in the clock source select register (CSELR) to "0" and stops the oscillation of the sub clock (SBCLK).
(To start the oscillation after such initialization, set the SCEN bit in the clock source select register
(CSELR) to "1".)
● Selecting an oscillation stabilization wait time
Supplying of the sub clock (SBCLK) starts after a wait for the oscillation of the sub clock to stabilize
once the oscillation has been enabled.
The SOSW2 to SOSW0 bits in the clock stabilization time select register (CSTBR) specify the oscillation
stabilization wait time of the sub clock (SBCLK).
Input at the "L" to the INIT pin or a return from an initialization reset (INIT) initializes the SOSW2 to
SOSW0 bits, returning the oscillation wait time to its initial value. In such cases, the initial value is 28 ×
Sub clock (SBCLK) period.
To change the oscillation stabilization wait time, set the SOSW2 to SOSW0 bits.
● End of the oscillation stabilization wait time
The sub clock (SBCLK) is supplied at the end of the oscillation stabilization wait time.
Checking the following values enables you to verify whether the sub clock (SBCLK) has entered the
oscillation stabilization wait time while operation of the sub clock (SBCLK) is enabled.
Oscillation stabilization wait state display
SCRDY = 0 in the clock source monitor register
(CMONR)
CM71-10158-1E
Oscillation stabilization state display
SCRDY = 1 in the clock source monitor
register (CMONR)
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CHAPTER 4 Clock Generating Parts
4.5
4.5.2
MB91665 Series
Switching the Source Clock (SRCCLK)
This section explains switching of the source clock (SRCCLK).
■ Overview
When "L" is input to the INIT pin or an initialization reset (INIT) is generated, the settings of the source
clock (SRCCLK) are initialized, and the main clock (MCLK) divided by 2 is set for the source clock
(SRCCLK).
The CKS1 and CKS0 bits of the clock source select register (CSELR) can be used to select the source
clock (SRCCLK) from the clock sources after the start of program operation.
For this change to the source clock (SRCCLK), no switch from the PLL clock (PLLCLK) to the sub clock
(SBCLK) or from the sub clock (SBCLK) to the PLL clock (PLLCLK) is possible. To do so, specify the
main clock (MCLK) divided by 2, and then switch it.
Figure 4.5-1 shows how to switch the source clock (SRCCLK).
Figure 4.5-1 How to switch the source clock (SRCCLK)
Main clock
(MCLK) divided by 2
PLL clock
(PLLCLK)
Sub clock
(SBCLK)
<Note>
Even if the source clock (SRCCLK) is switched, the oscillation enable settings (the values of the
SCEN bit, PCEN bit, and MCEN bit in the clock source select register (CSELR)) of each clock are
maintained. Stop the oscillation as necessary.
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MB91665 Series
CHAPTER 4 Clock Generating Parts
4.5
■ Procedures
● Switching from the main clock (MCLK) divided by 2 to the PLL clock (PLLCLK)
To switch the source clock (SRCCLK) from the main clock (MCLK) divided by 2 to the PLL clock
(PLLCLK), make settings by following the procedure below.
1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 00 or 01) of the clock source monitor register
(CMONR) to verify that the main clock (MCLK) divided by 2 is selected.
2. Set the PLL multiple rate and the PLL clock (PLLCLK) oscillation stabilization wait time in the PLL
configuration register (PLLCR).
3. Set the PCEN bit (PCEN=1) in the clock source select register (CSELR) to start the oscillation of the
PLL clock (PLLCLK).
4. Check the PCRDY bit (PCRDY = 1) in the clock source monitor register (CMONR) to verify that the
oscillation of the PLL clock (PLLCLK) has stabilized.
5. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 10) in the clock source select register (CSELR) to
switch the source clock (SRCCLK) to the PLL clock (PLLCLK).
6. Check the CKM1 and CKM0 bits (CKM1, CKM = 10) in the clock source monitor register (CMONR)
to verify that the source clock (SRCCLK) was switched to the PLL clock (PLLCLK).
<Note>
If the oscillation of the PLL clock (PLLCLK) has been enabled, steps 2 to 4 can be omitted.
● Switching from the PLL clock (PLLCLK) to the main clock (MCLK) divided by 2
To switch the source clock (SRCCLK) from the PLL clock (PLLCLK) to the main clock (MCLK)
divided by 2, make settings by following the procedure below.
1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 10) in the clock source monitor register
(CMONR) to verify that the PLL clock (PLLCLK) is selected.
2. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 00) in the clock source select register (CSELR) to
switch the source clock (SRCCLK) to the main clock (MCLK) divided by 2.
3. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 00) in the clock source monitor register
(CMONR) to verify that the source clock (SRCCLK) was switched to the main clock (MCLK)
divided by 2.
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CHAPTER 4 Clock Generating Parts
4.5
MB91665 Series
● Switching from the main clock (MCLK) divided by 2 to the sub clock (SBCLK)
To switch the source clock (SRCCLK) from the main clock (MCLK) divided by 2 to the sub clock
(SBCLK), make settings by following the procedure below.
1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 01) in the clock source monitor register
(CMONR) to verify that the main clock (MCLK) divided by 2 is selected.
2. Set the oscillation stabilization wait time of the sub clock (SBCLK) in the SOSW2 to SOSW0 bits in
the clock stabilization time select register (CSTBR).
3. Set the SCEN bit (SCEN=1) in the clock source select register (CSELR) to start the oscillation of the
sub clock (SBCLK).
4. Check the SCRDY bit (SCRDY = 1) in the clock source monitor register (CMONR) to verify that the
oscillation of the sub clock (SBCLK) has stabilized.
5. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 11) in the clock source select register (CSELR) to
switch the source clock (SRCCLK) to the sub clock (SBCLK).
6. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 11) in the clock source monitor register
(CMONR) to verify that the source clock (SRCCLK) was switched to the sub clock (SBCLK).
<Note>
If the oscillation of the sub clock (SBCLK) has been enabled, steps 2 to 4 can be omitted.
● Switching from the sub clock (SBCLK) to the main clock (MCLK) divided by 2
To switch the source clock (SRCCLK) from the sub clock (SBCLK) to the main clock (MCLK) divided
by 2, make settings by following the procedure below.
1. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 11) in the clock source monitor register
(CMONR) to verify that the sub clock (SBCLK) is selected.
2. Set the oscillation stabilization wait time of the main clock (MCLK) in the MOSW2 to MOSW0 bits
in the clock stabilization time select register (CSTBR).
3. Set the MCEN bit (MCEN=1) in the clock source select register (CSELR) to start the oscillation of the
main clock (MCLK).
4. Check the MCRDY bit (MCRDY = 1) in the clock source monitor register (CMONR) to verify that
the oscillation of the main clock (MCLK) has stabilized.
5. Set the CKS1 and CKS0 bits (CKS1, CKS0 = 01) in the clock source select register (CSELR) to
switch the source clock (SRCCLK) to the main clock (MCLK).
6. Check the CKM1 and CKM0 bits (CKM1, CKM0 = 01) in the clock source monitor register
(CMONR) to verify that the source clock (CRCCLK) was switched to the main clock (MCLK).
<Note>
If the oscillation of the main clock (MCLK) has been enabled, steps 2 to 4 can be omitted.
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CHAPTER 4 Clock Generating Parts
4.5
MB91665 Series
4.5.3
Multiple Rate for Generating the PLL Clock (PLLCLK)
This section explains how to calculate the clock frequency and the multiple rate related to generating the PLL
clock (PLLCLK).
PLL input clock frequency
= (Main oscillation frequency)/(Division rate set in the PDS bit in the PLL configuration register
(PLLCR))
PLL multiple rate
= (Division rate set in the ODS bit in the PLL configuration register (PLLCR)) × (Multiple rate set in the
PMS bit in the PLL configuration register (PLLCR))
PLL macro oscillation clock frequency
= (PLL input clock frequency) × PLL multiple rate
PLL clock (PLLCLK) frequency
= (PLL input clock frequency) × (Multiple rate set in the PMS bit in the PLL configuration register
(PLLCR))
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CHAPTER 4 Clock Generating Parts
4.5
MB91665 Series
Table 4.5-1 lists sample settings of the PLL clock (PLLCLK).
Table 4.5-1 Sample settings of the PLL clock (PLLCLK)
Main
Oscillation
Frequency
PLL Configuration Register
(PLLCR)
PDS3 to
PDS0
ODS1,
ODS0
PMS3 to
PMS0
PLL Input
Clock
Frequency
PLL Multiple
Rate
ODS × PMS
PLL Macro
Oscillation
Clock
Frequency
PLL
Clock
Frequency
4 MHz
0000
00
0111
4 MHz
Multiplied by 8
32 MHz
32 MHz
4.167 MHz
0000
00
0111
4.167 MHz
Multiplied by 8
33 MHz
33 MHz
48MHz
0010
10
0001
16 MHz
Multiplied by 6
96 MHz
32 MHz
4MHz
0000
10
0111
4 MHz
Multiplied by 24
96 MHz
32 MHz
8MHz
0000
10
0011
8 MHz
Multiplied by 12
96 MHz
32 MHz
<Notes>
•
•
134
The following conditions must be satisfied by the specified PLL input clock, PLL multiple rate,
and PLL macro oscillation clock.
PLL Input Clock Frequency
4 to 24 MHz
PLL Multiple Rate
Multiplied by 2 to 24
PLL Macro Oscillation Clock
Frequency
96 to 100 MHz
Source Clock
(when PLL clock is selected)
24 to 33 MHz
It is prohibited to set ODS=00 and PMS=0000 (PLL multiply rate=1).
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 5 Clock Division Control Part
This chapter explains the clock division control part that
generates internal clocks.
5.1 Overview
5.2 Internal Clocks
5.3 Configuration
5.4 Registers
5.5 Division Rate
5.6 Notes on Use
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CHAPTER 5 Clock Division Control Part
5.1
5.1
MB91665 Series
Overview
Internal clocks are generated by dividing the source clock (SRCCLK) input from a clock generating
part.
The clock division control part divides the source clock (SRCCLK) and generates internal clocks to
supply them to the CPU, bus, and/or peripheral functions.
Table 5.1-1 lists the internal clocks that are generated. These clocks are collectively called internal
clocks.
Table 5.1-1 Internal clocks that are generated
Clock Name
Generation Source Clock
Base clock (BCLK)
Source clock (SRCCLK) divided by a value from 1 to 8
CPU clock (CCLK)
Base clock (BCLK) divided by 1 (undivided)
On-chip bus clock (HCLK)
Base clock (BCLK) divided by 1 (undivided)
External bus clock (TCLK)
Base clock (BCLK) divided by a value from 1 to 8
Peripheral clock (PCLK)
Base clock (BCLK) divided by a value from 1 to 16
For details of the source clock (SRCCLK), see "CHAPTER 4 Clock Generating Parts".
136
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CHAPTER 5 Clock Division Control Part
5.2
MB91665 Series
5.2
Internal Clocks
This section explains the internal clocks.
■ Base clock (BCLK)
This clock is the generation source of all internal clocks.
The DIVB2 to DIVB0 bits of the divide clock configuration register 0 (DIVR0) are used when this clock
is generated by dividing the source clock (SRCCLK) by a value ranging from 1 to 8.
The clock can decrease at once the operating frequency of the entire device.
It is stopped in one of the following low-power dissipation modes:
•
Watch mode / main timer mode
•
Stop mode
■ CPU clock (CCLK)
This clock is supplied to the CPU in this device and generated from the base clock (BCLK).
Since it is generated without dividing the base clock (BCLK), the operating frequency is always the same
as that for the base clock (BCLK).
It is stopped in one of the following low-power dissipation modes:
•
Doze mode (during a stop time)
•
Sleep mode
•
Watch mode / main timer mode
•
Stop mode
Clock Name
CPU clock (CCLK)
Typical Supply Destination
CPU (instruction execution block)
■ On-chip bus clock (HCLK)
This clock is supplied to the on-chip bus and each circuit connected to the on-chip bus. It is generated
from the base clock (BCLK).
Since it is generated without dividing the base clock (BCLK), the operating frequency is always the same
as that for the base clock (BCLK).
It is stopped in one of the following low-power dissipation modes:
•
Bus sleep mode
•
Watch mode / main timer mode
•
Stop mode
Clock Name
On-chip bus clock (HCLK)
CM71-10158-1E
Typical Supply Destination
DMA controller (DMAC)
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CHAPTER 5 Clock Division Control Part
5.2
MB91665 Series
■ External bus clock (TCLK)
This clock is supplied to an external bus interface.
The DIVT2 to DIVT0 bits of divide clock configuration register 1 (DIVR1) are used when this clock is
generated by dividing the base clock (BCLK) by a value ranging from 1 to 8.
If there is no on-chip bus access in bus sleep mode, the clock can be stopped by specifying the TSTP bit
in divide clock configuration register 1 (DIVR1).
It is stopped in one of the following low-power dissipation modes regardless of the setting:
•
Watch mode / main timer mode
•
Stop mode
Clock Name
External bus clock (TCLK)
Typical Supply Destination
External bus interface
<Notes>
•
The same frequency as that for the external bus clock (TCLK) is output for the bus clock
(SYSCLK) from the SYSCLK pin.
•
If an odd number is specified for the division rate of the external bus clock (TCLK) (DIVT2 to
DIVT0 bits in divide clock configuration register 1 (DIVR1)), the duty ratio of the bus clock
(SYSCLK) output from the SYSCLK pin cannot be 50%. The "H" level output period becomes
50% or less of the output period.
•
When DIVT = 000, be sure to set as DIVB = 000.
•
Do not change the division rate of the external bus clock (TCLK) while the external bus area is
being accessed. For details of changing the division rate, see "5.6 Notes on Use".
■ Peripheral clock (PCLK)
This clock is supplied to the peripheral buses and each peripheral function connected to the buses.
The DIVP3 to DIVP0 bits of divide clock configuration register 2 (DIVR2) are used when this clock is
generated by dividing the base clock (BCLK) by a value ranging from 1 to 16.
It is stopped in one of the following low-power dissipation modes regardless of the setting:.
•
Watch mode / main timer mode
•
Stop mode
Clock Name
Peripheral clock (PCLK)
138
Typical Supply Destination
Peripheral bus
Clock control part
Reset controller
Watchdog timer
Interrupt controller
External interrupt
Delay interrupt
16-bit reload timer
Each peripheral function
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 5 Clock Division Control Part
5.3
MB91665 Series
5.3
Configuration
The source clock input from a clock generating part is divided by the value specified in a register and
output to a circuit.
■ Block diagram of the clock division control part
Figure 5.3-1 is a block diagram of the clock division control part.
Figure 5.3-1 Block diagram of the clock division control part
Source clock
(SRCCLK)
DIVB2 to DIVB0
(divide by value from
1 to 8)
Base clock
(BCLK)
CPU sleep
CPU clock
(CCLK)
Bus sleep
On-chip bus
clock
(HCLK)
Bus sleep
Not accessing the external bus
TSTP
DIVT2 to DIVT0
(divide by value from
1 to 8)
DIVP3 to DIVP0
(divide by value from
1 to 16)
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
External bus clock
(TCLK)
Peripheral clock
(PCLK)
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CHAPTER 5 Clock Division Control Part
5.4
5.4
MB91665 Series
Registers
This section explains the configuration and functions of registers of the clock division control part.
■ Registers of the clock division control part
Table 5.4-1 lists the registers of the clock division control part.
Table 5.4-1 Registers of the clock division control part
Abbreviated Register Name
140
Register Name
Reference
DIVR0
Divide clock configuration register 0
5.4.1
DIVR1
Divide clock configuration register 1
5.4.2
DIVR2
Divide clock configuration register 2
5.4.3
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 5 Clock Division Control Part
5.4
MB91665 Series
5.4.1
Divide Clock Configuration Register 0 (DIVR0)
This register sets the source clock (SRCCLK) division rate for generating the base clock (BCLK).
Figure 5.4-1 shows the bit configuration of divide clock configuration register 0 (DIVR0).
Figure 5.4-1 Bit configuration of divide clock configuration register 0 (DIVR0)
bit
Attribute
7
6
5
4
3
2
1
0
DIVB2
DIVB1
DIVB0
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
1
Initial value
R/W: Read/Write
[bit7 to bit5]: DIVB2 to DIVB0 (base clock division configuration bits)
These bits set the division rate for generating the base clock (BCLK) from the source clock (SRCCLK).
Since the CPU clock (CCLK) and the on-chip bus clock (HCLK) are generated without dividing the base
clock (BCLK), the frequency is the same as that for the base clock (BCLK).
DIVB2
DIVB1
DIVB0
Explanation
0
0
0
Divided by 1 (undivided)
0
0
1
Divided by 2
0
1
0
Divided by 3
0
1
1
Divided by 4
1
0
0
Divided by 5
1
0
1
Divided by 6
1
1
0
Divided by 7
1
1
1
Divided by 8
[bit4 to bit2]: Reserved bits
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
[bit1, bit0]: Reserved bits
CM71-10158-1E
In case of writing
Always write "1" to this (these) bit (bits)
In case of reading
"1" is read.
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CHAPTER 5 Clock Division Control Part
5.4
5.4.2
MB91665 Series
Divide Clock Configuration Register 1 (DIVR1)
This register sets the base clock (BCLK) division rate for generating the external bus clock (TCLK). It
also controls the stopping of the external bus clock (TCLK).
Figure 5.4-2 shows the bit configuration of divide clock configuration register 1 (DIVR1).
Figure 5.4-2 Bit configuration of divide clock configuration register 1 (DIVR1)
bit
Attribute
7
6
5
4
3
2
1
0
TSTP
DIVT2
DIVT1
DIVT0
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
0
0
Initial value
R/W: Read/Write
[bit7]: TSTP (External bus clock stop enable bit)
This bit specifies whether to stop the external bus clock (TCLK) when the on-chip bus is stopped in sleep
mode.
If such stopping is enabled, the external bus clock (TCLK) is not supplied except at the bus access time.
Written Value
142
Explanation
0
Do not stop the external bus clock (TCLK).
1
Stop the external bus clock (TCLK).
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 5 Clock Division Control Part
5.4
MB91665 Series
[bit6 to bit4]: DIVT2 to DIVT0 (External bus clock division configuration bits)
These bits set the division rate for generating the external bus clock (TCLK) from the base clock (BCLK).
DIVT2
DIVT1
DIVT0
Explanation
0
0
0
Divided by 1 (undivided)
0
0
1
Divided by 2
0
1
0
Divided by 3
0
1
1
Divided by 4
1
0
0
Divided by 5
1
0
1
Divided by 6
1
1
0
Divided by 7
1
1
1
Divided by 8
<Note>
Do not change the division rate of the external bus clock (TCLK) while the external bus area is
being accessed. For details of changing the division rate, see "5.6 Notes on Use".
[bit3 to bit0]: Reserved bits
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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CHAPTER 5 Clock Division Control Part
5.4
5.4.3
MB91665 Series
Divide Clock Configuration Register 2 (DIVR2)
This register sets the base clock (BCLK) division rate for generating the peripheral clock (PCLK).
Figure 5.4-3 shows the bit configuration of divide clock configuration register 2 (DIVR2).
Figure 5.4-3 Bit configuration of divide clock configuration register 2 (DIVR2)
bit
7
6
5
4
3
2
1
0
DIVP3
DIVP2
DIVP1
DIVP0
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
0
0
Attribute
Initial value
R/W: Read/Write
144
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CM71-10158-1E
CHAPTER 5 Clock Division Control Part
5.4
MB91665 Series
[bit7 to bit4]: DIVP3 to DIVP0 (Peripheral clock division configuration bits)
These bits set the division rate for generating the peripheral clock (PCLK) from the base clock (BCLK).
DIVP3
DIVP2
DIVP1
DIVP0
Explanation
0
0
0
0
Divided by 1 (undivided)
0
0
0
1
Divided by 2
0
0
1
0
Divided by 3
0
0
1
1
Divided by 4
0
1
0
0
Divided by 5
0
1
0
1
Divided by 6
0
1
1
0
Divided by 7
0
1
1
1
Divided by 8
1
0
0
0
Divided by 9
1
0
0
1
Divided by 10
1
0
1
0
Divided by 11
1
0
1
1
Divided by 12
1
1
0
0
Divided by 13
1
1
0
1
Divided by 14
1
1
1
0
Divided by 15
1
1
1
1
Divided by 16
[bit3 to bit0]: Reserved bits
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is red.
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CHAPTER 5 Clock Division Control Part
5.5
5.5
MB91665 Series
Division Rate
The clock division control part can set the division rate for each internal clock.
Figure 5.5-1 shows the division rate from the source clock for each internal clock.
Figure 5.5-1 Division rate from the source clock for each internal clock
Source clock
(SRCCLK)
Divided by value
from 1 to 8
Base clock
(BCLK)
CPU clock
(CCLK)
Divided by value
from 1 to 8
Divided by value
from 1 to 16
External bus clock
(TCLK)
Peripheral clock
(PCLK)
■ Division rates after initialization
Table 5.5-1 shows the division of internal clocks after a reset.
Table 5.5-1 Division rates after a reset
Clock Name
146
Division Rate after Initialization
Base clock (BCLK)
Source clock (SRCCLK) divided by 1
CPU clock (CCLK)
Base clock (BCLK) divided by 1
On-chip bus clock (HCLK)
Base clock (BCLK) divided by 1
External bus clock (TCLK)
Base clock (BCLK) divided by 2
Peripheral clock (PCLK)
Base clock (BCLK) divided by 4
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 5 Clock Division Control Part
5.5
MB91665 Series
■ Changing the division rate
After the division rate setting is changed, the changed division rate is enabled at the next rising edge of
the clock.
A
A
B
B
B
Clocks
Setting value of register
(division rate)
A
B
Change of
division rate
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CHAPTER 5 Clock Division Control Part
5.6
5.6
MB91665 Series
Notes on Use
Note the following points on setting the clock division rate.
Do not change the division rate of the external bus clock (TCLK) while the external bus area is being
accessed. For changing the division rate, perform the following processing to DIVT2 to DIVT0 bits in the
division clock configuration register 1 (DIVR1).
Example)
LDI
#value_of_divr1,
R0
; DIVR1 (DIVT2 to DIVT0 bits) setting
LDI
#_DIVR1,
R12
;
STB
R0,
@R12
; write
LDUB
@R12,
R0
; dummy processing
MOV
R0,
R0
; dummy processing
NOP
; dummy processing
NOP
; dummy processing
BRA
_escape_divr1
NOP
; dummy processing
; dummy processing
_escape_divr1
The execution program is written as follows.
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CM71-10158-1E
CHAPTER 6 Main Timer
This chapter explains the functions and operations of the
main timer function.
CM71-10158-1E
6.1
6.2
6.3
6.4
Overview
Configuration
Registers
Interrupts
6.5
An Explanation of Operations and Setting Procedure
Examples
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CHAPTER 6 Main Timer
6.1
6.1
MB91665 Series
Overview
The main timer operates with the main clock (MCLK).
The main timer is used to generate the oscillation stabilization wait time of the main clock (MCLK) and
PLL clock (PLLCLK).
The main timer counts the oscillation stabilization wait time of the main clock (MCLK) and PLL clock
(PLLCLK).
When main clock (MCLK) oscillation is stable, the main timer can also be used as an interval timer for
generating an interrupt request at regular intervals.
The main timer is cleared when:
•
"1" is written to the MTC bit of the main timer control register (MTMCR).
"1" is read from the MTC bit of the main timer control register (MTMCR) until the main timer is
cleared after "1" is written to the MTC bit.
•
Main clock (MCLK) oscillation is stopped.
(The MCEN bit of the clock source select register (CSELR) is 0.)
•
In stop mode
•
The main timer is stopped with the MTE bit (MTE = 0) of the main timer control register (MTMCR).
If main timer operation is disabled, the timer is stopped during periods other than the oscillation
stabilization wait time of the main clock (MCLK) and PLL clock (PLLCLK).
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CM71-10158-1E
CHAPTER 6 Main Timer
6.2
MB91665 Series
6.2
Configuration
This section explains the main timer configuration.
■ Main timer block diagram
For the main timer block diagram, see "■ Main clock (MCLK) generating part" in "CHAPTER 4 Clock
Generating Parts".
■ Clocks
Table 6.2-1 shows the clocks used by the main timer.
Table 6.2-1 Clocks used by the main timer
Clock Name
Operation clock
CM71-10158-1E
Description
Main clock (MCLK)
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CHAPTER 6 Main Timer
6.3
6.3
MB91665 Series
Registers
This section explains the configuration and functions of registers used by the main timer.
■ Registers of main timer
Table 6.3-1 shows the registers used by the main timer.
Table 6.3-1 Main timer registers
Abbreviated Register Name
MTMCR
152
Register Name
Main timer control register
FUJITSU SEMICONDUCTOR LIMITED
Reference
6.3.1
CM71-10158-1E
CHAPTER 6 Main Timer
6.3
MB91665 Series
6.3.1
Main Timer Control Register (MTMCR)
This register controls the main timer.
Figure 6.3-1 shows the bit configuration of the main timer control register (MTMCR).
Figure 6.3-1 Bit configuration of main timer control register (MTMCR)
bit
Attribute
7
6
5
4
3
2
1
0
MTIF
MTIE
MTC
MTE
MTS3
MTS2
MTS1
MTS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
1
1
1
Initial value
R/W: Read/Write
<Notes>
•
This register can be rewritten only when the main clock (MCLK) is oscillating stably (The
MCRDY bit of the clock source monitor register (CMONR) is 1).
Note that the MTIE bit can be rewritten even when the MCRDY bit is "0".
•
Software reset must be executed when both the MTE and MTC bits are "0". For details of the
software reset, see "CHAPTER 9 Reset".
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CHAPTER 6 Main Timer
6.3
MB91665 Series
[bit7]: MTIF (main timer interrupt flag bit)
This flag indicates that the main timer overflows.
The main timer overflows when:
•
The counter has finished counting the period that is set with the MTS3 to MTS0 bits.
•
The oscillation stabilization wait time of the main clock (MCLK) has elapsed after the MCEN bit of the
clock source select register (CSELR) was rewritten from "0" to "1".
•
The oscillation stabilization wait time of the main clock (MCLK) has elapsed after the system returns
from stop mode.
A main timer interrupt request occurs when this bit is set to "1" while the MTIE bit is "1".
MTIF
In case of reading
In case of writing
0
No overflow occurred.
This bit is cleared to "0".
1
An overflow occurred.
Ignored
This bit is also cleared to "0" when a DMA transfer is caused by a main timer interrupt request.
<Notes>
•
Disabling main timer operation with the MTE bit (MTE = 0) clears the main timer.
•
When the MTIE bit is set to "0", this bit is not cleared even when a DMA transfer is caused by a
main timer interrupt request.
•
After this device is reset by input of an "L" level signal from the INIT pin, an "H" level signal may
be input again from the INIT pin. In this case, this bit is not changed to "1" even after the
oscillation stabilization wait time of the main clock (MCLK) elapses.
•
If clearing the bit to "0" coincides with the occurrence of an overflow, the overflow occurrence is
given priority and this bit remains "1".
•
When a read-modify-write instruction is used, "1" is read.
[bit6]: MTIE (main timer interrupt enable bit)
The MTIE bit is used to specify whether to cause a main timer interrupt request when the main timer
overflows (MTIF=1).
A main timer interrupt request occurs when the MTIF bit is set to "1" while this bit is "1".
Written Value
154
Explanation
0
Disables generation of main timer interrupt requests.
1
Enables generation of main timer interrupt requests.
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CM71-10158-1E
CHAPTER 6 Main Timer
6.3
MB91665 Series
[bit5]: MTC (main timer clear bit)
Clear the main timer.
The operating state of the main timer can be verified by reading this bit.
MTC
In case of writing
In case of reading
0
Ignored
In normal operation
1
Clear the main timer.
The main timer is being cleared.
<Notes>
•
When a read-modify-write instruction is used, "0" is read.
•
Do not clear the main timer during oscillation stabilization wait time of the PLL clock (PLLCLK).
•
This register can be rewritten only while main clock (MCLK) oscillation is stable. Therefore, if
the following conditions are satisfied, the main timer cannot be cleared even when the bit is set
to "1":
- Main clock (MCLK) is oscillating (the MCEN bit of the clock source select register (CSELR) is
1).
- The main clock (MCLK) is in oscillation stopped/oscillation stabilization wait state (The
MCRDY bit of the clock source monitor register (CMONR) is 0).
•
Writing "1" to this bit at the same time that the MTE bit is changed from "0" to "1" clears the
main timer and then starts main timer operation.
•
Do not write "1" to this bit when it is "1".
•
As long as the MTC bit is "0", the MTIF bit may become "1".
[bit4]: MTE (main timer operation enable bit)
This bit enables/disables (stops) the operation of the main timer.
Written Value
Explanation
0
Disables (stops) the operation of the main timer.
1
Enables the operation of the main timer.
<Notes>
•
If the operation of the main timer is disabled (stopped), the main timer is stopped during periods
other than the oscillation stabilization wait time of the main clock (MCLK) and PLL clock
(PLLCLK).
•
Disabling (stopping) the operation of the main timer clears the main timer. While the main timer
is cleared, "1" is read from the MTC bit. As long as the MTC bit is "0", the MTIF bit may become
"1".
•
Do not change this bit from "1" to "0" during oscillation stabilization wait time of the PLL clock
(PLLCLK).
•
Do not write "1" to this bit when the MTC bit is "1".
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CHAPTER 6 Main Timer
6.3
MB91665 Series
[bit3 to bit0]: MTS3 to MTS0 (main timer period select bits)
These bits are used to select an overflow period of the main timer.
The main timer overflows when it finishes counting the period specified with these bits.
MTS3 MTS2 MTS1 MTS0
Overflow Period
4 MHz
8 MHz
48 MHz
1
0
0
0
29 × Main clock cycle
128.0 μs
64.0 μs
About 10.7 μs
1
0
0
1
210 × Main clock cycle
256.0 μs
128.0 μs
About 21.3 μs
1
0
1
0
211 × Main clock cycle
512.0 μs
256.0 μs
About 42.7 μs
1
0
1
1
212 × Main clock cycle
About 1 ms
512.0 μs
About 85.3 μs
1
1
0
0
213 × Main clock cycle
About 2 ms
About 1 ms
About 170.7 μs
1
1
0
1
214 × Main clock cycle
About 4 ms
About 2 ms
About 341.3 μs
1
1
1
0
215 × Main clock cycle
About 8 ms
About 4 ms
About 682.7 μs
1
1
1
1
216 × Main clock cycle
About 16.4 ms
About 8 ms
About 1.4 ms
Always write "1" to the MTS3 bit.
<Notes>
•
Change the values of these bits after stopping the main timer using the MTE bit (MTE = 0).
•
While the MTIE bit is set to "1", a main timer interrupt request is generated when the main timer
overflows.
Set these bits so that the main timer overflow period exceeds 5T (T: peripheral clock (PCLK)
period).
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CM71-10158-1E
CHAPTER 6 Main Timer
6.4
MB91665 Series
6.4
Interrupts
A main timer interrupt request is generated when the main timer overflows.
Table 6.4-1 outlines the interrupts that can be used with the main timer.
Table 6.4-1 Interrupts of the main timer
Interrupt request
Main timer interrupt
request
Interrupt request
flag
Interrupt request
enabled
Clearing an
interrupt request
MTIF=1 for MTMCR
MTIE=1 for MTMCR
Write "0" to the MTIF
bit for MTMCR
MTMCR: main timer control register (MTMCR)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests.
- Clears interrupt requests before enabling the generation of interrupt requests.
- Clears interrupt requests simultaneously with interrupts enabled.
•
For information on the interrupt vector number of each interrupt request, see "APPENDIX C
Interrupt Vectors".
•
Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to
the interrupt vector number. For the setting of interrupt levels, see "CHAPTER 10 Interrupt
Controller".
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CHAPTER 6 Main Timer
6.5
6.5
MB91665 Series
An Explanation of Operations and Setting
Procedure Examples
This section explains the operation of the main timer. Also, examples of procedures for setting the
operating state are shown.
6.5.1
Main Timer Operation
■ Overview
The main timer counts the oscillation stabilization wait time of the main clock (MCLK) and PLL clock
(PLLCLK).
When main clock (MCLK) oscillation is stable, the main timer can also be used as an interval timer for
generating an interrupt request at regular intervals.
If main timer operation is disabled with the MTE bit (MTE = 0) of the main timer control register
(MTMCR), the timer is stopped during periods other than the oscillation stabilization wait time of the
main clock (MCLK) and PLL clock (PLLCLK).
■ Operation
The main timer operates as follows:
1. Enable the main timer operation by the MTE bit of the main timer control register (MTMCR) (MTE =
1).
2. The main timer starts counting in synchronization with the main clock (MCLK).
The main timer continues counting while the MTE bit of the main timer control register (MTMCR) is
"1".
3. The main timer counts up to the value set in the MTS3 to MTS0 bits of the main timer control register
(MTMCR).
The MTIF bit of the main timer control register (MTMCR) changes to "1".
If the MTIE bit of the main timer control register (MTMCR) is "1" at this time, a main timer interrupt
request is generated.
To clear the main timer interrupt request, write "0" to the MTIF bit. The MTIF bit is cleared to "0".
If main timer operation is disabled with the MTE bit (MTE=0) of the main timer control register
(MTMCR) during main timer operation, the main timer stops counting and clears the counter value. For
more information, see "■ Clearing the timer".
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CHAPTER 6 Main Timer
6.5
MB91665 Series
■ Clearing the timer
The main timer is cleared when:
•
"1" is written to the MTC bit of the main timer control register (MTMCR).
"1" is read from the MTC bit of the main timer control register (MTMCR) until the main timer is
cleared after "1" is written to the MTC bit.
•
Main clock (MCLK) oscillation is stopped.
(The MCEN bit of the clock source select register (CSELR) is 0).
•
In stop mode
•
The main timer is stopped with the MTE bit (MTE = 0) of the main timer control register (MTMCR).
<Note>
The main timer control register (MTMCR) can be rewritten only when the oscillation of the main
clock (MCLK) is stable. Therefore, even if "1" is written to the MTC bit of the main timer control
register (MTMCR) when the following conditions are satisfied, the main timer cannot be cleared:
•
Main clock (MCLK) oscillation is oscillating (the MCEN bit of the clock source select register
(CSELR) is 1).
•
The main clock (MCLK) is in oscillation stopped/oscillation stabilization wait state (The MCRDY
bit of the clock source monitor register (CMONR) is 0).
■ Interrupt setting procedure
An example of the procedure for setting the main timer control register (MTMCR) is shown below.
1. Set the MTIE bit to disable main timer interrupts (MTIE=0).
2. Set the MTIF bit to clear the main timer interrupt flag (MTIF=0).
3. Set the MTE bit to disable main timer operation (MTE=0).
4. Read the MTC bit to verify that the main timer has been cleared (MTC=0).
5. Set the timer period in the MTS3 to MTS0 bits.
6. Set the MTIE bit to enable main timer interrupts (MTIE=1).
7. Set the MTE bit to enable main timer operation (MTE=1).
When the period that is set in the MTS3 to MTS0 bits elapses, a main timer interrupt request is
generated and processing moves to the interrupt processing routine.
8. Set the MTIF bit to clear the main timer interrupt flag (MTIF=0).
9. Read the MTIF bit once to complete clearing the main timer interrupt flag.
Issue the RETI instruction to return to normal program processing from the interrupt processing
routine.
<Note>
When "0" is written to the MTIF bit, the main timer interrupt flag is not cleared soon. After reading
the MTIF bit once to complete clearing the flag, it can be returned by the RETI instruction.
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CHAPTER 6 Main Timer
6.5
6.5.2
MB91665 Series
Transition to Stop Mode
Before transition to the stop mode, generation of main timer interrupt requests must be disabled.
Follow the procedure below for transition to the stop mode:
1. Set the PCEN bit of the clock source select register (CSELR) to stop PLL clock (PLLCLK) oscillation
(PCEN=0).
2. Set the MTIE bit of the main timer control register (MTMCR) to disable generation of main timer
interrupt requests (MTIE=0).
3. Set the MTE bit of the main timer control register (MTMCR) to disable main timer operation (MTE =
0).
4. Read the MTC bit of the main timer control register (MTMCR) to verify that the main timer is not
being cleared (MTC=0).
5. Set the MTIF bit of the main timer control register (MTMCR) to clear the main timer interrupt flag
(MTIF=0).
6. Set the oscillation stabilization wait time of the main clock (MCLK) in the MOSW3 to MOSW0 bits
of the clock stabilization time select register (CSTBR).
7. Transition to stop mode
<Note>
Before transition to stop mode, be sure to stop PLL clock (PLLCLK) oscillation.
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CM71-10158-1E
CHAPTER 7 Sub Timer
This chapter explains the functions and operations of the
sub timer.
CM71-10158-1E
7.1
7.2
7.3
7.4
Overview
Configuration
Registers
Interrupts
7.5
An Explanation of Operations and Setting Procedure
Examples
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CHAPTER 7 Sub Timer
7.1
7.1
MB91665 Series
Overview
The sub timer operates based on the sub clock (SBCLK).
It is used to generate the sub clock (SBCLK) oscillation stabilization wait time.
The sub timer counts the oscillation stabilization wait time of the sub clock (SBCLK).
When sub clock (SBCLK) oscillation is stable, the sub timer can also be used as an interval timer for
generating an interrupt request at regular intervals.
The sub timer is cleared when:
•
"1" is written to the STC bit of the sub timer control register (STMCR).
"1" is read from the STC bit of the sub timer control register (STMCR) until the sub timer is cleared
after "1" is written to the STC bit.
•
Sub clock (SBCLK) oscillation is stopped.
(The SCEN bit of the clock source select register (CSELR) is 0.)
•
In stop mode
•
The sub timer is stopped with the STE bit (STE=0) of the sub timer control register (STMCR).
If sub timer operation is disabled, the timer is stopped during periods other than the oscillation
stabilization wait time of the sub clock (SBCLK).
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CHAPTER 7 Sub Timer
7.2
MB91665 Series
7.2
Configuration
This section explains the sub timer configuration.
■ Sub timer block diagram
For details of the sub timer block diagram, see "■ Sub clock (SBCLK) generating part" in "CHAPTER 4
Clock Generating Parts".
■ Clocks
Table 7.2-1 shows the clocks used by the sub timer.
Table 7.2-1 Clocks used by the sub timer
Clock Name
Operation clock
CM71-10158-1E
Description
Sub clock (SBCLK)
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CHAPTER 7 Sub Timer
7.3
7.3
MB91665 Series
Registers
This section explains the configuration and functions of registers used by the sub timer.
■ Registers of sub timer
The registers used by the sub timer are listed in Table 7.3-1.
Table 7.3-1 Sub timer registers
Abbreviated Register Name
STMCR
164
Register Name
Sub timer control register
FUJITSU SEMICONDUCTOR LIMITED
Reference
7.3.1
CM71-10158-1E
CHAPTER 7 Sub Timer
7.3
MB91665 Series
7.3.1
Sub Timer Control Register (STMCR)
This register controls the sub timer.
Figure 7.3-1 shows the bit configuration of the sub timer control register (STMCR).
Figure 7.3-1 Bit configuration of sub timer control register (STMCR)
bit
Attribute
7
6
5
4
3
2
1
0
STIF
STIE
STC
STE
Reserved
STS2
STS1
STS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
1
1
Initial value
R/W: Read/Write
<Notes>
•
This register can be rewritten only when the sub clock (SBCLK) is oscillating stably. (The
SCRDY bit of the clock source monitor register (CMONR) is 1.)
Note that the STIE bit can be rewritten even when the SCRDY bit is "0".
•
Software reset must be executed when both the STE and STC bits are "0". For details of the
software reset, see "CHAPTER 9 Reset".
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CHAPTER 7 Sub Timer
7.3
MB91665 Series
[bit7]: STIF (sub clock timer interrupt flag bit)
This flag indicates that the sub timer caused an overflow.
The sub timer overflows when:
•
The counter has finished counting the period that is set with the STS2 to STS0 bits.
•
The oscillation stabilization wait time of the sub clock (SBCLK) has elapsed after the SCEN bit of the
clock source select register (CSELR) was rewritten from "0" to "1".
•
The oscillation stabilization wait time of the sub clock (SBCLK) has elapsed after the system returns
from stop mode.
A sub timer interrupt request occurs when this bit is set to "1" while the STIE bit is "1".
STIF
In case of reading
In case of writing
0
No overflow occurred.
This bit is cleared to "0".
1
An overflow occurred.
Ignored
This bit is also cleared to "0" when a DMA transfer is caused by a sub timer interrupt request.
<Notes>
•
Disabling sub timer operation with the STE bit (STE = 0) clears the sub timer.
•
When the STIE bit is set to "0", this bit is not cleared even when a DMA transfer is caused by a
sub timer interrupt request.
•
If clearing the bit to "0" coincides with the occurrence of an overflow, the overflow occurrence is
given priority and this bit remains "1".
•
When a read-modify-write instruction is used, "1" is read
[bit6]: STIE (sub timer interrupt enable bit)
The STIE bit is used to specify whether to cause a sub timer interrupt request when the sub timer
overflows (STIF=1).
A sub timer interrupt request occurs when the STIF bit is set to "1" while this bit is "1".
Written Value
166
Explanation
0
Disables generation of sub timer interrupt requests.
1
Enables generation of sub timer interrupt requests.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 7 Sub Timer
7.3
MB91665 Series
[bit5]: STC (sub timer clear bit)
This bit clears the sub timer.
The operating state of the sub timer can be verified by reading this bit.
STC
In case of writing
In case of reading
0
Ignored
In normal operation
1
Clear the sub timer.
The sub timer is being cleared.
<Notes>
•
When a read-modify-write instruction is used, "0" is read.
•
This register can be rewritten only while sub clock (SBCLK) oscillation is stable. Therefore, if
the following conditions are satisfied, the sub timer cannot be cleared even when the bit is set to
"1":
- Sub clock (SBCLK) is oscillating (the SCEN bit of the clock source select register (CSELR) is
1).
- The sub clock (SBCLK) is in oscillation stopped/oscillation stabilization wait state.
(The SCRDY bit of the clock source monitor register (CMONR) is 0.)
•
Writing "1" to this bit at the same time that the STE bit is changed from "0" to "1" clears the sub
timer and then starts sub timer operation.
•
Do not attempt to write "1" to this bit when it is "1".
•
As long as the STC bit is "0", the STIF bit may become "1".
[bit4]: STE (sub timer operation enable bit)
This bit controls the sub timer operation.
Written Value
Explanation
0
Disables (stops) the operation of the sub timer.
1
Enables the operation of the sub timer.
<Notes>
•
If the operation of the sub timer is disabled (stopped), the sub timer is stopped during periods
other than the oscillation stabilization wait time of the sub clock (SBCLK).
•
Disabling (stopping) the operation of the sub timer clears the sub timer. While the sub timer is
cleared, "1" is read from the STC bit. As long as the STC bit is "0", the STIF bit may become
"1".
•
Do not write "1" to this bit when the STC bit is "1".
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7.3
MB91665 Series
[bit3]: Reserved bit
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
[bit2 to bit0]: STS2 to STS0 (sub timer period select bits)
These bits are used to select an overflow period of the sub timer.
The sub timer overflows when it finishes counting the period specified with these bits.
STS2
STS1
STS0
Overflow Period
At 32768Hz
0
0
0
28 × Sub clock cycle
About 7.8 ms
0
0
1
29 × Sub clock cycle
About 15.6 ms
0
1
0
210 × Sub clock cycle
About 31.3 ms
0
1
1
211 × Sub clock cycle
62.5 ms
1
0
0
212 × Sub clock cycle
125.0 ms
1
0
1
213 × Sub clock cycle
250.0 ms
1
1
0
214 × Sub clock cycle
500.0 ms
1
1
1
215 × Sub clock cycle
1s
<Notes>
•
Change the values of these bits after stopping the sub timer using the STE bit (STE = 0).
•
While the STIE bit is set to "1", a sub timer interrupt request is generated when the sub timer
overflows.
Set these bits so that the sub timer overflow period is 5T (T: peripheral clock (PCLK) period) or
more than that.
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CHAPTER 7 Sub Timer
7.4
MB91665 Series
7.4
Interrupts
A sub timer interrupt request is generated when the sub timer overflows.
Table 7.4-1 outlines the interrupts that can be used with the sub timer.
Table 7.4-1 Interrupts of the sub timer
Interrupt request
Sub timer interrupt
request
Interrupt request
flag
STIF=1 for STMCR
Interrupt request
enabled
STIE=1 for STMCR
Clearing an
interrupt request
Write "0" to the STIF
bit for STMCR
STMCR: sub timer control register (STMCR)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests.
- Clears interrupt requests before enabling the generation of interrupt requests.
- Clears interrupt requests simultaneously with interrupts enabled.
•
For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt
Vectors".
•
Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to
the interrupt vector number. For details of the interrupt level settings, see "CHAPTER 10
Interrupt Controller".
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CHAPTER 7 Sub Timer
7.5
7.5
MB91665 Series
An Explanation of Operations and Setting
Procedure Examples
This section explains the operation of the sub timer. Also, examples of procedures for setting the
operating state are shown.
7.5.1
Sub timer operation
■ Overview
The sub timer counts the oscillation stabilization wait time of the sub clock (SBCLK).
When sub clock (SBCLK) oscillation is stable, the sub timer can also be used as an interval timer for
generating an interrupt request at regular intervals.
If sub timer operation is disabled with the STE bit (STE = 0) of the sub timer control register (STMCR),
the timer is stopped during periods other than the oscillation stabilization wait time of the sub clock
(SBCLK).
■ Operation
The sub timer operates as follows:
1. The STE bit of the sub timer control register (STMCR) enables (STE = 1) sub timer operation.
2. The sub timer starts counting in synchronization with the sub clock (SBCLK).
The sub timer continues counting while the STE bit of the sub timer control register (STMCR) is "1".
3. The sub timer counts up to the value specified in the STS2 to STS0 bits of the sub timer control
register (STMCR).
The STIF bit of the sub timer control register (STMCR) changes to "1".
If the STIE bit of the sub timer control register (STMCR) is "1" at this time, a sub timer interrupt
request is generated.
To clear the sub timer interrupt request, write "0" to the STIF bit. The STIF bit is cleared to "0".
If sub timer operation is disabled with the STE bit (STE = 0) of the sub timer control register (STMCR)
during sub timer operation, the sub timer stops counting and clears the counter value. For more
information, see "■ Clearing the timer".
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7.5
MB91665 Series
■ Clearing the timer
The sub timer is cleared when:
•
"1" is written to the STC bit of the sub timer control register (STMCR).
"1" is read from the STC bit of the sub timer control register (STMCR) until the sub timer is cleared
after "1" is written to the STC bit.
•
Sub clock (SBCLK) oscillation is stopped.
(The SCEN bit of the clock source select register (CSELR) is 0.)
•
In stop mode
•
The sub timer is stopped with the STE bit (STE = 0) of the sub timer control register (STMCR).
The sub timer is stopped for periods other than the oscillation stabilization wait time of the sub clock
(SBCLK).
<Note>
The sub timer control register (STMCR) can be rewritten only while the oscillation of the sub clock
(SBCLK) is stable. Therefore, even if "1" is written to the STC bit of the sub timer control register
(STMCR) when the following conditions are satisfied, the sub timer cannot be cleared:
•
Sub clock (SBCLK) is oscillating. (The SCEN bit of the clock source select register (CSELR) is
1.)
•
The sub clock (SBCLK) is in oscillation stopped/oscillation stabilization wait state. (The SCRDY
bit of the clock source monitor register (CMONR) is 0.)
■ Interrupt setting procedure
An example of the procedure for setting the sub timer control register (STMCR) is shown below.
1. Set the STIE bit to disable sub timer interrupts (STIE = 0).
2. Set the STIF bit to clear the sub timer interrupt flag (STIF = 0).
3. Set the STE bit to disable sub timer operation (STE = 0).
4. Read the STC bit to verify that the sub timer is operating normally (STC=0).
5. Set the timer period in the STS2 to STS0 bits.
6. Set the STIE bit to enable sub timer interrupts (STIE = 1).
7. Set the STE bit to enable sub timer operation (STE = 1).
When the period that is set in the STS2 to STS0 bits elapses, a sub timer interrupt request is generated
and processing moves to the interrupt processing routine.
8. Set the STIF bit to clear the sub timer interrupt flag (STIF = 0).
9. Read the STIF bit once to complete clearing the sub timer interrupt flag.
Issue the RETI instruction to return to normal program processing from the interrupt processing
routine.
<Note>
When "0" is written to the STIF bit, the sub timer interrupt flag is not cleared soon. After reading
the STIF bit once to complete clearing the flag, it can be returned by the RETI instruction.
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7.5
7.5.2
MB91665 Series
Transition to Stop Mode, and Watch Mode
Before transition to stop mode, interrupt operation by the sub timer must be disabled.
Follow the procedure below for transition to the stop mode:
1. Set the PCEN bit of the clock source select register (CSELR) to stop PLL clock (PLLCLK) oscillation
(PCEN=0).
2. Set the STIE bit of the sub timer control register (STMCR) to disable sub timer interrupts
(STIE = 0).
3. Set the STE bit of the sub timer control register (STMCR) to disable sub timer operation
(STE = 0).
4. Read the STC bit of the sub timer control register (STMCR) to confirm that the sub timer is not being
cleared (STC=0).
5. Set the STIF bit of the sub timer control register (STMCR) to clear the sub timer interrupt flag (STIF
= 0).
6. Set the oscillation stabilization wait time of the sub clock (SBCLK) in the SOSW2 to SOSW0 bits of
the clock stabilization time select register (CSTBR).
7. Transition to stop mode
<Note>
Before transition to the stop mode, be sure to stop PLL clock oscillation.
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CHAPTER 8 Low-power Dissipation Mode
This chapter explains the functions and operations of lowpower dissipation mode.
8.1
8.2
8.3
8.4
8.5
CM71-10158-1E
Overview
Configuration
Registers
An Explanation of Operations and Setting Procedure
Examples
Notes on Use
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8.1
8.1
MB91665 Series
Overview
This series can use low-power dissipation mode to reduce power dissipation.
■ Overview
This series can control power dissipation in the following way.
•
Clock control
-
Clock division
By changing the division ratio of each operation clock, operation frequency can be reduced.
-
Stop clock
This allows the user to specify a specific clock to stop the clock.
•
Doze mode
This mode intermittently operates the CPU repeatedly at a set operation rate.
•
Sleep mode
This mode operates only peripheral functions. One of the following two modes can be selected.
-
CPU sleep mode
This mode stops the operation of the CPU.
-
Bus sleep mode
This mode stops the CPU and on-chip bus.
•
Standby mode
One of the following three modes can be selected.
-
Main timer mode
This mode stops all the operations other than the main clock oscillation.
The sub clock oscillation can be specified arbitrarily.
-
Watch mode
-
Stop mode
This mode stops all the operations other than the sub clock oscillation.
This mode stops all operations including the oscillation of all clocks.
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8.2
MB91665 Series
8.2
Configuration
The configuration of the power dissipation controller is shown below.
■ Block diagram of power dissipation controller
Figure 8.2-1 is a block diagram of the power dissipation controller.
Figure 8.2-1 Block diagram of power dissipation controller
RUN [3:0]
RUN
SLP
SLP [3:0]
Reload value
selection
circuit
S
1 1
[5] [4] [3] [2] [1] [0] SLP value count
Q
R
end
CPU sleep request
RUN value count
end
DOZE counter
(6-bit down counter)
Peripheral clock (PCLK)
DOZE
SLEEP
S
STBCR read
Q
Bus sleep request
R
SLVL [1]
TIMER
S
STBCR read
Q
Clock stop request
R
Bus acknowledge
STOP
STBCR read
S
Q
Oscillation stop
request
R
Return
Reset (RST)
STBCR :
S
:
R
:
Q
:
Standby mode control register (STBCR)
Set
Reset
Output
•
Standby mode control register (STBCR)
This register controls low-power dissipation mode.
•
Sleep rate configuration register (SLPRR)
This register configures the operation state (RUN state) rate and sleep state rate (sleep rate) in doze
mode.
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8.2
•
MB91665 Series
Reload value selection circuit
A circuit for selecting to reload either the operation state (RUN state) rate or sleep state rate (Sleep
rate) which has been set in the sleep rate configuration register (SLPRR).
■ Clocks
Table 8.2-1 shows the clock used in the power dissipation controller.
Table 8.2-1 Clock used in power dissipation controller
Clock Name
Operation clock
176
Description
Peripheral clock (PCLK)
Remarks
-
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CHAPTER 8 Low-power Dissipation Mode
8.3
MB91665 Series
8.3
Registers
This section explains the configurations and functions of the registers that are required for controlling
power dissipation.
■ List of registers that control power dissipation
Table 8.3-1 is a list of registers that control power dissipation.
Table 8.3-1 List of registers that control power dissipation
Abbreviated
Register Name
CM71-10158-1E
Register Name
Reference
STBCR
Standby mode control register
8.3.1
SLPRR
Sleep rate configuration register
8.3.2
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8.3
8.3.1
MB91665 Series
Standby Mode Control Register (STBCR)
This register controls low-power dissipation mode.
Figure 8.3-1 shows the bit configuration of the standby mode control register (STBCR).
Figure 8.3-1 Bit configuration of the standby mode control register (STBCR)
bit
Attribute
7
6
5
4
3
2
1
0
STOP
TIMER
SLEEP
DOZE
Reserved
Reserved
SLVL1
SLVL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
1
Initial value
R/W: Read/Write
[bit7]: STOP (Stop mode enable bit)
This bit enables transition to stop mode.
Written Value
Explanation
0
Does not transit to stop mode.
1
Transits to stop mode.
If this register is read after this bit enables transition to stop mode, power dissipation mode moves to stop
mode.
If the return resource from stop mode occurs, this bit is cleared to "0". For information on return resource
from stop mode, see "■ Return from stop mode" in "8.4.6 Operation in Stop Mode".
[bit6]: TIMER (Main timer mode/watch mode enable bit)
This bit enables transition to main timer mode/watch mode.
Written Value
Explanation
0
Does not transit to main timer mode/watch mode.
1
Transits to main timer mode/watch mode.
If this register is read after this bit enables transition to main timer mode/watch mode, power dissipation
mode moves to main timer mode/watch mode.
If, however, transition to stop mode is enabled with the STOP bit (STOP = 1), the setting of this bit is
ignored even when transition to main timer mode/watch mode is enabled by writing "1" to this bit.
If the return resource from main timer mode/watch mode occurs, this bit is cleared to "0". For
information on return resource from main timer mode, see "■ Return from the main timer mode" in "8.4.4
Operation in Main Timer Mode". For information on return resource from watch mode, see "■ Return
from the watch mode" in "8.4.5 Operation in Watch Mode".
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MB91665 Series
[bit5]: SLEEP (Sleep mode enable bit)
This bit enables transition to sleep mode.
Written Value
Explanation
0
Does not transit to sleep mode.
1
Transits to sleep mode.
If this register is read after this bit enables transition to sleep mode, power dissipation mode moves to
sleep mode.
If, however, transition to stop mode/main timer mode/watch mode is enabled with the STOP bit/TIMER
bit (STOP/TIMER = 1), the setting of this bit is ignored even when transition to sleep mode is enabled by
writing "1" to this bit.
If the return resource from sleep mode occurs, this bit is cleared to "0". For information on return
resource from sleep mode, see "■ Return from sleep mode" in "8.4.3 Operation in Sleep Mode".
[bit4]: DOZE (Doze mode enable bit)
This bit enables transition to doze mode.
Written Value
Explanation
0
Does not transit to doze mode (CPU intermittent sleep).
1
The CPU transits to doze mode (CPU intermittent sleep).
While the SLVL1 bit is set to "0", if the return resource from doze mode occurs, this bit is cleared to "0".
For information on return resource from doze mode, see "■ Return from doze mode" in "8.4.2 Operation
in Doze Mode".
[bit3, bit2]: Reserved bits
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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MB91665 Series
[bit1, bit0]: SLVL1, SLVL0 (Standby level setting bits)
The meaning of the value to be written to this bit varies depending on the low-power dissipation mode to
move to.
Low-power
Dissipation Mode
Stop mode/
Main timer mode/
watch mode
Sleep mode
Doze mode
*
SLVL1
SLVL0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Explanation
Does not place the output from each pin in Hi-Z in
stop mode/main timer mode/watch mode.
Places the output from each pin in Hi-Z in stop mode/
main timer mode/watch mode.
When moving to sleep mode, power dissipation mode
moves to CPU sleep mode (stops only the operation of
the CPU).
When moving to sleep mode, power dissipation mode
moves to bus sleep mode (stops operations of the CPU
and on-chip bus). *
When interrupt request occur, the DOZE bit is cleared
to "0".
When interrupt request occur, the DOZE bit is not
cleared to "0".
During DMA transfer, the on-chip bus operates.
<Notes>
180
•
For information on pins of which the output can be placed in Hi-Z in stop mode/main timer
mode/watch mode, see "APPENDIX D Pin State in Each CPU State".
•
The setting value of SLVL0 bit has no effect on the operation.
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CHAPTER 8 Low-power Dissipation Mode
8.3
MB91665 Series
8.3.2
Sleep Rate Configuration Register (SLPRR)
This register configures the operation state (RUN state) rate and sleep state rate (sleep rate) in doze
mode.
Figure 8.3-2 shows the bit configuration of the sleep rate configuration register (SLPRR).
Figure 8.3-2 Bit configuration of the sleep rate configuration register (SLPRR)
bit
7
6
5
4
3
2
1
0
RUN3
RUN2
RUN1
RUN0
SLP3
SLP2
SLP1
SLP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
<Note>
If this register is rewritten in doze mode, the rewritten setting is reflected at the next stop/activation
timing.
[bit7 to bit4]: RUN3 to RUN0 (Operation period bits)
These bits set the period during which the CPU operates in doze mode.
The CPU operation period is calculated from the value that is set to these bits as follows.
(Value of this bit + 1) × 4 × tCYCP
tCYCP : Period of the peripheral clock (PCLK)
For details of operation period, see "8.4.2 Operation in Doze Mode".
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MB91665 Series
[bit3 to bit0]: SLP3 to SLP0 (Sleep state period bits)
These bits set the period of sleep state in doze mode.
The sleep state period is calculated from the value that is set to these bits as follows.
(Value of this bit + 1) × 4 × tCYCP
tCYCP : Period of the peripheral clock (PCLK)
For details of the sleep state period, see "8.4.2 Operation in Doze Mode".
<Notes>
182
•
A delay may occur when the CPU accepts the sleep request. In this case, the sleep period will
be shorter than that obtained from the above calculation formula.
•
If the sleep state period is short, the CPU may not enter the sleep state depending on the
operating status of the CPU.
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CHAPTER 8 Low-power Dissipation Mode
8.4
MB91665 Series
8.4
An Explanation of Operations and Setting
Procedure Examples
This section explains the operation and use of low-power dissipation mode and includes examples of
the procedure for setting this mode.
■ Overview
You can reduce power dissipation by changing the division ratio of the operation clock or stopping the
operation clock.
You can also use the following low-power dissipation modes:
•
Doze mode
This mode intermittently operates the CPU repeatedly at a set operation rate.
By repeating operation and stop of the CPU alternately in the set period, the average power dissipation
of the CPU can be reduced.
•
Sleep mode
In this mode, only the peripheral functions operate while the CPU and on-chip bus are stopped.
One of the following two modes can be selected.
-
CPU sleep mode
-
Bus sleep mode
This mode stops the operation of the CPU.
This mode stops the CPU and on-chip bus.
•
Standby mode
This mode stops the entire device to put it in a standby state.
One of the following three modes can be selected.
CM71-10158-1E
-
Main timer mode
-
Watch mode
-
Stop mode
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8.4
8.4.1
MB91665 Series
Operation When Clock Control Is Set
Power dissipation and CPU performance can be optimized by adjusting the operation clocks that are
built in this series.
■ Overview
To reduce power dissipation by controlling the clock, the following two methods are available.
•
Clock division
•
Stop clock
By changing the division ratio of each operation clock, the operation frequency can be reduced.
This allows the user to specify a specific clock to stop.
■ Clock division
By changing the division ratio of each operation clock, power dissipation can be reduced. The division
ratio of the operation clock can be individually set.
Table 8.4-1 shows each operation clock and settable division ratio.
Table 8.4-1 Operation clock and settable division ratio
Operation Clock
Division Ratio
Base clock (BCLK)
Source clock (SRCCLK) divided by 1 to 8.
External bus clock (TCLK)
Base clock (BCLK) divided by 1 to 8.
Peripheral clock (PCLK)
Base clock (BCLK) divided by 1 to 16.
<Note>
The division method or condition differs depending on the operation clock. For information on the
division of the operation clock, see "CHAPTER 5 Clock Division Control Part".
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8.4
MB91665 Series
■ Stopping the clock
You can reduce power dissipation by stopping the unused operation clock.
Table 8.4-2 shows the relationship between the operation clock that can be stopped and the deliver/stop
timing.
Table 8.4-2 Relationship between the operation clock that can be stopped and the
deliver/stop timing
Operation Clock
External bus clock (TCLK)
Deliver/Stop Timing
Bus in sleep mode
Enabling the stop of the external bus clock (TCLK) automatically disables the external bus clock (TCLK)
delivery during the period in which there is no access by using the external bus.
If an access is attempted, clock delivery is resumed automatically and delivery is disabled again after
access is completed. For information on conditions for disabling external bus clock (TCLK), see
"CHAPTER 5 Clock Division Control Part".
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8.4
8.4.2
MB91665 Series
Operation in Doze Mode
This mode intermittently operates the CPU in order to reduce the average power dissipation by the
CPU.
■ Overview
Using doze mode enables reducing the average power dissipation by the CPU by operating and stopping
the CPU alternately at a set interval. Maintain performance while reducing power dissipation by
changing the sleep rate according to the processing load.
■ Setting the period
If you set the CPU operation period in the RUN3 to RUN0 bits and sleep state period in the SLP3 to
SLP0 bits of the sleep rate configuration register (SLPRR), the period will be calculated from the set
value using the following calculation formula.
(RUN + 1) × 4 × tCYCP + (SLP + 1) × 4 × tCYCP
RUN: Value for the RUN3 to RUN0 bits
SLP: Value for the SLP3 to SLP0 bits
tCYCP : Period of the peripheral clock (PCLK)
Figure 8.4-1 shows each cycle.
Figure 8.4-1 Operation period and sleep state period
PCLK
CPU operation
SLEEP
RUN
SLEEP
(RUN + 1) × 4 × tCYCP
(SLP + 1) × 4 × tCYCP
RUN
tCYCP : Period of the peripheral clock (PCLK)
SLEEP : Sleep state
RUN
: Operating
<Notes>
186
•
The above calculation formula does not contain delay time for the CPU to accept the sleep
request. Therefore an error may occur.
•
If the setting of the sleep state period is short, the CPU may not enter the sleep state depending
on the operating status of the CPU.
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8.4
MB91665 Series
■ Transition
If "1" is written to the DOZE bit in the standby mode control register (STBCR) after the cycle is set, doze
mode is entered and the CPU starts intermittent operation by alternately running and stopping according
to the setting configured in the sleep rate configuration register (SLPRR).
To return from doze mode, write "0" in the DOZE bit of standby mode control register (STBCR).
<Note>
If the sleep rate configuration register (SLPRR) is rewritten in doze mode, the rewritten setting is
reflected at the next stop/operation transition timing.
■ Return from doze mode
The CPU returns from doze mode in either of the following cases.
•
This device is reset.
•
"0" is written to the DOZE bit of standby mode control register (STBCR).
•
An interrupt request is generated when the SLVL1 bit of standby mode control register (STBCR) is "0".
Except the above cases, the configuration is retained so that you can use doze mode even after returning
from sleep mode, main timer mode, watch mode, or stop mode.
8.4.3
Operation in Sleep Mode
This mode is used to reduce power dissipation in the event wait state.
If sleep mode is entered, it continues until a return resource occurs. When a return resource occurs, it
returns to the program operation after two or three clock period.
■ Overview
Using sleep mode can significantly reduce power dissipation in the event wait state by stopping the CPU
and on-chip bus while allowing only the peripheral functions to operate.
The following two modes are available for sleep mode.
•
CPU sleep mode
This mode stops only the operation of the CPU.
Because the clock continues to be delivered to the DMA controller (DMAC) or to the on-chip bus,
operations of these devices continue.
Though the power dissipation is larger than that in bus sleep mode, quick response can be given to the
DMA transfer request.
•
Bus sleep mode
This mode stops the operation of the CPU and on-chip bus.
It also disables the clock delivery to the DMAC controller (DMAC) or on-chip bus. For information
on disabling clock, see "CHAPTER 5 Clock Division Control Part".
However, if the DMA transfer request is accepted, the clock delivery to the DMA controller (DMAC)
or on-chip bus will be tentatively resumed to allow DMA transfer.
After the DMA transfer is completed, the clock delivery will be disabled again.
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MB91665 Series
You can set whether to disable external bus clock (TCLK) delivery in bus sleep mode, using the TSTP
bit in the divide clock configuration register 1 (DIVR1).
For information on the divide clock configuration register 1 (DIVR1), see "5.4.2 Divide Clock
Configuration Register 1 (DIVR1)".
While this mode is slower in responding to the DMA transfer request than in CPU sleep mode, it can
reduce power dissipation.
■ Setting
Table 8.4-3 shows the settings required before changing to sleep mode.
Table 8.4-3 Setting register
Registers
Bit
Explanation
Divide clock
configuration register 1
(DIVR1)
TSTP
Sets whether to enable the external bus clock (TCLK) delivery
0 = Enabling
1 = Disabling
Standby mode control
register (STBCR)
SLVL1
Sets whether to change to CPU sleep mode or to bus sleep mode
0 = Change to CPU sleep mode
1 = Change to bus sleep mode
<Note>
If the external bus clock (TCLK) delivery is disabled by setting the TSTP bit (TSTP =1) in divide
clock configuration register 1 (DIVR1), DMA transfer cannot be activated by the external DMA
transfer request.
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MB91665 Series
■ Transition
By following the steps below, power dissipation mode moves to sleep mode.
1. Write "0" to the STOP bit, write "0" to the TIMER bit, and write "1" to the SLEEP bit of standby
mode control register (STBCR).
2. Read standby mode control register (STBCR).
<Note>
To prevent the CPU from executing the next instruction before moving to sleep mode, perform the
dummy processing that uses the value which is read in the instruction subsequent to step 2, as
shown in the example.
Example)
LDI
#value_of_sleep, R0
; SLEEP bit=1, SLVL1, SLVL0 bit setting
LDI
#_STBCR, R12
;
STB
R0, @R12
; write
LDUB
@R12, R0
; read (move to sleep mode)
MOV
R0, R0
; dummy processing
NOP
; dummy processing
NOP
; dummy processing
■ Return from sleep mode
The CPU returns from sleep mode in either of the following cases.
•
This device is reset.
•
An interrupt request is generated (whose interrupt level is other than "31").
For information on the interrupt level, see "CHAPTER 10 Interrupt Controller".
<Notes>
•
If the interrupt request is not accepted by the CPU when returning from sleep mode due to the
interrupt request, the program is executed starting from the next instruction after entering sleep
mode.If the interrupt request is accepted by the CPU, the operation is branched to the interrupt
processing routine.
•
In bus sleep mode, if a DMA transfer request is generated, the on-chip bus clock (HCLK)
delivery is tentatively resumed to perform DMA transfer. The on-chip bus clock (HCLK) delivery
is again disabled after DMA transfer is completed.
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8.4
8.4.4
MB91665 Series
Operation in Main Timer Mode
Main timer mode is categorized as a standby mode. Standby mode stops the entire device to put it in
a standby state. By doing so, it can significantly reduce power dissipation in the external event wait
state. The permitted clock oscillation, however, operates, allowing less reduction in power dissipation
than in stop mode.
In main timer mode, select the main clock (MCLK) oscillation as a source clock (SRCCLK) for the
CPU.
If main timer mode is entered, it continues until a return resource occurs. When a return resource
occurs, it returns to the program operation after two or three clock period.
■ Overview
In main timer mode, because main clock (MCLK) oscillation is permitted as a source clock (SRCCLK)
for the CPU, the count operation of the main timer is executed.
The sub clock (SBCLK) oscillation can be specified arbitrarily.
■ Setting
Table 8.4-4 shows the settings required before changing to main timer mode.
Table 8.4-4 Setting register
Registers
Clock source select
register (CSELR)
Standby mode
control register
(STBCR)
Bit
Explanation
CKS1, CKS0
Selects main clock (MCLK) for the CPU source clock (SRCCLK)
(CKS1, CKS0=00 or 01)
PCEN
Stops PLL clock (PLLCLK) oscillation (PCEN = 0)
SCEN
Specify sub clock (SBCLK) oscillation.
0=Stop oscillation
1=Start oscillation
SLVL1
Sets the output signal from the pins in main timer mode
0 = Retain the state in effect before main timer mode is entered
1 = Hi-Z
<Note>
When moving to main timer mode, if the SLVL1 bit of the standby mode control register (STBCR) is
set to "0" while setting doze mode, the DOZE bit is cleared to "0" on returning from main timer
mode to end doze mode.
■ Transition
By following the steps below, power dissipation mode moves to main timer mode.
1. Write "0" to the STOP bit, write "1" to the TIMER bit, and write "0" to the SLEEP bit in the standby
mode control register (STBCR).
2. Read the standby mode control register (STBCR).
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<Note>
To prevent the CPU from executing the next instruction before moving to main timer mode, perform
the dummy processing that uses the value which is read in the instruction subsequent to step 2, as
shown in the example.
Example)
LDI
#value_of_timer, R0
; TIMER bit = 1, SLVL1, SLVL0 bit setting
LDI
#_STBCR, R12
;
STB
R0, @R12
; write
LDUB
@R12, R0
; read (move to main timer mode)
MOV
R0, R0
; dummy processing
NOP
; dummy processing
NOP
; dummy processing
■ Return from the main timer mode
The CPU returns from main timer mode in either of the following cases.
•
This device is reset.
•
Below interrupt requests are generated (whose interrupt level is other than "31").
-
Main timer interrupt
-
Sub timer interrupt
-
Watch counter interrupt
-
External interrupt
-
An interrupt by the WKUP bit of the USB function
For the interrupt level, see "CHAPTER 10 Interrupt Controller".
<Note>
If the interrupt request is not accepted by the CPU when returning from main timer mode due to the
interrupt request, the program is executed starting from the next instruction after entering main
timer mode.If the interrupt request is accepted by the CPU, the operation is branched to the
interrupt processing routine.
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8.4
8.4.5
MB91665 Series
Operation in Watch Mode
Watch mode is categorized as a standby mode. Standby mode stops the entire device to put it in a
standby state. By doing so, it can significantly reduce power dissipation in the external event wait
state. The permitted clock oscillation, however, operates, allowing less reduction in power dissipation
than in stop mode.
In watch mode, select the sub clock (SBCLK) oscillation as a source clock (SRCCLK) for the CPU.
If watch mode is entered, it continues until a return resource occurs. When a return resource occurs,
it returns to the program operation after two or three clock period.
■ Overview
In watch mode, because sub clock (SBCLK) oscillation is permitted as a source clock (SRCCLK) for the
CPU, the count operation of the sub timer and watch counter is executed.
■ Setting
Table 8.4-5 shows the settings required before changing to watch mode.
Table 8.4-5 Setting register
Registers
Clock source select
register (CSELR)
Standby mode
control register
(STBCR)
Bit
Explanation
CKS1, CKS0
Selects sub clock (SBCLK) for the CPU source clock
(SRCCLK) (CKS1, CKS0=11)
PCEN
Stops PLL clock (PLLCLK) oscillation (PCEN = 0)
MCEN
Stops main clock (MCLK) oscillation (MCEN = 0)
SLVL1
Sets the output signal from the pins in watch mode
0 = Retain the state in effect before watch mode is entered
1 = Hi-Z
<Note>
When moving to watch mode, if the SLVL1 bit of the standby mode control register (STBCR) is set
to "0" while setting doze mode, the DOZE bit is cleared to "0" on returning from watch mode to end
doze mode.
■ Transition
By following the steps below, power dissipation mode moves to watch mode.
1. Write "0" to the STOP bit, write "1" to the TIMER bit, and write "0" to the SLEEP bit in the standby
mode control register (STBCR).
2. Read the standby mode control register (STBCR).
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<Note>
To prevent the CPU from executing the next instruction before moving to watch mode, perform the
dummy processing that uses the value which is read in the instruction subsequent to step 2, as
shown in the example.
Example)
LDI
#value_of_timer, R0
; TIMER bit = 1, SLVL1, SLVL0 bit setting
LDI
#_STBCR, R12
;
STB
R0, @R12
; write
LDUB
@R12, R0
; read (move to watch mode)
MOV
R0, R0
; dummy processing
NOP
; dummy processing
NOP
; dummy processing
■ Return from the watch mode
The CPU returns from watch mode in either of the following cases.
•
This device is reset.
•
Below interrupt requests are generated (whose interrupt level is other than "31").
-
Sub timer interrupt request
-
Watch counter interrupt request
-
External interrupt request
-
An interrupt by the WKUP bit of the USB function.
For the interrupt level, see "CHAPTER 10 Interrupt Controller".
<Note>
If the interrupt request is not accepted by the CPU when returning from watch mode due to the
interrupt request, the program is executed starting from the next instruction after entering watch
mode.If the interrupt request is accepted by the CPU, the operation is branched to the interrupt
processing routine.
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8.4.6
MB91665 Series
Operation in Stop Mode
Stop mode is categorized as a standby mode. Standby mode stops the entire device to put it in a
standby state. By doing so, it can significantly reduce power dissipation in the external event wait
state.
Stop mode stops all operations including the oscillation of all clocks to minimize power dissipation.
■ Overview
Using stop mode can minimize power dissipation by stopping the oscillation of all clocks.
To return to the program operation after the return request is generated, however, a certain amount of
oscillation stabilization wait time is required.
■ Setting
The setting may differ depending on the source clock of the CPU (SRCCLK) before entering stop mode
and after returning from stop mode.
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● If the source clock (SRCCLK) of the CPU before/after stop mode is a sub clock
(SBCLK)
Table 8.4-6 shows the settings required before changing to stop mode.
Table 8.4-6 Setting register
Registers
Clock source select
register (CSELR)
Standby mode
control register
(STBCR)
Bit
Explanation
CKS1, CKS0
Selects sub clock (SBCLK) for the CPU source clock
(SRCCLK) (CKS1, CKS0=11)
PCEN
Stops PLL clock (PLLCLK) oscillation (PCEN = 0)
SLVL1
Sets the output signal from the pins in stop mode
0 = Retain the state in effect before stop mode is entered
1 = Hi-Z
<Note>
At transition to stop mode, if the SLVL1 bit of standby mode control register (STBCR) is set to "0"
while doze mode has been set, the DOZE bit is cleared to "0" when the CPU returns from stop
mode to end doze mode.
● If the source clock (SRCCLK) of the CPU before/after stop mode is a main
clock (MCLK)
Table 8.4-7 shows the settings required before changing to stop mode.
Table 8.4-7 Setting register
Registers
Clock source select
register (CSELR)
Standby mode
control register
(STBCR)
Bit
Explanation
CKS1, CKS0
Selects the main clock (MCLK) as a source clock
(SRCCLK) of the CPU
(CKS1, CKS0=00/01)
PCEN
Stops PLL clock (PLLCLK) oscillation (PCEN = 0)
SLVL1
Sets the output signal from the pins in stop mode
0 = Retain the state in effect before stop mode is entered
1 = Hi-Z
<Note>
At transition to stop mode, if the SLVL1 bit of standby mode control register (STBCR) is set to "0"
while doze mode has been set, the DOZE bit is cleared to "0" when the CPU returns from stop
mode to end doze mode.
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■ Transition
By following the steps below, power dissipation mode moves to stop mode.
1. Write "1" to the STOP bit write "0" to the TIMER bit, and write "0" to the SLEEP bit in the standby
mode control register (STBCR).
2. Read the standby mode control register (STBCR).
<Note>
To prevent the CPU from executing the next instruction before moving to stop mode, perform the
dummy processing that uses the value which is read in the instruction subsequent to step 2, as
shown in the example.
Example)
LDI
#value_of_stop, R0
; STOP bit = 1, SLVL1, SLVL0 bit setting
LDI
#_STBCR, R12
;
STB
R0, @R12
; write
LDUB
@R12, R0
; read (move to stop mode)
MOV
R0, R0
; dummy processing
NOP
; dummy processing
NOP
; dummy processing
■ Return from stop mode
The CPU returns from stop mode in either of the following cases.
•
This device is reset.
•
Below interrupt requests are generated (whose interrupt level is other than "31").
-
External interrupt
-
An interrupt by the WKUP bit of the USB function
For information on the interrupt level, see "CHAPTER 10 Interrupt Controller".
<Note>
If the interrupt request is not accepted by the CPU when returning from stop mode due to the
interrupt request, the program is executed starting from the next instruction after entering stop
mode.If the interrupt request is accepted by the CPU, the operation is branched to the interrupt
processing routine.
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8.5
MB91665 Series
8.5
Notes on Use
Note the following points on using low-power dissipation mode.
•
•
If the interrupt request is generated when low-power dissipation mode is switched to the following
modes, the switching is disabled.
-
Doze mode
-
Sleep mode
-
Main timer mode
-
Watch mode
-
Stop mode
For instance, sleep mode is not entered in the following cases. Move to sleep mode after clearing the
interrupt request.
-
CM71-10158-1E
In sleep mode, when returning from sleep mode due to an interrupt request that has not been
accepted by the CPU, an operation to move to sleep mode is performed again without clearing the
interrupt request.
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CHAPTER 9 Reset
This chapter explains the functions and operations of reset.
9.1
9.2
9.3
9.4
9.5
9.6
CM71-10158-1E
Overview
Configuration
Pins
Registers
Explanation of Operations
Operating State and Transition
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9.1
9.1
MB91665 Series
Overview
This section explains "reset" to initialize the internal circuit.
■ Overview
This device has the following three types of reset resource.
•
INIT pin input
•
Watchdog reset 0
•
Software reset
If either one of the reset resources occurs, operation of all the programs and internal circuits is stopped for
initialization.
This state is called a reset state.
If the reset resource is released, operation of the programs and the hardware starts.
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9.2
MB91665 Series
9.2
Configuration
The configuration of reset is shown.
■ Block diagram of reset
Figure 9.2-1 is a block diagram of reset.
Figure 9.2-1 Block diagram of reset
Reset
(RST)
Reset request
S
Q
RDLY
R
RSTCR
On-chip bus
Peripheral
clock (PCLK)
INIT pin
Delay
selector
8 bit
Generation of reset
Peripheral
clocks (PCLK)
4 bit
Extension
counter
Delay counter
Bus idle response
Initialize reset (INIT)
Noise
filter
S
Peripheral
clock
(PCLK)
Peripheral
clocks
(PCLK)
Q
Extension
counter
R
2 bit
Resource
extension counter
Reset request flag
Generation of reset
S
Peripheral clock
(PCLK)
Q
R
2 bit
Result extension
counter
Reset request flag
Generation of
reset
S
Watchdog reset 0
Peripheral clock
(PCLK)
4 bit
Q
RSTRR
R
2 bit
Resource
extension counter
IRRST
Reset request flag
ERST
Generation of
reset
WDG0
SRST
RSTRR
read
RSTRR: Reset result register (RSTRR)
RSTCR: Reset control register (RSTCR)
Software reset
request
SRST
RSTCR
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•
MB91665 Series
Reset result register (RSTRR)
This register indicates the reset resource.
•
Reset control register (RSTCR)
This register controls issuing of reset.
•
Delay counter
This counter counts the period from generation of the reset request until the bus enters the idle state.
If the bus does not enter the idle state within a certain period of time, the initialize reset (INIT) is
forcibly issued.
•
Result extension counter
This counter counts the amount of time for the reset resource to be extended. Each reset resource will
be retained until reset is issued.
■ Clocks
Table 9.2-1 shows clocks to be used for reset.
Table 9.2-1 Clocks used for reset
Clock Name
Operation clock
202
Description
Peripheral clock (PCLK)
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CHAPTER 9 Reset
9.3
MB91665 Series
9.3
Pins
This section explains the pins that are used for reset.
■ Overview
The following pins are used for reset.
•
INIT pin
The external input pins are used to input the reset request.
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9.4
9.4
MB91665 Series
Registers
This section explains the configuration and functions of registers used for reset.
■ List of registers used for reset
Table 9.4-1 shows the list of registers used for reset.
Table 9.4-1 List of registers used for reset
Abbreviated
Register Name
204
Register Name
Reference
RSTRR
Reset result register
9.4.1
RSTCR
Reset control register
9.4.2
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CHAPTER 9 Reset
9.4
MB91665 Series
9.4.1
Reset Result Register (RSTRR)
This register stores the reset resource.
It stores all the reset resources that have occurred since the power was turned on until this register is read.
Figure 9.4-1 shows the bit configuration of the reset result register (RSTRR).
Figure 9.4-1 Bit configuration of the reset result register (RSTRR)
bit
Attribute
7
6
5
4
3
2
1
0
IRRST
ERST
Undefined
WDG0
Undefined
Undefined
Undefined
SRST
R
R
R
R
R
R
R
R
Initial value
* This differs depending on the reset resource.
R: Read only
*: The initial values are as follows:
Reset Resource
Initial Value
INIT pin input
11XXXXXX
Watchdog reset 0
XXX1XXXX
Timeout of the watchdog reset 0
1XX1XXXX
Software reset
XXXXXXX1
Timeout for software reset
1XXXXXX1
Register reading
00000000
X: Not initialized.
<Note>
If this register is read, all the bits are cleared.
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[bit7]: IRRST (Irregular reset bit)
A reset is issued without waiting for completion of bus access. This is called an irregular reset. If an
irregular reset occurs, the contents of the memory may be damaged.
If either a reset by the INIT pin input or a reset timeout occurs, this bit changes to "1".
Read Value
Explanation
0
No irregular reset is detected.
The memory contents are guaranteed to be damage free.
1
An irregular reset is detected.
The contents of the memory may have been damaged during the last reset.
For details of the irregular reset, see "■ Irregular reset" in "9.5.3 Operation of Reset".
[bit6]: ERST (Reset pin input bit)
This bits indicates whether the reset by an INIT pin input has occurred.
Read Value
Explanation
0
Reset by an INIT pin input has not occurred.
1
Reset by an INIT pin input has occurred.
[bit5]: Undefined bit
In case of reading
A value is undefined.
[bit4]: WDG0 (Watchdog reset 0 bit)
This bit indicates whether the watchdog reset 0 has occurred.
If a reset timeout occurred in watchdog timer 0, the IRRST bit also changes to "1".
Read Value
Explanation
0
A watchdog reset 0 has not occurred.
1
A watchdog reset 0 has occurred.
[bit3 to bit1]: Undefined bits
In case of reading
A value is undefined.
[bit0]: SRST (Software reset bit)
This bit indicates whether a software reset (RSTCR:SRST) has occurred.
If a reset timeout occurred in the software reset (RSTCR:SRST), the IRRST bit also changes to "1".
Read Value
206
Explanation
0
A software reset (RSTCR:SRST) has not occurred.
1
A software reset (RSTCR:SRST) has occurred.
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CHAPTER 9 Reset
9.4
MB91665 Series
9.4.2
Reset Control Register (RSTCR)
This register controls issuing of reset.
Figure 9.4-2 shows the bit configuration of the reset control register (RSTCR).
Figure 9.4-2 Bit configuration of the reset control register (RSTCR)
bit
Attribute
7
6
5
4
3
2
1
0
RDLY2
RDLY1
RDLY0
Reserved
Reserved
Reserved
Reserved
SRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Initial value
R/W: Read/Write
[bit7 to bit5]: RDLY2 to RDLY0 (Reset issue delay bit)
These bits set the delay time for reset issuing, meaning the length of time that it takes for all the busses to
become idle after acceptance of the reset request (delay cycle).
RDLY2
RDLY1
RDLY0
Explanation
0
0
0
Peripheral clock (PCLK) × 2 cycles
0
0
1
Peripheral clock (PCLK) × 4 cycles
0
1
0
Peripheral clock (PCLK) × 8 cycles
0
1
1
Peripheral clock (PCLK) × 16 cycles
1
0
0
Peripheral clock (PCLK) × 32 cycles
1
0
1
Peripheral clock (PCLK) × 64 cycles
1
1
0
Peripheral clock (PCLK) × 128 cycles
1
1
1
Peripheral clock (PCLK) × 256 cycles
<Notes>
•
The values of each bit are initialized by reset. Writing after reset is possible only once.
•
If a low value is set for the delay cycle, a irregular reset due to the reset timeout will likely occur.
In contrast, if a high value is set for the delay cycle, it may take long for the reset to be issued
after the reset resource occurs.
•
For information on the irregular reset, see "■ Irregular reset" in "9.5.3 Operation of Reset".
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[bit4 to bit1]: Reserved bits
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
[bit0]: SRST (Software reset bit)
A software reset request occurs if the reset control register (RSTCR) is read after "1" is written to this bit.
Written Value
Explanation
0
A reset request has not occurred.
1
A reset request has occurred by reading this register.
<Notes>
208
•
After "1" is written to this bit, any subsequent writing in the reset control register (RSTCR) is
ignored until reset occurs.
•
Before generating a software reset request by writing "1" to SRST bit, switch the source clock to
the main clock (MCLK) divided by 2.
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CHAPTER 9 Reset
9.5
MB91665 Series
9.5
Explanation of Operations
This section explains the operation of reset.
9.5.1
Reset Types
Three types of resets are provided for this device, whose reset resources and contents for initialization
differ from one another.
•
Power-on reset (SINIT)
This reset is used to initialize the unstable state of the division circuit.
At the same time, initialize reset (INIT) and reset (RST) are issued.
•
Reset resource
- Input "L" level to INIT pin
Target of initialization
- Oscillation stabilization wait time of the main clock (MCLK)
Reset that concurrently occurs
- Initialize reset (INIT)
- Reset (RST)
Initialize reset (INIT)
Initializes the following registers to reset the clock control settings.
- Clock source select register (CSELR)
- Clock source monitor register (CMONR)
- PLL configuration register (PLLCR)
- Clock stabilization time select register (CSTBR)
Reset (RST) is issued at the same time.
•
Reset resource
- INIT pin input
- Reset time out
- Watchdog reset 0
Target of initialization
- Source clock = Main clock (MCLK) divided by 2
- Clock oscillation = Main clock oscillates, sub/PLL clock stopped
- Division rate of the PLL macro oscillation clock
- Multiplying factor of the PLL clock (PLLCLK)
- Oscillation stabilization wait time of the PLL clock
- Division rate of the PLL input clock
- Oscillation stabilization wait time of the sub clock
Reset that concurrently occurs
- Reset (RST)
Reset (RST)
This reset initializes the program operation.
CM71-10158-1E
Reset resource
- INIT pin input
- Reset time out
- Watchdog reset 0
- Software reset
Target of initialization
All the register settings and hardware other than those that are
initialized by the power-on reset (SINIT) and initialize reset (INIT).
Reset that concurrently occurs
No
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9.5
9.5.2
MB91665 Series
Reset Resource
There are three types of reset resource. The level of the reset that is issued differs depending on the reset
resource.
In addition, whether there is an occurrence of the irregular reset that issues initialize reset (INIT) without
verifying completion of bus access, also depends on the reset resource.
•
INIT pin input
An initialize reset (INIT) request occurs while "L" level is input in the INIT pin.
•
Generation source
"L" level is input in the INIT pin
Cancellation source
"H" level is input in the INIT pin
Reset level
Issues all of the three resets: power-on reset (SINIT), initialize reset (INIT), and
reset (RST)
Corresponding flag
ERST bit of the reset result register (RSTRR) = 1
Operation
Issues the power-on reset (SINIT), initialize reset (INIT), and reset (RST)
without waiting for a completion of bus access (irregular reset).
Watchdog reset 0
The watchdog reset 0 request is generated if the period set for the watchdog timer elapses. If the
watchdog reset 0 request is generated, the initialize reset (INIT) is issued.
•
Generation source
The period set for the watchdog timer elapses
Cancellation source
Automatically cancelled after the initialize reset (INIT) is issued.
Reset level
Issues the initialize reset (INIT) and reset (RST)
Corresponding flag
WDG0 bit of the reset result register (RSTRR) = 1
Operation
- Issues an initialize reset (INIT) and reset (RST) after the completion of bus
access is verified.
- Forcibly issues an initialize reset (INIT) and reset (RST) if a reset timeout
occurs before completion of bus access (irregular reset).
Software reset (RSTCR:SRST)
If the reset control resister (RSTCR) is read after "1" is written to the SRST bit of the reset control
register (RSTCR), a reset (RST) request is generated.
210
Generation source
The reset control register (RSTCR) is read after "1" is written to the SRST bit of
the reset control register (RSTCR).
* Set the main clock (MCLK) to the source clock (SRCCLK) before writing "1"
to SRST bit.
Cancellation source
Automatically cancelled after the reset (RST) is issued.
Reset level
Issues only reset (RST)
Corresponding flag
SRST bit of the reset result register (RSTRR) = 1
Operation
- Issues reset (RST) after verifying completion of bus access.
- Forcibly issues an initialize reset (INIT) and reset (RST) if a reset timeout
occurs before completion of bus access (irregular reset).
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CHAPTER 9 Reset
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MB91665 Series
■ Flow of reset result determination
Figure 9.5-1 Flow of reset result determination
Read RSTRR
(All bits of RSTRR will be cleared)
No
IRRST = 1 ?
Yes
No
ERST = 1 ?
Yes
Reset by
INIT pin = L
CM71-10158-1E
Determination of lower 6bit
(Reset time out)
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Determination of lower 6bit
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9.5
9.5.3
MB91665 Series
Operation of Reset
■ Flow of reset operation
A series of operations from the generation of reset, through reset state, until the CPU starts operation is
called a reset sequence.
Figure 9.5-2 shows the reset sequence.
Figure 9.5-2 Reset sequence
Generation of reset
resource
From the INIT pin, input the
"L" level
Generation of reset
resource
Watchdog reset 0
Generation of reset
resource
Software reset
Wait for bus idle
Wait for bus idle
Reset
timeout
Bus idle
state
Reset
timeout
Bus idle
state
Power-on reset
(Issue SINIT)
Issue initialize reset (INIT)
Issue reset (RST)
Issue reset (RST)
Cancel initialize reset (INIT)
Cancel reset (RST)
Fetch reset vector
Program starts
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1. Retrieval and extension of reset resource
The generated reset resource is asynchronously retrieved and retained until reset is issued.
2 bits of resource extension counter retains the reset resource for at least 4Ts (T: Peripheral clock
(PCLK) period).
2. Generation of the reset request
Reports the generated reset request to the internal bus controller to perform the following processing.
-
Stops the program operation of the CPU (same as for sleep mode).
-
Verifies that the idle request has been reported to all busses.
At the same time, the delay counter starts counting.
3. Acceptance of reset request and issue of reset
After all processing for the reset request is completed, the reset request is accepted.
An irregular reset is issued if a reset timeout occurs due to an overflow of the delay counter before
response of the completion from the bus.
4. Issue of reset
-
Input "L" level to INIT pin
Issues a power-on reset (SINIT), initialize reset (INIT), and reset (RST).
-
Watchdog reset 0
-
Reset time out
Issues initialize reset (INIT) and reset (RST).
Issues initialize reset (INIT) and reset (RST).
-
Software reset (RSTCR:SRST)
Issues reset (RST).
5. Cancellation of reset resource
If the reset resource is cancelled, the reset request is extended for a period of 4Ts (T: Peripheral
clock (PCLK)). The request is then retained for 16 Ts (T: Peripheral clock (PCLK)) reset period.
Therefore, the minimum cycle of reset issue is 20 Ts.
6. Cancellation of reset
When the reset cycle ends, reset is cancelled and the hardware starts operation.
7. Retrieval of the reset vector (fetch)
The CPU starts fetching the reset vector (000F FFFCH). The CPU retrieves the fetched reset vector in
the program counter (PC) to start program operation.
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■ Power-on reset (SINIT)
Initialize reset (INIT) and reset (RST) are also issued at the same time as the power-on reset (SINIT) is
issued. Figure 9.5-3 shows the respective reset issue sequence after the reset resource of the power-on
reset (SINIT) is cancelled.
Figure 9.5-3 Each reset issue sequence after the reset resource
of the power-on reset (SINIT) is cancelled
PCLK
SINIT
INIT
RST
PCLK × 16 cycles
PCLK × 16 cycles
Oscillation stabilization wait time + (PCLK × 4 cycles)
PCLK
SINIT
INIT
RST
214
:
:
:
:
Peripheral clock (PCLK)
Power-on reset (SINIT)
Initialize reset (INIT)
Reset (RST)
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CHAPTER 9 Reset
9.5
MB91665 Series
■ Initialize reset (INIT)
When initialize reset (INIT) is issued, reset (RST) is also issued at the same time.
Figure 9.5-4 shows the issue sequence of the respective resets after the reset resource of initialize reset
(INIT) is cancelled.
Figure 9.5-4 Issue sequence of each reset after cancellation of the reset resource of initialize reset (INIT)
PCLK
Reset
Resource
INIT
RST
PCLK × 4 cycles
PCLK × 16 cycles
PCLK × 16 cycles
PCLK : Peripheral clock (PCLK)
INIT
: Initialize reset (INIT)
RST
: Reset (RST)
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■ Reset (RST)
Figure 9.5-5 shows the respective reset issue sequence after the reset resource of reset (RST) is cancelled.
Figure 9.5-5 Each reset issue sequence after the reset resource of the reset (RST) is cancelled
PCLK
Reset
Resource
INIT
L
RST
PCLK × 4 cycles
PCLK × 16 cycles
PCLK : Peripheral clock (PCLK)
INIT
: Initialize reset (INIT)
RST
: Reset (RST)
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CHAPTER 9 Reset
9.5
MB91665 Series
9.5.4
Irregular reset
Irregular reset occurs in the following cases.
•
When an INIT pin input (INIT) is used
•
When a reset timeout occurs
(The delay counter overflows before the response from the bus is received during watchdog reset 0 /
software reset (RSTCR: SRST).)
If irregular reset occurs, the following processes are executed.
•
Initialize reset (INIT) is issued.
•
The IRRST bit of the reset result register (RSTRR) changes to "1".
<Note>
When irregular reset occurs, the bus access may be performed at the time of reset input. In this
case, the contents of the memory may be damaged.
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CHAPTER 9 Reset
9.6
9.6
MB91665 Series
Operating State and Transition
This section explains each operating state and how to control it.
■ Operating state
Figure 9.6-1 shows transition of the operating state.
Figure 9.6-1 Transition of the operating state
(1) INIT = L
(10) External interrupt that does not require the clock.
(2) INIT = H
(11) Sub timer interrupt/watch counter interrupt
(3) Oscillation stabilization wait end
(12) Switch from main to sub (write instruction)
(4) RST cancel
(13) Switch from sub to main (write instruction)
(5) Software reset (RST)
(14) Switch from main to PLL (write instruction)
(6) Sleep mode (write instruction)
(15) Switch from PLL to main (write instruction)
(7) Stop mode (write instruction)
(16) Watchdog reset/software reset timeout (INIT)
(8) Main timer mode/ watch mode (write instruction)
(17) INIT cancel
(9) Interrupt
(18) Main timer interrupt/sub timer interrupt/watch counter interrupt
Power on
(1)
Power-on reset
(SINIT)
(2)
(1)
When MCRDY = 0
Main oscillation
stabilization wait
reset
(1)
PLL sleep
(3)
(9)
(6)
When MCRDY = 1
(16)
(1) Setting initialization
PLL RUN
(1)
(INIT)
Doze mode
(15)
(14)
(17)
(16)
(10)
(4)
(1)
(11)
Main program reset
(RST)
Main timer mode
(1)
(16)
(10)
(1)
Watch mode
(8)
(5)
(13)
Main RUN
(18)
(8)
(7)
Sub RUN
(12)
Doze mode
(6)
(9)
Doze mode
(1)
(1)
(7)
(1)
(6)
Sub stop
(9)
(1)
Main stop
Main sleep
Sub sleep
(10)
(3)
(10)
(3)
Sub oscillation
stabilization wait
RUN
Main oscillation
stabilization wait
RUN
(1)
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(1)
(1)
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CHAPTER 9 Reset
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MB91665 Series
● RUN state (normal operation)
Program is running.
All the internal clocks are delivered and all the circuits are enabled.
The Hi-Z control of the external pins in stop state, main timer mode state and watch mode state is
cancelled.
● Sleep state
Program is stopped. Transition occurs by program operation.
Only program execution of the CPU is stopped. The peripheral circuits are enabled.
The built-in memories and external busses are suspended until the DMA controller (DMAC) request is
received.
In bus sleep mode, the internal bus is suspended until the DMA controller (DMAC) request is received.
•
If a valid interrupt request is generated, the device undergoes transition to the RUN state (normal
operation).
•
If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state.
● Watch mode state
The device is in a suspended state. Transition occurs by the program operation.
Internal circuits other than the oscillation circuits (sub clock (SBCLK)) are stopped.
The external pins can be uniformly set to Hi-Z (excluding certain pins).
•
If an external interrupt request is generated, the device undergoes transition to the RUN state (normal
operation).
•
If a sub timer interrupt, or watch counter interrupt request is generated, it undergoes transition to the
RUN state (normal operation).
•
If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state.
<Note>
Stop oscillation of the main clock (MCLK) and PLL clock (PLLCLK) before transition to watch
mode.
● Main timer mode state
The device is in a suspended state. Transition occurs by the program operation.
Internal circuits other than the oscillation circuits (main clock (MCLK) and sub clock (SBCLK)) are
stopped.
The external pins can be uniformly set to Hi-Z (excluding certain pins).
•
If an external interrupt is generated, the device undergoes transition to the RUN state (normal
operation).
•
If a main timer interrupt, sub timer interrupt, and watch counter interrupt requests are generated, it
undergoes transition to the RUN state (normal operation).
•
If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state.
<Note>
Stop oscillation of the PLL clock (PLLCLK) before transition to main timer mode.
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● Stop state
The device is in a suspended state. Transition occurs by the program operation.
All the internal circuits are suspended.
The external pins can be uniformly set to Hi-Z (excluding certain pins).
•
If an external interrupt request is generated, the device undergoes transition to the oscillation
stabilization wait RUN state.
•
If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state.
<Note>
Stop oscillation of the PLL clock (PLLCLK) before transition to the stop state.
● Oscillation stabilization wait RUN state
The device is in a suspended state. Transition to this state occurs after the device returns from the stop
state.
All the internal circuits are suspended (excluding timer operation for clock stabilization wait).
While all the internal clocks are stopped, oscillation circuits that have been enabled operate.
•
When the oscillation stabilization wait time elapses, the device undergoes transition to the RUN state
(normal operation).
•
If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state.
● Oscillation stabilization wait reset (RST) state
The device is in a suspended state. Transition occurs after the device returns from power-on reset
(SINIT).
All the internal circuits are suspended (excluding timer operation for oscillation stabilization wait).
While all the internal clocks are suspended, the main oscillation circuit operates.
•
When the oscillation stabilization wait time elapses, the device undergoes transition to the initialize
reset (INIT) state.
•
If "L" level is input in the INIT pin, it undergoes transition to the power-on reset (SINIT) state.
● Program reset (RST) state
Program is in the initialized state. Transition occurs when a reset (RST) request is accepted or after the
initialize reset (INIT) state ends.
The program execution of the CPU is suspended and the program counter is initialized. The peripheral
circuits are initialized (excluding certain circuits).
All the internal clocks as well as the oscillation circuits that have been enabled and the PLL clock
(PLLCLK) operate.
220
•
The reset (RST) request for the internal circuits is generated. When the reset (RST) request disappears,
transition to the RUN state (normal operation) occurs.
•
If "L" level is input in the INIT pin, the device undergoes transition to the power-on reset (SINIT) state.
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CHAPTER 9 Reset
9.6
MB91665 Series
● Initialize reset (INIT) state
This is the state in which all settings are initialized. Transition occurs when the initialize reset (INIT)
request is accepted.
The program execution of the CPU is suspended and the program counter is initialized. All the peripheral
circuits are initialized. The main clock (MCLK) oscillation circuit operates (while the sub clock
(SBCLK) oscillation circuit and PLL clock (PLLCLK) oscillation circuit stop operation). All the internal
clocks stop while the "L" level is being input in the INIT pin. Otherwise, they operate.
Initialize reset (INIT) and reset (RST) are output to the internal circuit.
•
When the initialize reset (INIT) request disappears, this state is cancelled and transition to the program
reset (RST) state occurs.
•
If "L" is input in the INIT pin, the device undergoes transition to the power-on reset (SINIT) state.
■ Priority of state transition requests
state transition requests are prioritized in the following order in any states. However, since some requests
are generated only in the particular states, they are enabled only in those states.
Highest priority
Power-on reset (SINIT) request
Initialize reset (INIT) request
Oscillation stabilization wait time end
Occurs only in the oscillation
stabilization wait reset state and
oscillation stabilization wait RUN state
Reset (RST) request
Lowest priority
CM71-10158-1E
Valid interrupt request
Occurs only in the RUN, sleep, stop, and
watch mode state
Stop mode request (register write)
Occurs only in the RUN state
Watch mode request (register write)
Occurs only in the RUN state
Sleep mode request (register write)
Occurs only in the RUN state
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CHAPTER 10 Interrupt Controller
This chapter explains the functions and operations of the
interrupt controller.
10.1
10.2
10.3
10.4
Overview
Configuration
Registers
An Explanation of Operations and Setting Procedure
Examples
10.5 Notes on Use
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CHAPTER 10 Interrupt Controller
10.1
MB91665 Series
10.1 Overview
The interrupt controller determines the priority of an interrupt request and sends the request to the
CPU.
■ Overview
The interrupt control has the following functions:
224
•
Accepts interrupt requests from peripheral functions.
•
Determines the priority of sending interrupt requests to the CPU according to the interrupt level and
interrupt vector.
•
Sends the highest priority interrupt request to the CPU.
•
Sends the interrupt vector number of the highest priority interrupt request to the CPU.
•
Generates a request for returning from sleep mode or stop mode according to an interrupt request with
an interrupt level other than "1111".
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CHAPTER 10 Interrupt Controller
10.2
MB91665 Series
10.2 Configuration
This section explains the interrupt controller configuration.
■ Block diagram of interrupt controller
Figure 10.2-1 shows a block diagram of the interrupt controller.
Figure 10.2-1 Block diagram of interrupt controller
Priority
determination
ICR00
ICR47
Level
Interrupt Level
Vector
Interrupt vector number
Request for return
Interrupt requests from peripheral functions
Peripheral bus
•
Interrupt priority determination circuit
This circuit determines the priority of an incoming interrupt request. It also generates a request to
return from sleep mode or stop mode.
•
Interrupt level generating circuit
This circuit transmits the interrupt level of an interrupt request to the CPU.
•
Interrupt vector generating circuit
This circuit sends the interrupt vector of an interrupt request to the CPU.
•
Interrupt control registers (ICR00 to ICR47)
These registers are used to set the interrupt levels of interrupt requests.
■ Clocks
Clock Name
Operation clock
CM71-10158-1E
Description
Peripheral clock (PCLK)
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10.3
MB91665 Series
10.3 Registers
This section explains the configurations and functions of the registers used by the interrupt controller.
■ Interrupt controller registers
Table 10.3-1 lists the interrupt controller registers.
Table 10.3-1 Interrupt controller registers
Abbreviated
Register Name
ICR00 to ICR47
226
Register Name
Interrupt control registers 00 to 47
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Reference
10.3.1
CM71-10158-1E
CHAPTER 10 Interrupt Controller
10.3
MB91665 Series
10.3.1
Interrupt Control Register (ICR00 to ICR47)
These registers are used to set interrupt levels. This register is provided for input of each interrupt.
Figure 10.3-1 shows the bit configuration of the interrupt control registers (ICR00 to ICR47).
Figure 10.3-1 Bit configuration of interrupt control registers (ICR00 to ICR47)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
Undefined
IL4
IL3
IL2
IL1
IL0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Attribute
Initial value
R/W: Read/Write
R:
Read only
[bit7 to bit5]: Undefined bits
CM71-10158-1E
In case of writing
Ignored
In case of reading
"1" is read.
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[bit4 to bit0]: IL4 to IL0 (interrupt level control bits)
These bits specify the interrupt level of an interrupt request.
When reset, the bits are initialized to IL4 to IL0=11111("11111B" is level 31 interrupt disabled).
IL4
IL3
IL2
IL1
IL0
Interrupt Level
1
0
0
0
0
16
1
0
0
0
1
17
1
0
0
1
0
18
1
0
0
1
1
19
1
0
1
0
0
20
1
0
1
0
1
21
1
0
1
1
0
22
1
0
1
1
1
23
1
1
0
0
0
24
1
1
0
0
1
25
1
1
0
1
0
26
1
1
0
1
1
27
1
1
1
0
0
28
1
1
1
0
1
29
1
1
1
1
0
30
Lowest level that can be set
1
1
1
1
1
31
Interrupt Disabled
Highest level that can be set
(Higher)
(Lower)
<Notes>
228
•
If the interrupt level that is set in this register is lower than the mask level in the CPU interrupt
level mask register (ILM), the interrupt request is masked on the CPU side.
•
The interrupt control register (ICR00 to ICR47) in which an interrupt level is set varies
depending on the peripheral function. For information on the correspondence between the
peripheral function and interrupt control register (ICR00 to ICR47), see "APPENDIX C Interrupt
Vectors".
•
IL4 bit is fixed to "1" and IL3 to IL0 can be set.
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CHAPTER 10 Interrupt Controller
10.4
MB91665 Series
10.4 An Explanation of Operations and Setting
Procedure Examples
This section explains the operations of the interrupt controller.
10.4.1
Explanation of Operations of Interrupt Controller
This section explains the three types of operations of the interrupt controller.
•
Specifying interrupt levels using interrupt control registers (ICR00 to ICR47)
•
Determining the priorities of interrupt requests
•
Generating a request to return from sleep mode or stop mode
■ Specifying an interrupt level
The procedure for setting interrupt levels using interrupt control registers (ICR00 to ICR47) is shown
below:
1. Set an interrupt level in the interrupt control register (ICR00 to ICR47) with the interrupt vector
number corresponding to the peripheral function for which an interrupt request needs to be
generated.
For information on the correspondence between interrupt control numbers and interrupt requests,
see "APPENDIX C Interrupt Vectors".
2. Enable generation of interrupt requests on the peripheral function for which an interrupt request
needs to be generated.
3. Activate the relevant peripheral function.
■ Determining the priorities of interrupt requests
The interrupt controller sends the interrupt level and interrupt vector number of the highest priority
interrupt request, among the interrupt requests that are concurrently generated, to the CPU.
The criteria for determining the priorities of interrupt requests are shown in order of determining:
1. Is the interrupt level of the interrupt request "30" or lower (Level 31 is "Interrupt Disabled").
2. Is the value of the interrupt level of the interrupt request the smallest.
3. If the interrupt level is the same, is the interrupt vector number of the interrupt request the
smallest.
If no interrupt request meets the above criteria, interrupt level "31" (11111B) that indicates no interrupt
request is output to the CPU.
■ Generating a request to return from sleep mode
If an interrupt request with an interrupt level other than "31" is generated, the interrupt controller
generates a request to the clock control part to return from sleep mode.
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CHAPTER 10 Interrupt Controller
10.4
MB91665 Series
■ Generating a request to return from stop mode
If an external interrupt request /USB function with an interrupt level other than "31" is generated, the
interrupt controller generates a request to the clock control part to return from stop mode.
After return from the stop mode, the interrupt priority determination circuit resumes operation only after
the operation of clock begins. The CPU thus executes instructions until the interrupt priority
determination circuit produces results.
<Note>
For interrupts that are not used as causes of return from stop mode, set interrupt level "31"
(Interrupt Disabled) in the corresponding interrupt control registers (ICR00 to ICR47).
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CHAPTER 10 Interrupt Controller
10.5
MB91665 Series
10.5 Notes on Use
Note the following points about using the interrupt controller.
■ Note on the program
•
For interrupt requests that should not be used to generate a request to return from sleep mode or stop
mode, set interrupt level "31" (Interrupt Disabled) in the corresponding interrupt control registers
(ICR00 to ICR47).
■ Notes on operations
•
CM71-10158-1E
If the interrupt level that is set in an interrupt control register (ICR00 to ICR47) is lower than the mask
level in the CPU interrupt level mask register (ILM), the interrupt request is masked on the CPU side.
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10.5
232
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CHAPTER 11 Interrupt Request BatchRead Function
This section explains the interrupt request batch-read
function.
11.1
11.2
11.3
11.4
CM71-10158-1E
Overview
Configuration
Registers
Notes on Use
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CHAPTER 11 Interrupt Request Batch-Read Function
11.1
MB91665 Series
11.1 Overview
The interrupt request batch-read function reads multiple interrupt requests assigned to one interrupt
vector all at once.
The bit search instruction of an FR80 family CPUs can be used to quickly check which interrupt
requests have been generated.
This function allows the user to check at one time whether interrupt requests that use the same interrupt
vector number have been generated.
Note that this function cannot clear the interrupt request flag. Use the register of each peripheral function
to clear the interrupt request flag.
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CHAPTER 11 Interrupt Request Batch-Read Function
11.2
MB91665 Series
11.2 Configuration
This section shows the configuration of the interrupt request batch-read function.
■ Block diagram of interrupt request batch-read function
Figure 11.2-1 is a block diagram of the interrupt request batch-read function.
Figure 11.2-1 Block diagram of interrupt request batch-read function
Peripheral bus
Interrupt request
Interrupt request
16 bit
batch-read
From each
peripheral function
registers
(IRPRxH,
IRPRxL)
■ Clocks
Clock Name
Operation clock
CM71-10158-1E
Description
Peripheral clock (PCLK)
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CHAPTER 11 Interrupt Request Batch-Read Function
11.3
MB91665 Series
11.3 Registers
This section explains the configuration and functions of registers used by the interrupt request batchread function.
■ Registers for interrupt request batch-read function
Table 11.3-1 lists the registers for the interrupt request batch-read function.
Table 11.3-1 Registers for the interrupt request batch-read function
Abbreviated
Register Name
236
Register Name
Reference
IRPR0H
Interrupt request batch-read register 0 upper
11.3.1
IRPR2L
Interrupt request batch-read register 2 lower
11.3.2
IRPR3H/ IRPR3L
Interrupt request batch-read register 3 upper/lower
11.3.3, 11.3.4
IRPR4H/ IRPR4L
Interrupt request batch-read register 4 upper/lower
11.3.5, 11.3.6
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CHAPTER 11 Interrupt Request Batch-Read Function
11.3
MB91665 Series
11.3.1
Interrupt Request Batch-Read Register 0 Upper
(IRPR0H)
The interrupt requests of 16-bit reload timer ch.0 to ch.2 are assigned to interrupt vector number 20
(decimal). This register can be read to check the channel on which an interrupt request has been
generated.
Figure 11.3-1 shows the bit configuration of interrupt request batch-read register 0 upper (IRPR0H).
Figure 11.3-1 Bit configuration of interrupt request batch-read register 0 upper (IRPR0H)
Interrupt request batch-read register 0 upper (IRPR0H)
bit
15
14
13
12
11
10
9
8
RTIR0
RTIR1
RTIR2
Undefined
Undefined
Undefined
Undefined
Undefined
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
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CHAPTER 11 Interrupt Request Batch-Read Function
11.3
MB91665 Series
The bit corresponding to the channel on which an interrupt request has been generated is set to "1".
Bit number
bit15
bit14
bit13
bit12 to bit8
238
Bit
RTIR0
RTIR1
RTIR2
Undefined
Value
Explanation
0
No interrupt request in reload timer ch.0
1
Interrupt request in reload timer ch.0
0
No interrupt request in reload timer ch.1
1
Interrupt request in reload timer ch.1
0
No interrupt request in reload timer ch.2
1
Interrupt request in reload timer ch.2
"0" is read.
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CHAPTER 11 Interrupt Request Batch-Read Function
11.3
MB91665 Series
11.3.2
Interrupt Request Batch-Read Register 2 Lower
(IRPR2L)
Interrupt vector number 41 (decimal) is used for the following peripheral functions:
• Main timer
• Sub timer
• Watch counter
This register can be read to check the peripheral function from which an interrupt request has been
generated.
Figure 11.3-2 shows the bit configuration of interrupt request batch-read register 2 lower (IRPR2L).
Figure 11.3-2 Bit configuration of interrupt request batch-read register 2 lower (IRPR2L)
bit
7
6
5
4
3
2
1
0
MCIR
SCIR
TCIR
Undefined
Undefined
Undefined
Undefined
Undefined
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to
"1".
Bit number
bit7
bit6
bit5
bit4 to bit0
CM71-10158-1E
Bit
MCIR
SCIR
TCIR
Undefined
Value
Explanation
0
No main timer interrupt request
1
Main timer interrupt request
0
No sub timer interrupt request
1
Sub timer interrupt request
0
No watch counter interrupt request
1
Watch counter interrupt request
"0" is read.
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CHAPTER 11 Interrupt Request Batch-Read Function
11.3
11.3.3
MB91665 Series
Interrupt Request Batch-Read Register 3 Upper
(IRPR3H)
Interrupt vector number 44 (decimal) is used for 32-bit input capture channels ch.0 to ch.3. This
register can be read to check on which channel an interrupt request has been generated.
Figure 11.3-3 shows the bit configuration of interrupt request batch-read register 3 upper (IRPR3H).
Figure 11.3-3 Bit configuration of Interrupt request batch-read register 3 upper (IRPR3H)
bit
15
14
13
12
11
10
9
8
ICIR0
ICIR1
ICIR2
ICIR3
Undefined
Undefined
Undefined
Undefined
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to
"1".
Bit number
bit15
bit14
bit13
bit12
bit11 to bit8
240
Bit
ICIR0
ICIR1
ICIR2
ICIR3
Undefined
Value
Explanation
0
No interrupt request on 32-bit input capture ch.0
1
Interrupt request on 32-bit input capture ch.0
0
No interrupt request on 32-bit input capture ch.1
1
Interrupt request on 32-bit input capture ch.1
0
No interrupt request on 32-bit input capture ch.2
1
Interrupt request on 32-bit input capture ch.2
0
No interrupt request on 32-bit input capture ch.3
1
Interrupt request on 32-bit input capture ch.3
"0" is read.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 11 Interrupt Request Batch-Read Function
11.3
MB91665 Series
11.3.4
Interrupt Request Batch-Read Register 3 Lower
(IRPR3L)
Interrupt vector number 37 (decimal) is used for the following peripheral functions:
• UART/CSIO/I2C ch.7 receive interrupt request
• 32-bit input capture ch.4 to ch.7
This register can be read to check the peripheral function from which an interrupt request has been
generated.
Figure 11.3-4 shows the bit configuration of interrupt request batch-read register 3 lower (IRPR3L).
Figure 11.3-4 Bit configuration of interrupt request batch-read register 3 lower (IRPR3L)
bit
7
6
5
4
3
2
1
0
ICIR4
ICIR5
ICIR6
ICIR7
Undefined
Undefined
Undefined
Undefined
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to
"1".
Bit number
bit7
bit6
bit5
bit4
bit3 to bit0
CM71-10158-1E
Bit
ICIR4
ICIR5
ICIR6
ICIR7
Undefined
Value
Explanation
0
No interrupt request on 32-bit input capture ch.4
1
Interrupt request on 32-bit input capture ch.4
0
No interrupt request on 32-bit input capture ch.5
1
Interrupt request on 32-bit input capture ch.5
0
No interrupt request on 32-bit input capture ch.6
1
Interrupt request on 32-bit input capture ch.6
0
No interrupt request on 32-bit input capture ch.7
1
Interrupt request on 32-bit input capture ch.7
"0" is read.
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CHAPTER 11 Interrupt Request Batch-Read Function
11.3
11.3.5
MB91665 Series
Interrupt Request Batch-Read Register 4 Upper
(IRPR4H)
Interrupt vector number 45 (decimal) is used for 32-bit output compare channels ch.0 to ch.3. This
register can be read to check on which channel an interrupt request has been generated.
Figure 11.3-5 shows the bit configuration of interrupt request batch-read register 4 upper (IRPR4H).
Figure 11.3-5 Bit configuration of Interrupt request batch-read register 4 upper (IRPR4H)
bit
15
14
13
12
11
10
9
8
OCIR0
OCIR1
OCIR2
OCIR3
Undefined
Undefined
Undefined
Undefined
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to
"1".
Bit number
bit15
bit14
bit13
bit12
bit11 to bit8
242
Bit
OCIR0
OCIR1
OCIR2
OCIR3
Undefined
Value
Explanation
0
No interrupt request on 32-bit output compare ch.0
1
Interrupt request on 32-bit output compare ch.0
0
No interrupt request on 32-bit output compare ch.1
1
Interrupt request on 32-bit output compare ch.1
0
No interrupt request on 32-bit output compare ch.2
1
Interrupt request on 32-bit output compare ch.2
0
No interrupt request on 32-bit output compare ch.3
1
Interrupt request on 32-bit output compare ch.3
"0" is read.
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CM71-10158-1E
CHAPTER 11 Interrupt Request Batch-Read Function
11.3
MB91665 Series
11.3.6
Interrupt Request Batch-Read Register 4 Lower
(IRPR4L)
Interrupt vector number 38 (decimal) is used for the following peripheral functions:
• UART/CSIO/I2C ch.7 transmit/transmit bus idle
• I2C ch.7 status interrupt request
• 32-bit output compare ch.4 to ch.7
This register can be read to check on which channels interrupt requests have been generated and the
types of interrupt requests.
Figure 11.3-6 shows the bit configuration of interrupt request batch-read register 4 lower (IRPR4L).
Figure 11.3-6 Bit configuration of interrupt request batch-read register 4 lower (IRPR4L)
bit
7
6
5
4
3
2
1
0
OCIR4
OCIR5
OCIR6
OCIR7
Undefined
Undefined
Undefined
Undefined
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
When an interrupt request is generated, the bit corresponding to the generated interrupt request is set to
"1".
Bit number
bit7
bit6
bit5
bit4
bit3 to bit0
CM71-10158-1E
Bit
OCIR4
OCIR5
OCIR6
OCIR7
Undefined
Value
Explanation
0
No interrupt request on 32-bit output compare ch.4
1
Interrupt request on 32-bit output compare ch.4
0
No interrupt request on 32-bit output compare ch.5
1
Interrupt request on 32-bit output compare ch.5
0
No interrupt request on 32-bit output compare ch.6
1
Interrupt request on 32-bit output compare ch.6
0
No interrupt request on 32-bit output compare ch.7
1
Interrupt request on 32-bit output compare ch.7
"0" is read.
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CHAPTER 11 Interrupt Request Batch-Read Function
11.4
MB91665 Series
11.4 Notes on Use
Note the following points about using the interrupt request batch-read function.
■ Notes on operations
•
244
Writing to the interrupt request batch-read register (IRPRx) is disabled. To cancel an interrupt request,
clear the interrupt request flag bit of the corresponding function register.
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CM71-10158-1E
CHAPTER 12 Delay Interrupt
This chapter explains the functions and operations of the
delay interrupt function.
12.1
12.2
12.3
12.4
Overview
Configuration
Registers
An Explanation of Operations and Setting Procedure
Examples
12.5 Notes on Use
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CHAPTER 12 Delay Interrupt
12.1
MB91665 Series
12.1 Overview
The delay interrupt function generates task switching interrupts used by a real-time OS.
■ Overview
The delay interrupt function generates task switching interrupt requests used by a real-time OS such as
REALOS. Software can use delay interrupts to generate interrupt requests to the CPU or cancel them.
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CHAPTER 12 Delay Interrupt
12.2
MB91665 Series
12.2 Configuration
This section explains the configuration of delay interrupts.
■ Delay interrupt block diagram
Figure 12.2-1 shows a delay interrupt block diagram.
Figure 12.2-1 Delay interrupt block diagram
peripheral bus
Delay interrupt control
register (DICR)
Interrupt
request
•
Delayed interrupt control register (DICR)
This register controls delay interrupts.
■ Clocks
Clock Name
Operation clock
CM71-10158-1E
Description
Peripheral clock (PCLK)
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CHAPTER 12 Delay Interrupt
12.3
MB91665 Series
12.3 Registers
This section explains the configuration and functions of the register used for delay interrupts.
■ Delay interrupt register
Table 12.3-1 shows the delay interrupt register.
Table 12.3-1 Delay interrupt register
Abbreviated
Register Name
DICR
248
Register Name
Delayed interrupt control register
FUJITSU SEMICONDUCTOR LIMITED
Reference
12.3.1
CM71-10158-1E
CHAPTER 12 Delay Interrupt
12.3
MB91665 Series
12.3.1
Delayed Interrupt Control Register (DICR)
This register controls delay interrupts.
Figure 12.3-1 shows the bit configuration of the delayed interrupt control register (DICR).
Figure 12.3-1 Bit configuration of delayed interrupt control register (DICR)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DLYI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
0
Attribute
Initial value
R/W: Read/Write
[bit7 to bit1]: Undefined bits
In case of writing
Ignored
In case of reading
"1" is read.
[bit0]: DLYI (delay interrupt control bit)
This bit is used to enable generation of delay interrupt requests or cancel the delay interrupt requests.
Written Value
Explanation
0
Cancels delay interrupt source or generates no delay
interrupt request
1
Generation of delay interrupt requests.
<Note>
This bit is used in the same way as other interrupt request flags. Clear this bit in the interrupt
processing routine and switch tasks accordingly.
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CHAPTER 12 Delay Interrupt
12.4
MB91665 Series
12.4 An Explanation of Operations and Setting
Procedure Examples
This section explains delay interrupt operations and the setting procedure for delay interrupts.
12.4.1
Explanation of Delay Interrupt Operations
Software can use delay interrupts to generate interrupt requests to the CPU or cancel them.
Table 12.4-1 lists the conditions for generating delay interrupts.
Table 12.4-1 Interrupt request generation conditions
Interrupt request
Delay interrupt request
Interrupt request
generation
Write "1" to the DLYI bit of the delayed interrupt control register (DICR).
Interrupt request
enabled
None (interrupts always enabled)
Clearing an interrupt
request
Write "0" to the DLYI bit of the delayed interrupt control register (DICR).
<Notes>
•
250
Delay interrupts cannot be used for DMA transfer requests.
•
For information on interrupt vector numbers, see "APPENDIX C Interrupt Vectors".
•
Use an interrupt control register (ICR47) to specify the interrupt level corresponding to the
interrupt vector number.For information on the setting of interrupt levels, see "CHAPTER 10
Interrupt Controller".
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CM71-10158-1E
CHAPTER 12 Delay Interrupt
12.5
MB91665 Series
12.5 Notes on Use
Note the following points about using delay interrupts.
■ Notes on the program
•
The delay interrupt control bit can be used in the same way as other interrupt request flags. Clear this
bit in the interrupt routine and switch tasks accordingly.
•
Delay interrupts cannot be used for DMA transfer requests.
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CHAPTER 12 Delay Interrupt
12.5
252
MB91665 Series
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 13 External Bus Interface
This chapter explains the functions and operations of the
external bus interface.
13.1
13.2
13.3
13.4
Overview
Configuration
Pins
Registers
13.5 Protocols
13.6 Timing Settings
13.7 Access Cycle Extension Using the RDY Pin
13.8 Number of Access Cycles
13.9 Address Information and Address Alignment
13.10 Data Alignment
13.11 CS Area Setting Procedure
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CHAPTER 13 External Bus Interface
13.1
MB91665 Series
13.1 Overview
The external bus interface connects this device with external machines (memory, I/O, and other
devices) to input and output data.
For MB91F669 (64 pins) and MB91F668 (48 pins), the pin specifications of the external bus are
different.
For details, refer to the list of external bus pins for each product.
■ Overview
The external bus interface has the following features:
•
Address information of up to 24 bits long (32-MB address space, maximum with address shift) can be
output.
* Only for a multiplex bus of MB91F669 (64 pins).
•
One of the following bus types can be selected:
-
Address data split bus
Access destination address information is output only to the address bus.
Asynchronous memory can be connected.
-
Address data multiplex bus
Access destination address information is output to both the address bus and data bus.
•
The following settings can be made individually for each of the 4 chip select areas (CS areas):
* Only MB91F669 (64 pins) has 4 chip select areas.
MB91F668 (48 pins) has 1 chip select area only.
-
CS area size: A value ranging from 64 KB to 32 MB can be set.
-
CS area location: Any location in the external bus area can be set.
•
The chip select settings corresponding to each CS area can be output.
•
The following settings can be made in each CS area:
-
Whether operations are valid or invalid
-
Data bus width (8 bits/16 bits)
* 8 bits only for MB91F668 (48 pins).
-
Whether the write operation is enabled or disabled (Disabled: Used as a read-only area)
-
Byte ordering (big endian/little endian)
* Only big endian can be specified for the CS0 area.
•
-
Address type (normal output/address shift output)
-
Bus type (address data split bus/address data multiplex bus)
The settings described below for periods (number of cycles) can be made in each CS area.
Settings common to read access and write access
-
Chip select delay cycle
Period from output of an address to enabling of the chip select
-
Address strobe output cycle
Address strobe validity period
-
Access cycle
Read/Write access cycle extension using the ready input pin
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CHAPTER 13 External Bus Interface
13.1
MB91665 Series
-
Address output cycle
Period in which the data output pins output address information (only for a multiplex bus)
Settings for read access
-
Read access automatic wait
Read strobe validity period
-
Read access setup cycle
Period from output of the chip select to enabling of the read strobe
-
Read access hold cycle
Period from disabling of the read strobe to disabling of the chip select
-
Read access idle cycle
Idle period after read access
Settings for write access
-
Write access automatic wait
Write strobe validity period
-
Write access setup cycle
Period from enabling of the chip select to enabling of the write strobe
-
Write access hold cycle
Period from disabling of the write strobe to disabling of the chip select
-
Write recovery cycle
Idle period after write access
Table 13.1-1 External bus pin functions (1 / 2)
CM71-10158-1E
Pin name
MB91F668 (48pins)
MB91F669 (64pins)
D00
❍
❍
D01
❍
❍
D02
❍
❍
D03
❍
❍
D04
❍
❍
D05
❍
❍
D06
❍
❍
D07
❍
❍
D08
❍
❍
D09
❍
❍
D10
❍
❍
D11
❍
❍
D12
❍
❍
D13
❍
❍
D14
❍
❍
D15
❍
❍
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CHAPTER 13 External Bus Interface
13.1
MB91665 Series
Table 13.1-1 External bus pin functions (2 / 2)
Pin name
MB91F668 (48pins)
MB91F669 (64pins)
A00/A16 *
-
❍
A01/A17 *
-
❍
A02/A18 *
-
❍
A03/A19 *
-
❍
A04/A20 *
-
❍
A05/A21 *
-
❍
A06/A22 *
-
❍
A07/A23 *
-
❍
CS0
❍
❍
CS1
-
❍
CS2
-
❍
CS3
-
❍
AS
❍
❍
RD
❍
❍
WR0
❍
❍
WR1
-
❍
RDY
-
❍
SYSCLK
-
❍
* The address function can be changed by MSS bit in EXBS register.
When the split bus is set, A00 to A07 are selected by setting MSS=0, and when the multiplex bus is set,
A16 to A23 are selected by setting MSS bit to 1.
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CHAPTER 13 External Bus Interface
13.2
MB91665 Series
13.2 Configuration
This section explains the configuration of the external bus interface.
■ Block diagram of the external bus interface
Figure 13.2-1 is a block diagram of the external bus interface.
External bus control signal
generation block
•
I/O cell
On-chip bus
Area decoder
On-chip bus controller
External bus access
controller
Write data buffer
External bus data
generation buffer
Read data assembly buffer
Read data buffer
External bus
On-chip bus
access accept
block
Registers
Figure 13.2-1 Block diagram of the external bus interface
On-chip bus access accept block
Accepts access requests to the external bus interface from the on-chip bus.
•
Area decoder block
•
On-chip bus controller
Determines which CS area is accessed.
Controls the on-chip bus.
•
Write data buffer
Stores data for output to an external machine in write access.
•
Read data assembly buffer
Assembles data that was first written by an external machine, split into parts and then input to the
external bus interface in read access.
•
External bus control signal generation block
Generates address strobe, chip select, read strobe, write strobe, and other signals.
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CHAPTER 13 External Bus Interface
13.2
•
MB91665 Series
External bus access controller
Controls the output periods and output timing of address strobe, chip select, read strobe, write strobe,
and other signals.
•
External bus data generation buffer
Splits data that will be output to an external machine into parts according to the bus width in write
access.
•
Read data buffer
Stores data written by an external device in read access.
■ Clocks
Table 13.2-1 lists the clock used with the external bus interface.
Table 13.2-1 Clock used with the external bus interface
Clock Name
Operation clock
Description
External bus clock (TCLK)
Remarks
Internal operation clock
A clock with the same frequency as that of the external bus clock (TCLK) can be output to the SYSCLK
pin as a bus clock.
<Note>
Do not change the division rate of the external bus clock (TCLK) while the external bus area is
being accessed. For details of changing the division rate, see "5.6 Notes on Use".
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CHAPTER 13 External Bus Interface
13.3
MB91665 Series
13.3 Pins
This section explains the pins of the external bus interface.
■ Overview
•
A23 to A00 pins
Address output pins of the external bus interface. These pins are used as an address bus, and they
output access destination address information.
These pins are multiplexed pins. For details of using the A23 to A00 pins of the external bus
interface, see "2.4 Setting Method for Pins".
•
D15 to D00 pins
Data I/O pins of the external bus interface. These pins are used as a data bus.
These pins are multiplexed pins. For details of using the D15 to D00 pins of the external bus
interface, see "2.4 Setting Method for Pins".
•
CS0 to CS3 pins
External bus interface chip select output pins
An external machine processes a request from the external bus interface during output of an "L" level
signal by one of these pins.
These pins are multiplexed pins. For details of using the CS0 to CS3 pins of the external bus
interface, see "2.4 Setting Method for Pins". For MB91F668 (48 pins), only CS0 pin can be used.
•
AS pin
External bus interface address strobe output pin
When outputting an "L" level signal, this pin operates as the address strobe, which indicates the start
of bus access.
This pin is a multiplexed pin. For details of using the AS pin of the external bus interface , see "2.4
Setting Method for Pins".
•
RD pin
External bus interface read strobe output pin
An external machine transmits data through the D15 to D00 pins during output of an "L" level signal
by this pin.
This pin is a multiplexed pin. For details of using the RD pin of the external bus interface , see "2.4
Setting Method for Pins".
•
WR0 and WR1 pins
External bus interface write strobe output pins. These pins perform write operations by the byte.
The write operation to an external machine can be performed during output of an "L" level signal by
one of these pins.
These pins are multiplexed pins. For details of using the WR0 and WR1 pins of the external bus
interface, see "2.4 Setting Method for Pins". For MB91F668 (48 pins), only WR0 pin can be used.
•
RDY pin
External bus interface ready input pin. Inputting an "L" level signal through this pin extends the
access cycle.
This pin is a multiplexed pin. For details of using the RDY pin of the external bus interface, see "2.4
Setting Method for Pins". For MB91F668 (48 pins), there is no RDY pin.
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CHAPTER 13 External Bus Interface
13.3
•
MB91665 Series
SYSCLK pin
External bus interface bus clock output pin
This pin is a multiplexed pin. For details of using the SYSCLK pin of the external bus interface, see
"2.4 Setting Method for Pins". For MB91F668 (48 pins), there is no SYSCLK pin.
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CHAPTER 13 External Bus Interface
13.4
MB91665 Series
13.4 Registers
This section explains the configuration and functions of registers of the external bus interface.
■ External bus interface registers
Table 13.4-1 lists the registers of the external bus interface.
Table 13.4-1 External bus interface registers
CS Area
0
1
2
3
Abbreviated
Register Name
Register Name
Reference
ASR0
CS0 area setting register
13.4.1
ACR0
CS0 area configuration register
13.4.2
AWR0
CS0 area wait register
13.4.3
ASR1
CS1 area setting register
13.4.1
ACR1
CS1 area configuration register
13.4.2
AWR1
CS1 area wait register
13.4.3
ASR2
CS2 area setting register
13.4.1
ACR2
CS2 area configuration register
13.4.2
AWR2
CS2 area wait register
13.4.3
ASR3
CS3 area setting register
13.4.1
ACR3
CS3 area configuration register
13.4.2
AWR3
CS3 area wait register
13.4.3
* For MB91F668 (48 pins), registers of CS0 only.
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CHAPTER 13 External Bus Interface
13.4
13.4.1
MB91665 Series
Area Setting Registers (ASR0 to ASR3)
These registers specify the CS areas (CS0 to CS3). Each of these registers is provided for one
corresponding CS area.
Figure 13.4-1 shows the bit configuration of the area setting registers (ASR0 to ASR3).
Figure 13.4-1 Bit configuration of the area setting registers (ASR0 to ASR3)
bit 31
16
SADR31 to SADR16
Attribute
R/W
Initial value (ASR0)
0
Initial value (ASR1 to ASR3)
X
bit 15
8
Reserved
Attribute
R/W
Initial value (ASR0)
0
Initial value (ASR1 to ASR3)
0
bit
7
6
5
4
3
2
1
0
ASZ3
ASZ2
ASZ1
ASZ0
Reserved
WREN
LEDN
CSEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (ASR0)
1
1
1
1
0
0
0
1
Initial value (ASR1 to ASR3)
X
X
X
X
0
X
X
0
Attribute
R/W: Read/Write
X: Undefined
<Notes>
262
•
Be sure that the CS areas are not set to overlap one other.
•
For details of setting these registers, see "13.11 CS Area Setting Procedure".
•
The initial value of the CS0 area setting register (ASR0) differs from those of the CS1 to CS3
area setting registers (ASR1 to ASR3).
•
Be sure to write data to these registers in units of words.
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[bit31 to bit16]: SADR31 to SADR16 (Start address specification bits)
These bits specify the start address of a CS area.
The upper 16 bits of a 32-bit address must be specified for these bits.
The range that begins from the address specified by these bits is allocated as a CS area with the size
specified by the ASZ3 to ASZ0 bits.
<Note>
The boundary of a CS area depends on the size specified by the ASZ3 to ASZ0 bits. Therefore,
the bits that are actually compared with an address vary depending on the size specified by the
ASZ3 to ASZ0 bits. To determine which bits are actually compared, see the ASZ3 to ASZ0 bits.
[bit15 to bit8]: Reserved bits
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
[bit7 to bit4]: ASZ3 to ASZ0 (Area size bits)
These bits set the size of a CS area.
Among the SADR31 to SADR16 bits, the bits that are actually compared with an address is determined
according to the size specified by these bits.
ASZ3
ASZ2
ASZ1
ASZ0
CS Area Size
Bits Compared with Address
0
0
0
0
64 KB
SADR31 to SADR16 bits
0
0
0
1
128 KB
SADR31 to SADR17 bits
0
0
1
0
256 KB
SADR31 to SADR18 bits
0
0
1
1
512 KB
SADR31 to SADR19 bits
0
1
0
0
1 MB
SADR31 to SADR20 bits
0
1
0
1
2 MB
SADR31 to SADR21 bits
0
1
1
0
4 MB
SADR31 to SADR22 bits
0
1
1
1
8 MB
SADR31 to SADR23 bits
1
0
0
0
16 MB
SADR31 to SADR24 bits
<Note>
Do not make any settings except those described in the table.
[bit3]: Reserved bit
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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[bit2]: WREN (Write enable bit)
This bit enables/disables the write operation to a CS area from an external machine.
Written Value
Explanation
0
Disables write.
1
Enables write.
<Note>
While the write operation is disabled, any write operation from the internal bus to a CS area is
ignored, and no external access is possible.
[bit1]: LEDN (Little endian setting bit)
This bit selects either big endian or little endian for the byte ordering of a CS area.
This bit in the CS0 area setting register (ASR0) is treated as an undefined bit since the CS0 area supports
only big endian.
•
In the CS0 area setting register (ASR0)
In case of writing
Ignored
In case of reading
"0" is read.
•
In the CS1 to CS3 area setting registers (ASR1 to ASR3)
Written Value
Explanation
0
Big endian
1
Little endian
[bit0]: CSEN (CS Area enable bit)
This bit enables/disables a CS area.
When enabled by this bit, the CS area starts operating according to the settings of this register and the
following registers:
•
Area setting register (ASR0 to ASR3)
•
Area configuration register (ACR0 to ACR3)
•
Area wait register (AWR0 to AWR3)
Written Value
264
Explanation
0
Disables the CS area.
1
Enables the CS area.
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13.4
MB91665 Series
13.4.2
Area Configuration Registers (ACR0 to ACR3)
These registers specify the bus for the CS areas (CS0 to CS3). Each of these registers is provided for
one corresponding CS area.
Figure 13.4-2 shows the bit configuration of the area configuration registers (ACR0 to ACR3).
Figure 13.4-2 Bit configuration of the area configuration registers (ACR0 to ACR3)
bit 31
8
Reserved
Attribute
R/W
Initial value (ACR0)
0
Initial value (ACR1 to ACR3)
0
bit
7
6
5
4
3
2
1
0
DBW1
DBW0
Reserved
Reserved
ADTY
BSTY
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (ACR0)
0
0
0
0
0
0
0
0
Initial value (ACR1 to ACR3)
X
X
0
0
X
X
0
X
Attribute
R/W: Read/Write
X: Undefined
<Notes>
•
For details of setting these registers, see "13.11 CS Area Setting Procedure".
•
The initial value of the CS0 area configuration register (ACR0) differs from those of the CS1 to
CS3 area configuration registers (ACR1 to ACR3).
•
Be sure to write data to these registers in units of words.
[bit31 to bit8]: Reserved bits
CM71-10158-1E
In case of writing
Always write "0" to this bit (these bits).
In case of reading
"0" is read.
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[bit7, bit6]: DBW1, DBW0 (Data bus width bits)
These bits set the data bus width.
DBW1
DBW0
Data Bus Width
0
0
8 bits
0
1
16 bits*
1
0
Setting prohibited
1
1
Setting prohibited
* The setting is prohibited for MB91F668(48pins).
The data bus width specified by these bits determines which data bus and write strobe output pins are
used.
Table 13.4-2 lists data bus widths and the corresponding pins used.
Table 13.4-2 Data bus widths and the corresponding pins used
Data Bus Width
Data Bus
Write Strobe Output Pin
8 bits
D15 to D08
WR0
16 bits
D15 to D00
WR0, WR1
[bit5, bit4]: Reserved bits
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
[bit3]: ADTY (Address type bit)
This bit specifies one of the following methods for output of access destination address information:
•
Normal output: Access destination address information is output without any modification.
•
Address shift output: Access destination address information is output after a bit shift is applied.
For details of such address information, see "13.9 Address Information and Address Alignment".
Written Value
266
Explanation
0
Normal output
1
Address shift output
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MB91665 Series
[bit2]: BSTY (Bus type bit)
This bit specifies a bus type. Either output of 24-bit address information from only the address bus (A23
to A00 pins) or output of such information to both the address bus (A23 to A00 pins) and data bus (D15
to D00 pins) can be set.
•
Address data split bus: Output of 24-bit address information from only the address bus (A23 to A00
pins).
•
Address data multiplex bus: Output of access destination address information to both the address bus
(A23 to A00 pins) and data bus (D15 to D00 pins).
Written Value
Explanation
0
Address data split bus
1
Address data multiplex bus
For MB91F669 (64 pins), set the address pin to be output by MSS bit in EXBS register.
When BSTY bit is 0, and MSS bit is 0:
A00 to A07 are enabled.
When BSTY bit is 1, and MSS bit is 1:
A16 to A23 are enabled.
For details of EXBS register, see "CHAPTER 14 I/O Ports".
Table 13.4-3 lists the pins that output address information during the address output cycle to set the
address data multiplex bus.
Table 13.4-3 Address information that is output and the pins used
BSTY
1
Data Bus
Width
Address Information Output
Pins That Output
Address Information
8 bits
bit7 to bit0 of address information
D15 to D08 pins
16 bits
bit15 to bit0 of address information
D15 to D00 pins
[bit1]: Reserved bit
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
[bit0]: Reserved bit
(ACR0)
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
(ACR1 to ACR3)
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
An initial values is undefined.
"0" is read after reading "0".
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13.4
13.4.3
MB91665 Series
Area Wait Registers (AWR0 to AWR3)
These registers set CS area wait and signal output periods. Each of these registers is provided for
one corresponding CS area.
Figure 13.4-3 shows the bit configuration of the area wait registers (AWR0 to AWR3).
Figure 13.4-3 Bit configuration of the area wait registers (AWR0 to AWR3)
bit
31
30
29
28
Reserved Reserved Reserved Reserved
Attribute
27
26
25
24
RWT3
RWT2
RWT1
RWT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (AWR0)
0
0
0
0
1
1
1
1
Initial value (ACR1 to ACR3)
0
0
0
0
X
X
X
X
23
22
21
20
19
18
17
16
WWT3
WWT2
WWT1
WWT0
RIDL1
RIDL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (AWR0)
0
0
0
0
0
0
0
0
Initial value (ACR1 to ACR3)
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
CSRD1
CSRD0
RDCS1
RDCS0
CSWR1
CSWR0
WRCS1
WRCS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (AWR0)
1
1
1
1
0
0
0
0
Initial value (ACR1 to ACR3)
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
ADCY1
ADCY0
ACS1
ACS0
ASCY
Reserved
RDYE
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (AWR0)
0
0
0
0
0
0
0
0
Initial value (ACR1 to ACR3)
X
X
X
X
X
0
X
0
bit
Attribute
bit
Attribute
bit
Attribute
WRCV1 WRCV0
R/W: Read/Write
X: Undefined
<Notes>
268
•
For details of setting these registers, see "13.11 CS Area Setting Procedure".
•
The initial value of the CS0 area wait register (AWR0) differs from those of the CS1 to CS3 area
wait registers (AWR1 to AWR3).
•
Be sure to write data to these registers in units of words.
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CHAPTER 13 External Bus Interface
13.4
MB91665 Series
[bit31 to bit28]: Reserved bits
In case of writing
Always write "0" to this bit (these bits).
In case of reading
"0" is read.
[bit27 to bit24]: RWT3 to RWT0 (Read access automatic wait bits)
These bits specify the read strobe output period (read access automatic wait).
The read strobe is output for a period of at least 1T (T: Bus clock period).
RWT3
RWT2
RWT1
RWT0
Explanation
0
0
0
0
0T
0
0
0
1
1T
0
0
1
0
2T
0
0
1
1
3T
0
1
0
0
4T
0
1
0
1
5T
0
1
1
0
6T
0
1
1
1
7T
1
0
0
0
8T
1
0
0
1
9T
1
0
1
0
10T
1
0
1
1
11T
1
1
0
0
12T
1
1
0
1
13T
1
1
1
0
14T
1
1
1
1
15T
T: Bus clock period
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[bit23 to bit20]: WWT3 to WWT0 (Write access automatic wait bits)
These bits specify the write strobe output period (write access automatic wait).
The write strobe is output for a period of at least 1T (T: Bus clock period).
WWT3
WWT2
WWT1
WWT0
Explanation
0
0
0
0
0T
0
0
0
1
1T
0
0
1
0
2T
0
0
1
1
3T
0
1
0
0
4T
0
1
0
1
5T
0
1
1
0
6T
0
1
1
1
7T
1
0
0
0
8T
1
0
0
1
9T
1
0
1
0
10T
1
0
1
1
11T
1
1
0
0
12T
1
1
0
1
13T
1
1
1
0
14T
1
1
1
1
15T
T: Bus clock period
270
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MB91665 Series
[bit19, bit18]: RIDL1, RIDL0 (Read access idle cycle bits)
These bits specify the idle cycles (read access idle cycles) that are inserted after read access.
If the access immediately after read access is any of the following, as many idle cycles as specified by
these bits are inserted after the read access:
•
Write access
•
Access to another CS area
•
Access to a CS area for which the address data multiplex bus is set as the bus type
RIDL1
RIDL0
Explanation
0
0
0T
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
<Notes>
•
Since all chip select signals are disabled ("H" level output from the CS0 to CS3 pins) and the
D15 to D00 pins become Hi-Z during a read access idle cycle, the next access does not begin
until the read access idle cycle ends.
•
No read access idle cycle is inserted during continuous read access of one CS area for which
the address data split bus is set as the bus type by the BSTY bit (BSTY=0) in the corresponding
area configuration register (ACR0 to ACR3).
[bit17, bit16]: WRCV1, WRCV0 (Write recovery cycle bits)
These bits specify the idle cycles (write recovery cycles) that are inserted after write access.
As many idle cycles as specified by these bits are inserted after an external machine reads data from this
device.
WRCV1
WRCV0
Explanation
0
0
0T
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
<Note>
Since all chip select signals are disabled ("H" level output from the CS0 to CS3 pins) and the write
strobe is also disabled ("H" level output from the WR0 and WR1 pins) during write recovery cycles,
the next access does not begin.
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[bit15, bit14]: CSRD1, CSRD0 (Read access setup cycle bits)
These bits set the period to enable the read strobe after the chip select is enabled (read access setup cycle).
CSRD1
CSRD0
Explanation
0
0
0T (same time)
0
1
After 1T
1
0
After 2T
1
1
After 3T
T: Bus clock period
<Note>
If the address data multiplex bus is set as the bus type by the BSTY bit (BSTY=1) in the
corresponding area configuration register (ACR0 to ACR3), settings must satisfy the following
condition in conformity with the protocol:
•
ACS + CSRD ≥ 1
ACS: ACS1, ACS0 bits
CSRD: CSRD1, CSRD0 bits
[bit13, bit12]: RDCS1, RDCS0 (Read access hold cycle bits)
These bits set the period to disable the chip select after the read strobe is disabled (read access hold
cycle).
RDCS1
RDCS0
Explanation
0
0
0T (same time)
0
1
After 1T
1
0
After 2T
1
1
After 3T
T: Bus clock period
[bit11, bit10]: CSWR1, CSWR0 (Write access setup cycle bits)
These bits set the period to enable the write strobe after the chip select is enabled (write access setup
cycle).
CSWR1
CSWR0
Explanation
0
0
0T (same time)
0
1
After 1T
1
0
After 2T
1
1
After 3T
T: Bus clock period
272
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CHAPTER 13 External Bus Interface
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MB91665 Series
<Note>
If the address data multiplex bus is set as the bus type by the BSTY bit (BSTY=1) in the
corresponding area configuration register (ACR0 to ACR3), settings must satisfy the following
condition in conformity with the protocol:
•
ACS + CSWR ≥ 1
ACS: ACS1, ACS0 bits
CSWR: CSWR1, CSWR0 bits
[bit9, bit8]: WRCS1, WRCS0 (Write access hold cycle bits)
These bits set the period to disable the chip select after the write strobe is disabled (write access hold
cycle).
WRCS1
WRCS0
Explanation
0
0
0T (same time)
0
1
After 1T
1
0
After 2T
1
1
After 3T
T: Bus clock period
[bit7, bit6]: ADCY1, ADCY0 (Address output extension cycle count bits)
These bits specify the period of address information output from the D15 to D00 pins, when the address
data multiplex bus is set as the bus type (BSTY=1) (number of address output extension cycles).
The period in which address information is output from the D15 to D00 pins (address output cycle) is at
least 1T (T: Bus clock period).
ADCY1
ADCY0
Explanation
0
0
0T
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
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<Notes>
•
If the address data split bus is set as the bus type by the BSTY bit (BSTY=0) in the
corresponding area configuration register (ACR0 to ACR3), the settings of these bits are
ignored.
•
To set a value other than "00" in these bits, settings must satisfy all of the following conditions in
conformity with the protocol:
- ADCY + 1 ≤ACS + CSRD
ADCY: ADCY1, ADCY0 bits
ACS: ACS1, ACS0 bits
CSRD: CSRD1, CSRD0 bits
- ADCY + 1 ≤ACS + CSWR
ADCY: ADCY1, ADCY0 bits
ACS: ACS1, ACS0 bits
CSWR: CSWR1, CSWR0 bits
•
If the period set by the ASCY1 and ASCY0 bits is greater than that set by these bits, the setting
of the ASCY1 and ASCY0 bits takes priority.
[bit5, bit4]: ACS1, ACS0 (Chip select delay cycle count bits)
These bits set the period to enable the chip select ("L" level output from the CS0 to CS3 pins) after output
of the address strobe (number of chip select delay cycles).
ACS1
ACS0
Explanation
0
0
0T
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
<Note>
If the address data multiplex bus is set as the bus type by the BSTY bit (BSTY=1) in the
corresponding area configuration register (ACR0 to ACR3), settings must satisfy all of the following
conditions in conformity with the protocol:
•
ACS + CSRD ≥ 1
ACS: ACS1, ACS0 bits
•
ACS + CSWR ≥ 1
ACS: ACS1, ACS0 bits
274
CSRD: CSRD1, CSRD0 bits
CSWR: CSWR1, CSWR0 bits
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CHAPTER 13 External Bus Interface
13.4
MB91665 Series
[bit3]: ASCY (Address strobe output extension cycle count bit)
This bit specifies the address strobe output period (number of address strobe output extension cycles).
The address strobe is output for a period of at least 1T (T: Bus clock period).
Written Value
Explanation
0
0T
1
1T
T: Bus clock period
<Note>
To set "1" in this bit, settings must satisfy all of the following conditions in conformity with the
protocol:
•
If the address data split bus is set as the bus type by the BSTY bit (BSTY=0) in the
corresponding area configuration register (ACR0 to ACR3)
- ACS + CSRD + RWT + RDCS ≥ 1
ACS: ACS1, ACS0 bits
CSRD: CSRD1, CSRD0 bits
RWT: RWT3 to RWT0 bits
RDCS: RDCS1, RDCS0 bits
- ACS + CSWR + WWT + WRCS ≥ 1
•
ACS: ACS1, ACS0 bits
CSWR: CSWR1, CSWR0 bits
WWT: WWT3 to WWT0 bits
WRCS: WRCS1, WRCS0 bits
If the address data multiplex bus is set as the bus type by the BSTY bit (BSTY=1) in the
corresponding area configuration register (ACR0 to ACR3)
- ACS + CSRD ≥ 2
ACS: ACS1, ACS0 bits
CSRD: CSRD1, CSRD0 bits
- ACS + CSWR ≥ 2
ACS: ACS1, ACS0 bits
CSWR: CSWR1, CSWR0 bits
[bit2]: Reserved bit
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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MB91665 Series
[bit1]: RDYE (RDY enable bit)
This bit specifies whether to enable the automatic wait period extension function that uses the RDY pin.
Written Value
Explanation
0
Disabled
1
Enabled
<Note>
To enable this function, use the RWT3 to RWT0 bits and WWT3 to WWT0 bits to specify "2" or a
higher value for the read access/write access automatic wait periods.
For details, see "13.7 Access Cycle Extension Using the RDY Pin".
[bit0]: Reserved bit
276
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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CM71-10158-1E
CHAPTER 13 External Bus Interface
13.5
MB91665 Series
13.5 Protocols
This section explains the protocols for external bus interface signals.
13.5.1
Address Data Split Bus Protocol
This section explains the address data split bus protocol.
In the explanation of the protocol, the address data split bus is set as the bus type by the BSTY bit
(BSTY=0) in the corresponding area configuration register (ACR0 to ACR3).
■ Read protocol
● Read operation example
Figure 13.5-1 shows an example of operations in read access.
Figure 13.5-1 Example of operations in read access
0
Pin
1
2
3
4
5
6
7
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A0
RDCS
ACS
CSRD
RWT
D0
Table 13.5-1 lists the setting value of each bit in the area wait registers (AWR0 to AWR3).
Table 13.5-1 Setting values of bits
Setting Item
CM71-10158-1E
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
01
Read access automatic wait
RWT3 to RWT0
0001
Read access idle cycle
RIDL1, RIDL0
00
Read access setup cycle
CSRD1, CSRD0
01
Read access hold cycle
RDCS1, RDCS0
01
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● Shortest read operation
Figure 13.5-2 shows the shortest operation in read access.
Figure 13.5-2 Shortest read access
1
Pin
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
Minimum bus cycle
: Input data from an external machine
Table 13.5-2 lists the setting value of each bit in the area wait registers (AWR0 to AWR3) in the shortest
read operation.
Table 13.5-2 Setting values of bits
Setting Item
278
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
00
Read access automatic wait
RWT3 to RWT0
0000
Read access idle cycle
RIDL1, RIDL0
00
Read access setup cycle
CSRD1, CSRD0
00
Read access hold cycle
RDCS1, RDCS0
00
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CHAPTER 13 External Bus Interface
13.5
MB91665 Series
● Explanation of signals
•
SYSCLK pin
This pin outputs the bus clock. For MB91F668 (48 pins), there is no SYSCLK pin.
•
AS pin
This pin outputs the address strobe (valid at the "L" level). It indicates the start of access.
•
A23 to A00 pins
These pins output access destination address information.
•
CS0 to CS3 pins
These pins output the chip select (valid at the "L" level). This indicates that the access destination is
the address in the corresponding CS area. For MB91F668 (48 pins), there is no CS0 pin.
•
WR0 and WR1 pins
Output by these pins is at the "H" level (invalid). For MB91F668 (48 pins), only WR0 pin can be
used.
•
RD pin
This pin outputs the read strobe (valid at the "L" level). It indicates read access.
•
D15 to D00 pins
These pins input data from an external machine.
● Access procedure
The read operation of the address data split bus follows the procedure below.
1. Enable the address strobe with the AS pin, and then output address information to the A23 to A00
pins.
2. Enable the chip select with the CS0 to CS3 pins.
3. Enable the read strobe with the RD pin.
4. Input read data from the D15 to D00 pins at the rising edge of the last bus clock within read strobe
validity interval.
5. Disable the read strobe of the RD pin.
6. Disable the chip select with the CS0 to CS3 pins.
Output of address information to the A23 to A00 pins continues until the read operation is completed.
The output period and output timing of each signal can be changed through the settings of the area wait
registers (AWR0 to AWR3). See "13.6 Timing Settings".
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■ Write protocol
● Write operation example
Figure 13.5-3 shows an example of operations in write access.
Figure 13.5-3 Example of operations in write access
0
Pin
1
2
3
4
5
6
7
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A0
WRCS
ACS
WWT
CSWR
D0
Table 13.5-3 lists the setting value of each bit in the area wait registers (AWR0 to AWR3).
Table 13.5-3 Setting values of bits
Setting Item
280
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
01
Write access automatic wait
WWT3 to WWT0
0001
Write recovery cycle
WRCV1, WRCV0
00
Write access setup cycle
CSWR1, CSWR0
01
Write access hold cycle
WRCS1, WRCS0
01
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CHAPTER 13 External Bus Interface
13.5
MB91665 Series
● Shortest write operation
Figure 13.5-4 shows the shortest operation in write access.
Figure 13.5-4 Shortest write operation
1
Pin
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
D
Minimum bus cycle
Table 13.5-4 lists the setting value of each bit in the area wait registers (AWR0 to AWR3) in the shortest
write operation.
Table 13.5-4 Setting values of bits
Setting Item
CM71-10158-1E
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
00
Write access automatic wait
WWT3 to WWT0
0000
Write recovery cycle
WRCV1, WRCV0
00
Write access setup cycle
CSWR1, CSWR0
00
Write access hold cycle
WRCS1, WRCS0
00
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MB91665 Series
● Explanation of signals
•
SYSCLK pin
This pin outputs the bus clock. For MB91F668 (48 pins), there is no SYSCLK pin.
•
AS pin
This pin outputs the address strobe (valid at the "L" level). It indicates the start of access.
•
A23 to A00 pins
These pins output access destination address information.
•
CS0 to CS3 pins
These pins output the chip select (valid at the "L" level). This indicates that the access destination is
the address in the corresponding CS area. For MB91F668 (48 pins), there is no CS0 pin.
•
WR0 and WR1 pins
These pins output the write strobe (valid at the "L" level). For MB91F668 (48 pins), only WR0 pin
can be used.
•
RD pin
Output by this pin is at the "H" level (invalid).
•
D15 to D00 pins
These pins output data to an external machine.
● Access procedure
The write operation of the address data split bus follows the procedure below.
1. Enable the address strobe with the AS pin, and then output address information to the A23 to A00 pins
and write data to the D15 to D00 pins.
2. Enable the chip select with the CS0 to CS3 pins.
3. Enable the write strobe with the WR0 and WR1 pins.
4. Disable the write strobe with the WR0 and WR1 pins.
5. Disable the chip select with the CS0 to CS3 pins.
Output of address information to the A23 to A00 pins and write data to the D15 to D00 pins continues
until the write operation is completed.
The output period and output timing of each signal can be changed through the settings of the area wait
registers (AWR0 to AWR3). See "13.6 Timing Settings".
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CHAPTER 13 External Bus Interface
13.5
MB91665 Series
13.5.2
Address Data Multiplex Bus Protocol
This section explains the address data multiplex bus protocol.
In the explanation of the protocol, the address data multiplex bus is set as the bus type by the BSTY bit
(BSTY=1) in the corresponding area configuration register (ACR0 to ACR3).
■ Read protocol
● Read operation example
Figure 13.5-5 shows an example of operations in read access.
Figure 13.5-5 Example of operations in read access
0
1
2
3
4
5
6
7
SYSCLK
Bus clock
Pin
Pin
Signal
AS
Address strobe
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
RDCS
ACS
CSRD
RWT
A0
D0
Table 13.5-5 lists the setting value of each bit in the area wait registers (AWR0 to AWR3).
Table 13.5-5 Setting values of bits
Setting Item
CM71-10158-1E
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
01
Read access automatic wait
RWT3 to RWT0
0001
Read access idle cycle
RIDL1, RIDL0
00
Read access setup cycle
CSRD1, CSRD0
01
Read access hold cycle
RDCS1, RDCS0
01
Number of address output extension cycles
ADCY1, ADCY0
00
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MB91665 Series
● Shortest read operation
Figure 13.5-6 shows one of the shortest operations in read access.
Figure 13.5-6 Shortest read access (ACS1 = 0, ACS0 = 1)
1
Pin
2
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
ACS
A
Minimum bus cycle
: Input data from an external machine
Table 13.5-6 lists the setting value of each bit in the area wait registers (AWR0 to AWR3) in the shortest
read operation.
Table 13.5-6 Setting values of bits
Setting Item
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
01
Read access automatic wait
RWT3 to RWT0
0000
Read access idle cycle
RIDL1, RIDL0
00
Read access setup cycle
CSRD1, CSRD0
00
Read access hold cycle
RDCS1, RDCS0
00
Number of address output extension cycles
ADCY1, ADCY0
00
The minimum bus cycle for the address data multiplex bus must be 2T (T: Bus clock period). Either the
number of chip select delay cycles or number of read access setup cycles must be "1" or higher. Figure
13.5-6 and Table 13.5-6 shows that "01B" is set as the number of chip select delay cycles (ACS1, ACS0).
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13.5
MB91665 Series
● Explanation of signals
•
SYSCLK pin
This pin outputs the bus clock. For MB91F668 (48 pins), there is no SYSCLK pin.
•
AS pin
This pin outputs the address strobe (valid at the "L" level). It indicates the start of access.
•
A23 to A00 pins
These pins output access destination address information.
•
CS0 to CS3 pins
These pins output the chip select (valid at the "L" level). This indicates that the access destination is
the address in the corresponding CS area. For MB91F668 (48 pins), there is no CS0 pin.
•
WR0 and WR1 pins
Output by this pin is at the "H" level (invalid). For MB91F668 (48 pins), only WR0 pin can be used.
•
RD pin
This pin outputs the read strobe (valid at the "L" level). It indicates read access.
•
D15 to D00 pins
These pins input data from an external machine after address information is output.
● Access procedure
The read operation of the address data multiplex bus follows the procedure below.
1. Enable the address strobe with the AS pin, and then output address information to the A23 to A00 pins
and D15 to D00 pins.
2. Enable the chip select with the CS0 to CS3 pins.
3. Enable the read strobe with the RD pin.
4. Input read data from the D15 to D00 pins at the rising edge of the last bus clock within read strobe
validity interval.
5. Disable the read strobe of the RD pin.
6. Disable the chip select with the CS0 to CS3 pins.
The address information on the D15 to D00 pins is the same as that on the A15 to A00 pins. The D15 to
D00 pins are placed in the high impedance state after the address information is output. Output of address
information to the A23 to A00 pins continues until the read operation is completed.
The output period and output timing of each signal can be changed through the settings of the area wait
registers (AWR0 to AWR3). See "13.6 Timing Settings".
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■ Write protocol
● Write operation example
Figure 13.5-7 shows an example of operations in write access.
Figure 13.5-7 Example of operations in write access
0
Pin
1
2
3
4
5
6
7
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
WRCS
ACS
CSWR
A0
WWT
D0
Table 13.5-7 lists the setting value of each bit in the area wait registers (AWR0 to AWR3).
Table 13.5-7 Setting values of bits
Setting Item
286
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
01
Write access automatic wait
WWT3 to WWT0
0001
Write recovery cycle
WRCV1, WRCV0
00
Write access setup cycle
CSWR1, CSWR0
01
Write access hold cycle
WRCS1, WRCS0
01
Number of address output extension cycles
ADCY1, ADCY0
00
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CHAPTER 13 External Bus Interface
13.5
MB91665 Series
● Shortest write operation
Figure 13.5-8 shows one of the shortest operations in write access.
Figure 13.5-8 Shortest write access (ACS1 = 0, ACS0 = 1)
1
Pin
2
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Address/Data
A
ACS
A
D
Minimum bus cycle
: Input data from an external machine
Table 13.5-8 lists the setting value of each bit in the area wait registers (AWR0 to AWR3) in the shortest
write operation.
Table 13.5-8 Setting values of bits
Setting Item
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
0
Number of chip select delay cycles
ACS1, ACS0
01
Write access automatic wait
WWT3 to WWT0
0000
Write recovery cycle
WRCV1, WRCV0
00
Write access setup cycle
CSWR1, CSWR0
00
Write access hold cycle
WRCS1, WRCS0
00
Number of address output extension cycles
ADCY1, ADCY0
00
The minimum bus cycle for the address data multiplex bus must be 2T (T: Bus clock period). Either the
number of chip select delay cycles or the number of write access setup cycles must be "1" or higher.
Figure 13.5-8 and Table 13.5-8 shows that "01B" is set as the number of chip select delay cycles (ACS1,
ACS0).
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CHAPTER 13 External Bus Interface
13.5
MB91665 Series
● Explanation of signals
•
SYSCLK pin
This pin outputs the bus clock. For MB91F668 (48 pins), there is no SYSCLK pin.
•
AS pin
This pin outputs the address strobe (valid at the "L" level). It indicates the start of access.
•
A23 to A00 pins
These pins output access destination address information.
•
CS0 to CS3 pins
These pins output the chip select (valid at the "L" level). This indicates the access destination is the
address in the corresponding CS area.
For MB91F668 (48 pins), there is no CS0 pin.
•
WR0 and WR1 pins
These pins output the write strobe (valid at the "L" level). They indicate write access. For MB91F668
(48 pins), only WR0 pin can be used.
•
RD pin
•
D15 to D00 pins
Output by this pin is at the "H" level (invalid).
These pins input data from an external machine after address information is output.
● Access procedure
The write operation of the address data multiplex bus follows the procedure below.
1. Enable the address strobe with the AS pin, and then output address information to the A23 to A00 pins
and D15 to D00 pins.
2. Output write data to the D15 to D00 pins.
3. Enable the chip select with the CS0 to CS3 pins.
4. Enable the write strobe with the WR pin.
5. Disable the write strobe with the WR pin.
6. Disable the chip select with the CS0 to CS3 pins.
The address information on the D15 to D00 pins is the same as that on the A15 to A00 pins. Output of
address information to the A23 to A00 pins continues until the write operation is completed.
Output of write data to the D15 to D00 pins continues until the write operation is completed.
The output period and output timing of each signal can be changed through the settings of the area wait
registers (AWR0 to AWR3). See "13.6 Timing Settings".
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13.6
MB91665 Series
13.6 Timing Settings
This section explains the external bus interface timing settings. The output periods and output timing
of signals can be set such that different types of external machines can be connected.
The following timing can be set with the bits of the area wait registers (AWR0 to AWR3):
-
Read access automatic wait
-
Write access automatic wait
-
Read access idle cycle
-
Write recovery cycle
-
Read access setup cycle
-
Read access hold cycle
-
Write access setup cycle
-
Write access hold cycle
-
Chip select delay cycle
-
Address output extension cycle
-
Address strobe output extension cycle
<Note>
In order to help readers easily understand changes in timing through such settings, each period is
set to the minimum value for the explanation of the basic protocol in this section.
Note that the settings for the basic protocol are different from the initial value settings.
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CHAPTER 13 External Bus Interface
13.6
13.6.1
MB91665 Series
Read Access Automatic Wait
The number of automatic wait cycles for read access is set. The read access automatic wait extends
the read strobe validity period.
The period in which the read strobe remains valid is a minimum of 1T (T: Bus clock period), when no
extension is applied. The length by which the period is extended can be specified as a period ranging
from 0T to 15T (T: Bus clock period) with the RWT3 to RWT0 bits of the area wait registers (AWR0 to
AWR3).
Table 13.6-1 lists the setting values of the RWT3 to RWT0 bits in the area wait registers (AWR0 to
AWR3) and the corresponding output periods of the read strobe.
Table 13.6-1 Setting values of RWT3 to RWT0 and output periods of the read strobe
RWT3
RWT2
RWT1
RWT0
Extension
Period
Read Strobe
Output Period
0
0
0
1
0T
1T
0
0
0
1
1T
2T
0
0
1
0
2T
3T
0
0
1
1
3T
4T
0
1
0
0
4T
5T
0
1
0
1
5T
6T
0
1
1
0
6T
7T
0
1
1
1
7T
8T
1
0
0
0
8T
9T
1
0
0
1
9T
10T
1
0
1
0
10T
11T
1
0
1
1
11T
12T
1
1
0
0
12T
13T
1
1
0
1
13T
14T
1
1
1
0
14T
15T
1
1
1
1
15T
16T
T: Bus clock period
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13.6
MB91665 Series
■ Address data split bus
Figure 13.6-1 shows an example in which the number of automatic wait cycles for read access is set to
"1".
Figure 13.6-1 Example of read access automatic wait settings (address data split bus)
2
1
Pin
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
RWT
: Input data from an external machine
Table 13.6-2 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown in
Figure 13.6-1 (values other than "0" are set in the bits).
Table 13.6-2 Setting values of bits
Setting Item
Read access automatic wait
CM71-10158-1E
Bit
RWT3 to RWT0
FUJITSU SEMICONDUCTOR LIMITED
Setting Value
0001
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13.6
MB91665 Series
■ Address data multiplex bus
Figure 13.6-2 shows an example in which the read access automatic wait cycle is set to "1".
Figure 13.6-2 Example of read access automatic wait settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Address/Data
A
ACS
RWT
A
: Input data from an external machine
Table 13.6-3 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown in
Figure 13.6-2 (values other than "0" are set in the bits).
Table 13.6-3 Setting values of bits
Setting Item
Bit
Setting Value
Read access automatic wait
RWT3 to RWT0
0001
Number of chip select delay cycles
ACS1, ACS0
01
Figure 13.6-2 and Table 13.6-3 show that 1T (T: Bus clock period) is set as the number of chip select
delay cycles because of restrictions of the address data multiplex bus protocol.
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CHAPTER 13 External Bus Interface
13.6
MB91665 Series
13.6.2
Write Access Automatic Wait
The number of automatic wait cycles for write access is set. The write access automatic wait cycle
extends the write strobe validity period.
The period in which the write strobe remains valid is a minimum of 1T (T: bus clock cycle), when no
extension is applied. The length by which the period is extended can be specified as a period ranging
from 0T to 15T (T: Bus clock period) with the WWT3 to WWT0 bits of the area wait registers (AWR0 to
AWR3).
Table 13.6-4 lists the setting values of the WWT3 to WWT0 bits in the area wait registers (AWR0 to
AWR3) and the corresponding output periods of the write strobe.
Table 13.6-4 Setting values of WWT3 to WWT0 and output periods of the write strobe
WWT3
WWT2
WWT1
WWT0
Extension
Period
Output Period
(Total)
0
0
0
1
0T
1T
0
0
0
1
1T
2T
0
0
1
0
2T
3T
0
0
1
1
3T
4T
0
1
0
0
4T
5T
0
1
0
1
5T
6T
0
1
1
0
6T
7T
0
1
1
1
7T
8T
1
0
0
0
8T
9T
1
0
0
1
9T
10T
1
0
1
0
10T
11T
1
0
1
1
11T
12T
1
1
0
0
12T
13T
1
1
0
1
13T
14T
1
1
1
0
14T
15T
1
1
1
1
15T
16T
T: Bus clock period
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MB91665 Series
■ Address data split bus
Figure 13.6-3 shows an example in which the write access automatic wait cycle is set to "1".
Figure 13.6-3 Example of write access automatic wait settings (address data split bus)
2
1
Pin
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
WWT
D
Table 13.6-5 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown in
Figure 13.6-3 (values other than "0" are set in the bits).
Table 13.6-5 Setting values of bits
Setting Item
Write access automatic wait
294
Bit
WWT3 to WWT0
FUJITSU SEMICONDUCTOR LIMITED
Setting Value
0001
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CHAPTER 13 External Bus Interface
13.6
MB91665 Series
■ Address data multiplex bus
Figure 13.6-4 shows an example in which the write access automatic wait cycle is set to "1".
Figure 13.6-4 Example of write access automatic wait settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
ACS
WWT
A
D
Table 13.6-6 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown in
Figure 13.6-4 (values other than "0" are set in the bits).
Table 13.6-6 Setting values of bits
Setting Item
Bit
Setting Value
Number of chip select delay cycles
ACS1, ACS0
01
Write access automatic wait
WWT3 to WWT0
0001
Figure 13.6-4 shows that 1T (T: Bus clock period) is set as the number of chip select delay cycles
because of restrictions of the address data multiplex bus protocol.
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13.6
13.6.3
MB91665 Series
Read Access Idle Cycle
The number of idle cycles for read access is set. If the read access idle cycle is set to "1" or higher,
idle cycles are inserted after read access is completed.
All the chip select signals are invalid and the D15 to D00 pins are Hi-Z during the read access idle cycle.
Inserting read access idle cycles prevents the read data received from an external machine that has a long
output-off time from colliding with data associated with subsequent access on the bus.
If the next access after read access is any of the following, read access idle cycles are inserted after the
read access is completed:
•
Write access
•
Access to another CS area
•
Access to a CS area for which the address data multiplex bus is set as the bus type
The read access idle period can be specified as a period ranging from 0T to 3T (T: Bus clock period) with
the RIDL1 and RIDL0 bits of the area wait registers (AWR0 to AWR3).
Table 13.6-7 lists the setting values of the RIDL1 and RIDL0 bits in the area wait registers (AWR0 to
AWR3) and the number of read access idle cycles.
Table 13.6-7 RIDL1 and RIDL0 bits and number of read access idle cycles
RIDL1
RIDL0
Number of Idle Cycles
0
0
0T (no read access idle)
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
<Note>
No read access idle cycle is inserted during continuous read access of the same CS area of the
address data split bus.
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CHAPTER 13 External Bus Interface
13.6
MB91665 Series
■ Address data split bus
Figure 13.6-5 shows an example in which the read access idle cycle is set to "1".
Figure 13.6-5 Example of read access idle cycle settings (address data split bus)
1
Pin
2
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
RIDL
: Input data from an external machine
Table 13.6-8 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown in
Figure 13.6-5 (values other than "0" are set in the bits).
Table 13.6-8 Setting values of bits
Setting Item
Read access idle cycle
CM71-10158-1E
Bit
RIDL1, RIDL0
FUJITSU SEMICONDUCTOR LIMITED
Setting Value
01
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■ Address data multiplex bus
Figure 13.6-6 shows an example in which the number of idle cycles for read access is set to "1".
Figure 13.6-6 Example of read access idle cycle settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Address/Data
A
ACS
RIDL
A
: Input data from an external machine
Table 13.6-9 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown in
Figure 13.6-6 (values other than "0" are set in the bits).
Table 13.6-9 Setting values of bits
Setting Item
Bit
Setting Value
Number of chip select delay cycles
ACS1, ACS0
01
Read access idle cycle
RIDL1, RIDL0
01
Figure 13.6-6 shows that 1T (T: Bus clock period) is set as the number of chip select delay cycles
because of restrictions of the address data multiplex bus protocol.
298
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13.6.4
Write Recovery Cycle
The number of write access recovery cycles is set. If the write recovery cycle is set to "1" or higher,
recovery cycles are inserted after write access is completed.
All the chip select signals and the write strobe signal are invalid, and D15 to D00 pins become Hi-Z
during write recovery cycles. If the next external machine to be accessed has restrictions between access
operations, write recovery cycles are inserted after write access.
The write recovery cycle period can be specified as a period ranging from 0T to 3T (T: Bus clock period)
with the WRCV1 and WRCV0 bits of the area wait registers (AWR0 to AWR3).
Table 13.6-10 lists the setting values of the WRCV1 and WRCV0 bits in the area wait registers (AWR0
to AWR3) and the number of write recovery cycles.
Table 13.6-10 WRCV1, WRCV0 bits and number of write recovery cycles
WRCV1
WRCV0
Number of Write Recovery Cycles
0
0
0T (no write recovery)
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
<Note>
If a value other than 0T (T: Bus clock period) is set as a write recovery cycle period, write recovery
cycles are always inserted after write access.
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MB91665 Series
■ Address data split bus
Figure 13.6-7 shows an example in which the write recovery cycle is set to 1T (T: Bus clock period).
Figure 13.6-7 Example of write recovery cycle settings (address data split bus)
2
1
Pin
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
WRCV
D
Table 13.6-11 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-7 (values other than "0" are set in the bits).
Table 13.6-11 Setting values of bits
Setting Item
Write recovery cycle
300
Bit
WRCV1, WRCV0
FUJITSU SEMICONDUCTOR LIMITED
Setting Value
01
CM71-10158-1E
CHAPTER 13 External Bus Interface
13.6
MB91665 Series
■ Address data multiplex bus
Figure 13.6-8 shows an example in which the write recovery cycle is set to 1T (T: Bus clock period).
Figure 13.6-8 Example of write recovery cycle settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
ACS
A
WRCV
D
Table 13.6-12 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-8 (values other than "0" are set in the bits).
Table 13.6-12 Setting values of bits
Setting Item
Bit
Setting Value
Number of chip select delay cycles
ACS1, ACS0
01
Write recovery cycle
WRCV1, WRCV0
01
Figure 13.6-8 shows that 1T (T: Bus clock period) is set as the number of chip select delay cycles
because of restrictions of the address data multiplex bus protocol.
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13.6.5
MB91665 Series
Read Access Setup Cycle
The number of setup cycles for read access is set. The setup cycles extend the period beginning
from enabling of the chip select to enabling of the read strobe.
The period beginning from enabling of the chip select to enabling of the read strobe can be specified as a
period ranging from 0T to 3T (T: Bus clock period) with the CSRD1 and CSRD0 bits of the area wait
registers (AWR0 to AWR3).
Table 13.6-13 lists the setting values of the CSRD1 and CSRD0 bits in the area wait registers (AWR0 to
AWR3) and the number of delay cycles.
Table 13.6-13 CSRD1 and CSRD0 bits and number of delay cycles
CSRD1
CSRD0
Number of Delay Cycles
0
0
0T (valid simultaneously with chip select)
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
■ Address data split bus
Figure 13.6-9 shows an example in which the read access setup cycle is set to 1T (T: Bus clock period).
Figure 13.6-9 Example of read access setup cycle settings (address data split bus)
1
Pin
2
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
CSRD
: Input data from an external machine
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Table 13.6-14 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-9 (values other than "0" are set in the bits).
Table 13.6-14 Setting values of bits
Setting Item
Read access setup cycle
Bit
Setting Value
CSRD1, CSRD0
01
■ Address data multiplex bus
Figure 13.6-10 shows an example in which the read access setup cycle is set to 1T (T: Bus clock period).
Figure 13.6-10 Example of read access setup cycle settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Address/Data
A
CSRD
A
: Input data from an external machine
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Table 13.6-15 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-10 (values other than "0" are set in the bits).
Table 13.6-15 Setting values of bits
Setting Item
Bit
Read access setup cycle
CSRD1, CSRD0
Setting Value
01
<Note>
If the address data multiplex bus is set as the bus type (BSTY=1), settings of the area wait
registers (AWR0 to AWR3) must completely satisfy the following condition in conformity with the
protocol:
•
ACS + CSRD ≥ 1
ACS: ACS1, ACS0 bits
13.6.6
CSRD: CSRD1, CSRD0 bits
Read Access Hold Cycle
The number of hold cycles for read access is set. The hold cycles extend the period beginning from
disabling of the chip select to disabling of the read strobe.
The period beginning from disabling of the read strobe to disabling of the chip select can be specified as a
period ranging from 0T to 3T (T: Bus clock period) with the RDCS1 and RDCS0 bits of the area wait
registers (AWR0 to AWR3).
Table 13.6-16 lists the setting values of the RDCS1 and RDCS0 bits in the area wait registers (AWR0 to
AWR3) and the number of delay cycles.
Table 13.6-16 RDCS1 and RDCS0 bits and number of delay cycles
RDCS1
RDCS0
Number of Delay Cycles
0
0
0T (invalid simultaneously with read strobe)
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
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MB91665 Series
■ Address data split bus
Figure 13.6-11 shows an example in which the read access hold cycle is set to 1T (T: Bus clock period).
Figure 13.6-11 Example of read access hold cycle settings (address data split bus)
1
Pin
2
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
RDCS
: Input data from an external machine
Table 13.6-17 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-11 (values other than "0" are set in the bits).
Table 13.6-17 Setting values of bits
Setting Item
Read access hold cycle
CM71-10158-1E
Bit
RDCS1, RDCS0
FUJITSU SEMICONDUCTOR LIMITED
Setting Value
01
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MB91665 Series
■ Address data multiplex bus
Figure 13.6-12 shows an example in which the read access hold cycle is set to 1T (T: Bus clock period).
Figure 13.6-12 Example of read access hold cycle settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
ACS
RDCS
A
: Input data from an external machine
Table 13.6-18 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-12 (values other than "0" are set in the bits).
Table 13.6-18 Setting values of bits
Setting Item
Bit
Setting Value
Number of chip select delay cycles
ACS1, ACS0
01
Read access hold cycle
RDCS1, RDCS0
01
Figure 13.6-12 shows that 1T (T: Bus clock period) is set as the number of chip select delay cycles
because of restrictions of the address data multiplex bus protocol.
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CHAPTER 13 External Bus Interface
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MB91665 Series
13.6.7
Write Access Setup Cycle
The number of setup cycles for write access is set. The setup cycles extend the period beginning
from enabling of the chip select to enabling of the write strobe.
The period beginning from enabling of the chip select to enabling of the write strobe can be specified as a
period ranging from 0T to 3T (T: Bus clock period) with the CSWR1 and CSWR0 bits of the area wait
registers (AWR0 to AWR3).
Table 13.6-19 lists the setting values of the CSWR1 and CSWR0 bits in the area wait registers (AWR0 to
AWR3) and the number of delay cycles.
Table 13.6-19 CSWR1 and CSWR0 bits and number of delay cycles
CSWR1
CSWR0
Number of Delay Cycles
0
0
0T (valid simultaneously with chip select)
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
■ Address data split bus
Figure 13.6-13 shows an example in which the write access setup cycle is set to 1T (T: Bus clock
period).
Figure 13.6-13 Example of write access setup cycle settings (address data split bus)
2
1
Pin
CM71-10158-1E
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
CSWR
D
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Table 13.6-20 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-13 (values other than "0" are set in the bits).
Table 13.6-20 Setting values of bits
Setting Item
Write access setup cycle
Bit
Setting Value
CSWR1, CSWR0
01
■ Address data multiplex bus
Figure 13.6-14 shows an example in which the write access setup cycle is set to 1T (T: Bus clock
period).
Figure 13.6-14 Example of write access setup cycle settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Address/Data
A
CSWR
A
D
Table 13.6-21 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-13 (values other than "0" are set in the bits).
Table 13.6-21 Setting values of bits
Setting Item
Write access setup cycle
Bit
CSWR1, CSWR0
Setting Value
01
<Note>
If the address data multiplex bus is set as the bus type (BSTY=1), settings of the area wait
registers (AWR0 to AWR3) must completely satisfy the following condition in conformity with the
protocol:
•
ACS + CSWR ≥ 1
ACS: ACS1, ACS0 bits
308
CSWR: CSWR1, CSWR0 bits
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CHAPTER 13 External Bus Interface
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MB91665 Series
13.6.8
Write Access Hold Cycle
The number of hold cycles for write access is set. The hold cycles extend the period beginning from
disabling of the chip select to disabling of the write strobe.
The period beginning from disabling of the write strobe to disabling of the chip select can be specified as
a period ranging from 0T to 3T (T: Bus clock period) with the WRCS1 and WRCS0 bits on the area wait
registers (AWR0 to AWR3).
Table 13.6-22 lists the setting values of the WRCS1 and WRCS0 bits in the area wait registers (AWR0 to
AWR3) and the number of write access hold cycles.
Table 13.6-22 WRCS1 and WRCS0 bits and number of delay cycles
WRCS1
WRCS0
Number of Write Access Hold Cycles
0
0
0T (invalid simultaneously with write strobe)
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
■ Address data split bus
Figure 13.6-15 shows an example in which the write access hold cycle is set to 1T (T: Bus clock period).
Figure 13.6-15 Example of write access hold cycle settings (address data split bus)
2
1
Pin
CM71-10158-1E
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
WRCS
D
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Table 13.6-23 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-15 (values other than "0" are set in the bits).
Table 13.6-23 Setting values of bits
Setting Item
Write access hold cycle
Bit
Setting Value
WRCS1, WRCS0
01
■ Address data multiplex bus
Figure 13.6-16 shows an example in which the write access hold cycle is set to 1T (T: Bus clock period).
Figure 13.6-16 Example of write access hold cycle settings (address data multiplex bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Data
A
ACS
WRCS
A
D
Table 13.6-24 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-16 (values other than "0" are set in the bits).
Table 13.6-24 Setting values of bits
Setting Item
Bit
Setting Value
Number of chip select delay cycles
ACS1, ACS0
01
Write access hold cycle
WRCS1, WRCS0
01
Figure 13.6-16 shows that 1T (T: Bus clock period) is set as the number of chip select delay cycles
because of restrictions of the address data multiplex bus protocol.
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MB91665 Series
13.6.9
Chip Select Delay Cycle
The number of chip select delay cycles is set. The period from enabling of the address strobe to
enabling of the chip select is set.
For chip select output, if address setup requires a certain length of time or the same CS area is accessed
continuously, the address delay cycle is set to use an edge of the chip select.
The chip select enable timing following the address strobe time can be delayed by a period ranging from
0T to 3T (T: Bus clock period) with the ACS1 and ACS0 bits of the area wait registers (AWR0 to
AWR3).
Table 13.6-25 lists the setting values of the ACS1 and ACS0 bits in the area wait registers (AWR0 to
AWR3) and the number of delay cycles.
Table 13.6-25 ACS1 and ACS0 bits and number of delay cycles
ACS1
ACS0
Number of Delay Cycles
0
0
0T (output simultaneously with address strobe output)
0
1
1T
1
0
2T
1
1
3T
T: Bus clock period
<Note>
If the address data multiplex bus is set as the bus type (BSTY=1), settings of the area wait
registers (AWR0 to AWR3) must satisfy all of the following conditions in conformity with the
protocol:
•
ACS + CSRD ≥ 1
ACS: ACS1, ACS0 bits
•
CSRD: CSRD1, CSRD0 bits
ACS + CSWR ≥ 1
ACS: ACS1, ACS0 bits
CM71-10158-1E
CSWR: CSWR1, CSWR0 bits
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MB91665 Series
■ Address data split bus
Figure 13.6-17 shows an example in which the chip select is delayed by 1T (T: Bus clock period).
Figure 13.6-17 Example of chip select delay cycle settings (address data split bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
A
ACS
: Input data from an external machine
Table 13.6-26 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-17 (values other than "0" are set in the bits).
Table 13.6-26 Setting values of bits
Setting Item
Number of chip select delay cycles
312
Bit
ACS1, ACS0
FUJITSU SEMICONDUCTOR LIMITED
Setting Value
01
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CHAPTER 13 External Bus Interface
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MB91665 Series
■ Address data multiplex bus
Figure 13.6-18 shows an example in which the chip select is delayed by 1T (T: Bus clock period).
Figure 13.6-18 Example of chip select delay cycle settings (address data multiplex bus)
2
1
Pin
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Address/Data
A
ACS
A
D
Table 13.6-27 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-18 (values other than "0" are set in the bits).
Table 13.6-27 Setting values of bits
Setting Item
Number of chip select delay cycles
CM71-10158-1E
Bit
ACS1, ACS0
FUJITSU SEMICONDUCTOR LIMITED
Setting Value
01
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13.6.10
MB91665 Series
Address Output Extension Cycle
The address output extension cycle for the address data multiplex bus is set (BSTY=1). It specifies
the period in which address information is output to the D15 to D00 pins.
The period in which address information is output from the D15 to D00 pins (address output cycle) is at
least 1T (T: bus clock cycle). The number of address output extension cycles can be specified as a period
ranging from 0T to 3T (T: Bus clock period) with the ADCY1 and ADCY0 bits of the area wait registers
(AWR0 to AWR3).
Table 13.6-28 lists the setting values of the ADCY1 and ADCY0 bits in the area wait registers (AWR0 to
AWR3) and the address output cycle.
Table 13.6-28 ADCY1 and ADCY0 bits and extension cycle
ADCY1
ADCY0
Extension Period
Address Output Cycle (Total Length)
0
0
0T (no delay)
1T
0
1
1T
2T
1
0
2T
3T
1
1
3T
4T
T: Bus clock period
<Note>
The period set as the address output extension cycle must be equal to or longer than that of the
address strobe output extension cycle. If the set period used for the address output extension
cycle is shorter than that of the address strobe output extension cycle, the address strobe output
extension cycle is used in place of the address output extension cycle.
•
ADCY ≥ ASCY
•
if (ADCY < ASCY) then ADCY = ASCY
ADCY: ADCY1, ADCY0 bits
ASCY: ASCY1, ASCY0 bits
Even if the address output cycle is changed with the ADCY1 and ADCY0 bits of the area wait
registers (AWR0 to AWR3), the output periods and output timing of the other signals are not
changed.
Therefore, to change the address output cycle, make area wait register (AWR0 to AWR3) settings
that satisfy all of the following conditions in conformity with the protocol:
•
ADCY + 1 ≤ACS + CSRD
ADCY: ADCY1, ADCY0 bits
ACS: ACS1, ACS0 bits
CSRD: CSRD1, CSRD0 bits
•
ADCY + 1 ≤ACS + CSWR
ADCY: ADCY1, ADCY0 bits
ACS: ACS1, ACS0 bits
CSWR: CSWR1, CSWR0 bits
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MB91665 Series
■ Address data multiplex bus
Figure 13.6-19 shows an example in which the address output cycle is extended by 1T (T: Bus clock
period).
Figure 13.6-19 Example of address output extension cycle settings
2
1
Pin
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Address/Data
A
ACS
CSRD
A
ADCY
: Input data from an external machine
Table 13.6-29 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-19 (values other than "0" are set in the bits).
Table 13.6-29 Setting values of bits
Setting Item
Bit
Setting Value
Address output extension cycle count bits
ADCY1, ADCY0
01
Number of chip select delay cycles
ACS1, ACS0
01
Read access setup cycle
CSRD1, CSRD0
01
Table 13.6-29 shows that 1T (T: Bus clock period) is set as the number of chip select delay cycles, and
1T (T: Bus clock period) is set for the read access setup cycle. This is because of ADCY + 1 ≤ACS +
CSRD, which is a restriction of the address data multiplex bus protocol.
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13.6.11
MB91665 Series
Address Strobe Output Extension Cycle
The address strobe output extension cycle is set. It specifies the period in which the address strobe is
kept enabled.
The address strobe output period is at least 1T (T: bus clock cycle). The address strobe output period can
be extended by 0T or 1T (T: Bus clock period) with the ASCY bit of the area wait registers (AWR0 to
AWR3).
Table 13.6-30 lists the setting values of the ASCY bit in the area wait registers (AWR0 to AWR3) and the
corresponding address strobe output periods.
Table 13.6-30 ASCY bit and address strobe output periods
ASCY
Extension Period
Total Output Period
0
0T (no extension)
1T
1
1T
2T
T: Bus clock period
<Note>
To extend the address strobe output period, make area wait register (AWR0 to AWR3) settings that
satisfy all of the following conditions in conformity with the protocol:
•
With the address data split bus as the bus type (BSTY=0)
- ACS + CSRD + RWT + RDCS ≥ 1
ACS: ACS1, ACS0 bits
CSRD: CSRD1, CSRD0 bits
RWT: RWT3 to RWT0 bits
RDCS: RDCS1, RDCS0 bits
- ACS + CSWR + WWT + WRCS ≥ 1
•
ACS: ACS1, ACS0 bits
CSWR: CSWR1, CSWR0 bits
WWT: WWT3 to WWT0 bits
WRCS: WRCS1, WRCS0 bits
With the address data multiplex bus as the bus type (BSTY=1)
- ACS + CSRD ≥ 2
- ADCY + 1 ≤ACS + CSRD
ACS: ACS1, ACS0 bits
CSRD: CSRD1, CSRD0 bits
- ACS + CSWR ≥ 2
- ADCY + 1 ≤ACS + CSWR
ACS: ACS1, ACS0 bits
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CSWR: CSWR1, CSWR0 bits
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CHAPTER 13 External Bus Interface
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MB91665 Series
■ Address data split bus
Figure 13.6-20 shows an example in which the address strobe output extension cycle is extended by 1T
(T: Bus clock period).
Figure 13.6-20 Example of address strobe output extension cycle settings (address data split bus)
1
Pin
2
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
RD
Read strobe
Pin
Signal
D15 to D00
Data
ASCY
A
CSRD
: Input data from an external machine
Table 13.6-31 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-20 (values other than "0" are set in the bits).
Table 13.6-31 Setting values of bits
Setting Item
Bit
Setting Value
Number of chip select strobe output extension cycles
ASCY
1
Number of read access setup cycles
CSRD1, CSRD0
01
Table 13.6-31 shows that 1T (T: Bus clock period) is set for the read access setup cycle because of
protocol restrictions.
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CHAPTER 13 External Bus Interface
13.6
MB91665 Series
■ Address data multiplex bus
Figure 13.6-21 shows an example in which the address strobe output extension cycle is extended by 1T
(T: Bus clock period).
Figure 13.6-21 Example of address strobe output extension cycle settings (address data multiplex bus)
2
1
Pin
3
SYSCLK
Bus clock
Pin
Signal
AS
Address strobe
Pin
Signal
A23 to A00
Address information
Pin
Signal
CS0 to CS3
Chip select
Pin
Signal
WR0, WR1
Write strobe
Pin
Signal
D15 to D00
Address/Data
ASCY
A
ACS
A
ADCY
D
Table 13.6-32 lists the setting values of the area wait registers (AWR0 to AWR3) for the example shown
in Figure 13.6-21 (values other than "0" are set in the bits).
Table 13.6-32 Setting values of bits
Setting Item
Bit
Setting Value
Number of address strobe output extension cycles
ASCY
1
Number of chip select delay cycles
ACS1, ACS0
10
Number of address output extension cycles
ADCY1, ADCY0
01
Table 13.6-32 shows that 2T (T: Bus clock period) is set as the number of address delay cycles and 1T
(T: Bus clock period) is set for the address output extension cycle because of restrictions of the address
data multiplex bus protocol.
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CHAPTER 13 External Bus Interface
13.7
13.7 Access Cycle Extension Using the RDY
Pin
This section explains access cycle extension using the RDY pin of the external bus interface.
The effective period of the read strobe/write strobe can be extended by input of an "L" level signal
through the RDY pin.
The read strobe/write strobe are disabled in the next cycle and the read access cycle and write access
cycle are finished by input of an "H" level signal through the RDY pin.
To use the supported access cycle extension function that uses the RDY pin, write "1" to the RDYE bit in
the area wait registers (AWR0 to AWR3).
<Note>
To enable this function, use the RWT3 to RWT0 bits and WWT3 to WWT0 bits of the area wait
registers (AWR0 to AWR3) to specify "2" or a higher value for the read access automatic wait/write
access automatic wait period.
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CHAPTER 13 External Bus Interface
13.7
MB91665 Series
Figure 13.7-1 shows an example of access cycle extension using the RDY pin.
Figure 13.7-1 Example of access cycle extension using the RDY pin
0
Pin
Pin
Signal
1
2
3
4
5
6
7
8
9
10
SYSCLK
Bus clock
AS
Address strobe
Basic example in which automatic
wait cycle is set to 2 cycles
Pin
Signal
CS0 to CS3
Chip select
Pin
Sign
RD: Read strobe
Pin
Sign
WR0, WR1:
Write strobe
Automatic wait cycle
Example in which wait cycle in above
basic example is extended by 3
cycles by RDY pin
Pin
Signal
RDY
Wait cycle extension
Pin
Signal
CS0 to CS3
Chip select
Pin
Sign
RD: Read strobe
Pin
Sign
WR0, WR1:
Write strobe
Automatic wait cycle
Cycle extended with RDY
Table 13.7-1 lists the setting values of read access automatic wait registers (RWT0 to RWT3) and write
access automatic wait registers (WWT0 to WWT3) for the example shown in Table 13.7-1.
Table 13.7-1 Setting values of each bit
320
Setting Item
Bit
Setting Value
Read access automatic wait
RWT3 to RWT0
0010
Write access automatic wait
WWT3 to WWT0
0010
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CHAPTER 13 External Bus Interface
13.7
<Notes>
•
To not extend the automatic wait period, input an "H" level signal through the RDY pin.
•
Before the start of "L" level signal input through the RDY pin, the address strobe output ("L"
level output from the AS pin) and chip select output ("L" level output from the CS0 to CS3 pins)
must be verified.
•
The "L" level signal input through the RDY pin must start before the end of the automatic wait
period.
•
An "H" level signal must be input through the RDY pin after the end of the required extension
cycle.
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CHAPTER 13 External Bus Interface
13.8
MB91665 Series
13.8 Number of Access Cycles
This section explains the number of cycles required for one bus access operation of the external bus
interface.
■ Address data split bus
The following formulas can be used to calculate the numbers of read access cycles and write access
cycles:
•
Read access
Address/data output (1T) + ACS (0 to 3T) + CSRD (0 to 3T) + RWT (0 to 15T) +
RDCS (0 to 3T) = Minimum of 1T to maximum of 25T
ACS: Number of address output extension cycles
CSRD: Number of read access setup cycles
RWT: Read access automatic wait period
RDCS: Number of read access hold cycles
T:
•
Bus clock period
Write access
Address/data output (1T) + ACS (0 to 3T) + CSWR (0 to 3T) + WWT (0 to 15T) +
WRCS (0 to 3T) = Minimum of 1T to maximum of 25T
ACS: Number of address output extension cycles
CSWR:Number of write access setup cycles
WWT: Write access automatic wait period
WRCS:Number of write access hold cycles
T:
322
Bus clock period
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CHAPTER 13 External Bus Interface
13.8
MB91665 Series
■ Address data multiplex bus
The following formulas can be used to calculate the numbers of read access cycles and write access
cycles:
•
Read access
Address output (1T) + ACS (0 to 3T) + CSRD (0 to 3T) + data output (1T) + RWT (0 to 15T) +
RDCS (0 to 3T) = Minimum of 2T to maximum of 26T
ACS: Number of address output extension cycles
CSRD: Number of read access setup cycles
RWT: Read access automatic wait period
RDCS: Number of read access hold cycles
T:
•
Bus clock period
Write access
Address output (1T) + ACS (0 to 3T) + CSWR (0 to 3T) + data output (1T) + WWT (0 to 15T) +
WRCS (0 to 3T) = Minimum of 2T to maximum of 26T
ACS: Number of address output extension cycles
CSWR:Number of write access setup cycles
WWT: Write access automatic wait period
WRCS:Number of write access hold cycles
T:
CM71-10158-1E
Bus clock period
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CHAPTER 13 External Bus Interface
13.9
MB91665 Series
13.9 Address Information and Address
Alignment
This section describes address information for the external bus interface and explains address
alignment.
13.9.1
Address Information
This section explains bus types and address types of the external bus interface.
Pins that output address information vary depending on the combinations of the following settings:
•
Bus type (BSTY bit in an area configuration register (ACR0 to ACR3))
•
Address type (ADTY bit in an area configuration register (ACR0 to ACR3))
•
Data bus width (DBW1 and DBW0 bits in an area configuration register (ACR0 to ACR3))
Table 13.9-1 lists the correspondence between setting values of an area configuration register (ACR0 to
ACR3) and pins that output address information.
Table 13.9-1 Correspondence between setting values of an area configuration register
(ACR0 to ACR3) and pins that output address information
Address
Type
(ADTY)
Bus Type
(BSTY)
Bus Width
(DBW1, DBW0)
0
0
00 (8 bits)
A23 to A16
A07 to A00
Pins*
D15 to D08 Pins D7 to D00 Pins
(Address
(Address
Output Cycle) Output Cycle)
bit7 to bit0
-
-
00 (8 bits)
bit23 to bit16
bit7 to bit0
-
01 (16 bits)
bit23 to bit16
bit15 to bit8
bit7 to bit0
00 (8 bits)
bit7 to bit0
-
-
01 (16 bits)
bit8 to bit1
-
-
00 (8 bits)
bit23 to bit16
bit7 to bit0
-
01 (16 bits)
bit24 to bit17
bit16 to bit9
bit8 to bit1
01 (16 bits)
1
1
0
1
* In MB91F669, MSS bit is used to select external bus address select register (EXBS) of I/O port
control part.
There is no address pin in MB91F668.
ADTY : 0 = Normal output; 1 = Address shift output
BSTY : 0 = Address data split bus; 1 = Address data multiplex bus
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CHAPTER 13 External Bus Interface
13.9
MB91665 Series
13.9.2
Address Alignment
This section explains address alignment.
The external bus interface does not detect a misalignment of the address of an access destination.
Therefore, forcible alignment applies as follows in cases of word access or half word access:
•
Word access (32-bit access)
The lower 2 bits of the address to be output are always "00" regardless of the lower 2 bits of the
address specified by the program concerned.
•
Half word access (16-bit access)
If the lower 2 bits of the address specified by the program concerned are "00" or "01", the lower 2 bits
of the address to be output is "00". If the lower 2 bits of the address specified by the program are "10"
or "11", the lower 2 bits of the address to be output are "10".
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
13.10 Data Alignment
This section explains the data alignment of the external bus interface.
■ Endian
The external bus interface enables the byte ordering for the CS areas, except the CS0 area, to be set.
The byte ordering is specified by the LEDN bit in an area setting register (ASR0 to ASR3), and either big
endian (LEDN = 0) or little endian (LEDN = 1) can be selected.
Big endian stores data in different ways than little endian.
Storage of "01234567H"
•
Big endian
"01" is stored in the first byte, "23" in the second byte, "45" in the third byte, and "67" in the fourth
byte.
For details of access when big endian is set, see "13.10.1 Big Endian".
•
Little endian
"67" is stored in the first byte, "45" in the second byte, "23" in the third byte, and "01" in the fourth
byte.
If a data bus is connected, byte locations on the data bus are swapped according to the bus width.
For details of access when little endian is set, see "13.10.2 Little Endian".
Figure 13.10-1 shows the data format of big endian, and Figure 13.10-2 shows that of little endian.
Figure 13.10-1 Big endian data format
Memory
31
01
0
01
Address +0
Address
23
45
67
+1
+2
+3
Register bus
23
Half word access
45
67
01
Address +0
23
45
67
+1
+2
+3
Byte access
01
326
23
45
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
Bytes of the word data or half word data placed in an address space are arranged in the order in which the
most significant byte is located at the lowest address and the least significant byte is located at the highest
address.
Figure 13.10-2 Little endian data format
Memory
31
0
01
67
Address +3
Address
23
45
67
+2
+1
+0
Register bus
45
Half word access
23
01
45
Address +1
67
01
23
+0
+3
+2
Byte access
67
45
23
01
Bytes of the word data or half word data placed in an address space are arranged in the order in which the
most significant byte is located at the highest address and the least significant byte is located at the lowest
address.
<Notes>
•
The CS0 area supports only big endian. Little endian cannot be set for the CS0 area.
•
If an external machine is connected, the big endian areas must physically be separated from the
little endian areas.
■ Divided access
The data alignment for each access size of the external bus interface varies depending on the endian type
and data bus width.
Either 8 bits or 16 bits can be selected for each CS area as the data bus width by using the DBW1 and
DBW0 bits of the area configuration registers (ACR0 to ACR3).
An access operation whose access size is wider than the bus width specified by the DBW1 and DBW0
bits is performed only after being divided into multiple access operations. Table 13.10-1 lists the number
of times that an access operation is divided for each access size.
Table 13.10-1 Number of divided access operations
Bus Width
Access Size
Byte
CM71-10158-1E
Half Word
Word
8 bits
1 time
2 times
4 times
16 bits
1 time
1 time
2 times
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CHAPTER 13 External Bus Interface
13.10
13.10.1
MB91665 Series
Big Endian
If "0" is set in the LEDN bit in an area setting register (ASR1 to ASR3), the corresponding area is
treated as a big endian area.
This section explains big endian access and modes of connection.
■ Big endian access
● 16-bit external bus interface access
Table 13.10-2 lists the data alignment for each access size and corresponding control signals for the
setting of big endian together with a data bus width of 16 bits.
In the case where the access size is the length of a word, access is divided into 2 access operations.
Table 13.10-2 16-bit external bus interface access
Access
Size
Byte
Half
word
Word
Output Pin
Address
Lower 2 Bits
A01, A00
D15 to D08
D07 to D00
Data bit7 to bit0
WR0
WR1
00
"00"
O
01
"00"
10
"10"
11
"11"
0n
"00"
Data bit15 to
bit8
Data bit7 to bit0
O
O
1n
"10"
Data bit15 to
bit8
Data bit7 to bit0
O
O
nn
Divided access
First time: "00"
Data bit31 to
bit24
Data bit23 to
bit16
O
O
Divided access
Second time:
"10"
Data bit15 to
bit8
Data bit7 to bit0
O
O
Data bit7 to bit0
Data bit7 to bit0
O
O
Data bit7 to bit0
O
<Note>
In the above access examples, "0" (without shift) is set in the ADTY bit in an area configuration
register (ACR0 to ACR3).
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
● 8-bit external bus interface access
Table 13.10-3 lists the data alignment for each access size and corresponding control signals for the
setting of big endian together with a data bus width of 8 bits.
In the case where the access size is the length of a half word, access is divided into 2 access operations; in
the case where the access size is the length of a word, access is divided into 4 access operations.
Table 13.10-3 8-bit external bus interface access
Access
Size
Byte
Half
word
Address
Lower 2
Bits
CM71-10158-1E
A01, A00
D15 to D08
D07 to D00
WR0
00
"00"
Data bit7 to bit0
O
01
"01"
Data bit7 to bit0
O
10
"10"
Data bit7 to bit0
O
11
"11"
Data bit7 to bit0
O
0n
Divided access
First time: "00"
Data bit15 to bit8
O
Divided access
Second time: "01"
Data bit7 to bit0
O
Divided access
First time: "10"
Data bit15 to bit8
O
Divided access
Second time: "11"
Data bit7 to bit0
O
Divided access
First time: "00"
Data bit31 to bit24
O
Divided access
Second time: "01"
Data bit23 to bit16
O
Divided access
Third time: "10"
Data bit15 to bit8
O
Divided access
Fourth time: "11"
Data bit7 to bit0
O
1n
Word
Output Pin
nn
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
■ How to connect asynchronous memory
In the following connection examples, asynchronous memory is connected with external bus pins for an
area for which big endian is set.
● Connection example for a 16-bit external bus interface
The CS3 area used in this example is an area with a bus width of 16 bits and the setting of big endian, and
two 256K × 8-bit SRAM modules are connected to the CS3 area.
The A18, A17, A16 pins, WR0 and WR1 pins, and D15 to D00 pins are used.
Figure 13.10-3 shows the connection example with the above conditions.
Figure 13.10-3 Example for a 16-bit bus width (multiplex) (MB91F669 (64 pins))
This LSI
AS
D15 to D00
LE
OE
D[17:0] Q[17:0]
A14 to A00
D15 to D01
A18, A17, A16
A17,A16,A15
CS3
CS
RD
OE
WR0
WE
SRAM
256K ×
8 bits
I/O7 to I/O0
D15 to D08
A17 to A0
CS
OE
WR1
SRAM
256K ×
8 bits
WE
I/O7 to I/O0
D07 to D00
OE : Output enable
WE : Write enable
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
● Connection example for an 8-bit external bus interface
The CS3 area used in this example is an area with a bus width of 8 bits and the setting of big endian, and
a 256K × 8-bit SRAM module is connected to the CS3 area.
The A18, A17, A16 pins, WR0 and WR1 pins, and D15 to D00 pins are used.
Figure 13.10-4 shows the connection example with the above conditions.
Figure 13.10-4 Example for an 8-bit bus width (multiplex) (MB91F669 (64 pins))
This LSI
AS
A17, A16, D15 to D00
CS3
LE
OE
D[17:0] Q[17:0]
A17 to A00
A17, A16, D15 to D00
CS
RD
OE
WR0
WE
D15 to D08
SRAM
256K ×
8 bits
I/O7 to I/O0
OE : Output enable
WE : Write enable
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CHAPTER 13 External Bus Interface
13.10
13.10.2
MB91665 Series
Little Endian
If "1" is set in the LEDN bit in an area setting register (ASR1 to ASR3), the corresponding area is
treated as a little endian area.
This section explains little endian access and modes of connection.
■ Little endian access
● 16-bit external bus interface access
Table 13.10-4 lists the data alignment for each access size and corresponding control signals for the
setting of little endian together with a data bus width of 16 bits.
In the case where the access size is the length of a word, access is divided into two access operations.
Table 13.10-4 16-bit external bus interface access
Access
Size
Byte
Address
Lower 2
Bits
Output Pin
A00, A01
D15 to D08
D07 to D00
Data bit7 to bit0
WR0
WR1
00
"00"
O
01
"01"
10
"10"
11
"11"
Half
word
0n
"00"
Data bit7 to bit0
Data bit15 to bit8
O
O
1n
"10"
Data bit7 to bit0
Data bit15 to bit8
O
O
Word
nn
Divided access
First time: "00"
Data bit7 to bit0
Data bit15 to bit8
O
O
Divided access
Second time:
"10"
Data bit23 to
bit16
Data bit31 to
bit24
O
O
Data bit7 to bit0
Data bit7 to bit0
O
O
Data bit7 to bit0
O
Note: In the above access example, the ADTY bit in an area configuration register (ACR0 to ACR3) is set
to "0" (without shift).
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
● 8-bit external bus interface access
Table 13.10-5 lists the data alignment for each access size and corresponding control signals for the
setting of little endian together with a data bus width of 8 bits.
In the case where the access size is the length of a half word, access is divided into 2 access operations; in
the case where the access size is the length of a word, access is divided into 4 access operations.
Table 13.10-5 8-bit external bus interface access
Access
Size
Byte
Half
word
Address
Lower 2
Bits
CM71-10158-1E
A00, A01
D15 to D08
D07 to D00
WR0
00
"00"
Data bit7 to bit0
O
01
"01"
Data bit7 to bit0
O
10
"10"
Data bit7 to bit0
O
11
"11"
Data bit7 to bit0
O
0n
Divided access
First time: "00"
Data bit7 to bit0
O
Divided access
Second time: "01"
Data bit15 to bit8
O
Divided access
First time: "10"
Data bit7 to bit0
O
Divided access
Second time: "11"
Data bit15 to bit8
O
Divided access
First time: "00"
Data bit7 to bit0
O
Divided access
Second time: "01"
Data bit15 to bit8
O
Divided access
Third time: "10"
Data bit23 to bit16
O
Divided access
Fourth time: "11"
Data bit31 to bit24
O
1n
Word
Output Pin
nn
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
■ How to connect an external machine with a little endian area
The following figures show how to connect data bus and byte enable signals with a little endian external
machine.
● Connection example for a 16-bit external bus interface
If an external machine with a little endian area with a bus width of 16 bits is connected, data bus width
must be swapped in the unit of byte as shown in Figure 13.10-5.
Figure 13.10-5 Connection example in which the data bus width is swapped in the unit of byte
External machine with little endian area
This LSI
00
Data bus pins
Lower 2 bits of address
01
D15 to D08 D07 to D00
01
D15 to D08
00
D07 to D00
Data bus pins
In the above example, the external machine with the little endian area is connected to the CS3 area. The
CS3 area is set with a 16-bit bus width and as a little endian area.
Figure 13.10-6 shows the connection example with the above conditions.
The WR0 and WR1 pins and the D15 to D00 pins are used.
Figure 13.10-6 How to connect an external machine with a little endian area
with a data bus when the bus width is 16 bits (MB91F669 (64 pins))
This LSI
External machine with little endian area
A07 to A00
CS3
CS: Chip select
RD
RD: Read strobe
WR0
WR: Write strobe
D15 to D08
WR1
D07 to D00
334
A07 to A00: Address bus
D07 to D00: Data bus (MSB)
WR: Write strobe
D15 to D08: Data bus
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CHAPTER 13 External Bus Interface
13.10
MB91665 Series
● Connection example for an 8-bit external bus interface
Figure 13.10-7 shows the bit positions of the data bus and byte enable signal used in the connection
example.
Figure 13.10-7 Bit positions of the data bus and byte enable signal
External machine with little endian area
This LSI
Lower 2 bits of address
00
Data bus pins
00
D07 to D00
D15 to D08
Data bus pins
Figure 13.10-8 shows that an external machine with a little endian area is connected to the CS3 area. The
CS3 area is set with a 8-bit bus width and as a little endian area.
Figure 13.10-8 shows the connection example with the above conditions.
The WR0 pin and the D15 to D08 pins are used.
Figure 13.10-8 How to connect an external machine with a little endian area with a data bus
when the bus width is 8 bits (MB91F669 (64 pins))
This LSI
External machine with little endian area
A07 to A00
CS3
CS: Chip select
RD
RD: Read strobe
WR0
WR: Write strobe
D15 to D08
CM71-10158-1E
A07 to A00: Address bus
D07 to D00: Data bus
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CHAPTER 13 External Bus Interface
13.11
MB91665 Series
13.11 CS Area Setting Procedure
This section explains how to set the CS area.
Note the following about making CS area settings:
•
CS area setting must be made at the initial setting time after a reset and must not be changed at a later
time.
•
To make settings or changes for CS areas, use the initial setting program stored in ROM.
<Note>
Do not change the setting of a CS area while the CS area is being accessed.
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CHAPTER 13 External Bus Interface
13.11
MB91665 Series
■ Setting procedure
Figure 13.11-1 is a flowchart for a CS area setting procedure example.
Figure 13.11-1 CS area setting procedure flow
CS setting start
Change of CS0
setting or creation of another CS
area in 0000 0000H to 7FFF FFFFH
area
NO
YES
Disable CS0,
write "0" to CSEN bit in ASR0
Write setting value in ACR (n)
Write setting value in AWR (n)
Enable CS area
Write setting value in ASR (n)
YES
Setting of another CS area
NO
Read data from ASR (n)
Compare value read from ASR (n) and
value written to ASR (n)
CS setting end
CM71-10158-1E
ASR (n) : ASR0 to ASR3 ... Area setting registers
ACR (n) : ACR0 to ACR3 ... Area configuration registers
AWR (n) : AWR0 to AWR3 ... Area wait registers
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CHAPTER 13 External Bus Interface
13.11
MB91665 Series
1. Write "0000 0000H" to the area setting register (ASR0) through word access (only when changing the
CS0 area or allocating another CS area to the 0000 0000H to 7FFF FFFFH area).
2. Write a setting value in an area configuration register (ACR0 to ACR3) through word access.
Use the area configuration register (ACR0 to ACR3) to make the following settings:
-
Data bus width
-
Address type
-
Bus type
3. Write a setting value to an area wait register (AWR0 to AWR3) through word access.
4. Write a setting value to area setting register (ASR0 to ASR3) through word access.
Make the following settings with an area setting register (ASR0 to ASR3):
-
CS area
-
Write enable
-
Byte ordering (except for the CS0 area)
-
CS area enable/disable
5. To make settings for another CS area, repeat steps 2 to 4.
6. Read the area setting register (ASR0 to ASR3).
7. Compare the read values and the values that have been set in the area setting register (ASR0 to
ASR3).
Verify that the CS area settings are reflected in the subsequent access operations by reading the area
setting register (ASR0 to ASR3) that was the last one set , and verify that the setting values and read
values are the same.
To wait for the CS area settings to be reflected in the subsequent access operations by reading the area
setting register (ASR0 to ASR3) that was the last one set, and compare the setting values and read values.
Reading and comparison are dummy processing. There is no effect to the comparison results.
<Notes>
•
To change the CS0 area or allocate another CS area to the 0000 0000H to 7FFF FFFFH area,
first disable the CS0 area by using the CSEN bit (CSEN = 0) of the CS0 area setting register
(ASR0).
•
Notes on area setting register (ASR0 to ASR3) settings
- Be sure that CS areas do not overlap one another. If any CS areas overlap, operation is not
guaranteed.
- The upper bits of the start address are set in the SADR31 to SADR16 bits. However,
depending on the size of the area, the boundary is fixed in advance. The ASZ3 to ASZ0 bits
that are valid bits must be set according to the CS area size. The SADR31 to SADR16 bits
that are invalid must be set to "0".
338
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CHAPTER 13 External Bus Interface
13.11
MB91665 Series
■ CS area setting example
An example of setting values for the ASZ3 to ASZ0 bits and SADR31 to SADR16 bits in an area setting
register (ASR0 to ASR3) and CS areas actually allocated is shown below.
•
CS0 area settings
CS0 area setting register (ASR0): ASZ3 to ASZ0 = 0010B
CS0 area setting register (ASR0): SADR31 to SADR16 = 002CH
→002C 0000H to 002F FFFFH is the CS0 area.
•
CS1 area settings
CS1 area setting register (ASR1): ASZ3 to ASZ0 = 0000B
CS1 area setting register (ASR1): SADR31 to SADR16 = 0026H
→0026 0000H to 0026 FFFFH is the CS1 area.
•
CS2 area settings
CS2 area setting register (ASR2): ASZ3 to ASZ0 = 0100B
CS2 area setting register (ASR2): SADR31 to SADR16 = 0030H
→0030 0000H to 003F FFFFH is the CS2 area.
•
CS3 area settings
CS3 area setting register (ASR3): ASZ3 to ASZ0 = 0010B
CS3 area setting register (ASR3): SADR31 to SADR16 = 0FFCH
→0FFC 0000H to 0FFF FFFFH is the CS3 area.
<Note>
For example, the space between 0031 0000H and 1M byte can not be allocated.
Supposedly performing the following settings, CS2 area will be 0030 0000H to 003F FFFFH.
CS2 area setting register (ASR2): ASZ3 to ASZ0=0100B
CS2 area setting register (ASR2): SADR31 to SADR16=0031H
In these settings, SADR31 to SADR20 bits are valid and SADR19 to SADR16 bits are not
subjected to compare the address.
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CHAPTER 13 External Bus Interface
13.11
MB91665 Series
Figure 13.11-2 shows the CS areas in the above example.
Figure 13.11-2 CS area example
Initial state
Setting example
0000 0000H
0000 0000H
0026 0000H
0027 0000H
CS1 area
64 KB
CS0 area
256 KB
CS2 area
1 MB
CS3 area
256 KB
002C 0000H
0030 0000H
CS0 area
0040 0000H
0FFC 0000H
1000 0000H
340
7FFF FFFFH
7FFF FFFFH
FFFF FFFFH
FFFF FFFFH
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CM71-10158-1E
CHAPTER 14 I/O Ports
This chapter explains the functions and operations of the
I/O ports.
14.1
14.2
14.3
14.4
Overview
Configuration
Pins
Registers
14.5 Notes on Use
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CHAPTER 14 I/O Ports
14.1
MB91665 Series
14.1 Overview
Pins of this series that are not used for the external bus interface or peripheral functions can be used
as I/O ports.
■ Overview
The I/O ports have the following features:
•
Each pin can be specified as an I/O port used only as an input port or output port.
•
Each pin can be specified as a pin used as an I/O port or a pin for a peripheral function or the external
bus interface.
Also, one of the I/O modes listed below can be selected depending on the register settings:
Table 14.1-1 lists the I/O modes.
Table 14.1-1 I/O modes
I/O mode
Access to PDR
Port input mode
Port output mode
Peripheral function
output mode *
PDR:
In case of reading
(except RMW
instructions)
The levels of external pins are read.
In case of reading
(RMW instructions)
The PDR value is read.
In case of writing
The written value is stored in a PDR.
In case of reading
(except RMW
instructions)
The PDR value is read.
In case of reading
(RMW instructions)
The PDR value is read.
In case of writing
The written value is stored in a PDR and
output to an external pin.
In case of reading
(except RMW
instructions)
The output level from a peripheral
function or the PDR value is read.
In case of reading
(RMW instructions)
The PDR value is read.
In case of writing
The written value is stored in a PDR.
Port data register (PDR0 to PDRK)
RMW instruction: Read-modify-write instruction
*:
342
The value that is read varies depending on the register settings.
•
A pull-up resistor can be set for each pin.
•
If Hi-Z is set to a pin with the CPU in standby mode (stop mode/watch mode/main timer mode), input
is fixed at "0". However, input is not fixed at "0" for external interrupt requests whose generation is
enabled and it can be used.
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CHAPTER 14 I/O Ports
14.1
MB91665 Series
•
A peripheral function can be assigned to any pin available for peripheral functions, if more than one pin
is available, and peripheral function output from the pin can be enabled/disabled.
However, if the peripheral function has more than one I/O, each I/O must be set to individual ports
belonging to the same group.
Example: Ch.1 multifunction serial interface settings
Serial Data
Output
SOUT1 pin
(Port 0)
Serial Clock I/O
SCK1 pin (Port 0)
SCK1_1 pin (Port 1)
Serial Data Input
Valid Port
SIN1 pin (Port 0)
Port 0
SIN1_1 pin (Port 1)
Setting prohibited
SIN1 pin (Port 0)
SIN1_1 pin (Port 1)
SOUT1_1 pin
(Port 1)
SCK1 pin (Port 0)
SIN1 pin (Port 0)
SIN1_1 pin (Port 1)
SCK1_1 pin (Port 1)
SIN1 pin (Port 0)
SIN1_1 pin (Port 1)
Port 1
<Note>
The setting method of port function of following pins are different from MB91V650.
Maximum of 3 PFR registers should be set for one pin.
Refer to "2.4 Setting Method for Pins".
P14 to P17, P20 to P27, P50 to P57, P60, P61, P80, and P81.
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CHAPTER 14 I/O Ports
14.2
MB91665 Series
14.2 Configuration
This series has the following 3 types of built-in I/O port:
• Ordinary I/O ports
• Analog input multifunction I/O ports
• Analog output multifunction I/O ports
■ Overview
3 types of built-in I/O port that this series has are described below.
•
Ordinary I/O ports
These I/O ports have basic configurations in which the ports are used also for I/O of peripheral
functions. Each port consists of the following blocks:
•
-
Port function registers (PFR0 to PFRH)
-
Port data direction registers (DDR0 to DDRK)
-
Extended port function registers (EPFR0 to EPFR35)
-
Pull-up resistor control registers (PCR0 to PCR8)
-
Port data registers (PDR0 to PDRK)
Analog input multifunction I/O ports
These I/O ports are used also for analog input of the 10-bit A/D converter. Each port consists of an
analog input enable block and the ordinary I/O port blocks.
The analog input multifunction ports are P77 to P70, and P83 to P80.
•
N-ch open drain control I/O ports
These I/O ports can control I/O port output with N-ch open drain (low output only).
-
•
Open drain control registers (NDE0 to NDE1)
External bus address select function
This function switches address pins when split bus and multiplex bus are set.
-
344
External bus address select register (EXBS)
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CHAPTER 14 I/O Ports
14.2
MB91665 Series
■ Block diagrams
● Ordinary I/O ports
Figure 14.2-1 is a block diagram of an ordinary I/O port.
Figure 14.2-1 Block diagram of an ordinary I/O port
External bus interface
Slave interface
Peripheral
function
0
CMOS
Input
selection
CMOS
schmitt
1
Peripheral bus
DDR
Port data
direction
control
PFR
Vcc
EPFR
R
PCR
PDR
Pins
External bus
control output
Peripheral
function output
•
Output
selection
Port data direction registers (DDR0 to DDRK)
These registers set the I/O directions of pins used as general-purpose ports.
For a pin for a peripheral function or the external bus interface, these registers set the contents read
from a port data register (PDR0 to PDRK).
•
Port function registers (PFR0 to PFRH)
These registers select how to use individual pins.
•
Extended port function registers (EPFR0 to EPFR35)
These registers set the pin to which a peripheral function is assigned from among the multiple pins
available for peripheral functions. Peripheral function output from such pins is enabled/disabled
according to the registers.
•
Pull-up resistor control registers (PCR0 to PCR8)
These registers set pull-up resistors. With one register provided for each port, a pull-up resistor can be
connected to each pin.
•
Port data registers (PDR0 to PDRK)
These registers store output data. The meanings of read and written values vary depending on the
mode of the port.
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CHAPTER 14 I/O Ports
14.2
MB91665 Series
● Analog input multifunction I/O port
Figure 14.2-2 is a block diagram of an analog input multifunction I/O port.
Figure 14.2-2 Block diagram of an analog input multifunction I/O port
A/D input
CMOS
schmitt
Peripheral
function
0
Input
selection
1
Analog
input
enable
Peripheral bus
DDR
PFR
Port data
direction
control
Vcc
EPFR
R
PCR
PDR
Pins
External bus
control output
Peripheral
function output
Output
selection
The analog input multifunction I/O port consists of the blocks that are components of each ordinary I/O
port and the analog input enable block.
This block enables analog input from pins for which input is enabled by the A/D channel enable
register (ADCHE).
<Notes>
346
•
The analog input multifunction ports are P77 to P70, and P83 to P80.
•
In serial write mode selected by the MD1 and MD0 pins (MD1, MD0 = 01), digital input is
enabled and analog input is disabled only for P75 (AN5 pin).
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CHAPTER 14 I/O Ports
14.2
MB91665 Series
■ Clocks
Table 14.2-1 lists the clocks used for I/O ports.
Table 14.2-1 Clocks used for I/O ports
Clock name
Operation clock
CM71-10158-1E
Description
Peripheral clock (PCLK)
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CHAPTER 14 I/O Ports
14.3
MB91665 Series
14.3 Pins
This section explains the pins of I/O ports.
■ Overview
The I/O ports belonging to a port with the same suffix can be read/written at the same time.
348
•
P00 to P07 (port 0)
•
P10 to P17 (port 1)
•
P20 to P27 (port 2)
•
P50 to P57 (port 5)
•
P60, P61 (port 6)
•
P70 to P77 (port 7)
•
P80 to P83 (port 8)
•
PH2, PH3 (port H)
•
PK0, PK1 (port K)
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CHAPTER 14 I/O Ports
14.4
MB91665 Series
14.4 Registers
This section explains the configuration and functions of the registers used for I/O ports.
■ List of registers for I/O ports
Table 14.4-1 lists the registers for I/O ports.
Table 14.4-1 Registers for I/O ports (1 / 2)
Port
Common
0
1
2
3
4
CM71-10158-1E
Abbreviated
Register Name
Register Name
Reference
EPFR0 to EPFR35
Extended port function register 0 to 35
14.4.3
ADCHE
A/D channel enable register
14.4.6
NDE0
N-ch open drain control register 0
14.4.7
NDE1
N-ch open drain control register 1
14.4.7
EXBS
External bus address select register
14.4.8
FRID
FR identification data register
14.4.9
DDR0
Port data direction register 0
14.4.1
PFR0
Port function register 0
14.4.2
PCR0
Pull-up resistor control register 0
14.4.5
PDR0
Port data register 0
14.4.4
DDR1
Port data direction register 1
14.4.1
PFR1
Port function register 1
14.4.2
PCR1
Pull-up resistor control register 1
14.4.5
PDR1
Port data register 1
14.4.4
DDR2
Port data direction register 2
14.4.1
PFR2
Port function register 2
14.4.2
PDR2
Port data register 2
14.4.4
DDR3
Port data direction register 3
14.4.1
PFR3
Port function register 3
14.4.2
DDR4
Port data direction register 4
14.4.1
PFR4
Port function register 4
14.4.2
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14.4
MB91665 Series
Table 14.4-1 Registers for I/O ports (2 / 2)
Port
5
6
7
8
A
G
H
K
350
Abbreviated
Register Name
Register Name
Reference
DDR5
Port data direction register 5
14.4.1
PFR5
Port function register 5
14.4.2
PCR5
Pull-up resistor control register 5
14.4.5
PDR5
Port data register 5
14.4.4
DDR6
Port data direction register 6
14.4.1
PFR6
Port function register 6
14.4.2
PCR6
Pull-up resistor control register 6
14.4.5
PDR6
Port data register 6
14.4.4
DDR7
Port data direction register 7
14.4.1
PFR7
Port function register 7
14.4.2
PCR7
Pull-up resistor control register 7
14.4.5
PDR7
Port data register 7
14.4.4
DDR8
Port data direction register 8
14.4.1
PFR8
Port function register 8
14.4.2
PCR8
Pull-up resistor control register 8
14.4.5
PDR8
Port data register 8
14.4.4
DDRA
Port data direction register A
14.4.1
PFRA
Port function register A
14.4.2
DDRG
Port data direction register G
14.4.1
PFRG
Port function register G
14.4.2
DDRH
Port data direction register H
14.4.1
PFRH
Port function register H
14.4.2
PDRH
Port data register H
14.4.4
DDRK
Port data direction register K
14.4.1
PDRK
Port data register K
14.4.4
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CHAPTER 14 I/O Ports
14.4
MB91665 Series
14.4.1
Port Data Direction Registers (DDR0 to DDRK)
These registers set the I/O directions of pins used as general-purpose ports.
For a pin for a peripheral function or the external bus interface, these registers set the contents read
from a port data register (PDR0 to PDRK).
The meaning of a read/written value of the port data register (PDR0 to PDRK) varies depending on the
setting of each bit in this port data direction register and the settings of a port function register (PFR0 to
PFRH).
Figure 14.4-1 shows the bit configuration of the port data direction registers (DDR0 to DDRK).
Figure 14.4-1 Bit configuration of the port data direction registers (DDR0 to DDRK)
bit
7
6
5
4
3
2
1
0
Initial value
Attribute
DDR0
DDR07
DDR06
DDR05
DDR04
DDR03
DDR02
DDR01
DDR00
0000 0000
R/W
DDR1
DDR17
DDR16
DDR15
DDR14
DDR13
DDR12
DDR11
DDR10
0000 0000
R/W
DDR2
DDR27
DDR26
DDR25
DDR24
DDR23
DDR22
DDR21
DDR20
0000 0000
R/W
DDR3
DDR37
DDR36
DDR35
DDR34
Reserved
DDR32
DDR31
DDR30
0000 0000
R/W
DDR4
DDR47
DDR46
DDR45
DDR44
DDR43
DDR42
DDR41
DDR40
0000 0000
R/W
DDR5
DDR57
DDR56
DDR55
DDR54
DDR53
DDR52
DDR51
DDR50
0000 0000
R/W
DDR6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DDR61
DDR60
0000 0000
R/W
DDR7
DDR77
DDR76
DDR75
DDR74
DDR73
DDR72
DDR71
DDR70
0000 0000
R/W
DDR8
Reserved
Reserved
Reserved
Reserved
DDR83
DDR82
DDR81
DDR80
0000 0000
R/W
DDRA
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
Reserved Reserved 0000 0000
R/W
DDRG
DDRG7
DDRG6
DDRG5
DDRG4
DDRG3
DDRG2
DDRG1
DDRG0
0000 0000
R/W
DDRH
Undefined
Undefined
Undefined
Undefined
DDRH3
DDRH2
DDRH1
DDRH0
XXXX 0000
R/W
DDRK
Undefined
Undefined
Undefined
Undefined
Reserved
Reserved
DDRK1
DDRK0
XXXX 0000
R/W
R/W: Read/Write
X:
Undefined
<Note>
Always write "0" to the reserved bits.
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CHAPTER 14 I/O Ports
14.4
MB91665 Series
Each bit sets the I/O direction of the corresponding port.
Written Value
Explanation
0
Input direction
1
Output direction
The meaning of a read/written value of a port data register (PDR0 to PDRK) varies depending on the
setting of each bit in one of these port data direction registers and the settings of a port function register
(PFR0 to PFRH).
Table 14.4-2 shows the relationship between the register settings and read/written values of the port data
registers (PDR0 to PDRK).
Table 14.4-2 Relationship between register settings and read/written values of the port
data registers (PDR0 to PDRK)
Mode
Port input
mode
Port output
mode
Peripheral
function
output mode *
DDR
PFR
0
0
1
0
1
*
0
1
1
PDR
In case of reading (except
RMW instructions)
The output level of an external pin is
read.
In case of reading (RMW
instructions)
The PDR value is read.
In case of writing
The written value is saved in a PDR.
In case of reading (except
RMW instructions)
The PDR value is read.
In case of reading (RMW
instructions)
The PDR value is read.
In case of writing
The written value is saved in a PDR
and output to an external pin.
In case of reading (except
RMW instructions)
The output level from a peripheral
function is read.
In case of reading (RMW
instructions)
The PDR value is read.
In case of writing
The written value is saved in a PDR.
In case of reading (except
RMW instructions)
The PDR value is read.
In case of reading (RMW
instructions)
The PDR value is read.
In case of writing
The written value is saved in a PDR.
The functions of the output pins of external functions must be assigned to the appropriate pins by
the extended port function registers (EPFR0 to EPFR35), and output from the pins must be enabled.
DDR: Port data direction register (DDR0 to DDRK)
PFR: Port function register (PFR0 to PFRH)
PDR: Port data register (PDR0 to PDRK)
RMW instruction: Read-modify-write instruction
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CHAPTER 14 I/O Ports
14.4
MB91665 Series
<Notes>
•
The input to a peripheral function is always connected to the pin assigned by an appropriate bit
in an extended port function register (EPFR0 to EPFR35). Use port input mode for input to a
peripheral function.
However, when input from the 10-bit A/D converter is enabled, input is always fixed at "0", and
output from the port is always fixed at Hi-Z.
In serial write mode selected by the MD1 and MD0 pins (MD1, MD0 = 01), digital input is
enabled and analog input is disabled only for P75 (AN5 pin).
•
When this device is reset, the settings of these registers are reset to the initial value (00H), and
the I/O direction of every port becomes input.
•
To use PK0 and PK1 as low-speed oscillation pins, be sure to set the I/O directions of the ports
to input (DDRK0 = 0, DDRK1 = 0) in port data direction register K (DDRK).
(If PK0 and PK1 is used as a low-speed oscillation pin when the I/O direction of the related port
has been set to output, the PDR value is output from the pin when low-speed oscillation is
disabled.)
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14.4
14.4.2
MB91665 Series
Port Function Registers (PFR0 to PFRH)
These registers select how to use individual pins.
The meaning of a read/written value of a port data register (PDR0 to PDRK) varies depending on the
setting of each bit in one of these port function registers and the settings of a port data direction register
(DDR0 to DDRK).
For details, see "14.4.1 Port Data Direction Registers (DDR0 to DDRK)".
Figure 14.4-2 shows the bit configuration of the port function registers (PFR0 to PFRH).
Figure 14.4-2 Bit configuration of the port function registers (PFR0 to PFRH)
bit
7
6
5
4
3
2
1
0
Initial value
Attribute
PFR0
PFR07
PFR06
PFR05
PFR04
PFR03
PFR02
PFR01
PFR00
0000 0000
R/W
PFR1
PFR17
PFR16
PFR15
PFR14
PFR13
PFR12
PFR11
PFR10
0000 0000
R/W
PFR2
PFR27
PFR26
PFR25
PFR24
PFR23
PFR22
PFR21
PFR20
0000 0000
R/W
PFR3
PFR37
PFR36
PFR35
PFR34
Reserved
PFR32
PFR31
PFR30
0000 0000
R/W
PFR4
PFR47
PFR46
PFR45
PFR44
PFR43
PFR42
PFR41
PFR40
0000 0000
R/W
PFR5
PFR57
PFR56
PFR55
PFR54
PFR53
PFR52
PFR51
PFR50
0000 0000
R/W
PFR6
Reserved
Reserved
Undefined
Reserved
Reserved
Undefined
PFR61
PFR7
PFR77
PFR76
PFR75
PFR74
PFR73
PFR72
PFR71
PFR70
0000 0000
R/W
PFR8
Reserved
Reserved
Reserved
Reserved
PFR83
PFR82
PFR81
PFR80
0000 0000
R/W
PFRA
PFRA7
PFRA6
Undefined
PFRA4
PFRA3
PFRA2
Reserved
Reserved 00X0 0000
R/W
PFRG
Undefined
PFRG6
PFRG5
PFRG4
Undefined
PFRG2
PFRG1
PFRG0
X000 X000
R/W
PFRH
Undefined Undefined Undefined Undefined Undefined
PFRH2
Undefined
PFRH0
XXXX X0X0
R/W
Undefined 00X0 0X0X
R/W
R/W: Read/Write
X:
Undefined
<Note>
Always write "0" to the reserved bits.
The port function registers specify each pin as either a pin used as a general-purpose port or a pin for the
peripheral function specified by an extended port function register (EPFR0 to EPFR35).
Written Value
354
Explanation
0
General-purpose port
1
Peripheral function
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MB91665 Series
The following function and I/O settings can be made for each pin according to the settings of bits in one
of these registers and the corresponding bits in an extended port function register (EPFR0 to EPFR35):
PFR
EPFR
0
0
1
Function of
Corresponding
Pin
Output
from
Peripheral
Functions
Input to
Peripheral
Functions
Port
Output
External External
Bus Pin Bus Pin
Output
Input
Disabled
Enabled
Set by
DDR
Disabled
Enabled
Sets the function
Output pin of a
assigned to the
peripheral
output pin of a
function
peripheral function
and enables output.
Enabled
Enabled
Disabled
Disabled
Enabled
Cancels the
assignment of a
function to the
output pin of a
peripheral
function, or
disables output
External bus pin
(external bus
multiplexed pin)
Disabled
Enabled
Disabled
Enabled
Enabled
Port (other than
external bus
multiplexed pin)
Disabled
Enabled
Set by
DDR
-
-
Port*
PFR: Corresponding bit in a port function register (PFR0 to PFRH)
EPFR: Corresponding bit in an extended port function register (EPFR0 to EPFR35)
* To use the following ports as a port, 2 to 3 PFRs should be set.
P14 to P17 : PFR14 to PFR17, PFR34 to PFR37
P20, P21 :
PFR20, PFR21, PFR40, PFR41, PFRA3, PFRA4
P22, P23 :
PFR22, PFR23, PFR42, PFR43, PFRG0, PFRG1
P24 to P27 : PFR24 to PFR27, PFR44 to PFR47
P50 :
PFR50, PFRA2
P51 to P53 : PFR51 to PFR53, PFRG4 to PFRG6
P54 to P56 : PFR54 to PFR56, PFR30 to PFR32
CM71-10158-1E
P57 :
PFR57, PFRA7
P60, P61 :
PFR60, PFR61, PFRG2, PFRH0
P80, P81 :
PFR80, PFR81, PFRA6
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<Notes>
•
When this device is reset, the settings of these registers are reset to the initial value (00H), and
all ports are set to operate as input ports.
•
If this register specifies a pin as a general-purpose port, the corresponding pin will operate as a
general-purpose port even if a peripheral function has been assigned to that pin in one of the
extended port function registers (EPFR0 to EPFR35).
•
When analog input is enabled through the settings of the A/D channel enable register (ADCHE),
input from ports and other functions is fixed at "0" regardless of the settings of these registers.
•
To enable the functions of external bus interface pins, make the following settings:
1. Disable output from all peripheral functions by using the corresponding bits of the extended
port function registers (EPFR0 to EPFR35).
2. Write "1" to the corresponding bits in this register to set peripheral functions as the functions
of the pins.
•
The input to a peripheral function is always connected to the pin assigned by an appropriate bit
in an extended port function register (EPFR0 to EPFR35). Use port input mode for input to a
peripheral function.
However, when input from the 10-bit A/D converter is enabled, input is always fixed at "0", and
output from the port is always fixed at Hi-Z.
356
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CHAPTER 14 I/O Ports
14.4
MB91665 Series
14.4.3
Extended Port Function Registers (EPFR0 to EPFR35)
These registers set the pin to which a function is assigned from among the multiple pins available for
the function. Output from such pins is enabled/disabled according to the registers.
Figure 14.4-3 shows the bit configuration of the extended port function registers (EPFR0 to EPFR35).
Figure 14.4-3 Bit configuration of the extended port function registers (EPFR0 to EPFR35)
bit
7
6
5
4
3
2
1
0
Initial value
EPFR0
Undefined
Undefined
OUT1E2
OUT1E1
OUT1E0
OUT0E2
OUT0E1
OUT0E0
XX00 0000
EPFR1
Undefined
Undefined
OUT3E2
OUT3E1
OUT3E0
OUT2E2
OUT2E1
OUT2E0
XX00 0000
EPFR2
Undefined
Undefined
OUT5E2
OUT5E1
OUT5E0
OUT4E2
OUT4E1
OUT4E0
XX00 0000
EPFR3
Undefined
Undefined
OUT7E2
OUT7E1
OUT7E0
OUT6E2
OUT6E1
OUT6E0
XX00 0000
EPFR4
IN3E1
IN3E0
IN2E1
IN2E0
IN1E1
IN1E0
IN0E1
IN0E0
0000 0000
EPFR5
IN7E1
IN7E0
IN6E1
IN6E0
IN5E1
IN5E0
IN4E1
IN4E0
0000 0000
EPFR6
SOUT0E2
SOUT0E1
SOUT0E0
SCK0E2
SCK0E1
SCK0E0
SIN0E1
SIN0E0
0000 0000
EPFR7
Undefined
Undefined
Undefined
SOUT1E1
SOUT1E0
SCK1E1
SCK1E0
SIN1E
XXX0 0000
EPFR8
Undefined
Undefined
Undefined
SOUT2E1
SOUT2E0
SCK2E1
SCK2E0
SIN2E
XXX0 0000
EPFR9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR10
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR12
Undefined
Undefined
Undefined
SOUT6E1
SOUT6E0
SCK6E1
SCK6E0
SIN6E
EPFR13
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
UDIN1E1
UDIN1E0
Reserved
Reserved
EPFR18
Reserved
Reserved
Reserved
Reserved
EPFR19
Undefined
Undefined
Undefined
Undefined
EPFR20
Undefined
Undefined
TIOA1E1
TIOA1E0
TIOB1E
TIOA0E1
EPFR21
Undefined
Undefined
TIOA3E1
TIOA3E0
TIOB3E
TIOA2E1
EPFR22
Reserved
Reserved
Reserved
Reserved
Reserved
EPFR23
Reserved
Reserved
Reserved
Reserved
EPFR24
Reserved
Reserved
Reserved
EPFR25
Reserved
Reserved
Reserved
EPFR26
Reserved
Reserved
EPFR27
Reserved
Reserved
ADTRG0E2 ADTRG0E1 ADTRG0E0
XXX0 0000
0000 0000
XAE
XXXX 0001
TIOA0E0
TIOB0E
XX00 0000
TIOA2E0
TIOB2E
XX00 0000
Reserved
Reserved
Reserved
0000 0000
Reserved
Reserved
Reserved
Reserved
0000 0000
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR28
INT7E
INT6E
INT5E
INT4E
INT3E
INT2E
INT1E
INT0E
0000 0000
EPFR29
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR30
Undefined
Undefined
Undefined
Undefined
INT19E
INT18E
INT17E
INT16E
XXXX 0000
EPFR31
Undefined
INT23E1
INT23E0
INT22E1
INT22E0
INT21E1
INT21E0
INT20E
X000 0000
EPFR32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000 0000
EPFR33
Undefined
Undefined
TMO1E1
TMO1E0
TMI1E
TMO0E1
TMO0E0
TMI0E
XX00 0000
EPFR34
Undefined
TMO2E1
TMO2E0
TMI2E
FRCK1E1
FRCK1E0
FRCK0E1
FRCK0E0 X000 0000
EPFR35
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X000 0000
Attribute: R/W (Read/Write) for all the bits
X: Undefined
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MB91665 Series
<Notes>
•
Always write "0" to the reserved bits.
•
The pins that are specified as general-purpose ports in settings of the port function registers
(PFR0 to PFRH) are treated as general-purpose I/O ports regardless of the settings of these
registers.
•
When analog input is enabled through the settings of the A/D channel enable register (ADCHE),
input from ports is fixed at "0" regardless of the settings of these registers or port function
registers (PFR0 to PFRH).
•
A single pin cannot be used as an output pin for multiple peripheral functions. Also, a single
output function cannot be assigned to multiple pins.
•
A single pin can be used as an input pin for multiple peripheral functions. However, a single
input function cannot be assigned to multiple pins.
•
If multiple functions are assigned to one pin, the order of priority is as follows:
1. X0A/X1A
2. Multifunction serial interface
3. Base timer
4. 16-bit reload timer
5. 32-bit output compare
•
The input to a peripheral function is always connected to the pin assigned by an appropriate bit
in an extended port function register (EPFR0 to EPFR35). Use port input mode for input to a
peripheral function.
However, when input from the 10-bit A/D converter or output from the 8-bit D/A converter is
enabled, input is fixed at "0".
•
Before changing the pin to which peripheral function output is assigned through the settings of
this register, make the following settings:
- Set port input mode for the pin to which the function is currently assigned and the pin to which
it will be assigned.
- Disable the assigned peripheral function.
•
358
Before changing the pin to which a peripheral function input is assigned through the settings of
this register, disable the assigned peripheral function.
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CHAPTER 14 I/O Ports
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MB91665 Series
● Extended port function register 0 (EPFR0) to extended port function register 3
(EPFR3)
[bit5 to bit0]: OUTxE2 to OUTxE0 (Output compare output pin select bits)
2 output pins for 32-bit output compare are provided for each channel.
These bits select the pins used by ch.0 to ch.7 for 32-bit output compare. The OUT0E2 to OUT0E0 bits
correspond to ch.0, the OUT1E2 to OUT1E0 bits correspond to ch.1,..., and the OUT7E2 to OUT7E0
bits correspond to ch.7.
OUTxE2
0
OUTxE1
0
1
1
0
1
OUTxE0
Port Number
Pin Name
0
-
Output disabled
1
Port 0
OUTx pin
0
Port 1
OUTx_1 pin
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
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● Extended port function register 4 (EPFR4) to extended port function register 5
(EPFR5)
[bit7 to bit0]: INxE1, INxE0 (Input capture input pin select bits)
2 input pins for 32-bit input capture are provided for each channel (ch.0 to ch.3 only).
These bits select the pins used by ch.0 to ch.7 for 32-bit input capture. The IN0E1 and IN0E0 bits
correspond to ch.0, the IN1E1 and IN1E0 bits correspond to ch.1,..., and the IN7E1 and IN7E0 bits
correspond to ch.7.
INxE1
0
1
360
INxE0
Port Number
Pin Name
0
Port 0
INx pin
1
Port 1
INx_1 pin
0
-
Setting prohibited
1
-
Setting prohibited
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CHAPTER 14 I/O Ports
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MB91665 Series
● Extended port function register 6 (EPFR6)
[bit7 to bit5]: SOUT0E2 to SOUT0E0 (Serial interface ch.0 serial data pin select bits)
These bits select one pin from the SOUT0 and SOUT0_1 pins to assign the serial data output function of
multifunction serial interface ch.0 to the pin.
SOUT0E2
0
SOUT0E1
0
1
1
0
1
SOUT0E0
Port Number
Pin Name
0
-
Output disabled
(Input: SOUT0 pin
(Port 0))
1
Port 0
SOUT0 pin
0
Port 1
SOUT0_1 pin
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The pins selected by the following bits must be assigned to the same port number:
- SOUT0E2 to SOUT0E0 (serial data output pins)
- SCK0E2 to SCK0E0 (serial clock I/O pins)
- SIN0E1, SIN0E0 (serial data input pins)
•
The serial data pins operate as input pins according to peripheral function settings. The input of
a peripheral function is always connected to the selected pin, and if these bits are set to "000",
the input is connected to the SOUT0 pin (port 0).
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[bit4 to bit2]: SCK0E2 to SCK0E0 (Serial interface ch.0 serial clock pin select bits)
These bits select one pin from the SCK0 and SCK0_1 pins to assign the serial clock I/O function of
multifunction serial interface ch.0 to the pin.
SCK0E2
0
SCK0E1
0
1
1
0
1
SCK0E0
Port Number
Pin Name
0
-
Output disabled
(Input: SCK0 pin
(Port 0))
1
Port 0
SCK0 pin
0
Port 1
SCK0_1 pin
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The pins selected by the following bits must be assigned to the same port number:
- SOUT0E2 to SOUT0E0 (serial data output pins)
- SCK0E2 to SCK0E0 (serial clock I/O pins)
- SIN0E1, SIN0E0 (serial data input pins)
•
362
The input of a peripheral function is always connected to the selected pin, and if these bits are
set to "000", the input is connected to the SCK0 pin (port 0).
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CHAPTER 14 I/O Ports
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MB91665 Series
[bit1, bit0]: SIN0E1, SIN0E0 (Serial interface ch.0 serial data input select bits)
These bits select one pin from the SIN0 and SIN0_1 pins to assign the serial data input function of
multifunction serial interface ch.0 to the pin.
SIN0E1
0
1
SIN0E0
Port Number
Pin Name
0
Port 0
SIN0 pin
1
Port 1
SIN0_1 pin
0
-
Setting prohibited
1
-
Setting prohibited
<Note>
•
The pins selected by the following bits must be assigned to the same port number:
- SOUT0E2 to SOUT0E0 (serial data output pins)
- SCK0E2 to SCK0E0 (serial clock I/O pins)
- SIN0E1, SIN0E0 (serial data input pins)
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● Extended port function register 7 (EPFR7), extended port function register 8
(EPFR8)
[bit4, bit3]: SOUTxE1, SOUTxE0 (Serial interface ch.1, ch.2 serial data pin select bits)
2 serial data output pins are provided for each channel in multifunction serial interface ch.1, ch.2.
These bits select one of the pins to assign the serial data output function to it for each channel. The
SOUT1E1 and SOUT1E0 bits correspond to ch.1, the SOUT2E1 and SOUT2E0 bits correspond to ch.2.
SOUTxE1
SOUTxE0
Port Number
Pin Name
0
0
-
Output disabled (Input: SOUTx pin
(Port 0))
0
1
Port 0
SOUTx pin
1
0
Port 1
SOUTx_1 pin
1
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The pins used for the same channel (the pins selected by the following bits) must be assigned
to the same port number:
- SOUTxE1, SOUTxE0 (serial data output pins)
- SCKxE1, SCKxE0 (serial clock I/O pins)
- SINxE (serial data input pin)
•
364
Serial data pins operate as input pins according to peripheral function settings. The input of a
peripheral function is always connected to the selected pin, and if these bits are set to "00", the
input is connected to the SOUTx pin (port 0).
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CHAPTER 14 I/O Ports
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MB91665 Series
[bit2, bit1]: SCKxE1, SCKxE0 (Serial interface ch.1, ch.2 serial clock pin select bits)
2 serial clock I/O pins are provided for each channel in multifunction serial interface ch.1, ch.2.
These bits select one of the pins to assign the serial clock I/O function to it for each channel. The
SCK1E1 and SCK1E0 bits correspond to ch.1, the SCK2E1 and SCK2E0 bits correspond to ch.2.
SCKxE1
SCKxE0
Port Number
Pin Name
0
0
-
Output disabled (Input: SCKx pin
(Port 0))
0
1
Port 0
SCKx pin
1
0
Port 1
SCKx_1 pin
1
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The pins used for the same channel (the pins selected by the following bits) must be assigned
to the same port number:
- SOUTxE1, SOUTxE0 (serial data output pins)
- SCKxE1, SCKxE0 (serial clock I/O pins)
- SINxE (serial data input pin)
•
The input of the serial clock is always connected to the selected pin, and if these bits are set to
"00", the input is connected to the SCKx pin (port 0).
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MB91665 Series
[bit0]: SINxE (Serial interface ch.1, ch.2 serial data input select bits)
2 serial data input pins are provided for each channel in multifunction serial interface ch.1, ch.2.
These bits select one of the pins to assign the serial data input function to it for each channel. The SIN1E
bit corresponds to ch.1, the SIN2E bit corresponds to ch.2.
SINxE
Port Number
Pin Name
0
Port 0
SINx pin
1
Port 1
SINx_1 pin
<Note>
•
The pins used for the same channel (the pins selected by the following bits) must be assigned
to the same port number:
- SOUT0E2 to SOUT0E0 (serial data output pins)
- SCK0E2 to SCK0E0 (serial clock I/O pins)
- SIN0E1, SIN0E0 (serial data input pins)
● Extended port function register 12 (EPFR12)
[bit4, bit3]: SOUTxE1, SOUTxE0 (Serial interface ch.6 serial data pin select bits)
These bits select whether to enable the serial data output pin of multifunction serial interface ch.6. The
SOUT6E1 and SOUT6E0 bits correspond to ch.6.
366
SOUTxE1
SOUTxE0
Port Number
Pin name
0
0
-
Output disabled (Input: SOUTx pin (Port 0))
0
1
Port 0
SOUTx pin
1
0
-
Setting prohibited
1
1
-
Setting prohibited
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CHAPTER 14 I/O Ports
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MB91665 Series
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
Serial data pins operate as input pins according to peripheral function settings. The input of a
peripheral function is always connected to the selected pin, and if these bits are set to "00", the
input is connected to the SOUTx pin (port 0).
[bit2, bit1]: SCKxE1, SCKxE0 (Serial interface ch.6 serial clock pin select bits)
These bits select whether to enable the serial clock I/O pin of multifunction serial interface ch.6. The
SCK6E1 and SCK6E0 bits correspond to ch.6.
SCKxE1
SCKxE0
Port Number
Pin name
0
0
-
Output disabled (Input: SCKx pin (Port 0))
0
1
Port 0
SCKx pin
1
0
-
Setting prohibited
1
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The input of the serial clock is always connected to the selected pin, and if these bits are set to
"00", the input is connected to the SCKx pin (port 0).
[bit0]: SINxE (Serial interface ch.6 serial data input select bit)
This bit selects one pin to assign it as the serial data input pin of multifunction serial interface ch.6.
Always set "0" to this bit.
SINxE
CM71-10158-1E
Port Number
Pin name
0
Port 0
SINx pin
1
-
Setting prohibited
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MB91665 Series
● Extended port function register 18 (EPFR18)
[bit3, bit2]: UDIN1E1, UDIN1E0 (Up/Down counter input pin select bits)
2 pins are provided for use in ch.1 of the 16-bit up/down counter.
These bits select one of the pins as the pin used in the 16-bit up/down counter of ch.1.
368
UDINxE1
UDINxE0
Port number
Pin name
0
0
Port 0
AIN1/BIN1/ZIN1 pins
0
1
Port 1
AIN1_1/BIN1_1/ZIN1_1 pins
1
0
-
Setting prohibited
1
1
-
Setting prohibited
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CHAPTER 14 I/O Ports
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MB91665 Series
● Extended port function register 19 (EPFR19)
[bit3 to bit1]: ADTRG0E2 to ADTRG0E0 (A/D conversion activation trigger pin select bits)
These bits select the pins to be assigned as external trigger input pins for 10-bit A/D converter.
ADTRG0E2
ADTRG0E1
ADTRG0E0
Port Number
0
0
0
Port 0
ADTRG0 pin
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
1
1
0
1
Pin Name
[bit0]: XAE (Clock oscillation I/O pin enable bit)
This bit cuts off port input when the low-speed clock oscillation function is enabled. Always set XAE = 1
when the low-speed clock oscillation function is enabled.
Written Value
Explanation
0
Enables port input.
1
Disables port input.
<Note>
•
These pins can be used as follows when the low-speed oscillation function has been disabled
by this bit:
- General-purpose port
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● Extended port function register 20 (EPFR20) to extended port function register
21 (EPFR21)
[bit5, bit4, bit2, bit1]: TIOAxE1, TIOAxE0 (Base timer ch.0 to ch.3 pin select bits)
2 output pins are provided for each channel in base timer ch.0 to ch.3.
These bits select one of the pins as the pin used by each channel in base timer ch.0 to ch.3. The TIOA0E1
and TIOA0E0 bits correspond to ch.0, the TIOA1E1 and TIOA1E0 bits correspond to ch.1,..., and the
TIOA3E1 and TIOA3E0 bits correspond to ch.3.
TIOAxE1
TIOAxE0
Port Number
Pin Name
0
0
-
Output disabled (Odd-numbered
channel input: TIOAx pin (Port 0))
0
1
Port 0
TIOAx pin
1
0
Port 1
TIOAx_1 pin
1
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The pins used for the same channel (the pins selected by the following bits) must be assigned
to the same port number:
- TIOAxE1, TIOAxE0 (base timer output pins)
- TIOBxE (base timer input pin)
•
The base timer output pins (TIOAx pins) of the odd-numbered channels (TIOAx pin) operate as
input pins according peripheral function settings. The input of a peripheral function is always
connected to the selected pin. If these bits are set to "00", the input is connected to the TIOAx
pin (port 0).
[bit3, bit0]: TIOBxE (Base timer ch.0 to ch.3 pin input select bits)
2 input pins are provided for each channel in base timer ch.0 to ch.3.
These bits select one of the pins as the pin used by each channel in base timer ch.0 to ch.3. The TIOB0E
bit corresponds to ch.0, the TIOB1E bit corresponds to ch.1,..., and the TIOB3E bit corresponds to ch.3.
TIOBxE
370
Port Number
Pin Name
0
Port 0
TIOBx pin
1
Port 1
TIOBx_1 pin
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MB91665 Series
<Note>
•
The pins used for the same channel (the pins selected by the following bits) must be assigned
to the same port number:
- TIOAxE1, TIOAxE0 (base timer output pins)
- TIOBxE (base timer input pin)
● Extended port function register 28 (EPFR28)
[bit7 to bit4]: INT7E to INT4E (External interrupt request pin enable bits)
These bits select one of the pins as that used by each channel in external interrupt request ch.4 to ch.7.
The INT7E bit corresponds to ch.7, the INT6E bit corresponds to ch.6,... and the INT4E bit corresponds
to ch.4.
INTxE
Port Number
Pin name
0
Port 0
INTx pin
1
-
Setting prohibited
[bit3, bit2]: INT3E, INT2E (External interrupt request pin enable bits)
Two input pins are provided for each channel in external interrupt request ch.2, ch.3.
These bits select one of the pins as that used by each channel in external interrupt request ch.2, ch.3. The
INT2E bit corresponds to ch.2, the INT3E bit corresponds to ch.3.
INTxE
Port number
Pin name
0
Port 0
INTx pin
1
Port 1
INTx_1 pin
[bit1, bit0]: INT1E, INT0E (External interrupt request pin enable bits)
The setting is prohibited.
● Extended port function register 30 (EPFR30)
[bit3 to bit0]: INT19E to INT16E (External interrupt request pin enable bits)
These bits select whether to enable the input pins of each channel in external interrupt request ch.16 to
ch.19.
The INT16E bit corresponds to ch.16, the INT17E bit corresponds to ch.17,..., and the INT19E bit
corresponds to ch.19.
INTxE
CM71-10158-1E
Port Number
Pin Name
0
Port 0
INTx pin
1
-
Setting prohibited
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MB91665 Series
● Extended port function register 31 (EPFR31)
[bit6 to bit1]: INT23E1, INT23E0 to INT21E1, INT21E0 (External interrupt request pin
enable bits)
These bits select whether to enable the input pins of each channel in external interrupt request ch.21 to
ch.23.
The INT21E1 and INT21E0 bits correspond to ch.21, the INT22E1 and INT22E0 bits correspond to
ch.22, and the INT23E1 and INT23E0 bits correspond to ch.23.
INTxE1
INTxE0
Port
Number
Pin Name
0
0
Port 0
INTx pin
0
1
-
Setting prohibited
1
0
-
Setting prohibited
1
1
-
Setting prohibited
[bit0]: INT20E (External interrupt request pin enable bit)
This bit select whether to enable the input pin of external interrupt request ch.20.
INT20E
372
Port Number
Pin Name
0
Port 0
INT20 pin
1
-
Setting prohibited
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CHAPTER 14 I/O Ports
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MB91665 Series
● Extended port function register 33 (EPFR33)
[bit5, bit4, bit2, bit1]: TMOxE1, TMOxE0 (Reload timer ch.0 to ch.1 output pin select bits)
2 output pins are provided for each channel in 16-bit reload timer ch.0 and ch.1.
These bits select one of the pins as the pin used by each of 16-bit reload timer ch.0 and ch.1. The
TMO0E1 and TMO0E0 bits correspond to ch.0, and the TMO1E1 and TMO1E0 bits correspond to ch.1.
TMOxE1
0
1
TMOxE0
Port Number
Pin Name
0
-
Output disabled
1
Port 0
TMOx pin
0
Port 1
TMOx_1 pin
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The pins used for the same channel (the pins selected by the following bits) must be assigned
to the same port number:
- TMOxE1, TMOxE0 (16-bit reload timer output pins)
- TMIxE (16-bit reload timer input pin)
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MB91665 Series
[bit3, bit0]: TMIxE (Reload timer ch.0 to ch.1 input pin select bits)
2 input pins are provided for each channel in 16-bit reload timer ch.0 and ch.1.
These bits select one of the pins as the pin used by each of 16-bit reload timer ch.0 and ch.1. The TMI0E
bit corresponds to ch.0, and the TMI1E bit corresponds to ch.1.
TMIxE
Port Number
Pin Name
0
Port 0
TMIx pin
1
Port 1
TMIx_1 pin
<Note>
•
The pins used for the same channel (the pins selected by the following bits) must be assigned
to the same port number:
- TMOxE1, TMOxE0 (16-bit reload timer output pins)
- TMIxE (16-bit reload timer input pin)
● Extended port function register 34 (EPFR34)
[bit6, bit5]: TMO2E1, TMO2E0 (Reload timer ch.2 output pin select bits)
2 output pins are provided for 16-bit reload timer ch.2.
This bit selects one of the pins as the pin used by 16-bit reload timer ch.2.
TMO2E1
0
1
TMO2E0
Port Number
Pin Name
0
-
Output disabled
1
Port 0
TMO2 pin
0
Port 1
TMO2_1 pin
1
-
Setting prohibited
<Notes>
•
The corresponding pins can be used as output pins for other functions when output has been
disabled by these bits.
•
If the corresponding pins are not used as output pins for other functions when output has been
disabled by these bits, the pins can be used as follows:
- Other than external bus multiplexed pin: General-purpose port
- External bus multiplexed pin: External bus
•
The pins selected by the following bits must be assigned to the same port number:
- TMO2E1, TMO2E0 (16-bit reload timer output pins)
- TMI2E (16-bit reload timer I/O pin)
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14.4
MB91665 Series
[bit4]: TMI2E (Reload timer ch.2 input pin select bit)
2 input pins are provided for 16-bit reload timer ch.2.
This bit selects one of the pins as the pin used by 16-bit reload timer ch.2.
TMI2E
Port Number
Pin Name
0
Port 0
TMIx pin
1
Port 1
TMIx_1 pin
<Note>
•
The pins selected by the following bits must be assigned to the same port number:
- TMO2E1, TMO2E0 (16-bit reload timer output pins)
- TMI2E (16-bit reload timer I/O pin)
[bit3 to bit0]: FRCKxE1, FRCKxE0 (Free-run timer ch.0 and ch.1 input pin select bits)
These bits select whether to enable the input pins of each channel in 32-bit free-run timer ch.0 and ch.1.
FRCKxE1
FRCKxE0
0
0
Port 0
FRCKx pin
1
-
Setting prohibited
0
-
Setting prohibited
1
-
Setting prohibited
1
CM71-10158-1E
Port Number
Pin Name
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CHAPTER 14 I/O Ports
14.4
14.4.4
MB91665 Series
Port Data Registers (PDR0 to PDRK)
These registers store I/O data.
The values read from or written to these registers vary depending on the settings of a port data direction
register (DDR0 to DDRK) and port function register (PFR0 to PFRH). For details of a read value or
written value, see "14.4.1 Port Data Direction Registers (DDR0 to DDRK)".
Figure 14.4-4 shows the bit configuration of the port data registers (PDR0 to PDRK).
Figure 14.4-4 Bit configuration of the port data registers (PDR0 to PDRK)
bit
7
6
5
4
3
2
1
0
Initial value
Attribute
PDR0
PDR07
PDR06
PDR05
PDR04
PDR03
PDR02
PDR01
PDR00
XXXX XXXX
R/W
PDR1
PDR17
PDR16
PDR15
PDR14
PDR13
PDR12
PDR11
PDR10
XXXX XXXX
R/W
PDR2
PDR27
PDR26
PDR25
PDR24
PDR23
PDR22
PDR21
PDR20
XXXX XXXX
R/W
PDR5
PDR57
PDR56
PDR55
PDR54
PDR53
PDR52
PDR51
PDR50
XXXX XXXX
R/W
PDR6
Reserved
Reserved
Reserved
Reserved
PDR61
PDR60
XXXX XXXX
R/W
PDR7
PDR77
PDR76
PDR75
PDR74
PDR73
PDR72
PDR71
PDR70
XXXX XXXX
R/W
PDR8
Reserved
Reserved
Reserved
Reserved
PDR83
PDR82
PDR81
PDR80
XXXX XXXX
R/W
PDRH
Undefined Undefined Undefined Undefined
PDRH3
PDRH2 Reserved Reserved XXXX XXXX
R/W
PDRK
Undefined Undefined Undefined Undefined
Reserved Reserved PDRK1
Reserved Reserved
PDRK0 XXXX XXXX
R/W
R/W: Read/Write
X: Undefined
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CHAPTER 14 I/O Ports
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MB91665 Series
<Notes>
•
If these registers are read with a read-modify-write instruction, the value of these registers is
read regardless of the settings of the following registers:
- Port data direction registers (DDR0 to DDRK)
- Port function registers (PFR0 to PFRH)
•
The value of these registers is not initialized even when this device is reset.
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CHAPTER 14 I/O Ports
14.4
14.4.5
MB91665 Series
Pull-up Resistor Control Registers (PCR0 to PCR8)
These registers set pull-up resistors. One bit is provided for each of the pins for which pull-up
resistors can be set, and a pull-up resistor can be set in the corresponding pin by writing "1" to the bit
corresponding to the pin.
Figure 14.4-5 shows the bit configuration of the pull-up resistor control registers (PCR0 to PCR8).
Figure 14.4-5 Bit configuration of the pull-up resistor control registers (PCR0 to PCR8)
bit
7
6
5
4
3
2
1
0
Initial value
Attribute
PCR0
PCR07
Reserved
Reserved
Reserved
PCR03
Reserved
PCR01
Reserved 0000 0000
R/W
PCR1
PCR17
PCR16
PCR15
PCR14
PCR13
Reserved
Reserved
Reserved 0000 0000
R/W
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
0000 0000
R/W
PCR6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCR61
PCR60
0000 0000
R/W
PCR7
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
0000 0000
R/W
PCR8
Reserved
Reserved
Reserved
Reserved
PCR83
PCR82
PCR81
PCR80
0000 0000
R/W
R/W: Read/Write
X: Undefined
Each bit in the pull-up resistor control registers specifies whether a pull-up resistor is set for the assigned
pin.
When a pull-up this register is set, the pull-up resistor is connected to the pin.
Written Value
Explanation
0
The pull-up resistor is not set.
1
The pull-up resistor is set.
<Note>
•
Pull-up resistors are not set in the following cases regardless of the settings of these registers:
- In port output (in peripheral function output)
- In stop mode (with Hi-Z selected)
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CHAPTER 14 I/O Ports
14.4
MB91665 Series
14.4.6
A/D Channel Enable Register (ADCHE)
This register specifies whether to input analog signals from the AN0 to AN11 pins.
One bit is provided for each of the pins for which A/D analog input can be set, and A/D analog input
can be enabled for the corresponding pin by writing "1" to the bit corresponding to the pin.
Figure 14.4-6 shows the bit configuration of the A/D channel enable register (ADCHE).
Figure 14.4-6 Bit configuration of the A/D channel enable register (ADCHE)
bit
31
Attribute
Initial value
24
23
18
17
12
11
0
Reserved
ADE23 to ADE18
Reserved
ADE11 to ADE0
R/W
R/W
R/W
R/W
--------
111111
------
1111 1111 1111
R/W: Read/Write
[bit23 to bit18, bit11 to bit0]: ADE23 to ADE18, ADE11 to ADE0
(Analog input enable bits)
These bits enables/disables analog signal input from the pin corresponding to the bit.
Written Value
Explanation
0
Disables analog signal input.
1
Enables analog signal input.
The ADE11 bit corresponds to ch.11, the ADE10 bit corresponds to ch.10, ..., the ADE1 bit corresponds
to ch.1, and the ADE0 bit corresponds to ch.0.
For ADE23 to ADE18, set 0 to these bits to use Port 1 (TMIx_1,TMOx_1) of the reload timer I/O.
<Notes>
•
To use any of the AN0 to AN11 pins as analog signal input pins of the 10-bit A/D converter, be
sure to write "1" to the bits corresponding to the channels.
•
When analog input is enabled through the settings of this register, input from ports and
peripheral functions is fixed at "0" and output to them is fixed at Hi-Z regardless of the settings
of the port function registers (PFR0 to PFRH) or extended port function registers (EPFR0 to
EPFR35).
•
For MB91F668 (48 pins), there is no AN10 and AN11 pins.
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CHAPTER 14 I/O Ports
14.4
14.4.7
MB91665 Series
N-ch Open Drain Control Register (NDE0, NDE1)
These registers are N-ch open drain control registers. For the pins that can be set for N-ch open drain
control (P00, P02, P04, P06, P10, P12, P20, P21, P22, P24, P25, P26, and P27), N-ch open drain
control can be set to each pin by writing "1" to the corresponding pins.
Figure 14.4-7 shows the bit configuration of N-ch open drain control registers (NDE0, NDE1).
Figure 14.4-7 Bit configuration of N-ch open drain control registers (NDE0, NDE1)
bit
7
6
5
4
3
2
1
0
Initial value
Attribute
NDE0
P27NDE
P26NDE
P25NDE
P24NDE
-
P22NDE
P21NDE
P20NDE
00000000
R/W
NDE1
-
-
P12NDE
P10NDE
P06NDE
P04NDE
P02NDE
P00NDE
00000000
R/W
R/W: Read/Write
Specify whether to set N-ch open drain control to the pins assigned by each bit.
Setting value
Explanation
0
CMOS output
1
N-ch open drain output
* This setting is valid when the general port is output, and the peripheral function is output.
<Note>
•
This register does not exist in MB91V650. CMOS output is fixed.
•
P05, P11, and P23 are 5V tolerance pins, but the peripheral functions are input pins.
Therefore, they are not corresponded to open drain control.
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MB91665 Series
Table 14.4-3 Open drain control supported I/O ports
Pin name
CM71-10158-1E
Setting bit
MB91F668(48pins) MB91F669(64pins)
P00/D00/TIOA0/SOUT0_1/IN0
P00NDE
❍
❍
P02/D02/TIOA1/SCK0_1/IN2
P02NDE
❍
❍
P04/D04/TIOA2/SOUT1/IN4
P04NDE
❍
❍
P06/D06/TIOA3/SCK1/IN6
P06NDE
❍
❍
P10/D08/SOUT2/INT0
P10NDE
❍
❍
P12/D10/SCK2/INT2
P12NDE
❍
❍
P20/A00/TMO1_1/A16
P20NDE
-
❍
P21/A01/TMO2_1/A17
P21NDE
-
❍
P22/A02/TIOA0_1/SCK2_1/A18
P22NDE
-
❍
P24/A04/OUT0/A20
P24NDE
-
❍
P25/A05/OUT1/A21
P25NDE
-
❍
P26/A06/OUT2/A22
P26NDE
-
❍
P27/A07/OUT3/A23
P27NDE
-
❍
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CHAPTER 14 I/O Ports
14.4
14.4.8
MB91665 Series
External Bus Address Select Register (EXBS)
This register selects whether to use the external bus address as A00 to A07 (split bus) or A16 to A23
(multiplex bus) when selecting the external bus address in PFR2 register.
Figure 14.4-8 shows the bit configuration of the external bus address select register (EXBS).
Figure 14.4-8 Bit configuration of external bus address select register (EXBS)
bit
EXBS
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
MSS
Initial value
Attribute
---- ---0
R/W
Address data
split bus (MSS=0*)
Address data
multiplex bus (MSS=1*)
P20/A00/TMO1_1/A16
A00
A16
P21/A01/TMO2_1/A17
A01
A17
P22/A02/TIOA0_1/SCK2_1/A18
A02
A18
P23/A03/TIOB0_1/A19
A03
A19
P24/A04/OUT0/A20
A04
A20
P25/A05/OUT1/A21
A05
A21
P26/A06/OUT2/A22
A06
A22
P27/A07/OUT3/A23
A07
A23
Pin name
* MSS bit is valid when the external function is selected in EPFR register.
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CHAPTER 14 I/O Ports
14.4
MB91665 Series
14.4.9
FR Identification Data Register (FRID)
This register identifies the product by software.
Figure 14.4-9 shows the bit configuration of FR identification data register (FRID).
Figure 14.4-9 Bit configuration of FR identification data register (FRID)
bit 31
0 Initial value
FRID
Attribute
*
R
R: Read only
*: The initial values are as follows.
Product name
Bit31 to Bit29
Bit28
Bit27 to Bit16
Bit15 to Bit0
Reserved bit
MASK:0
FLASH:1
Product type
Reserved bit
MB91F669(64pins)
100
1
0110 0110 1001 (669H)
XXXXXXXXXXXXXXXX
MB91F668(48pins)
100
1
0110 0110 1000 (668H)
XXXXXXXXXXXXXXXX
* The value for MB91V650 is 8650020FH.
<Notes>
•
For an evaluation product, writing is enabled in emulator mode only.
•
Be sure to access this register in units of words.
•
This register is initialized by tool reset (TRSTX).
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CHAPTER 14 I/O Ports
14.5
MB91665 Series
14.5 Notes on Use
Note the following points about using I/O ports:
•
The order of priority of registers is as follows:
1. A/D channel enable register (ADCHE)
2. Port function registers (PFR0 to PFRH)
3. Extended port function registers (EPFR0 to EPFR35)
If settings are inconsistent, the setting with the higher order of priority is used.
•
When analog input is enabled by the A/D channel enable register (ADCHE), input from ports is fixed at
"0" and output from ports is fixed at Hi-Z.
•
If multiple functions are assigned to one pin, the order of priority is as follows:
1. X0A/X1A
2. Multifunction serial interface
3. Base timer
4. 16-bit reload timer
5. 32-bit output compare
•
A single pin cannot be used as an output pin for multiple peripheral functions. Also, a single output
function cannot be assigned to multiple pins.
•
A single pin can be used as an input pin for multiple peripheral functions. However, a single input
function cannot be assigned to multiple pins.
•
If Hi-Z is set to a pin in standby mode (stop mode/watch mode/main timer mode), input is fixed at "0".
However, input is not fixed at "0" for external interrupt requests whose generation is enabled and it can
be used.
•
Before changing the pin to which a peripheral function output is assigned, set port input mode for the
relevant pins (the pin to which the function is currently assigned and the pin to which it will be
assigned) and disable the assigned peripheral function.
•
Before changing the pin to which a peripheral function input is assigned, disable the assigned
peripheral function.
•
To use PK0 and PK1 as low-speed oscillation pins, set the I/O directions of the ports to input
(DDRK0 = 0, DDRK1 = 0) in port data direction register K (DDRK).
•
The pin to which peripheral functions are assigned can be set, if the peripheral functions can be
assigned to more than one pin, and peripheral function output from the pin can be enabled/disabled.
However, if the peripheral function has more than one I/O, each I/O must be set to individual ports
belonging to the same group.
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CHAPTER 14 I/O Ports
14.5
MB91665 Series
Example: Ch.1 multifunction serial interface settings
Serial Data
Output
Serial Clock I/O
SOUT1 pin (Port 0)
SCK1 pin (Port 0)
SCK1_1 pin (Port 1)
Serial Data
Input
Effective port
SIN1 pin (Port 0)
Port 0
SIN1_1 pin (Port 1)
Setting prohibited
SIN1 pin (Port 0)
SIN1_1 pin (Port 1)
SOUT1_1 pin (Port 1)
SCK1 pin (Port 0)
SIN1 pin (Port 0)
SIN1_1 pin (Port 1)
SCK1_1 pin (Port 1)
SIN1 pin (Port 0)
SIN1_1 pin (Port 1)
CM71-10158-1E
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Port 1
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14.5
386
MB91665 Series
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CM71-10158-1E
CHAPTER 15 External Interrupt
Controllers
This chapter explains the functions and operations of
external interrupt controllers.
15.1
15.2
15.3
15.4
15.5
CM71-10158-1E
Overview
Configuration
Pins
Registers
Explanation of Operations and Setting Procedure
Examples
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CHAPTER 15 External Interrupt Controllers
15.1
MB91665 Series
15.1 Overview
The external interrupt controllers detect edges/levels in external interrupt signals, and they control
external interrupt requests.
This series has 16 built-in signal input pins for external interrupts.
■ Overview
An external interrupt controller generates an external interrupt request when it detects a preset edge/level
in an external interrupt signal.
The edge/level to be detected can be selected from the following 4 types:
•
"H" level
•
"L" level
•
Rising edge
•
Falling edge
Also, external interrupt requests can be used for a return from sleep mode or standby mode (watch mode
or stop mode).
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CHAPTER 15 External Interrupt Controllers
15.2
MB91665 Series
15.2 Configuration
This section shows the configuration of an external interrupt controller.
■ Block diagram of an external interrupt controller
Figure 15.2-1 is a block diagram of an external interrupt controller.
Figure 15.2-1 Block diagram of an external interrupt controller
Peripheral bus
16
8
8
Enable interrupt request register
(ENIR0, ENIR2)
7
6
5
4
3
2
1
0
External interrupt request
register
(EIRR0, EIRR2)
External interrupt request
level register
(ELVR0, ELVR2)
7
15 14
6
5
4
3
2
1
0
8
1
0
Edge/Level detection
circuit
16
INT0 to INT7,
INT16 to INT23
Interrupt
request
16
•
External interrupt request level register (ELVR0, ELVR2)
This register sets the edge/level used to determine whether a signal input to the INT0 to INT7, INT16
to INT23 pins is for an external interrupt request.
•
External interrupt request register (EIRR0, EIRR2)
This register maintains the states of interrupt sources (indicating which pins have generated external
interrupt requests).
•
Enable interrupt request register (ENIR0, ENIR2)
This register specifies whether external interrupt requests are enabled/disabled.
•
Edge/Level detection circuit
This circuit detects edges/levels in signals input to the INT0 to INT7, INT16 to INT23 pins.
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■ Clocks
Table 15.2-1 lists the clock used by the external interrupt controllers.
Table 15.2-1 Clock used by the external interrupt controllers
Clock Name
Operation clock
390
Description
Peripheral clock (PCLK)
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CHAPTER 15 External Interrupt Controllers
15.3
MB91665 Series
15.3 Pins
This section explains the pins of the external interrupt controllers.
■ Overview
The external interrupt controllers have the following pins:
•
INT0 to INT7, INT16 to INT23 pins
These are external interrupt signal input pins.
These pins are multiplexed pins. For details of using the INT0 to INT7, INT16 to INT23 pins of the
external interrupt controllers, see "2.4 Setting Method for Pins".
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15.4
MB91665 Series
15.4 Registers
This section explains the configurations and functions of the registers for the external interrupt
controllers.
■ List of registers for the external interrupt controllers
Table 15.4-1 lists the registers for the external interrupt controllers.
Table 15.4-1 Registers for the external interrupt controllers
Channel
Common
392
Abbreviated
Register Name
Register Name
Reference
ELVR0
External interrupt request level register 0
15.4.1
EIRR0
External interrupt request register 0
15.4.2
ENIR0
Enable interrupt request register 0
15.4.3
ELVR2
External interrupt request level register 2
15.4.1
EIRR2
External interrupt request register 2
15.4.2
ENIR2
Enable interrupt request register 2
15.4.3
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CHAPTER 15 External Interrupt Controllers
15.4
MB91665 Series
15.4.1
External Interrupt Request Level Registers (ELVR0,
ELVR2)
These registers set the edges/levels to be detected for external interrupt requests.
Figure 15.4-1 shows the bit configuration of the external interrupt request level registers (ELVR0,
ELVR2).
Figure 15.4-1 Bit configuration of the external interrupt request level registers (ELVR0, ELVR2)
External interrupt request level register 0 (ELVR0)
bit
Attribute
Initial value
bit
Attribute
Initial value
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
External interrupt request level register 2 (ELVR2)
bit
Attribute
Initial value
bit
Attribute
Initial value
15
14
13
12
11
10
9
8
LB23
LA23
LB22
LA22
LB21
LA21
LB20
LA20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
LB19
LA19
LB18
LA18
LB17
LA17
LB16
LA16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
R/W: Read/Write
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LB23 to LB0, LA23 to LA0 (Detection condition selection bits)
These bits select the edges/levels to be detected in signals for external interrupt requests. An external
interrupt request is recognized upon detection of the edge/level selected by one of these bits.
The LB0 to LB23 bits correspond to the INT0 to INT7, INT16 to INT23 bits, and the LA0 to LA23 bits
similarly correspond to the INT0 to INT7, INT16 to INT23 bits. For example, the INT0 pin is set with the
LB0 and LA0 bits.
LB23 to LB0
LA23 to LA0
Explanation
0
0
"L" level detection
0
1
"H" level detection
1
0
Rising edge detection
1
1
Falling edge detection
To use an external interrupt request to return from standby mode, see "15.5.2 Return from Standby
Mode".
<Notes>
•
For detection of an edge/level specified by these bits, the pulse width of the signal must be 3T
or higher (T: Peripheral clock (PCLK) period). If a signal with a narrower pulse width is input,
this device may not operate correctly.
•
While "L" level detection/"H" level detection is set as the detection condition, the state of an
interrupt source is maintained in the external interrupt request registers (EIRR0, EIRR2) even if
the corresponding external interrupt request is canceled. Therefore, the external interrupt
request remains at the interrupt controller, to which it has been output. To cancel the external
interrupt request output to the interrupt controller, set "0" in the corresponding bit in the external
interrupt request register (EIRR0, EIRR2).
However, even when the external interrupt request register (EIRR0, EIRR2) is cleared, the
external interrupt request remains as is while any signals at the effective level are input from the
INT0 to INT7, INT16 to INT23 pins.
For diagrams illustrating operations that maintain the state of an interrupt source or clear an
interrupt source, see "■ Canceling an external interrupt request" of "15.5 Explanation of
Operations and Setting Procedure Examples".
•
If the detection condition is changed by rewriting these bits, an incorrect interrupt source may be
generated. To prevent incorrect interrupt sources from being generated when the detection
condition has been changed, perform the following operations:
1. Read the external interrupt request level register (ELVR0, ELVR2).
2. Write "0" in the external interrupt request register (EIRR0, EIRR2) to clear the interrupt
source.
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CHAPTER 15 External Interrupt Controllers
15.4
MB91665 Series
15.4.2
External Interrupt Request Registers (EIRR0, EIRR2)
These registers maintain the states of interrupt sources of external interrupt requests (indicating which
pins have generated the external interrupt requests).
Figure 15.4-2 shows the bit configuration of the external interrupt request registers (EIRR0, EIRR2).
Figure 15.4-2 Bit configuration of the external interrupt request registers (EIRR0, EIRR2)
External interrupt request register 0 (EIRR0)
bit
Attribute
Initial value
7
6
5
4
3
2
1
0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
External interrupt request register 2 (EIRR2)
bit
Attribute
Initial value
7
6
5
4
3
2
1
0
ER23
ER22
ER21
ER20
ER19
ER18
ER17
ER16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
R/W: Read/Write
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ER23 to ER16, ER7 to ER0 (External interrupt request flag bits)
These bits indicate that external interrupt requests have been detected.
The ER0 to ER7, ER16 to ER23 bits correspond to the INT0 to INT7, INT16 to INT23 pins. For example,
the ER0 bit is used to detect external interrupt requests from the INT0 pin, and the ER23 bit is used to
detect external interrupt requests from the INT23 pin.
An external interrupt request is generated when "1" is set in any of the EN0 to EN7, EN16 to EN23 bits of
an enable interrupt request register (ENIR0, ENIR2) and the corresponding bit among the ER0 to ER7,
ER16 to ER23 bits becomes "1".
ER23 to ER16,
ER7 to ER0
In Case of Reading
In Case of Writing
0
No external interrupt request has been
detected.
The interrupt source is cleared.
1
An external interrupt request has been
detected.
Ignored
<Notes>
396
•
When a read-modify-write instruction is used, "1" is read.
•
As long as a signal at the effective level is being input from any of the INT0 to INT7, INT16 to
INT23 pins when "L" level detection/"H" level detection has been set as the detection condition
by an external interrupt request level register (ELVR0, ELVR2), "1" is set in the corresponding
bit among the ER23 to ER0 bits even after the bit is cleared.
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CHAPTER 15 External Interrupt Controllers
15.4
MB91665 Series
15.4.3
Enable Interrupt Request Registers (ENIR0, ENIR2)
These registers enable/disable external interrupt requests.
Figure 15.4-3 shows the bit configuration of the enable interrupt request registers (ENIR0, ENIR2).
Figure 15.4-3 Bit configuration of the enable interrupt request registers (ENIR0, ENIR2)
Enable interrupt request register 0 (ENIR0)
bit
Attribute
Initial value
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Enable interrupt request register 2 (ENIR2)
bit
Attribute
Initial value
7
6
5
4
3
2
1
0
EN23
EN22
EN21
EN20
EN19
EN18
EN17
EN16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
R/W: Read/Write
EN23 to EN16, EN7 to EN0 (Interrupt enable bits)
These bits enable/disable external interrupts.
Each of the EN0 to EN7, EN16 to EN23 bits corresponds to the respective bits of the external interrupt
request registers (EIRR0, EIRR2).
Written Value
CM71-10158-1E
Explanation
0
Disables generation of external interrupt requests.
The states of interrupt sources are maintained, but external interrupt requests are
not output.
1
Enables generation of external interrupt requests.
External interrupt requests are output.
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15.5
MB91665 Series
15.5 Explanation of Operations and Setting
Procedure Examples
This section explains the operations of the external interrupt controllers and provides examples of
setting procedures.
15.5.1
Operations of the External Interrupt Controllers
■ Overview
If external interrupts are enabled, an external interrupt controller outputs an external interrupt request
when it detects a preset edge/level in a signal input to an external signal input pin.
The edge/level to be detected can be selected from the following 4 types:
-
"H" level
-
"L" level
-
Rising edge (Only when return from standby mode "L" level detection at the INT0 to INT7 pins,
and rising edge detection at the INT16 to INT23 pins)
-
Falling edge (Only when return from standby mode "H" level detection at the INT0 to INT7 pins,
and falling edge detection at the INT16 to INT23 pins)
If an interrupt request from another peripheral device is generated at the same time, the interrupt
controller determines their order of priority. An external interrupt is generated for the external interrupt
request that has the higher priority.
Figure 15.5-1 shows operation with the external interrupt controllers.
Figure 15.5-1 Operation with the external interrupt controllers
External interrupt Interrupt requests
controllers
from peripheral
functions
ELVR
Interrupt controller
Interrupt
request level
ICRyy
Comparator
EIRR
ENIR
CPU
ICRxx
Comparator
ILM
Interrupt source
ICR
ILM
ELVR
EIRR
ENIR
398
: Interrupt control register (ICR00 to ICR47)
: Interrupt level mask register (ILM)
: External interrupt request level register (ELVR0, ELVR2)
: External interrupt request register (EIRR0, EIRR2)
: Enable interrupt request register (ENIR0, ENIR2)
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15.5
MB91665 Series
■ Setting procedure
To set an external interrupt, follow the procedure below.
1. Disable external interrupts by using an enable interrupt request register (ENIR0, ENIR2).
2. Change the detection condition (effective edge /level) by using an external interrupt request level
register (ELVR0, ELVR2).
3. Read the external interrupt request level register (ELVR0, ELVR2).
4. Clear interrupt sources by using an external interrupt request register (EIRR0, EIRR2).
5. Enable external interrupts by using the enable interrupt request register (ENIR0, ENIR2).
<Notes>
•
Before making settings for the external interrupt controller, disable external interrupts by using
an enable interrupt request register (ENIR0, ENIR2).
•
Before enabling output of external interrupt requests, clear interrupt sources by using an
external interrupt request register (EIRR0, EIRR2).
■ Control operations
Each external interrupt controller issues external interrupt requests to the interrupt controller in the
following sequence:
1. The external interrupt controller detects the edge/level specified by an external interrupt request level
register (ELVR0, ELVR2) in a signal input to any of the INT0 to INT7, INT16 to INT23 pins.
2. The external interrupt controller determines whether external interrupts are enabled by checking the
enable interrupt request registers (ENIR0, ENIR2).
3. If external interrupts are enabled, the external interrupt controller outputs an external interrupt request
to the interrupt controller.
■ Canceling an external interrupt request
While "L" level detection/"H" level detection is set as the detection condition for external interrupts, the
state of an interrupt source is maintained in the external interrupt request registers (EIRR0, EIRR2) even
if the corresponding external interrupt request is canceled. Therefore, the external interrupt remains at the
interrupt controller, to which a request for it has been output.
To cancel the external interrupt request output to the interrupt controller, set "0" in the corresponding bit
in an external interrupt request register (EIRR0, EIRR2). This operation clears the interrupt source, and
the external interrupt request is canceled.
However, even when the external interrupt request register (EIRR0, EIRR2) is cleared, the external
interrupt remains at the interrupt controller, to which for a request it has been output, while any signals at
the effective level are input from the INT0 to INT7, INT16 to INT23 pins.
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Figure 15.5-2 shows the state of an interrupt source being maintained, and Figure 15.5-3 shows the
clearing of an interrupt source.
Figure 15.5-2 Maintaining the state of an interrupt source
Input of external
interrupt request
Edge/Level detection
External interrupt request
register (EIRR0, EIRR2)
Gate
Interrupt controller
Interrupt source maintained in same state even after cancellation of
external interrupt request
Figure 15.5-3 Clearing of an interrupt source
INT input
"H" level
"H" level detection is set
(LBx bit, LAx bit = 01 in ELVR)
Interrupt request output
Interrupt request canceled by
writing of "0" to EIRR
ELVR: External interrupt request level register (ELVR0, ELVR2)
EIRR: External interrupt request register (EIRR0, EIRR2)
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CHAPTER 15 External Interrupt Controllers
15.5
MB91665 Series
15.5.2
Return from Standby Mode
■ Overview
External interrupt requests can be used for a return from standby mode (watch mode or stop mode). A
signal already input to any of the INT0 to INT7, INT16 to INT23 pins in standby mode in asynchronous
input can be used for a return from standby mode.
■ Settings
Before a transition to standby mode, the following setting for the INT0 to INT7, INT16 to INT23 pins
must be made with the enable interrupt request registers (ENIR0, ENIR2):
-
Pins used for the return from standby mode: Enable interrupt request output.
-
Pins not used for the return from standby mode: Disable interrupt request output.
■ Return operation
This device returns from standby mode when the effective level is detected in a signal input to the INT0
to INT7, INT16 to INT23 pins in standby mode.
Table 15.5-1 shows the relationship between external interrupt request detection conditions and the levels
for returning from standby mode.
Table 15.5-1 Relationship between external interrupt request detection conditions and
the levels for returning from standby mode
Detection Condition
LB23 to LB0
LA23 to LA0
Level for Returning from Standby
Mode
"L" level detection
0
0
"L" level detection
"H" level detection
0
1
"H" level detection
Rising edge detection
1
0
"L" level detection at the INT0 to INT7
pins, and rising edge detection at the
INT16 to INT23 pins
Falling edge detection
1
1
"H" level detection at the INT0 to INT7
pins, and falling edge detection at the
INT16 to INT23 pins
After this device returns from standby mode, other external interrupt requests cannot be recognized until
the oscillation stabilization wait time has elapsed. To output an external interrupt request after this device
returns from standby mode, input an external interrupt request signal after the oscillation stabilization
wait time has elapsed.
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Figure 15.5-4 shows an example of operation at the time of return from standby mode, where the INT0
and INT1 pins are used.
Figure 15.5-4 Operation when returning from standby mode
INT1
INT0
Internal STOP
Internal operation
(RUN)
Instruction
execution (run)
X0
Peripheral clock
(PCLK)
Clearing of external
interrupt request flag
ER0
EN0
"1" (enabled before transition to standby mode)
ER1
EN1
"1" (enabled before transition to standby mode)
STANDBY
ER1, ER0
EN1, EN0
STANDBY
RUN
402
Oscillation stabilization wait time
RUN
: ER1 and ER0 bits of external interrupt request register 0 (EIRR0)
: EN1 and EN0 bits of enable interrupt request register 0 (ENIR0)
: Standby mode
: Active
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CHAPTER 15 External Interrupt Controllers
15.5
MB91665 Series
15.5.3
Return from Sleep Mode
■ Overview
External interrupt requests can be used for a return from sleep mode.
■ Settings
Before a transition to sleep mode, the following setting for the INT0 to INT7, INT16 to INT23 pins must
be made with the enable interrupt request registers (ENIR0, ENIR2):
-
Pins used for the return from sleep mode: Enable interrupt request output.
-
Pins not used for the return from sleep mode: Disable interrupt request output.
■ Return operation
This device returns from sleep mode when a signal at the specified level/edge is input to the INT0 to
INT7, INT16 to INT23 pins in sleep mode.
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15.5
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MB91665 Series
CM71-10158-1E
CHAPTER 16 Watchdog Timer
This chapter explains the functions and operations of the
watchdog timer.
16.1 Overview
16.2 Configuration
16.3 Registers
16.4 Explanation of Operations and Setting Procedure
Examples
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CHAPTER 16 Watchdog Timer
16.1
MB91665 Series
16.1 Overview
The watchdog timer is a monitoring timer used to determine whether software hangs up or performs
other abnormal operations.
■ Overview
If the watchdog timer is not cleared before the specified period has elapsed, it judges that software has
hung up and outputs a reset request to the CPU. This reset request is called a watchdog reset request.
The operation of the watchdog timer requires that it be continually and periodically cleared before the
specified period has elapsed. If an abnormal operation of software such as hanging up prevents it from
being periodically cleared, it overflows and outputs a watchdog reset request.
406
•
The watchdog timer counts cycles while a program is active on the CPU, and it stops counting while
the CPU is stopped (in sleep mode, stop mode, or watch mode).
•
The watchdog timer can detect a transition to standby mode (watch mode/stop mode), and it can output
a watchdog reset request to the CPU.
•
If an incorrect value is written to watchdog timer clear pattern register 0 (WDTCPR0), the watchdog
timer outputs a watch reset request to the CPU.
•
The following period can be selected as the watchdog timer period:
peripheral clock (PCLK) x (29 to 224)
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CHAPTER 16 Watchdog Timer
16.2
MB91665 Series
16.2 Configuration
This section shows the configuration of the watchdog timer.
■ Block diagram of the watchdog timer
Figure 16.2-1 is a block diagram of the watchdog timer.
Figure 16.2-1 Block diagram of the watchdog timer
Register
value holding
Comparison circuit
circuit
Watchdog timer clear
pattern register 0
(WDTCPR0)
CPAT7 to CPAT0
Internal reset signal
PCLK
Standby mode
(Watch mode/stop mode)
Watchdog timer control
register 0
(WDTCR0)
R
PCLK
RSTP
Q
Watchdog reset
request
S
Sleep mode
Overflow
EN RST
Watchdog timer control
register 0
(WDTCR0)
PCLK
Overflow period
selection circuit
Watchdog timer
(24-bit up counter)
WT3 to WT0
PCLK
EN
RST
R
S
Q
: Peripheral clock (PCLK)
: Enabled
: Reset
: Reset
: Set
: Output
•
Watchdog timer control register 0 (WDTCR0)
This register controls the operation of the watchdog timer.
•
Watchdog timer clear pattern register 0 (WDTCPR0)
This register activates and clears the watchdog timer.
•
Watchdog timer
This is a 24-bit up counter.
•
Register value holding circuit
This circuit retains the value written in watchdog timer clear pattern register 0 (WDTCPR0).
•
Comparison circuit
This circuit compares the value written in watchdog timer clear pattern register 0 (WDTCPR0) with
the previous value that was written.
•
Overflow period selection circuit
This circuit selects the overflow period of the watchdog timer.
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MB91665 Series
■ Clocks
Table 16.2-1 lists the clock used by the watchdog timer.
Table 16.2-1 Clock used by the watchdog timer
Clock Name
Operation clock
408
Description
Peripheral clock (PCLK)
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CHAPTER 16 Watchdog Timer
16.3
MB91665 Series
16.3 Registers
This section explains the configuration and functions of registers for the watchdog timer.
■ List of registers for the watchdog timer
Table 16.3-1 lists the registers for the watchdog timer.
Table 16.3-1 Registers for the watchdog timer
Abbreviated
Register Name
CM71-10158-1E
Register Name
Reference
WDTCR0
Watchdog timer control register 0
16.3.1
WDTCPR0
Watchdog timer clear pattern register 0
16.3.2
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CHAPTER 16 Watchdog Timer
16.3
16.3.1
MB91665 Series
Watchdog Timer Control Register 0 (WDTCR0)
This register controls the operation of the watchdog timer.
Figure 16.3-1 shows the bit configuration of watchdog timer control register 0 (WDTCR0).
Figure 16.3-1 Bit configuration of watchdog timer control register 0 (WDTCR0)
bit
7
6
5
4
3
2
1
0
Reserved
RSTP
Reserved
Reserved
WT3
WT2
WT1
WT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
<Note>
This register can be written only prior to activation of the watchdog timer.
[bit7]: Reserved bit
410
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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CHAPTER 16 Watchdog Timer
16.3
MB91665 Series
[bit6]: RSTP (Stop mode detection reset enable bit)
This bit specifies whether to enable output of a watchdog reset request at the transition time of the CPU to
standby mode (watch mode/stop mode) while the watchdog timer is active.
Written Value
Explanation
0
Disables output of a watchdog reset request.
The counting of the watchdog timer is suspended when a transition to standby
mode (watch mode/stop mode) is detected, and it remains suspended until a return
from standby mode.
1
Enables output of a watchdog reset request.
A watchdog reset request is output when a transition to standby mode (watch
mode/stop mode) is detected.
<Notes>
•
To use standby mode (watch mode/stop mode), set "0" in this bit.
•
This register can be written only before the watchdog timer is activated. If "1" is set in this bit
after the watchdog timer is activated, standby mode (watch mode/stop mode) is detected and a
watchdog reset request is output. Therefore, standby mode becomes unusable.
[bit5, bit4]: Reserved bits
CM71-10158-1E
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
"0" is read.
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16.3
MB91665 Series
[bit3 to bit0]: WT3 to WT0 (Watchdog timer period selection bits)
These bits select one of the following periods as the period from watchdog timer clearing to watchdog
reset request output.
WT3 to WT0
Watchdog Timer Period
0000
PCLK x 29
0001
PCLK x 210
0010
PCLK x 211
0011
PCLK x 212
0100
PCLK x 213
0101
PCLK x 214
0110
PCLK x 215
0111
PCLK x 216
1000
PCLK x 217
1001
PCLK x 218
1010
PCLK x 219
1011
PCLK x 220
1100
PCLK x 221
1101
PCLK x 222
1110
PCLK x 223
1111
PCLK x 224
PCLK : Period of Peripheral clock (PCLK)
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CHAPTER 16 Watchdog Timer
16.3
MB91665 Series
16.3.2
Watchdog Timer Clear Pattern Register 0 (WDTCPR0)
This register activates and clears the watchdog timer.
Figure 16.3-2 shows the bit configuration of watchdog timer clear pattern register 0 (WDTCPR0).
Figure 16.3-2 Bit configuration of watchdog timer clear pattern register 0 (WDTCPR0)
bit 7
0
CPAT7 to CPAT0
Attribute
R/W
Initial value
0
R/W: Read/Write
[bit7 to bit0]: CPAT7 to CPAT0 bits
The watchdog timer is activated when any value is written to this register after this device is reset.
To prevent a watchdog reset request from being output after the watchdog timer is activated, the timer
must be cleared before the timer period has elapsed.
To clear the watchdog timer, invert the bit pattern written in these bits and write the inverted value to the
bits.
For details of clearing the watchdog timer, see "■ Clearing the watchdog timer" in "16.4.1 Operations of
the Watchdog Timer".
CM71-10158-1E
CPAT7 to CPAT0
In Case of Writing
Value obtained by inverting
the written value
After being activated, the watchdog
timer is cleared.
Value other than that
obtained by inverting the
written value
A watchdog reset request is output
immediately.
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In Case of Reading
"0" is read.
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CHAPTER 16 Watchdog Timer
16.4
MB91665 Series
16.4 Explanation of Operations and Setting
Procedure Examples
This section explains the operations of the watchdog timer. Also, examples of procedures for setting
operating states are shown.
16.4.1
Operations of the Watchdog Timer
If the watchdog timer is not periodically cleared even though the program is designed to do so, a
malfunction is judged to have occurred and the watchdog timer outputs a watchdog reset request to
the CPU.
■ Overview
While the watchdog timer is operating, if it is not cleared before the specified period has elapsed, it
judges that software has hung up and outputs a watchdog reset request to the CPU.
A watchdog reset request is also output if an incorrect value is written to watchdog timer clear pattern
register 0 (WDTCPR0) or at the transition time of the CPU to standby mode (watch mode/stop mode).
Also, the watchdog timer stops the counting operation when the CPU is stopped.
■ Settings
To use the watchdog timer, specify the following with watchdog timer control register 0 (WDTCR0)
before activating the watchdog timer:
•
Period from watchdog timer clearing to the watchdog reset request output (WT3 to WT0 bits)
•
Whether to enable output of a watchdog reset request at the transition time of the CPU to standby mode
(watch mode/stop mode) (RSTP)
<Notes>
•
The watchdog timer performs counting only while the CPU is operating. Therefore, the WT3 to
WT0 bits must be set based on the setting of the number of program steps and the clock
division setting.
•
To use standby mode (watch mode/stop mode), set "0" in the RSTP bit.
•
If "1" is set in the RSTP bit after the watchdog timer is activated, standby mode (watch mode/
stop mode) cannot be used.
■ Operations
The watchdog timer is activated when any value is written to the CPAT7 to CPAT0 bits of watchdog
timer clear pattern register 0 (WDTCPR0) after this device is reset. The counter value changes in sync
with the rising edge of the peripheral clock (PCLK) while the CPU is active.
Unless the watchdog timer is cleared before the period specified by the WT3 to WT0 bits of watchdog
timer control register 0 (WDTCR0) has elapsed, a watchdog reset request is output to the CPU.
Also, the watchdog timer temporarily stops counting while the CPU is stopped, such as during doze mode
or sleep mode.
The value of the watchdog timer is not cleared while the counting is temporarily stopped. When the
counting resumes, it starts from the value at which it was stopped.
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CHAPTER 16 Watchdog Timer
16.4
MB91665 Series
<Notes>
•
Even during DMA transfer with the DMA controller (DMAC), the watchdog timer continues
counting as long as the CPU is operating.
•
Since the peripheral clock (PCLK) is stopped during the oscillation stabilization wait time of the
CPU source clock (SRCCLK), the watchdog timer also stops counting during this time.
•
Sampling of the CPU operation state is performed using the peripheral clock (PCLK). Therefore,
a change in the operating state that does not last longer than the period of the peripheral clock
(PCLK) may be ignored.
■ Clearing the watchdog timer
The watchdog timer can be cleared by inverting the value written in the CPAT7 to CPAT0 bits of
watchdog timer clear pattern register 0 (WDTCPR0) at the watchdog timer activation time and writing the
inverted value to these bits.
For example, if "55H" is written in the CPAT7 to CPAT0 bits of watchdog timer clear pattern register 0
(WDTCPR0) at the watchdog timer activation time, the watchdog timer can be cleared by writing the
inverted value "AAH" to the bits.
Clearing of the watchdog timer can be subsequently repeated by alternately writing "55H" and "AAH" to
the CPAT7 to CPAT0 bits.
However, a watchdog reset request is output to the CPU when any value other than the inverted values is
written to the CPAT7 to CPAT0 bits.
<Note>
If it is difficult to maintain the value written in these bits, writing of a value to them can be followed
by writing of its inverted value (e.g., writing "AAH" then writing "55H") every time the watchdog timer
is cleared.
■ Output of a watchdog reset request
The watchdog timer outputs a watchdog reset request to the CPU in any of the following cases:
•
The period specified by the WT3 to WT0 bits of watchdog timer control register 0 (WDTCR0) has
elapsed (overflow).
•
The value written in the CPAT7 to CPAT0 bits of watchdog timer clear pattern register 0 (WDTCPR0)
is different from the value obtained by inverting the written value.
•
There is a transition by the CPU to standby mode (watch mode/stop mode) (a watchdog reset request
may be output depending on the setting of the RSTP bit of watchdog timer control register 0
(WDTCR0)).
For details of the operations after output of a watchdog reset request, see "9.5 Explanation of Operations"
of "CHAPTER 9 Reset".
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CHAPTER 16 Watchdog Timer
16.4
416
MB91665 Series
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CM71-10158-1E
CHAPTER 17 Watch Counter
This chapter explains the functions and operations of the
watch counter.
17.1
17.2
17.3
17.4
Overview
Configuration
Registers
Interrupts
17.5 Explanation of Operations and Setting Procedure
Examples
17.6 Notes on Use
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CHAPTER 17 Watch Counter
17.1
MB91665 Series
17.1 Overview
The watch counter is a timer that counts down starting from the specified value, and it generates an
interrupt request at the time that the 6-bit down counter enters an underflow condition.
Interrupt requests can be generated at a period ranging from 125 ms to 64 s.
This series has 1 built-in channel for the watch counter.
* This function is not available when the sub clock (SBCLK) is not being used.
■ Overview
•
The count clock can be selected from 4 types of clock, and interrupt requests can be set to be generated
at an interval ranging from a minimum of 125 ms to a maximum of 64 s.
Table 17.1-1 lists the count clocks and counting periods.
Table 17.1-1 Count clocks and counting periods
Counting Period (FCL = 32.768 kHz)
Period of Count Clock
212/FCL
125 ms
213/FCL
250 ms
214/FCL
500 ms
215/FCL
1s
FCL
•
Sub clock (SBCLK) frequency
A number between 0 and 63 can be set as the value used for counting by the 6-bit down counter.
If "60" is the count value used for a counting period of 1 second, an interrupt request is generated at an
interval of 1 minute. If "0" is the count value used for a counting period of 1 second, an interrupt
request is generated at an interval of 64 seconds.
•
418
An interrupt request can be generated at the time that the 6-bit down counter enters an underflow
condition.
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CHAPTER 17 Watch Counter
17.2
MB91665 Series
17.2 Configuration
This section shows the watch counter configuration.
■ Block diagram of the watch counter
Figure 17.2-1 is a block diagram of the watch counter.
Figure 17.2-1 Block diagram of the watch counter
CTR5 CTR4 CTR3 CTR2 CTR1 CTR0
RLC5 RLC4 RLC3 RLC2 RLC1 RLC0
Counter value
Reload value
Counter clearing
6-bit down
Peripheral bus
counter
Underflow
Count clock
selection
212/FCL
213/FCL
From
sub timer
214/FCL
215/FCL
Interrupt request
Enabling of
interrupts
WCEN WCOP
CS1
CS0 WCIE WCIF
FCL: Sub clock frequency
•
6-bit down counter
This is the 6-bit down counter of the watch counter. It reloads the value set in the watch counter reload
register (WCRL) and starts a countdown.
•
Watch counter reload register (WCRL)
This register specifies the value used by the watch counter to start counting. The 6-bit down counter
counts down starting from the value set in this register.
•
Watch counter read register (WCRD)
This register reads the value in the 6-bit down counter. Also, the register can be read to check the
count value.
•
Watch counter control register (WCCR)
This register controls the operation of the watch counter.
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CHAPTER 17 Watch Counter
17.2
MB91665 Series
■ Clocks
Table 17.2-1 lists the clocks used by the watch counter.
Table 17.2-1 Clocks used by the watch counter
Clock Name
Description
Remarks
Operation clock
Peripheral clock (PCLK)
-
Count clock
Sub timer output
Sub timer period*
* The sub timer period is specified by the STS2 to STS0 bits in the sub timer control register
(STMCR). For details of the sub timer, see "CHAPTER 7 Sub Timer".
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CHAPTER 17 Watch Counter
17.3
MB91665 Series
17.3 Registers
This section explains the configurations and functions of the registers for the watch counter.
■ List of registers for the watch counter
Table 17.3-1 lists the registers for the watch counter.
Table 17.3-1 Registers for the watch counter
Abbreviated
Register Name
CM71-10158-1E
Register Name
Reference
WCRL
Watch counter reload register
17.3.1
WCCR
Watch counter control register
17.3.2
WCRD
Watch counter read register
17.3.3
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CHAPTER 17 Watch Counter
17.3
17.3.1
MB91665 Series
Watch Counter Reload Register (WCRL)
This register specifies the value used by the watch counter to start counting. The 6-bit down counter
counts down starting from the value set in the register.
The register specifies the reload value for the 6-bit down counter. If the 6-bit down counter enters an
underflow condition, the value in this register is reloaded in the 6-bit down counter, and the countdown is
restarted.
Figure 17.3-1 shows the bit configuration of the watch counter reload register (WCRL).
Figure 17.3-1 Bit configuration of the watch counter reload register (WCRL)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
RLC5
RLC4
RLC3
RLC2
RLC1
RLC0
Attribute
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
R/W: Read/Write
-: Undefined
[bit7, bit6]: Undefined bits
In case of writing
Ignored
In case of reading
"0" is read.
[bit5 to bit0]: RLC5 to RLC0 (Counter reload value setting bits)
These bits set the reload value for the 6-bit down counter.
The 6-bit down counter counts downwards from the reload value and enters an underflow condition when
its value reaches "1". If "0" is set in these bits, it performs 64 countdowns from "63" to "0".
<Notes>
422
•
If the value of these bits is changed to another value while the 6-bit down counter is active, an
underflow occurs and the new value is then reloaded.
•
If the value of these bits is changed to another value at the same time that an underflow
interrupt request is generated, the correct value is not reloaded. Be sure to rewrite the value of
these bits either when the watch counter is stopped or in the interrupt processing routine before
an interrupt request is generated.
•
To verify whether the reload value is correctly set, read this register.
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CHAPTER 17 Watch Counter
17.3
MB91665 Series
17.3.2
Watch Counter Control Register (WCCR)
This register selects a count clock for the watch counter or enables/disables generation of interrupt
requests. The register also enables/disables the operation of the watch counter.
Figure 17.3-2 shows the bit configuration of the watch counter control register (WCCR).
Figure 17.3-2 Bit configuration of the watch counter control register (WCCR)
bit
7
6
5
4
3
2
1
0
WCEN
WCOP
Undefined
Undefined
CS1
CS0
WCIE
WCIF
R/W
R
-
-
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
R: Read only
-: Undefined
[bit7]: WCEN (Watch counter operation enable bit)
This bit enables/disables the operation of the watch counter.
Written Value
Explanation
0
The watch counter is disabled/stopped. The value in the 6-bit down
counter is cleared to "000000B".
1
The watch counter is enabled/started.
<Notes>
•
Output of the sub timer is used for the count clock of the watch counter, and the peripheral clock
(PCLK) is used for the settings of each register. Since the sub timer and peripheral clock
(PCLK) are not synchronized, an error of up to 1T (T: Count clock period) may occur at the
count start time, depending on the time at which "1" is written to this bit.
•
Before writing "1" to this bit to start the operation of the watch counter, verify that the watch
counter is stopped by checking the WCOP bit (WCOP = 0).
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CHAPTER 17 Watch Counter
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[bit6]: WCOP (Watch counter operating state flag bit)
This bit indicates the operating state of the watch counter.
Read Value
Explanation
0
The watch counter is stopped.
1
The watch counter is active.
[bit5, bit4]: Undefined bits
In case of writing
Ignored
In case of reading
"0" is read.
[bit3, bit2]: CS1, CS0 (Count clock selection bits)
These bits set the count clock of the watch counter.
CS1
CS0
Count Clock
0
0
212/FCL
0
1
213/FCL
1
0
214/FCL
1
1
215/FCL
FCL
Sub clock (SBCLK) frequency
<Note>
The following conditions must be satisfied when the information in these bits is changed:
•
WCEN bit = 0 (watch counter operation disabled)
•
WCOP bit = 0 (watch counter stopped)
[bit1]: WCIE (Interrupt request enable bit)
This bit specifies whether to generate an underflow interrupt request at the time that the 6-bit down
counter enters an underflow condition (WCIF bit = 1).
Written Value
424
Explanation
0
Disables generation of an underflow interrupt request.
1
Enables generation of an underflow interrupt request.
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CHAPTER 17 Watch Counter
17.3
MB91665 Series
[bit0]: WCIF (Interrupt request flag bit)
This bit indicates whether the 6-bit down counter has entered an underflow condition.
If "1" is set in the WCIE bit, an interrupt request is generated when "1" is set in this bit.
WCIF
In Case of Reading
In Case of Writing
0
The down counter has not entered an
underflow condition.
This bit is cleared to "0".
1
The down counter has entered an
underflow condition.
Ignored
<Note>
When a read-modify-write instruction is used, "1" is read.
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CHAPTER 17 Watch Counter
17.3
17.3.3
MB91665 Series
Watch Counter Read Register (WCRD)
This register reads the value in the 6-bit down counter.
Figure 17.3-3 shows the bit configuration of the watch counter read register (WCRD).
Figure 17.3-3 Bit configuration of the watch counter read register (WCRD)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
CTR5
CTR4
CTR3
CTR2
CTR1
CTR0
Attribute
-
-
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
-: Undefined
<Note>
If the 6-bit down counter is operating when its value is read, the register value must be read twice
and verified to be the same value.
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CHAPTER 17 Watch Counter
17.4
MB91665 Series
17.4 Interrupts
The 6-bit down counter enters an underflow condition when the value in the 6-bit down counter
becomes "000001B", and an underflow interrupt request is then generated.
Table 17.4-1 outlines the interrupts that can be used with the watch counter.
Table 17.4-1 Interrupts of the watch counter
Interrupt request
Underflow interrupt
request
Interrupt request
flag
WCIF=1 for WCCR
Interrupt request
enabled
WCIE=1 for WCCR
Clearing an
interrupt request
Write "0" to the WCIF
bit for WCCR
WCCR: watch counter control register (WCCR)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling generation of interrupt requests.
- Clear interrupt requests before enabling the generation of interrupt requests.
- Clear interrupt requests simultaneously with interrupts enabled.
•
For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt
Vectors".
•
To set the interrupt level corresponding to the interrupt vector number, use an interrupt control
register (ICR00 to ICR47). For details of setting interrupt levels, see "CHAPTER 10 Interrupt
Controller".
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CHAPTER 17 Watch Counter
17.5
MB91665 Series
17.5 Explanation of Operations and Setting
Procedure Examples
This section explains operations of the watch counter. Also, examples of procedures for setting the
operating state are shown.
17.5.1
Operations of the Watch Counter
The watch counter is a timer that counts down starting from the value set in the watch counter reload
register (WCRL), and it generates an interrupt request at the time that the 6-bit down counter enters
an underflow condition.
To operate the watch counter, follow the procedure below.
1. Select a count clock by using the CS1 and CS0 bits of the watch counter control register (WCCR).
2. Set a count value to the RLC5 to RLC0 bits in the watch counter reload register (WCRL).
3. Enable the operation of the watch counter by using the WCEN bit (WCEN = 1) of the watch counter
control register (WCCR).
Start a countdown. Counting is performed at the rising edge of the count clock.
4. If the 6 -bit down counter enters an underflow condition, the value of the WCIF bit in the watch
counter control register (WCCR) is changed to "1".
At this time, if generation of underflow interrupt requests has been enabled by the WCIE bit in the
watch counter control register (WCCR), an underflow interrupt request is generated.
Also, the value that is set in the RLC5 to RLC0 bits in the watch counter reload register (WCRL) is
reloaded in the 6-bit down counter, and the countdown is restarted.
5. If the value of the RLC5 to RLC0 bits in the watch counter reload register (WCRL) is changed to
another value while the watch counter is active, the watch counter is updated with the new value at the
next reload time.
6. The underflow interrupt request is cleared when "0" is written to the WCIF bit in the watch counter
control register (WCCR).
7. The 6-bit down counter is cleared to "000000B" and the counting operation is stopped when "0" is
written to the WCEN bit in the watch counter control register (WCCR).
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CHAPTER 17 Watch Counter
17.5
MB91665 Series
Figure 17.5-1 shows the operation of the watch counter.
Figure 17.5-1 Operation of the watch counter
WCEN bit
➆
➂
Count clock
CS1 and CS0 bits
➀
RLC5 to RLC0 bits
➁
7
9
➄
CTR5 to CTR0 bits
0
7
6
5
4
3
2
1
9
8
7
6
5
4
0
WCIF bit
➃
➅
<Notes>
•
Output of the sub timer is used for the count clock of the watch counter, and the peripheral clock
(PCLK) is used for the settings of each register. Since the sub timer and peripheral clock
(PCLK) are not synchronized, an error of up to 1T (T: Count clock period) may occur at the
count start time, depending on the time at which "1" is written to the WCEN bit in the watch
counter control register (WCCR).
•
Since the count clock from the sub timer is also stopped when the sub clock (SBCLK) is
stopped, the 6-bit down counter is stopped too. Even when the sub clock (SBCLK) starts
operating again, the watch counter cannot count counter values correctly. Before using the
watch counter when the sub clock (SBCLK) starts operating again, be sure to write "0" to the
WCEN bit in the watch counter control register (WCCR) to clear the counter value to "000000B".
•
Even when the CPU is operating in watch mode, the watch counter continues operating as long
as the sub timer is operating. The watch mode of the CPU can be canceled with the watch
counter interrupt processing routine.
•
If the sub timer is cleared while the watch counter is active, counting values correctly may
become impossible. Stop the watch counter by using the WCEN bit (WCEN = 0) of the watch
counter control register (WCCR), and then clear the sub timer.
•
After the watch counter is stopped by writing "0" to the WCEN in the watch counter control
register (WCCR), be sure to verify that the watch counter is stopped by checking the WCOP bit
(WCOP = 0) in the watch counter control register (WCCR) before reactivating the watch counter
by using the WCEN bit (WCEN = 1).
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CHAPTER 17 Watch Counter
17.6
MB91665 Series
17.6 Notes on Use
Note the following points about using the watch counter.
■ Notes on operations
430
•
If the sub timer is cleared while the watch counter is active, counting values correctly may become
impossible. Stop the watch counter by using the WCEN bit (WCEN = 0) of the watch counter control
register (WCCR), and then clear the sub timer.
•
After the watch counter is stopped by the WCEN bit (WCEN = 0) in the watch counter control register
(WCCR), be sure to verify that the watch counter is stopped by checking the WCOP bit (WCOP = 0) in
the watch counter control register (WCCR) before reactivating the watch counter by using the WCEN
bit (WCEN = 1).
•
Since the watch counter uses output of the sub timer as the count clock, the setting of the sub timer
must not be changed while the watch counter is active.
•
The watch counter enters an underflow condition when it counts downwards from "000001B". It counts
downwards from the reload value to "1". If the value is set to "0", it performs 64 countdowns.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 18 32-bit Free-Run Timer
This chapter explains the functions and operations of the
32-bit free-run timer.
18.1
18.2
18.3
18.4
Overview
Configuration
Pins
Registers
18.5 Interrupts
18.6 An Explanation of Operations and Setting Procedure
Examples
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CHAPTER 18 32-bit Free-Run Timer
18.1
MB91665 Series
18.1 Overview
The 32-bit free-run timer is an up-counter that counts up to the predetermined value.
After counting up to the specified value, the free-run timer clears the value and starts counting again
or generates an interrupt request. The count value is also used as the reference time for 32-bit output
compare or 32-bit input capture.
This series microcontroller has 2 built-in channels for the 32-bit free-run timer.
■ Overview
The 32-bit free-run timer is part of the compare timer. The compare timer comprises the following three
peripheral functions:
-
32-bit free-run timer (2 channels)
-
32-bit output compare (8 channels)
See "CHAPTER 20 32-bit Output Compare".
-
32-bit input capture (8 channels)
See "CHAPTER 19 32-bit Input Capture".
This chapter explains the 32-bit free-run timer.
•
Count clock: One of the following can be selected:
-
Internal clock (peripheral clock)
Can be selected from 9 types, which are peripheral clocks (PCLK) divided by 1, 2, 4, 8, 16, 32,
64,128, and 256.
•
External clock
Interrupt request: Can be issued in the following cases:
The count value of the 32-bit free-run timer matches the preset value (compare clear interrupt).
•
432
Of the values of the 2 channels of the 32-bit free-run timer, one can be selected for use as the reference
time for 32-bit output compare and 32-bit input capture.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 18 32-bit Free-Run Timer
18.2
MB91665 Series
18.2 Configuration
The 32-bit free-run time is part of the compare timer. The following is a block diagram of the compare
timer and the 32-bit free-run timer.
■ Compare timer block diagram
The compare timer consists of the following blocks.
•
32-bit free-run timer
•
Free-run timer selector
The free-run timer selector selects the 32-bit free-run timer used as the reference time for the 32-bit
output compare and 32-bit input capture.
•
32-bit input capture (8 channels)
•
32-bit output compare (8 channels)
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CHAPTER 18 32-bit Free-Run Timer
18.2
MB91665 Series
Figure 18.2-1 is a compare timer block diagram.
Figure 18.2-1 Compare timer block diagram
FRCK0 pin
32-bit free-run timer
ch.0
Interrupt request
Compare clear
ch.0
FRCK1 pin*
32-bit free-run timer
ch.1
Timer 0
Interrupt request
Compare clear
ch.1
Timer 1
Free-run timer selector
Peripheral bus
Timer 0
or
Timer 1
Count
value
Interrupt request
32-bit
input
capture
(× 4)
Interrupt request
Input capture ch.0
Input capture ch.1
Input capture ch.2
Input capture ch.3
Interrupt request
Interrupt request
IN0 to IN3 pins
IN0 to IN3
Count
value
32-bit
input
capture
(× 4)
Count
value
Input capture ch.4
Input capture ch.5
Input capture ch.6
Input capture ch.7
Interrupt request
Interrupt request
Interrupt request
Interrupt request
IN4 to IN7 pins
IN4 to IN7
Interrupt request
Interrupt request
Interrupt request
32-bit
Interrupt request
output
compare
OUT0 to OUT3
(× 4)
Count
value
Interrupt request
Interrupt request
Interrupt request
32-bit
Interrupt request
output
compare
OUT4 to OUT7
(× 4)
Output compare ch.0
Output compare ch.1
Output compare ch.2
Output compare ch.3
OUT0 to
OUT3 pins
Output compare ch.4
Output compare ch.5
Output compare ch.6
Output compare ch.7
OUT4 to
OUT7 pins
* For MB91F668 (48 pins), there is no FRCK1 pin.
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CM71-10158-1E
CHAPTER 18 32-bit Free-Run Timer
18.2
MB91665 Series
■ 32-bit free-run timer block diagram
Figure 18.2-2 is a block diagram of the 32-bit free-run timer.
Figure 18.2-2 32-bit free-run timer block diagram
Internal clock (PCLK)
TCCSL0
STOP
SCLR
CLK3
CLK2
CLK1
Prescaler
CLK0
External clock input (FRCK0)
TCDT0
STOP
CLR
Stop
32-bit free-run timer
ch.0
Selection circuit
CK
To free-run timer selector
Comparison
circuit
Compare clear register 0
(CPCLR0)
Stop free-run timer 0
(To free-run timer selector)
Peripheral bus
Interrupt request
ICLR
ICRE
ECKE
TCCSH0
Internal clock (PCLK)
TCCSL1
STOP
SCLR
CLK3
CLK2
CLK1
Prescaler
CLK0
External clock input (FRCK1)
TCDT1
STOP
Stop
32-bit free-run timer
ch.1
CLR
Selection circuit
CK
To free-run timer selector
Comparison
circuit
Compare clear register 1
(CPCLR1)
Stop free-run timer 1
(To free-run timer selector)
Interrupt request
ICLR
ICRE
ECKE
TCCSH1
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CHAPTER 18 32-bit Free-Run Timer
18.2
•
MB91665 Series
32-bit free-run timer
This counter counts up to the value that is set in the compare clear register (CPCLR0, CPCLR1)
•
Timer status control register upper/lower (TCCSH0/TCCSL0, TCCSH1/TCCSL1)
•
Compare clear register (CPCLR0, CPCLR1)
This register controls the operation of the 32-bit free-run timer.
The 32-bit up counter counts up to the value that is set in this register.
•
Timer data register (TCDT0, TCDT1)
This register is used to set the value with which the timer starts counting or to read the current count
value.
•
Prescaler
When the internal clock (peripheral clock) is selected for the count clock, the prescaler divides the
peripheral clock (PCLK)
•
Selection circuit
The selection circuit selects whether to use the internal clock (peripheral clock) or external clock
(FRCK0, FRCK1) for the count clock.
•
Comparison circuit
The comparison circuit compares the count value of the 32-bit free-run timer and the value set in the
compare clear register (CPCLR0, CPCLR1).
■ Clocks
Table 18.2-1 lists the clocks used for the 32-bit free-run timer.
Table 18.2-1 Clocks used for 32-bit free-run timer
Clock Name
436
Description
Remarks
Operation clock
Peripheral clock (PCLK)
-
Count clock
Internal clock (peripheral clock)
Created through division of the peripheral
clock (PCLK).
External clock
Input from the FRCK0 and FRCK1 pins
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CHAPTER 18 32-bit Free-Run Timer
18.3
MB91665 Series
18.3 Pins
This section explains the pins used by the 32-bit free-run timer.
■ Overview
•
FRCK0 and FRCK1 pins
These pins are 32-bit free-run timer external clock input pins. These pins are multiplexed pins.
To use these pins as the FRCK0 and FRCK1 pins of the 32-bit free-run timer, see "2.4 Setting
Method for Pins".
■ Relationship between pins and channels
Table 18.3-1 shows the relationship between channels and pins.
Table 18.3-1 Relationship between channels and pins
Channel
Input Pin
0
FRCK0
1
FRCK1*
* For MB91F668 (48 pins), there is no FRCK1.
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CHAPTER 18 32-bit Free-Run Timer
18.4
MB91665 Series
18.4 Registers
This section explains the configuration and functions of the registers used by the 32-bit free-run timer.
■ 32-bit free-run timer registers
Table 18.4-1 lists the registers of the 32-bit free-run timer.
Table 18.4-1 32-bit free-run timer registers
Channel
Abbreviated Register
Name
Common
FRTSEL
Free-run timer select register
18.4.1
0
CPCLR0
Compare clear register 0
18.4.2
TCCSH0/TCCSL0
Timer status control register upper0/lower0
18.4.4
TCDT0
Timer data register 0
18.4.3
CPCLR1
Compare clear register 1
18.4.2
TCCSH1/TCCSL1
Timer status control register upper1/lower1
18.4.4
TCDT1
Timer data register 1
18.4.3
1
438
Register Name
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Reference
CM71-10158-1E
CHAPTER 18 32-bit Free-Run Timer
18.4
MB91665 Series
18.4.1
Free-Run Timer Select Register (FRTSEL)
This register specifies the channel for use as the reference time for 32-bit output compare and 32-bit
input capture, of the 2 channels of 32-bit free-run timer.
Figure 18.4-1 shows the bit configuration of the free-run timer select register (FRTSEL).
Figure 18.4-1 Bit configuration of free-run timer select register (FRTSEL)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FRS1
FRS0
Attribute
-
-
-
-
-
-
R/W
R/W
Initial value
X
X
X
X
X
X
0
0
R/W: Read/Write
-: Undefined
X: Undefined
[bit7 to bit2]: Undefined bits
In case of writing
Ignored
In case of reading
A value is undefined.
[bit1, bit0]: FRS1, FRS0 (free-run timer selection bit)
These bits select the 32-bit free-run timer channel used as the reference time for the 32-bit output
compare and 32-bit input capture.
FRS1
FRS0
Explanation
Free-run Timer
Channel
0
0
ch.0
32-bit output compare (ch.0 to ch.7)
32-bit input capture (ch.0 to ch.7)
0
1
ch.0
32-bit output compare (ch.0 to ch.3)
32-bit input capture (ch.0 to ch.3)
ch.1
32-bit output compare (ch.4 to ch.7)
32-bit input capture (ch.4 to ch.7)
ch.0
32-bit output compare (ch.0 to ch.7)
ch.1
32-bit input capture (ch.0 to ch.7)
1
1
CM71-10158-1E
Use
0
1
Setting prohibited
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CHAPTER 18 32-bit Free-Run Timer
18.4
18.4.2
MB91665 Series
Compare Clear Register (CPCLR0, CPCLR1)
This register sets the comparison value of the 32-bit free-run timer.
When the 32-bit free-run timer counts up and reaches the value that is set in this register, the count
value of the 32-bit free-run timer is cleared to "0000 0000H".
Figure 18.4-2 shows the bit configuration of the compare clear register (CPCLR0, CPCLR1).
Figure 18.4-2 Bit configuration of compare clear register (CPCLR0, CPCLR1)
bit 31
0
CL31 to CL0
Attribute
R/W
Initial value
1
R/W: Read/Write
<Notes>
•
Rewrite this register while the 32-bit free-run timer is stopped.
The 32-bit free-run timer is stopped when the STOP bit of the timer status control register lower
(TCCSL0, TCCSL1) is "1".
•
440
Be sure to access this register in units of words.
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CHAPTER 18 32-bit Free-Run Timer
18.4
MB91665 Series
18.4.3
Timer Data Register (TCDT0, TCDT1)
This register is used to set the value with which the 32-bit free-run timer starts counting or to read the
current count value.
Figure 18.4-3 shows the bit configuration of the timer data register (TCDT0, TCDT1).
Figure 18.4-3 Bit configuration of timer data register (TCDT0, TCDT1)
bit 31
0
T31 to T0
Attribute
R/W
Initial value
0
R/W: Read/Write
The 32-bit free-run timer counts up starting from the value written to this register. If this register is read,
the count value of the 32-bit free-run timer is read.
<Notes>
•
Rewrite this register while the 32-bit free-run timer is stopped.
The 32-bit free-run timer is stopped when the STOP bit of the timer status control register lower
(TCCSL0, TCCSL1) is "1".
•
Be sure to access this register in units of half word.
•
The write value and read value of this register are different.
•
If one of the following occurs, the count value of the 32-bit free-run timer (the value of this
register) is promptly cleared to "0000 0000H".
- This device is reset.
- "1" is written to the SCLR bit of the timer status control register lower (TCCSL0, TCCSL1).
- The count value of the 32-bit free-run time matches the value of the compare clear register
(CPCLR0, CPCLR1).
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CHAPTER 18 32-bit Free-Run Timer
18.4
18.4.4
MB91665 Series
Timer Status Control Register Upper/Lower
(TCCSH0/TCCSL0, TCCSH1/TCCSL1)
This register controls the operation of the 32-bit free-run timer.
Figure 18.4-4 shows the bit configuration of the timer status control register upper/lower (TCCSH0/
TCCSL0, TCCSH1/TCCSL1).
Figure 18.4-4 Bit configuration of timer status control register upper/lower
(TCCSH0/TCCSL0, TCCSH1/TCCSL1)
Timer status control register upper (TCCSH0 TCCSH1)
bit
Attribute
15
14
13
12
11
10
9
8
ECKE
Undefined
Undefined
Undefined
Undefined
Undefined
ICLR
ICRE
R/W
-
-
-
-
-
R/W
R/W
0
X
X
X
X
X
0
0
Initial value
Timer status control register lower (TCCSL0, TCCSL1)
bit
7
6
5
4
3
2
1
0
Undefined
STOP
Undefined
SCLR
CLK3
CLK2
CLK1
CLK0
Attribute
-
R/W
-
R/W
R/W
R/W
R/W
R/W
Initial value
X
1
X
0
0
0
0
0
R/W: Read/Write
-: Undefined
X: Undefined
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CHAPTER 18 32-bit Free-Run Timer
18.4
MB91665 Series
[bit15]: ECKE (Clock selection bit)
This bit selects the count clock of the 32-bit free-run timer.
Written Value
Explanation
0
Selects the internal clock (peripheral clock).
1
Selects an external clock.
An internal clock (peripheral clock) is generated by dividing the peripheral clock (PCLK). If an internal
clock (peripheral clock) is selected, CLK3 to CLK0 bits must be used to select the division rate of the
peripheral clock (PCLK).
An external clock is input through the FRCK0 and FRCK1 pins. When an external clock is selected, the
timer counts on both edges of the signal input through the FRCK0 or FRCK1 pin.
For MB91F668 (48 pins), there is no FRCK1 pin.
<Notes>
•
The count clock changes as soon as this bit is changed.
•
Rewrite this bit while the 32-bit free-run timer, 32-bit input capture, and 32-bit output compare
are all stopped.
[bit14 to bit10]: Reserved bits
In case of writing
Ignored
In case of reading
A value is undefined.
[bit9]: ICLR (compare clear interrupt request flag bit)
This bit indicates that the count value of the 32-bit free-run timer matches the value set in the compare
clear register (CPCLR0, CPCLR1).
If "1" is set in the ICRE bit when this bit is "1", a compare clear interrupt request is generated.
ICLR
In Case of Reading
In Case of Writing
0
The count value does not match the preset value.
This bit is cleared to "0".
1
The count value matches the preset value.
Ignored
<Note>
When a read-modify-write instruction is used, "1" is read.
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CHAPTER 18 32-bit Free-Run Timer
18.4
MB91665 Series
[bit8]: ICRE (compare clear interrupt request enable bit)
This bit is specifies whether to generate a compare clear interrupt request when the count value of the 32bit free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1) (ICLR bit = 1).
Written Value
Explanation
0
Disables generation of compare clear interrupt requests.
1
Enables generation of compare clear interrupt requests.
[bit7]: Undefined bit
In case of writing
Ignored
In case of reading
A value is undefined.
[bit6]: STOP (timer operation enable bit)
This bit enables (starts) or disables (stops) the count operation of the 32-bit free-run timer.
Written Value
Explanation
0
Enables (starts) the count function.
1
Disables (stops) the count function.
<Note>
When the 32-bit free-run timer is stopped, the 32-bit output compare is also stopped.
[bit5]: Undefined bit
In case of writing
Ignored
In case of reading
A value is undefined.
[bit4]: SCLR (timer clear bit)
This bit clears the count value of the 32-bit free-run timer to "0000 0000H".
SCLR
In Case of Writing
0
Does not clear the count value.
1
Clears the count value.
In Case of Reading
"0" is read.
<Note>
When this bit is set to "1", the count value is cleared at the next count clock timing.
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CHAPTER 18 32-bit Free-Run Timer
18.4
MB91665 Series
[bit3 to bit0]: CLK3 to CLK0 (clock frequency selection bits)
These bits select the division rate of the peripheral clock (PCLK) when the internal clock (peripheral
clock) is selected for the count clock of the 32-bit free-run timer,
The count cycle is determined by using the division rate selected by these bits and the peripheral clock
(PCLK) frequency.
Table 18.4-2 provides an example of count cycles that are set according to the relationship between the
values written to these bits and the peripheral clock (PCLK).
Table 18.4-2 Example of written values and count cycles
CLK3
CLK2
CLK1
CLK0
PCLK
Division
Rate
PCLK Frequency
32 MHz 16 MHz
8 MHz
4 MHz
1 MHz
0
0
0
0
Divided
by 1
31.25 ns
62.5 ns
125 ns
0.25 μs
1 μs
0
0
0
1
Divided
by 2
62.5 ns
125 ns
0.25 μs
0.5 μs
2 μs
0
0
1
0
Divided
by 4
125 ns
0.25 μs
0.5 μs
1 μs
4 μs
0
0
1
1
Divided
by 8
0.25 μs
0.5 μs
1 μs
2 μs
8 μs
0
1
0
0
Divided
by 16
0.5 μs
1 μs
2 μs
4 μs
16 μs
0
1
0
1
Divided
by 32
1 μs
2 μs
4 μs
8 μs
32 μs
0
1
1
0
Divided
by 64
2 μs
4 μs
8 μs
16 μs
64 μs
0
1
1
1
Divided
by 128
4 μs
8 μs
16 μs
32 μs
128 μs
1
0
0
0
Divided
by 256
8 μs
16 μs
32 μs
64 μs
256 μs
PCLK: Peripheral clock (PCLK)
<Notes>
•
Do not use any settings other than those listed in Table 18.4-2.
•
The count clock changes as soon as this bit is rewritten.
•
Rewrite this bit while the 32-bit free-run timer, 32-bit input capture, and 32-bit output compare
are all stopped.
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CHAPTER 18 32-bit Free-Run Timer
18.5
MB91665 Series
18.5 Interrupts
An interrupt request (compare clear interrupt request) is generated when the count value of the 32-bit
free-run timer matches the value set in the compare clear register (CPCLR0, CPCLR1).
Table 18.5-1 outlines the interrupts that can be used with the 32-bit free-run timer.
Table 18.5-1 Interrupts of the 32-bit free-run timer
Interrupt request
Compare clear
interrupt request
Interrupt request
flag
ICLR=1 for TCCSH
Interrupt request
enabled
ICRE=1 for TCCSH
Clearing an
interrupt request
Write "0" to the ICLR
bit for TCCSH
TCCSH: timer status control register upper (TCCSH0, TCCSH1)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests.
- Clears interrupt requests before enabling the generation of interrupt requests.
- Clears interrupt requests simultaneously with interrupts enabled.
446
•
For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt
Vectors".
•
Use an interrupt control register (ICR00 to ICR47) to set the interrupt level corresponding to the
interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10
Interrupt Controller".
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 18 32-bit Free-Run Timer
18.6
MB91665 Series
18.6 An Explanation of Operations and Setting
Procedure Examples
This section explains the operation of the 32-bit free-run timer. Also, examples of procedures for
setting the operating state are shown.
■ Overview
The 32-bit free-run timer uses an internal clock (peripheral clock) or an external clock as count clock and
counts up starting from the value set in the timer data register (TCDT0, TCDT1) to the value set in the
compare clear register (CPCLR0, CPCLR1).
•
Internal clock (peripheral clock)
Can be selected from 9 types, which are peripheral clocks (PCLK) divided by 1, 2, 4, 8, 16, 32,
64,128, and 256.
•
External clock
The timer counts up at both edges. The count start timing varies depending on the initial value of the
external clock input through the FRCK0 or FRCK1 pin.
The count value of the 32-bit free-run timer is used as the reference time for 32-bit output compare or 32bit input capture.
■ Timer clearing
The count value of the 32-bit free-run timer is promptly cleared when one of the following conditions is
met:
•
This count value matches the value that is set in the compare clear register (CPCLR0, CPCLR1).
•
The SCLR bit of the timer status control register lower (TCCSL0, TCCSL1) is set to 1 to clear the
count value of the 32-bit free-run timer.
•
"0000 0000H" is written to the timer data register (TCDT0, TCDT1) while the 32-bit free-run timer is
stopped.
•
This device is reset.
When the count value of the 32-bit free-run timer matches the value set in the compare clear register
(CPCLR0, CPCLR1), the count value is cleared in synchronization with the count timing.
Figure 18.6-1 shows the timer clear timing.
Figure 18.6-1 Timer clear timing
Peripheral clock (PCLK)
Compare clear register
(CPCLR0, CPCLR1) value
N
Count timing
Count value
CM71-10158-1E
N
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0000H
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CHAPTER 18 32-bit Free-Run Timer
18.6
18.6.1
MB91665 Series
Operation When an Internal Clock (Peripheral Clock) Is
Selected
A divided peripheral clock (PCLK) is used as the count clock.
■ Count operation
When the STOP bit of the timer status control register lower (TCCSL0, TCCSL1) is set to 0 to enable the
32-bit free-run timer, the timer counts up starting from the value set in the timer data register (TCDT0,
TCDT1) to the value set in the compare clear register (CPCLR0, CPCLR1).
■ Compare clear
When the count value of the 32-bit free-run timer matches the value set in the compare clear register
(CPCLR0, CPCLR1), the count value is cleared in synchronization with the count timing (compare clear).
After compare clear, the timer starts counting again.
Figure 18.6-2 shows the compare clear timing.
Figure 18.6-2 Compare clear timing
Count value
FFFF FFFFH
BFFF FFFFH
7FFF FFFFH
3FFF FFFFH
0000 0000 H
Time
Timer start
Comparison results matched
Reset
Compare clear
registers
FFFFH
7FFFH
BFFFH
(CPCLR0, CPCLR1)
■ Interrupt processing
An interrupt request can be generated when the count value of the 32-bit free-run timer matches the value
set in the compare clear register (CPCLR0, CPCLR1).
The interrupt request can be cleared by writing "0" to the ICLR bit of the timer status control register
upper (TCCSH0 TCCSH1).
Figure 18.6-3 shows the interrupt request generation timing.
Figure 18.6-3 Interrupt request generation timing
Count value
N-1
N
0
1
Compare clear
interrupt request
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CM71-10158-1E
CHAPTER 18 32-bit Free-Run Timer
18.6
MB91665 Series
18.6.2
Operation When an External Clock Is Selected
The external clock input through the FRCK0 or FRCK1 pin is used as the count clock.
■ Count operation
Upon detection of a valid edge through the FRCK0 or FRCK1 pin while the STOP bit of the timer status
control register lower (TCCSL0, TCCSL1) is set to 0 to enable the 32-bit free-run timer, the timer counts
up starting from the value set in the timer data register (TCDT0, TCDT1) to the value set in the compare
clear register (CPCLR0, CPCLR1).
The count timing varies depending on the signal level input through the FRCK0 or FRCK1 pin when the
free-run timer is enabled.
Table 18.6-1 lists the count timings applicable when an external clock is selected.
Table 18.6-1 Count timings applicable when an external clock is selected
Signal Level
When Timer Is
Enabled
Count Timing
"H" level
Starts counting at a rising edge and thereafter counts up at both edges.
"L" level
Starts counting at a falling edge and thereafter counts up at both edges.
Figure 18.6-4 shows the count timing applicable when an external clock is selected (ECKE=1).
Figure 18.6-4 Count timing applicable when an external clock is selected
External clock input
ECKE bit
Count clock
Count value
N
N+1
N+2
■ Compare clear
Same as when an internal clock (peripheral clock) is selected. See "■ Compare clear" in "18.6.1
Operation When an Internal Clock (Peripheral Clock) Is Selected".
■ Interrupt processing
Same as when an internal clock (peripheral clock) is selected. See "■ Interrupt processing" in "18.6.1
Operation When an Internal Clock (Peripheral Clock) Is Selected".
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CHAPTER 18 32-bit Free-Run Timer
18.6
450
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MB91665 Series
CM71-10158-1E
CHAPTER 19 32-bit Input Capture
This chapter explains the functions and operations of the
32-bit input capture.
19.1 Overview
19.2 Configuration
19.3 Pins
19.4 Registers
19.5 Interrupts
19.6 An Explanation of Operations and Setting Procedure
Examples
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CHAPTER 19 32-bit Input Capture
19.1
MB91665 Series
19.1 Overview
Upon detection of an input signal edge that is set in advance, the 32-bit input capture saves the value
of the 32-bit free-run timer at the time.
This series microcontroller has 8 built-in input capture channels.
■ Overview
The 32-bit input capture is part of the compare timer. The compare timer comprises the following three
functions:
-
32-bit free-run timer (2 channels)
-
32-bit output compare (8 channels)
See "CHAPTER 18 32-bit Free-Run Timer".
See "CHAPTER 20 32-bit Output Compare".
-
32-bit input capture (8 channels)
This chapter explains the 32-bit input capture.
•
One of the following three triggers can be selected to save the value of the 32-bit free-run timer.
-
Rising edge
-
Falling edge
-
Both edges
•
An interrupt request can be generated upon detection of an input signal edge that is set in advance.
•
Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value is
saved by the 32-bit input capture can be selected.
For details of the procedure for selecting the 32-bit free-run timer, see "18.4.1 Free-Run Timer Select
Register (FRTSEL)" in "CHAPTER 18 32-bit Free-Run Timer".
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CHAPTER 19 32-bit Input Capture
19.2
MB91665 Series
19.2 Configuration
This section explains the configuration of the 32-bit input capture.
■ 32-bit input capture block diagram
Figure 19.2-1 is a block diagram of the 32-bit input capture.
Figure 19.2-1 32-bit input capture block diagram
From the free-run timer selector
Input capture
data register 0 (IPCP0)
Edge detection
ICP0
ICE0
EG10
IN0
ICS01
EG00
Interrupt request 0
Input capture
data register 1 (IPCP1)
Edge detection
IN1
ICS01
ICP1
ICE1
EG11
EG01
Interrupt request 1
Input capture
data register 2 (IPCP2)
Edge detection
IN2
ICS23
Peripheral bus
ICP2
ICE2
EG12
EG02
Interrupt request 2
Input capture
data register 3 (IPCP3)
Edge detection
IN3
ICS23
ICP3
ICE3
EG13
EG03
Interrupt request 3
Input capture
data register 4 (IPCP4)
Edge detection
IN4
ICS45
ICP4
ICE4
EG14
EG04
Interrupt request 4
Input capture
data register 5 (IPCP5)
Edge detection
IN5
ICS45
ICP5
ICE5
EG15
EG05
Interrupt request 5
Input capture
data register 6 (IPCP6)
Edge detection
IN6
ICS67
ICP6
ICE6
EG16
EG06
Interrupt request 6
Input capture
data register 7 (IPCP7)
Edge detection
IN7
ICS67
ICP7
ICE7
EG17
EG07
Interrupt request 7
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19.2
•
MB91665 Series
Input capture data registers (IPCP0 to IPCP7)
Free-run timer values are saved to these registers.
•
Input capture status control registers (ICS01 to ICS67)
These registers are used to control the operation and state of the 32-bit input capture.
<Note>
For details of the compare timer block diagram, see "■ Compare timer block diagram" in
"CHAPTER 18 32-bit Free-Run Timer".
■ Clocks
Table 19.2-1 lists the clock used for the 32-bit input capture.
Table 19.2-1 Clock used for 32-bit input capture
Clock Name
Operation clock
454
Description
Peripheral clock (PCLK)
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CHAPTER 19 32-bit Input Capture
19.3
MB91665 Series
19.3 Pins
This section explains the pins used by the 32-bit input capture.
■ Overview
•
IN0 to IN7 pins
Input pins of 32-bit input capture. These pins are multiplexed pins. To use these pins as input pins of
the 32-bit input capture, see "2.4 Setting Method for Pins".
■ Relationship between pins and channels
Table 19.3-1 lists the relationship between channels and pins.
Table 19.3-1 Relationship between channels and pins
Channel
CM71-10158-1E
Input Pin
0
IN0
1
IN1
2
IN2
3
IN3
4
IN4
5
IN5
6
IN6
7
IN7
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19.4
MB91665 Series
19.4 Registers
This section explains the configuration and functions of registers used by the 32-bit input capture.
■ Registers of 32-bit input capture
Table 19.4-1 lists the registers of the 32-bit input capture.
Table 19.4-1 Registers of 32-bit input capture
Channel
456
Abbreviated
Register Name
Register Name
Reference
Common
FRTSEL
Free-run timer select register
18.4.1
Common to 0 and 1
ICS01
Input capture status control register 01
19.4.1
Common to 2 and 3
ICS23
Input capture status control register 23
19.4.1
Common to 4 and 5
ICS45
Input capture status control register 45
19.4.1
Common to 6 and 7
ICS67
Input capture status control register 67
19.4.1
0
IPCP0
Input capture data register 0
19.4.2
1
IPCP1
Input capture data register 1
19.4.2
2
IPCP2
Input capture data register 2
19.4.2
3
IPCP3
Input capture data register 3
19.4.2
4
IPCP4
Input capture data register 4
19.4.2
5
IPCP5
Input capture data register 5
19.4.2
6
IPCP6
Input capture data register 6
19.4.2
7
IPCP7
Input capture data register 7
19.4.2
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CHAPTER 19 32-bit Input Capture
19.4
MB91665 Series
19.4.1
Input Capture Status Control Registers
(ICS01 to ICS67)
These registers are used to control the operation and state of the 32-bit input capture.
Figure 19.4-1 shows the bit configuration of the input capture status control register (ICS01 to ICS67).
Figure 19.4-1 Bit configuration of input capture status control register (ICS01 to ICS67)
bit
7
6
5
4
3
2
1
0
ICPm
ICPn
ICEm
ICEn
EG1m
EG0m
EG1n
EG0n
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
[bit7, bit6]: ICPm, ICPn (interrupt request flag bit)
Each of these bits indicates that a valid edge has been detected at pins IN0 to IN7. When this bit is "1"
while ICEm or ICEn bit is set to "1", an edge detection interrupt request is generated.
The ICPm bit corresponds to the odd-numbered channel, and the ICPn bit corresponds to the evennumbered channel.
ICPm, ICPn
In Case of Reading
In Case of Writing
0
A valid edge is not detected.
This bit is cleared to "0".
1
A valid edge is detected.
Ignored
Table 19.4-2 lists the relationship between the ICPm bits and ICPn bits and channels.
Table 19.4-2 Relationship between bits and channels
Input Capture Status
Registers
ICPm Bit
Supported
Channel
ICPn Bit
Supported
Channel
ICS01
ICP1
ch.1
ICP0
ch.0
ICS23
ICP3
ch.3
ICP2
ch.2
ICS45
ICP5
ch.5
ICP4
ch.4
ICS67
ICP7
ch.7
ICP6
ch.6
<Note>
When a read-modify-write instruction is used, "1" is read.
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[bit5, bit4]: ICEm, ICEn (interrupt request enable bits)
Each of these bits specifies whether to generate an edge detection interrupt request when a valid edge is
detected through pins IN0 to IN7 (ICPm, ICPn=1).
The ICEm bit corresponds to the odd-numbered channel, and the ICEn bit corresponds to the evennumbered channel.
Written Value
Explanation
0
Disables generation of edge detection interrupt requests.
1
Enables generation of edge detection interrupt requests.
Table 19.4-3 shows the relationship between the ICEm bits and ICEn bits and channels.
Table 19.4-3 Relationship between bits and channels
Input Capture Status
Registers
ICEm Bit
Supported
Channel
ICEn Bit
Supported
Channel
ICS01
ICE1
ch.1
ICE0
ch.0
ICS23
ICE3
ch.3
ICE2
ch.2
ICS45
ICE5
ch.5
ICE4
ch.4
ICS67
ICE7
ch.7
ICE6
ch.6
[bit3, bit2]: EG1m, EG0m (edge selection bits)
These bits select a valid edge for the 32-bit input capture of the odd-numbered channel.
When the edge selected here is detected, the value of the 32-bit free-run timer is saved to the input
capture data register (IPCP0 to IPCP7).
EG1m
458
EG0m
Explanation
0
0
No edge detected (input capture stopped)
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
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CHAPTER 19 32-bit Input Capture
19.4
MB91665 Series
Table 19.4-4 shows the relationship between the EG1m and EG0m bits and channels.
Table 19.4-4 Relationship between bits and channels
Input Capture Status Registers
EG1m, EG0m Bits
Supported Channel
ICS01
EG11, EG01
ch.1
ICS23
EG13, EG03
ch.3
ICS45
EG15, EG05
ch.5
ICS67
EG17, EG07
ch.7
<Note>
If a value other than "00" is written to these bits, the operation of the corresponding channel is
enabled at the same time as a valid edge is selected.
[bit1, bit0]: EG1n, EG0n (edge selection bits)
These bits select a valid edge for the 32-bit input capture of the even-numbered channel.
When the edge selected here is detected, the value of the 32-bit free-run timer is saved to the input
capture data register (IPCP0 to IPCP7).
EG1n
CM71-10158-1E
EG0n
Explanation
0
0
No edge detected (input capture stopped)
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
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MB91665 Series
The bit names of EG1n and EG0n vary depending on the channel.
Table 19.4-5 shows the relationship between bits and channels.
Table 19.4-5 Relationship between bits and channels
Input Capture Status Registers
EG1n, EG0n Bits
Supported Channel
ICS01
EG10, EG00
ch.0
ICS23
EG12, EG02
ch.2
ICS45
EG14, EG04
ch.4
ICS67
EG16, EG06
ch.6
<Note>
If a value other than "00" is written to these bits, the operation of the corresponding channel is
enabled at the same time as a valid edge is selected.
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CHAPTER 19 32-bit Input Capture
19.4
MB91665 Series
19.4.2
Input Capture Data Register (IPCP0 to IPCP7)
This register saves the value of the 32-bit free-run timer. When a valid edge is detected in the input
signal through pins IN0 to IN7, the value of the 32-bit free-run timer is saved to this register.
Figure 19.4-2 shows the bit configuration of the input capture data register (IPCP0 to IPCP7).
Figure 19.4-2 Bit configuration of input capture data register (IPCP0 to IPCP7)
bit 31
0
CP31 to CP0
Attribute
R
Initial value
X
R: Read only
X: Undefined
<Notes>
•
Be sure to read this register in units of words.
•
Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose
value is to be saved to this register varies depending on the free-run timer select register
(FRTSEL) setting. For details, see "18.4.1 Free-Run Timer Select Register (FRTSEL)" in
"CHAPTER 18 32-bit Free-Run Timer".
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CHAPTER 19 32-bit Input Capture
19.5
MB91665 Series
19.5 Interrupts
Upon detection of a valid edge in the input signal through pins IN0 to IN7, an interrupt request is
generated (edge detection interrupt request).
Table 19.5-1 outlines the interrupts that can be used with the 32-bit input capture.
Table 19.5-1 Interrupts of the 32-bit input capture
Interrupt
request
Edge detection
interrupt request
Interrupt request flag
Interrupt request
enabled
Clearing an interrupt
request
Even-numbered channel:
ICPn=1 for ICS
Odd-numbered channel:
ICPm=1 for ICS
Even-numbered channel:
ICEn=1 for ICS
Odd-numbered channel:
ICEm=1 for ICS
Write "0" to the next bit.
Even-numbered channel:
ICPn bit for ICS
Odd-numbered channel:
ICPm bit for ICS
ICS: input capture status control register (ICS01 to ICS67)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests.
- Clears interrupt requests before enabling the generation of interrupt requests.
- Clears interrupt requests at the same time with interrupts enabled.
462
•
For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt
Vectors".
•
Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to
the interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10
Interrupt Controller".
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CHAPTER 19 32-bit Input Capture
19.6
MB91665 Series
19.6 An Explanation of Operations and Setting
Procedure Examples
This section explains the operation of the 32-bit input capture. Also, examples of procedures for
setting the operating state are shown.
19.6.1
Explanation of 32-bit Input Capture Operation
Upon detection of an input signal edge that is set in advance, the 32-bit input capture saves the value
of the 32-bit free-run timer at the time.
■ Operation
Selecting a valid edge with the following bits of the input capture status control register (ICS01 to ICS67)
enables 32-bit input capture operation.
•
Selecting valid edge of odd-numbered channel/enabling operation: EG1m, EG0m
•
Selecting valid edge of even-numbered channel/enabling operation: EG1n, EG0n
When a valid edge is detected at pins IN0 to IN7 while 32-bit input capture operation is enabled, the
value of the 32-bit free-run timer at the time is saved to the input capture data register (IPCP0 to IPCP7).
If interrupt request generation has been enabled, an edge detection interrupt request is generated.
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MB91665 Series
Figure 19.6-1 shows the 32-bit input capture operation.
Figure 19.6-1 32-bit input capture operation
In case of ch.0 and ch.1
Value of 32-bit free-run timer
FFFF FFFFH
BFFF FFFFH
7FFF FFFFH
3FFF FFFFH
0000 0000 H
Time
Reset
IN0 pin
IN1 pin
Example of IN pin
IPCP0
Undefined
IPCP1
Undefined
Example of IPCP
Undefined
3FFFH
7FFFH
BFFFH
3FFFH
Interrupt request 0
Interrupt request 1
Example of interrupt
request
An interrupt request is generated again upon
a valid edge.
IN0 pin
: Rising edge
IN1 pin
: Falling edge
Example of IN pin : Both edges
IPCP0
: Input capture data register 0 (IPCP0)
IPCP1
: Input capture data register 1 (IPCP1)
The interrupt request is cleared by software.
<Note>
Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value
is to be saved varies depending on the free-run timer select register (FRTSEL) setting. For details,
see "18.4.1 Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 18 32-bit Free-Run Timer".
464
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CHAPTER 19 32-bit Input Capture
19.6
MB91665 Series
When a valid edge is detected, a capture signal is generated to synchronize with the internal clock
(peripheral clock). The generation of interrupt requests and the saving of 32-bit free-run timer values are
performed based on the capture signals. Figure 19.6-2 shows an example of capture signal timing.
Figure 19.6-2 Example of capture signal timing
Internal clock
(Peripheral clock)
32-bit free-run timer value
Input capture input
N
N+1
Effective edge
Capture signal
IPCP
N+1
Interrupt request
IPCP: Input capture data register (IPCP0 to IPCP7)
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19.6
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CHAPTER 20 32-bit Output Compare
This chapter explains the functions and operations of the
32-bit output compare.
20.1 Overview
20.2 Configuration
20.3 Pins
20.4 Registers
20.5 Interrupts
20.6 An Explanation of Operations and Setting Procedure
Examples
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CHAPTER 20 32-bit Output Compare
20.1
MB91665 Series
20.1 Overview
After 32-bit free-run timer counts up to the preset value, the 32-bit output compare function inverts the
level of output from a pin or generates an interrupt request.
This series microcontroller has 8 built-in channels for the 32-bit output compare.
■ Overview
The 32-bit output compare is part of the compare timer. The compare timer comprises the following
three functions:
-
32-bit free-run timer (2 channels)
-
32-bit output compare (8 channels)
-
32-bit input capture (8 channels)
See "CHAPTER 18 32-bit Free-Run Timer".
See "CHAPTER 19 32-bit Input Capture".
This chapter explains the 32-bit output compare.
•
2 channels of the 32-bit output compare can be used either independently of each other or as a pair.
If the 2 channels of the 32-bit output compare are used as a pair, comparison can be performed by 2
channels at one time and thus the CPU load can be reduced.
The combinations of channels that can be used as pairs are as follows:
-
ch.0 and ch.1
-
ch.2 and ch.3
-
ch.4 and ch.5
-
ch.6 and ch.7
•
The output levels at the OUT0 to OUT7 pins at the time of activation of the 32-bit output compare can
be set.
•
An interrupt request can be generated when the count value of the 32-bit free-run timer matches the
preset value (compare value).
•
Of the 2 channels of 32-bit free-run timer, the channel for use as the 32-bit output compare can be
selected.
For details of how to select the 32-bit free-run timer, see "18.4.1 Free-Run Timer Select Register
(FRTSEL)" in "CHAPTER 18 32-bit Free-Run Timer".
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CHAPTER 20 32-bit Output Compare
20.2
MB91665 Series
20.2 Configuration
This section explains the configuration of the 32-bit output compare.
■ 32-bit output compare block diagram
Figure 20.2-1 is a block diagram of the 32-bit output compare.
Figure 20.2-1 32-bit output compare block diagram
From the free-run timer selector
Peripheral bus
OCCP0, OCCP2
Output
Inverted circuit
Comparison circuit
IOP1
OUT0, OUT2 pins
IOP0 IOE1 IOE0
Interrupt request 0
OCCP1, OCCP3
Interrupt request 1
Comparison circuit
Output
Inverted circuit
IOP1
IOP0 IOE1 IOE0
OUT1, OUT3 pins
CMOD
Interrupt request 2
OCCP4, OCCP6
Interrupt request 3
Output
Inverted circuit
Comparison circuit
IOP1
OUT4, OUT6 pins
IOP0 IOE1 IOE0
Interrupt request 4
OCCP5, OCCP7
Interrupt request5
Comparison circuit
Output
Inverted circuit
IOP1
IOP0 IOE1 IOE0
OUT5, OUT7 pins
CMOD
Interrupt request 6
Interrupt request 7
OCCP0 to OCCP7: Output compare registers (OCCP0 to OCCP7)
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CHAPTER 20 32-bit Output Compare
20.2
•
MB91665 Series
Output compare register (OCCP0 to OCCP7)
This register sets the value (compare value) to be compared with the count value of the 32-bit free-run
timer.
•
Compare control register
This register controls the operation of the 32-bit output compare. This register is divided into the
following two registers:
•
-
Compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7)
-
Compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6)
Comparison circuit
This circuit compares the count value of the 32-bit free-run timer and the compare value that is set in
the output compare register (OCCP0 to OCCP7).
<Note>
For details of the compare timer block diagram, see "■ Compare timer block diagram" in
"CHAPTER 18 32-bit Free-Run Timer".
■ Clocks
Table 20.2-1 lists the clock used for the 32-bit output compare.
Table 20.2-1 Clock used for 32-bit output compare
Clock Name
Operation clock
470
Description
Peripheral clock (PCLK)
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CHAPTER 20 32-bit Output Compare
20.3
MB91665 Series
20.3 Pins
This section explains the pins used by the 32-bit output compare.
■ Overview
•
OUT0 to OUT7 pins
These are the output pins of the 32-bit output compare. These pins are multiplexed pins.
For details of how to use these pins as the OUT0 to OUT7 pins of the 32-bit output compare, see "2.4
Setting Method for Pins".
■ Relationship between pins and channels
Table 20.3-1 lists the relationship between channels and pins.
Table 20.3-1 Relationship between channels and pins
Channel
CM71-10158-1E
Output Pin
0
OUT0
1
OUT1
2
OUT2
3
OUT3
4
OUT4
5
OUT5
6
OUT6
7
OUT7
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CHAPTER 20 32-bit Output Compare
20.4
MB91665 Series
20.4 Registers
This section explains the configuration and functions of the registers used by the 32-bit output
compare.
■ 32-bit output compare registers
Table 20.4-1 lists the registers of the 32-bit output compare.
Table 20.4-1 Registers of 32-bit output compare
Channel
Register Name
Reference
Common
FRTSEL
Free-run timer select register
18.4.1
Common to 0 and 1
OCSH1
Compare control register upper1
20.4.2
OCSL0
Compare control register lower 0
20.4.3
OCSH3
Compare control register upper 3
20.4.2
OCSL2
Compare control register lower 2
20.4.3
OCSH5
Compare control register upper5
20.4.2
OCSL4
Compare control register lower 4
20.4.3
OCSH7
Compare control register upper7
20.4.2
OCSL6
Compare control register lower 6
20.4.3
0
OCCP0
Output compare register 0
20.4.1
1
OCCP1
Output compare register 1
20.4.1
2
OCCP2
Output compare register 2
20.4.1
3
OCCP3
Output compare register 3
20.4.1
4
OCCP4
Output compare register 4
20.4.1
5
OCCP5
Output compare register 5
20.4.1
6
OCCP6
Output compare register 6
20.4.1
7
OCCP7
Output compare register 7
20.4.1
Common to 2 and 3
Common to 4 and 5
Common to 6 and 7
472
Abbreviated
Register Name
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CHAPTER 20 32-bit Output Compare
20.4
MB91665 Series
20.4.1
Output Compare Register (OCCP0 to OCCP7)
This register sets the value (compare value) to be compared with the count value of the 32-bit free-run
timer. Set the compare value in this register before activating the 32-bit free-run timer.
Figure 20.4-1 shows the bit configuration of the output compare register (OCCP0 to OCCP7).
Figure 20.4-1 Bit configuration of output compare register (OCCP0 to OCCP7)
0
bit 31
OP31 to OP0
Attribute
R/W
Initial value
0
R/W: Read/Write
<Notes>
•
This register can be rewritten even while the 32-bit free-run timer is active.
•
The value written to this register is immediately used as a compare value. Therefore, if the
compare value is rewritten from a small value to a large value during operation of the 32-bit
free-run timer, an interrupt request is generated twice while the 32-bit free-run timer counts
once.
To prevent this problem, rewrite this register by using interrupt processing by the 32-bit free-run
timer.
•
Be sure to access this register in units of words (32 bits).
•
Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose
value is to be compared with the value set in this register varies depending on the free-run timer
select register (FRTSEL) setting. For details, see "18.4.1 Free-Run Timer Select Register
(FRTSEL)" in "CHAPTER 18 32-bit Free-Run Timer".
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CHAPTER 20 32-bit Output Compare
20.4
20.4.2
MB91665 Series
Compare Control Register Upper (OCSH1, OCSH3,
OCSH5, OCSH7)
This register is used to specify whether to use the 2 channels of the 32-bit output compare
independently of each other or as a pair. The register is also used to set the level of signals output
through the OUT0 to OUT7 pins when the 32-bit output compare function is activated.
Figure 20.4-2 shows the bit configuration of the compare control register upper (OCSH1, OCSH3,
OCSH5, OCSH7).
Figure 20.4-2 Bit configuration of compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7)
bit
15
14
13
12
11
10
9
8
Undefined
Undefined
Undefined
CMOD
Undefined
Undefined
OTD1
OTD0
Attribute
-
-
-
R/W
-
-
R/W
R/W
Initial value
X
X
X
0
X
X
0
0
R/W: Read/Write
-: Undefined
X: Undefined
[bit15 to bit13]: Undefined bits
474
In case of writing
Ignored
In case of reading
A value is undefined.
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CHAPTER 20 32-bit Output Compare
20.4
MB91665 Series
[bit12]: CMOD (output level invert mode bit)
This bit is used to specify whether to use the 2 channels of the 32-bit output compare independently of
each other or as a pair. The invert mode of wave forms output from pins changes depending on this
setting.
Written Value
Explanation
0
2 channels of the 32-bit output compare are used independently of each other.
When the compare value of the output compare register (OCCP0 to OCCP7)
matches the count value of the 32-bit free-run timer, the output level from the
corresponding pin is inverted.
1
2 channels of the 32-bit output compare are used as a pair.
When the compare value of the output compare register (OCCP0 to OCCP7)
matches the value of the 32-bit free-run timer, the invert mode is inverted as shown
below:
When the count value matches the compare value of the even-numbered channel
output compare register (OCCP0, OCCP2, OCCP4, OCCP6): the output levels
from the following pins are inverted:
- Output level from the pin corresponding to the channel
- Output level from the pin corresponding to the odd-numbered channel used as a
pair.
When the count value matches the compare value of the odd-numbered channel
output compare register (OCCP1, OCCP3, OCCP5, OCCP7): the output level
from the following pin is inverted:
- Output level from the pin corresponding to the channel
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CHAPTER 20 32-bit Output Compare
20.4
MB91665 Series
Table 20.4-2 summarizes the invert timings for output levels from OUT0 to OUT7 pins when "1" is set to
this bit.
Table 20.4-2 Output level invert timing
Register Whose Compare Value Matches the
Value of the 32-bit Free-run Timer
Pin Whose Output Level Inverts
Output compare register 0 (OCCP0)
OUT0 pin, OUT1 pin
Output compare register 1 (OCCP1)
OUT1 pin
Output compare register 2 (OCCP2)
OUT2 pin, OUT3 pin
Output compare register 3 (OCCP3)
OUT3 pin
Output compare register 4 (OCCP4)
OUT4 pin, OUT5 pin
Output compare register 5 (OCCP5)
OUT5 pin
Output compare register 6 (OCCP6)
OUT6 pin, OUT7 pin
Output compare register 7 (OCCP7)
OUT7 pin
<Notes>
•
If the same compare value is set for the even-numbered and odd-numbered channels of the 32bit output compare, the operation is the same as when the 2 channels of the 32-bit output
compare are used independently of each other, even when "1" is set to this bit.
•
Be sure to set "1" to this bit when the 2 channels of the 32-bit output compare are used as a
pair.
[bit11, bit10]: Reserved bits
In case of writing
Ignored
In case of reading
A value is undefined.
[bit9]: OTD1 (output level bit)
This bit sets the signal level output from pins (OUT1, OUT3, OUT5, OUT7) when the odd-numbered
channel of the 32-bit output compare is activated.
OTD1
In Case of Writing
0
The "L" level is output.
1
The "H" level is output.
In Case of Reading
The output level is read.
<Note>
Do not rewrite this bit during 32-bit output compare operation.
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20.4
MB91665 Series
[bit8]: OTD0 (output level bit)
This bit sets the signal level output from pins (OUT0, OUT2, OUT4, OUT6) when the even-numbered
channels of the 32-bit output compare are activated.
OTD0
In Case of Writing
0
The "L" level is output.
1
The "H" level is output.
In Case of Reading
The output level is read.
<Note>
Do not rewrite this bit during 32-bit output compare operation.
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CHAPTER 20 32-bit Output Compare
20.4
20.4.3
MB91665 Series
Compare Control Register Lower (OCSL0, OCSL2,
OCSL4, OCSL6)
This register enables or disables 32-bit output compare operation or controls interrupt requests.
Figure 20.4-3 shows the bit configuration of the compare control register lower (OCSL0, OCSL2,
OCSL4, OCSL6).
Figure 20.4-3 Bit configuration of compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6)
bit
7
6
5
4
3
2
1
0
IOP1
IOP0
IOE1
IOE0
Undefined
Undefined
CST1
CST0
R/W
R/W
R/W
R/W
–
–
R/W
R/W
0
0
0
0
X
X
0
0
Attribute
Initial value
R/W: Read/Write
–: Undefined
X: Undefined
[bit7]: IOP1 (odd-numbered channel compare match interrupt request flag bit)
This bit indicates that the compare value of the odd-numbered channel output compare register (OCCP1,
OCCP3, OCCP5, OCCP7) matches the count value of the 32-bit free-run timer.
If "1" is set to the IOE1 bit when this bit is "1", a compare match interrupt request is generated.
IOP1
In Case of Reading
In Case of Writing
0
A comparison result indicates no match.
This bit is cleared to "0".
1
A comparison result indicates a match.
Ignored
<Note>
When a read-modify-write instruction is used, "1" is read.
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MB91665 Series
[bit6]: IOP0 (even-numbered channel compare match interrupt request flag bit)
This bit indicates that the compare value of the even-numbered channel output compare register (OCCP0,
OCCP2, OCCP4, OCCP6) matches the count value of the 32-bit free-run timer.
If "1" is set to the IOE0 bit when this bit is "1", a compare match interrupt request is generated.
IOP0
In Case of Reading
In Case of Writing
0
A comparison result indicates no match.
This bit is cleared to "0".
1
A comparison result indicates a match.
Ignored
<Note>
When a read-modify-write instruction is used, "1" is read.
[bit5]: IOE1 (odd-numbered channel compare match interrupt enable bit)
This bit specifies whether to generate a compare match interrupt request when the value of the oddnumbered channel output compare register (OCCP1, OCCP3, OCCP5, OCCP7) matches the count value
of the 32-bit free-run timer (IOP1=1).
Written Value
Explanation
0
Disables generation of compare match interrupt requests.
1
Enables generation of compare match interrupt requests.
[bit4]: IOE0 (even-numbered channel compare match interrupt enable bit)
This bit specifies whether to generate a compare match interrupt request when the value of the evennumbered channel output compare register (OCCP0, OCCP2, OCCP4, OCCP6) matches the count value
of the 32-bit free-run timer (IOP0=1).
Written Value
Explanation
0
Disables generation of compare match interrupt requests.
1
Enables generation of compare match interrupt requests.
[bit3, bit2]: Undefined bits
CM71-10158-1E
In case of writing
Ignored
In case of reading
A value is undefined.
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CHAPTER 20 32-bit Output Compare
20.4
MB91665 Series
[bit1]: CST1 (odd-numbered channel compare enable bit)
This bit enables or disables the comparison between odd-numbered channel 32-bit output compare and
the count value of the 32-bit free-run timer.
Written Value
Explanation
0
Disables comparison.
1
Enables comparison.
<Note>
When the 32-bit free-run timer is stopped, the comparison of 32-bit output compare is also stopped.
[bit0]: CST0 (even-numbered channel compare enable bit)
This bit enables or disables the comparison between even-numbered channel 32-bit output compare and
the count value of the 32-bit free-run timer.
Written Value
Explanation
0
Disables comparison.
1
Enables comparison.
<Note>
When the 32-bit free-run timer is stopped, the comparison of 32-bit output compare is also stopped.
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CHAPTER 20 32-bit Output Compare
20.5
MB91665 Series
20.5 Interrupts
An interrupt request (compare match interrupt request) is generated when the count value of the 32bit free-run timer matches the value set in the output compare register (OCCP0 to OCCP7).
Table 20.5-1 outlines the interrupts that can be used with the 32bit output compare.
Table 20.5-1 Interrupts of the 32-bit output compare
Interrupt
request
Compare result
match interrupt
request
Interrupt request flag
Interrupt request
enabled
Clearing an interrupt
request
Even-numbered channel:
IOP0=1 for OCSL
Odd-numbered channel:
IOP1=1 for OCSL
Even-numbered channel:
IOE0=1 for OCSL
Odd-numbered channel:
IOE1=1 for OCSL
Write "0" to the next bit
Even-numbered
channel:
IOP0 bit for OCSL
Odd-numbered channel:
IOP1 bit for OCSL
OCSL: compare control register lower (OCSL0, OCSL2, OCSL4, OCSL6)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests.
- Clears interrupt requests before enabling the generation of interrupt requests.
- Clears interrupt requests simultaneously with interrupts enabled.
•
For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt
Vectors".
•
Use an interrupt control register (ICR00 to ICR47) to set the interrupt level corresponding to the
interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10
Interrupt Controller".
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CHAPTER 20 32-bit Output Compare
20.6
MB91665 Series
20.6 An Explanation of Operations and Setting
Procedure Examples
This section explains the 32-bit output compare operation. Also, examples of procedures for setting
the operating state are shown.
■ Overview
2 channels of the 32-bit output compare can be used either independently of each other or as a pair.
20.6.1
When the 2 Channels Are Used Independently of Each
Other
This section explains the 32-bit output compare operation when the 2 channels are used
independently of each other.
■ Overview
When the CMOD bit of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7) is set to
"0", the 2 channels of the 32-bit output compare operate independently of each other.
The output level of the pin corresponding to the channel is inverted when the count value of the 32-bit
free-run timer matches the compare value of the output compare register (OCCP0 to OCCP7).
<Note>
Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose value
is to be compared with the value set in the output compare register (OCCP0 to OCCP7) varies
depending on the free-run timer select register (FRTSEL) setting. For details, see " 18.4.1 FreeRun Timer Select Register (FRTSEL)" in "CHAPTER 18 32-bit Free-Run Timer".
■ Operation
Writing "1" to the following bit enables the 32-bit output compare operation.
•
Enabling even-numbered channel operation: CST0 bit of compare control register lower (OCSL0,
OCSL2, OCSL4, OCSL6)
•
Enabling odd-numbered channel operation: CST1 bit of compare control register lower (OCSL0,
OCSL2, OCSL4, OCSL6)
When the count value of the 32-bit free-run timer matches the compare value of the output compare
register (OCCP0 to OCCP7) while the 32-bit output compare is enabled, the following bits are set to "1":
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CHAPTER 20 32-bit Output Compare
20.6
MB91665 Series
•
Even-numbered channel: IOP0 bit of compare control register lower (OCSL0, OCSL2, OCSL4,
OCSL6)
•
Odd-numbered channel: IOP1 bit of compare control register lower (OCSL0, OCSL2, OCSL4,
OCSL6)
If interrupt request generation has been enabled, a compare match interrupt request is generated.
Also, the output levels from the OUT0 to OUT7 pins are inverted.
Figure 20.6-1 shows the operation in independent operation mode.
Figure 20.6-1 Operation in independent operation mode
Using ch.0 and ch.1 independently of each other
Count value
FFFF FFFFH
BFFF FFFFH
7FFF FFFFH
3FFF FFFFH
0000 0000 H
Time
Reset
OCCP0
BFFFH
OCCP1
7FFFH
OUT0 pin
OUT1 pin
Clearing an interrupt
request
Interrupt at ch.0
Clearing an interrupt
request
Interrupt at ch.1
Clearing an interrupt
request
Clearing an interrupt
request
Clearing an interrupt
request
Clearing an interrupt
request
OCCP0: Output compare register 0 (OCCP0)
OCCP1: Output compare register 1(OCCP1)
A compare match interrupt request or a change in the pin output level occurs upon detection of a compare
match.
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Figure 20.6-2 shows the generation of compare match interrupt requests and changes in the pin output
level.
Figure 20.6-2 Generation of compare match interrupt requests and changes in the pin output level
Peripheral clock (PCLK)
Free-run timer count value
N-1
Output compare register
(OCCP0 to OCCP7)
N
N-1
N
N
Compare match output trigger
Output level
Interrupts
Interrupts
<Note>
When using 2 channels of the 32-bit output compare independently of each other, be sure to write
"0" to the CMOD bit of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7).
20.6.2
When the 2 Channels Are Used as a Pair
This section explains the 32-bit output compare operation using the even-numbered and oddnumbered channels in pairs.
■ Overview
When the CMOD bit of the compare control register upper (OCSH1, OCSH3, OCSH5, OCSH7) is set to
"1", the 2 channels of the 32-bit output compare operate in pairs.
By using the even-numbered and odd-numbered channels of the 32-bit output compare in pairs, compare
values for 2 channels can be updated by 1 interrupt.
The combinations of even-numbered and odd-numbered channels that can be used in pairs are as follows:
484
•
ch.0 and ch.1
•
ch.2 and ch.3
•
ch.4 and ch.5
•
ch.6 and ch.7
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CHAPTER 20 32-bit Output Compare
20.6
MB91665 Series
■ Operation
Writing "1" to the following bit enables the 32-bit output compare operation.
•
Enabling even-numbered channel operation: CST0 bit of compare control register lower (OCSL0,
OCSL2, OCSL4, OCSL6)
•
Enabling odd-numbered channel operation: CST1 bit of compare control register lower (OCSL0,
OCSL2, OCSL4, OCSL6)
When the count value of the 32-bit free-run timer matches the compare value of the output compare
register (OCCP0 to OCCP7) while the 32-bit output compare is enabled, the following bits are set to "1":
•
Even-numbered channel: IOP0 bit of compare control register lower (OCSL0, OCSL2, OCSL4,
OCSL6)
•
Odd-numbered channel: IOP1 bit of compare control register lower (OCSL0, OCSL2, OCSL4,
OCSL6)
If interrupt request generation has been enabled, a compare match interrupt request is generated.
Also, the output levels from the OUT0 to OUT7 pins are inverted. The pin whose output level is inverted
varies depending on the channel of the output compare register (OCCP0 to OCCP7) whose compare value
matches the count value of the 32-bit free-run timer.
Table 20.6-1 shows the relationship between the channels for which compare values are set and the pins
whose output levels are inverted.
Table 20.6-1 Relationship between the channels for which compare values are set and
the pins whose output levels are inverted
Register Whose Compare Value Matches the Value
of the 32-bit Free-run Timer
CM71-10158-1E
Pin Whose Output Level Inverts
Output compare register 0 (OCCP0)
OUT0 pin, OUT1 pin
Output compare register 1 (OCCP1)
OUT1 pin
Output compare register 2 (OCCP2)
OUT2 pin, OUT3 pin
Output compare register 3 (OCCP3)
OUT3 pin
Output compare register 4 (OCCP4)
OUT4 pin, OUT5 pin
Output compare register 5 (OCCP5)
OUT5 pin
Output compare register 6 (OCCP6)
OUT6 pin, OUT7 pin
Output compare register 7 (OCCP7)
OUT7 pin
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CHAPTER 20 32-bit Output Compare
20.6
MB91665 Series
Figure 20.6-3 shows the operation using even-numbered and odd-numbered channels in pairs.
Figure 20.6-3 Operation using even-numbered and odd-numbered channels in pairs
Using ch.0 and ch.1 in pairs.
Count value
FFFF FFFFH
BFFF FFFFH
7FFF FFFFH
3FFF FFFFH
0000 0000 H
Time
Reset
OCCP0
BFFFH
OCCP1
7FFFH
OUT0 pin
OUT1 pin
Interrupt at ch.0
Interrupt at ch.1
Clearing an interrupt
request
Clearing an interrupt
request
Clearing an interrupt
request
Clearing an interrupt
request
Corresponding to ch.0
Corresponding to ch.0
and ch.1
Clearing an interrupt request
Clearing an interrupt
request
OCCP0: Output compare register 0 (OCCP0)
OCCP1: Output compare register 1 (OCCP1)
A compare match interrupt request or a change in the pin output level occurs upon detection of a compare
match.
See "20.6.1 When the 2 Channels Are Used Independently of Each Other" for details of the generation of
compare match interrupt requests and changes in the pin output level.
<Notes>
486
•
When using even-numbered and odd-numbered channels of the 32-bit output compare in pairs,
be sure to write "1" to the CMOD bit of the compare control register upper (OCSH1, OCSH3,
OCSH5, OCSH7).
•
Of the 2 channels of the 32-bit free-run timer, the channel of the 32-bit free-run timer whose
value is to be compared with the value set in the output compare register (OCCP0 to OCCP7)
varies depending on the free-run timer select register (FRTSEL) setting. For details, see "18.4.1
Free-Run Timer Select Register (FRTSEL)" in "CHAPTER 18 32-bit Free-Run Timer".
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 21 16-bit Reload Timer
This chapter explains the functions and operations of the
16-bit reload timer.
21.1
21.2
21.3
21.4
Overview
Configuration
Pins
Registers
21.5 Interrupts
21.6 An Explanation of Operations and Setting Procedure
Examples
21.7 Notes on Use
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CHAPTER 21 16-bit Reload Timer
21.1
MB91665 Series
21.1 Overview
The 16-bit reload timer is a down counter that performs a countdown from a preset value. This timer
can be used as an interval timer that counts down synchronously with an internal clock (peripheral
clock), and it can also be used as an event counter that counts external events.
This series has 3 built-in channels of the 16-bit reload timer.
■ Overview
•
Timer mode: Internal timer mode and event counter mode are available.
-
Interval timer mode
It counts down synchronously with an internal clock (peripheral clock). The internal clock
(peripheral clock) is selected from 6 clock types, which are peripheral clocks (PCLK) divided by
2, 4, 8, 16, 32, and 64.
-
Event counter mode
It detects and counts the edges (rising edge/falling edge/both edges) of the external clock.
Cascade mode that counts ch.0 outputs with ch.1 and ch.1 outputs with ch.2 is also available.
•
•
Operation mode: One of the following four modes can be selected.
-
Single mode: Timer counter
-
Dual mode: PPG (Programmable Pulse Generator)
-
Compare mode: PWM (Pulse Width Modulator)
-
Capture mode: PWC (Pulse Width Counter)
Input pin function: In interval timer mode, the trigger input function or gate input function can be
selected for the input pin function.
-
Trigger input function
When it detects a valid edge (rising edge/falling edge/both edges) from the input pin, it starts
counting.
-
Gate input function
It continues counting as long as the input pin maintains its effective level of input.
•
Interrupt request
An interrupt request (UF bit) can be generated when the down counter enters an underflow condition
(in all modes).
A capture interrupt (EF bit) can be generated when a retrigger is generated (in capture mode only).
A compare interrupt (EF bit) can be generated when a compare match is occurred (in compare mode
only in event counter mode).
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CHAPTER 21 16-bit Reload Timer
21.2
MB91665 Series
21.2 Configuration
This section explains the 16-bit reload timer configuration.
■ Block diagram of the 16-bit reload timer
Figure 21.2-1 is a block diagram of the 16-bit reload timer.
Read/Write
Mode control
MOD0
Read/Write
Reload selector
Peripheral bus
Figure 21.2-1 Block diagram of the 16-bit reload timer
TMRLRA
Read only
buffer
RELD
Capture mode
TMRLRB
Read/Write
MOD1
Reload
INTE
TMR
UF
Compare
mode
Count
comparator
Capture
Underflow
Interrupt
request
Compare
result
EF
End of one shot
OUTL
Peripheral clock
(PCLK)
Count
control
Counting enabled
Trigger
Trigger
Output
FF
TMO pin
CNTE
TRG
Gate
CSL2
CSL1
Clock select
circuit
Select
CSL0
GATE
Prescaler
Edge
Control
Peripheral clock
(PCLK)
TMI pin
Peripheral clock
(PCLK)
CM71-10158-1E
Input +
Synchronization
FF
Gate
Control
TRGM1
Select
TRGM0
TMCSR
The bits are in random order.
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CHAPTER 21 16-bit Reload Timer
21.2
•
MB91665 Series
Timer control status register (TMCSR0 to TMCSR2)
This register controls the operations of the 16-bit reload timer.
•
16-bit timer reload register A/B (TMRLRA0 to TMRLRA2/TMRLRB0 to TMRLRB2)
This register sets the reload values.
•
16-bit timer register (TMR0 to TMR2)
This register operates as a down counter. When this register is read, the down counter value can be
read.
•
Prescaler
•
Clock select circuit
When the interval timer mode is selected, the prescaler divides the peripheral clock (PCLK).
The clock select circuit selects a count clock.
•
Edge controller
The edge controller controls the detection edges of signals when the TMI0 to TMI2 pins are used as
trigger input pins.
•
Gate controller
The gate controller controls the signal levels of the signals input from the pins when the TMI0 to
TMI2 pins are used as gate input pins.
•
Count controller
The count controller controls the counts of the 16-bit reload timer.
■ Clocks
Table 21.2-1 shows the clock used for the 16-bit reload timer.
Table 21.2-1 Clock used for the 16-bit reload timer
Clock Name
490
Description
Remarks
Operation clock
Peripheral clock (PCLK)
-
Count clock
Internal clock (peripheral
clock)
Created through division of the
peripheral clock (PCLK).
External clock
Input from TMI0 to TMI2 pins
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CM71-10158-1E
CHAPTER 21 16-bit Reload Timer
21.3
MB91665 Series
21.3 Pins
This section explains the pins of the 16-bit reload timer.
■ Overview
There are two types of 16-bit reload timer as follows.
•
TMO0 to TMO2 pins
16-bit reload timer wave form output pin
These pins are multiplexed pins. For information on using as the wave form output pin of the 16-bit
reload timer, see "2.4 Setting Method for Pins".
•
TMI0 to TMI2 pins
16-bit reload timer input pin This inputs count clock, clock, trigger, or gate depending on its setting.
These pins are multiplexed pins. For information on using as the input pin of the 16-bit reload timer,
see "2.4 Setting Method for Pins".
■ Relationship between pins and channels
Table 21.3-1 outlines the relationship between channels and pins.
Table 21.3-1 Relationship between channels and pins
Channel
CM71-10158-1E
Wave Form Output Pin
Input Pin
0
TMO0
TMI0
1
TMO1
TMI1
2
TMO2
TMI2
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CHAPTER 21 16-bit Reload Timer
21.4
MB91665 Series
21.4 Registers
This section explains the configuration and functions of registers used by the 16-bit reload timer.
■ Registers of 16-bit reload timer
Table 21.4-1 lists the registers of the 16-bit reload timer.
Table 21.4-1 Registers of 16-bit reload timer
Channel
Abbreviated
Register Name
0
TMCSR0
Timer control status register 0
21.4.1
TMRLRA0
16-bit timer reload register A0
21.4.2
TMRLRB0
16-bit timer reload register B0
21.4.2
TMR0
16-bit timer register 0
21.4.2
TMCSR1
Timer control status register 1
21.4.1
TMRLRA1
16-bit timer reload register A1
21.4.2
TMRLRB1
16-bit timer reload register B1
21.4.2
TMR1
16-bit timer register 1
21.4.3
TMCSR2
Timer control status register 2
21.4.1
TMRLRA2
16-bit timer reload register A2
21.4.2
TMRLRB2
16-bit timer reload register B2
21.4.2
TMR2
16-bit timer register 2
21.4.3
1
2
492
Register Name
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Reference
CM71-10158-1E
CHAPTER 21 16-bit Reload Timer
21.4
MB91665 Series
21.4.1
Timer Control Status Register (TMCSR0 to TMCSR2)
This register controls the operations of the 16-bit reload timer.
Figure 21.4-1 shows the bit configuration of the timer control status registers (TMCSR0 to TMCSR2).
Figure 21.4-1 Bit configuration of the timer control status registers (TMCSR0 to TMCSR2)
bit
15
14
13
12
11
10
9
8
MOD1
MOD0
TRGM1
TRGM0
CSL2
CSL1
CSL0
GATE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
EF
Undefined
OUTL
RELD
INTE
UF
CNTE
TRG
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
0
X
0
0
0
0
0
0
Attribute
Initial value
bit
Attribute
Initial value
R/W: Read/Write
-: Undefined
X: Undefined
[bit15, bit14]: MOD1, MOD0 (Mode select bits)
These bits select the operation mode of the timer as follows.
MOD1
MOD0
0
0
Single mode (timer counter)
1
Dual mode (PPG)
0
Compare mode (PWM)
1
Capture mode (PWC)
1
Operation mode
For details of the operation in each mode, see "21.6 An Explanation of Operations and Setting Procedure
Examples".
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CHAPTER 21 16-bit Reload Timer
21.4
MB91665 Series
[bit13, bit12]: TRGM1, TRGM0 (Input pin operation selection bit)
This bit selects the operation of TMI0 to TMI2 pins of the 16-bit reload timer.The meaning of this bit
varies depending whether the 16-bit reload timer is used in interval timer mode, or in event counter mode.
•
Interval timer mode (CSL2 to CSL0 = 000 to 101)
-
Select the trigger input function with TMI0 to TMI2 pins (GATE = 0).
Select an effective edge.
When the edge set with this bit is detected in the signal input from the TMI0 to TMI2 pins, the
down counter starts counting down.
-
Select the gate function with TMI0 to TMI2 pins (GATE = 1).
Select an effective level.
The down counter counts down only while the signal of the level that is set with this bit is input
from the TMI0 to TMI2 pins.
TRGM0
0
0
Edge detection disabled
"L" level
0
1
Rising edge
"H" level
1
0
Falling edge
"L" level
1
1
Both edges
"H" level
*
When the Trigger Input Is
Selected *
(GATE =0)
When the Gate Function Is
Selected
(GATE =1)
TRGM1
When "1" is written in the TRG bit, the down counter starts counting down regardless of the setting
of this bit.
•
In event counter mode (CSL2 to CSL0 = 110, 111)
Select an effective edge.
When the edge set with this bit is detected in the signal input from the TMI0 to TMI2 pins, the down
counter starts counting down.
TRGM1
TRGM0
Explanation
0
0
Setting prohibited
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
<Note>
Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE =
0).
If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless
of the value of the CNTE bit.
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[bit11 to bit9]: CSL2 to CSL0 (Count source selection bits)
This bit selects the timer mode of the 16-bit reload timer. In interval timer mode, it also selects the
division rate of the peripheral clock (PCLK), and in event counter mode, it also selects whether to use
cascade mode and whether to use the external clock.
*
CSL2
CSL1
CSL0
Explanation
0
0
0
0
0
1
Peripheral clock (PCLK) divided by 4 (= 22)
0
1
0
Peripheral clock (PCLK) divided by 8 (= 23)
0
1
1
Peripheral clock (PCLK) divided by 16 (= 24)
1
0
0
Peripheral clock (PCLK) divided by 32 (= 25)
1
0
1
Peripheral clock (PCLK) divided by 64 (= 26)
1
1
0
1
1
1
Interval timer
mode
Event counter
mode
Peripheral clock (PCLK) divided by 2 (= 21)
Cascade mode*
External clock
For information on the operation when cascade mode is selected, see "21.6.3 Operation in Cascade
Mode".
<Notes>
•
Be sure to change this bit after operation of the down counter is stopped by the CNTE bit
(CNTE = 0).
If this bit is changed at the same time that the CNTE bit is changed, this bit is changed
regardless of the value of the CNTE bit.
•
To use the 2-channel 16-bit reload timer connected in cascade, set this bit as shown below.
- Channel with smaller number: Select interval timer mode or an external clock.
- Channel with larger number: Specify cascade mode.
•
When event counter mode is selected for this bit, the setting of the GATE bit is ignored.
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[bit8]: GATE (Gate input enable bit)
When the timer mode is set to interval timer mode, this bit selects the functions to be assigned to the
TMI0 to TMI2 pins.
•
Trigger input function: When an effective edge is input from TMI0 to TMI2 pins, a countdown starts.
•
Gate function: A countdown is performed only while the effective level signal is input from TMI0 to
TMI2 pins.
Written Value
Explanation
0
Trigger input function
1
Gate function
<Notes>
•
Be sure to change this bit after operation of the down counter is stopped by the CNTE bit
(CNTE = 0).
If this bit is changed at the same time that the CNTE bit is changed, this bit is changed
regardless of the value of the CNTE bit.
•
If event counter mode is selected with CSL2 to CSL0 bits (CSL2 to CSL0 = 110/111), this bit
setting is ignored.
[bit 7]: EF (Extended interrupt flag)
This flag indicates that a compare match interrupt is generated in the compare mode (PWM) of the event
counter mode or a capture input interrupt is generated in the capture mode (PWC).
Set resource
Compare mode (PWM) in event counter
mode*
TMR = count down from TMRLRB
Capture mode (PWC)
Capture input (retrigger)
Clear resource
Writing "0" to this bit or reset
* The compare match interrupt does not occur in the interval timer mode.
Writing "1" to this bit is ignored.
In the compare mode, a set clear is performed in sync with the count clock.
When a read-modify-write instruction is used, "1" is always read.
[bit6]: Undefined bit
496
In case of writing
Ignored
In case of reading
A value is undefined.
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21.4
MB91665 Series
[bit5]: OUTL (Output polarity setting bit)
When the 16-bit reload timer is activated, this bit sets the signal level of the signals to be output from
TMO0 to TMO2 pins.
Written Value
Explanation
0
Normal polarity ("L" level)
1
Inverted polarity ("H" level)
<Note>
Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE =
0).
If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless
of the value of the CNTE bit.
[bit4]: RELD (Reload operation enable bit)
This bit selects any of the following operation modes for the 16-bit reload timer.
•
One shot mode
When the down counter enters an underflow condition, counting stops in this mode until the next
activation trigger is input.
•
Reload mode
When the down counter enters an underflow condition in this mode, the value of the 16-bit timer
reload register A (TMRLRA0 to TMRLRA2) is reloaded to the down counter so that it continues
counting.
Written Value
Explanation
0
One shot mode*
1
Reload mode
* However, in dual one-shot function, TMRLRB is reloaded simultaneously with an underflow of
TMRLRA occurs, and it continues counting. Then, the count operation is stopped simultaneously with
an underflow of TMRLRB occurs.
<Note>
Be sure to change this bit after operation of the down counter is stopped by the CNTE bit (CNTE =
0).
If this bit is changed at the same time that the CNTE bit is changed, this bit is changed regardless
of the value of the CNTE bit.
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[bit3]: INTE (Interrupt request enable bit)
This bit sets whether to generate the underflow interrupt request when the down counter underflows (UF
bit = 1).
Written Value
Explanation
0
Disables generation of underflow (UF) interrupt requests, and extended (EF)
interrupt requests.
1
Enables generation of underflow (UF) interrupt requests, and extended (EF)
interrupt requests.
[bit2]: UF (Underflow interrupt request flag bit)
This bit indicates that the down counter enters an underflow condition.
If the INTE is set to "1" when this bit is "1", an underflow interrupt request is generated.
UF
In Case of Reading
In Case of Writing
0
The down counter has not entered an
underflow condition.
This bit is cleared to "0".
1
The down counter has entered an
underflow condition.
Ignored
[bit1]: CNTE (Count operation enable bit)
This bit enables/disables the operation of the down counter.
Written Value
Explanation
0
Stops the count operation.
1
Enables the count operation (activation trigger wait).
<Note>
If "0" is written to this bit during a down counter operation, the down counter stops.
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21.4
MB91665 Series
[bit0]: TRG (Software trigger bit)
This bit activates the 16-bit reload timer through software. When "1" is written to this bit, the down
counter loads the value of the 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and starts
counting.
TRG
In Case of Writing
0
Ignored
1
Activates the 16-bit reload timer.
In Case of Reading
"0" is read.
<Notes>
•
The down counter does not operate while the CNTE bit is "0" even if "1" is written to this bit.
•
When the 16-bit reload timer operation is enabled (CNTE=1), if "1" is written to this bit, the down
counter starts regardless of the setting of TRGM1 or TRGM0 bit.
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21.4
21.4.2
MB91665 Series
16-bit Timer Reload Register A/B
(TMRLRA0 to TMRLRA2/TMRLRB0 to TMRLRB2)
This register sets the initial value of the down counter.
In reload mode, if an underflow occurs, the value of this register is reloaded to the down counter.
Figure 21.4-2 shows the bit configuration of the 16-bit timer reload register A (TMRLRA0 to
TMRLRA2) and 16-bit timer reload register B (TMRLRB0 to TMRLRB2).
Figure 21.4-2 Bit configuration of 16-bit timer reload register A (TMRLRA0 to TMRLRA2) and
16-bit timer reload register B (TMRLRB0 to TMRLRB2)
bit 15
0
D15 to D0
Attribute
R/W
Initial value
X
R/W: Read/Write
X: Undefined
TMRLRB0, 1, and 2 are used as described below by the settings of bit15, 14:MOD1, MOD0 in TMCSR
register.
Mode
MOD1
MOD0
Function of TMRLRA
Function of TMRLRB
Single mode
(timer counter)
0
0
Reload counter value
Does not use.
Dual mode (PPG)
0
1
L width (OUTL=0)
counter value
H width (OUTL=0)
counter value
Compare mode
(PWM)*2
1
0
Cycle counter value*1
H width (OUTL=0)
counter value*1
Capture mode
(PWC)
1
1
Reload counter value
Stores TMR value when a
retrigger is input.
*1 When TMRLRA is greater than TMRLRB.
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21.4
MB91665 Series
*2 The H width and L width in compare mode are as below depending on the values of TMRLRA and
TMRLRB.
-
The cycle of TMRLRA+1, and "H" width of TMRLRB when TMRLRB is smaller than TMRLRA
(OUTL=0).
TMRLRA+1
TMRLRB
The cycle of TMRLRA+1, and "L" width of TMRLRB (OUTL=1)
TMRLRA+1
-
When TMRLRB = 0
TMRLRB
(OUTL=0) "L" output is fixed
(OUTL=1) "H" output is fixed
-
When TMRLRB > TMRLRA
(OUTL=0) "H" output is fixed
(OUTL=1) "L" output is fixed
-
When TMRLRB = TMRLRA
(OUTL=0) "L" output of 1 cycle and "H" width of TMRLRB
(OUTL=1) "H" output of 1 cycle and "L" width of TMRLRB
To write/read to this register, be sure to use a 16-bit data transfer instruction.
When this register is used as a counter value, an underflow occurs after one count when 0000H is written
and 65,536 counts when FFFFH is written.
<Note>
Be sure to access this register in units of half words.
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21.4
21.4.3
MB91665 Series
16-bit Timer Register (TMR0 to TMR2)
When this register is read, the down counter value can be read.
Figure 21.4-3 shows the bit configuration of the 16-bit timer registers (TMR0 to TMR2).
Figure 21.4-3 Bit configuration of 16-bit timer register (TMR0 to TMR2)
bit 15
0
D15 to D0
Attribute
R
Initial value
X
R: Read only
X: Undefined
<Note>
Be sure to read this register in units of half words.
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CHAPTER 21 16-bit Reload Timer
21.5
MB91665 Series
21.5 Interrupts
An underflow interrupt request is generated when the down counter enters an underflow condition.
■ Overview
Table 21.5-1 outlines the interrupts that can be used with the 16-bit reload timer
Table 21.5-1 Interrupts of the 16-bit reload timer
Interrupt request
Interrupt request
flag
Interrupt request
enabled
Clearing an
interrupt request
Underflow interrupt
request
UF=1 for TMCSR
INTE=1 for TMCSR
Write "0" to the UF bit
for TMCSR
Extended interrupt
request
EF=1 for TMCSR
INTE=1 for TMCSR
Write "0" to the EF bit
for TMCSR
TMCSR: timer control status register (TMCSR0 to TMCSR2)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests.
- Clears interrupt requests before enabling the generation of interrupt requests.
- Clears interrupt requests simultaneously with interrupts enabled.
•
For details of the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt
Vectors".
•
Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to
the interrupt vector number. For information on the settings of the interrupt levels, see
"CHAPTER 10 Interrupt Controller".
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21.6
MB91665 Series
21.6 An Explanation of Operations and Setting
Procedure Examples
This chapter explains the operations of the 16-bit reload timer. Also, examples of procedures for
setting the operating state are shown.
■ Overview
The 16-bit reload timer is a down counter that counts down from a preset value.One of the following
timer modes can be selected using the CSL2 to CSL0 bits of the timer control status register (TMCSR0 to
TMCSR2).
•
Interval timer mode (CSL2 to CSL0 = 000 to 101)
It operates with the count clock, which is the divided peripheral clock (PCLK).
•
Event counter mode (CSL2 to CSL0 = 110, 111)
In this mode, the counter counts every time an effective edge is input from TMI0 to TMI2 pins.
Cascade mode that counts ch.0 outputs with ch.1 and ch.1 outputs with ch.2 is also available.
■ How to set the signal level of the signals output from TMO0 to TMO2 pins.
The signal level of the signals output from TMO0 to TMO2 pins varies with the settings of OUTL bit of
the timer control status register (TMCSR0 to TMCSR2).
Figure 21.6-1 shows the OUTL bits and their output wave forms.
Figure 21.6-1 TMO output other than compare mode (PWM)
Mode
OUTL
Initial
value
trigger
Counting
UF
UF
UF
A
Single mode
(timer counter)
at one-shot
Single mode
(timer counter)
at reload
0
trigger wait state
1
A
A
A
A
B
trigger wait
state
A
B
A
0
1
0
Dual mode (PPG)
at one-shot
1
0
Dual mode (PPG)
at reload
1
* When the timer output is enabled in capture mode, the timer output waveform is same as in single
mode.
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The following figure, CMP (compare match) shows the timing of a down counter generation from
TMRLRB = TMR.
Figure 21.6-2 TMO output in compare mode (PWM)
Mode
OUTL
Compare mode (PWM)
at one-shot
(TMRLRB < TMRLRA)
0
Compare mode (PWM)
at one-shot
(TMRLRB = TMRLRA)
0
Initial
value
trigger
Counting
CMP
Counting
UF
CMP
A
trigger wait state
1
A
trigger wait state
1 count
1
A
Compare mode (PWM)
at reload
(TMRLRB < TMRLRA)
0
1
A
1 count
0
Compare mode (PWM)
at reload
(TMRLRB = TMRLRA)
1
Mode
OUTL
Compare mode (PWM)
at one-shot
(TMRLRB > TMRLRA)
0
Compare mode (PWM)
at one-shot
(TMRLRB = 0)
0
Initial
value
trigger
Counting
H clip
Compare mode (PWM)
at reload
(TMRLRB > TMRLRA)
Compare mode (PWM)
at reload
(TMRLRB = 0)
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1 count
UF
Counting
A
trigger wait state
1
L clip
A
trigger wait state
H clip
A
1
0
1
0
L clip
A
1
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21.6
21.6.1
MB91665 Series
Operation in Interval Timer Mode
This section explains the operation for using the 16-bit reload timer that counts synchronously with the
internal clock (peripheral clock) in interval timer mode.
The count clock is generated by dividing the peripheral clock (PCLK).
■ Setting
This section also explains the settings required for using the 16-bit reload timer in interval timer mode.
● Interval timer mode settings
To use the 16-bit reload timer in interval timer mode, make any of the following settings for the CSL2 to
CSL0 bits of the timer control status register (TMCSR0 to TMCSR2), and select the division rate of the
peripheral clock (PCLK).
506
CSL2
CSL1
CSL0
Timer Mode
0
0
0
0
0
1
Divided by 4 (= 22)
0
1
0
Divided by 8 (= 23)
0
1
1
Divided by 16 (= 24)
1
0
0
Divided by 32 (= 25)
1
0
1
Divided by 64 (= 26)
Interval timer mode
Division Rate of
Peripheral Clock
Divided by 2 (= 21)
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21.6
MB91665 Series
● Selection of the counter operation
The mode selection bit (bit15,14:MOD1, MOD0 in TMCSR register) and the reload operation enable bit
(bit4:RELD in TMCSR register) select the operation when an underflow of the counter is generated.
For details of the operations in each mode, see the section for operations.
MOD1
MOD0
Mode
RELD
0
0
Single mode
(timer counter)
0 (one-shot)
Dual mode
(PPG)
0 (one-shot)
1
1 (reload)
0
1
Stops counting at FFFFH
Reloads TMRLRA
1. Reloads TMRLRB
*
2. Stops counting at FFFFH
1 (reload)
1
Operation of when an underflow is
generated
Compare mode
(PWM)
0 (one-shot)
Capture mode
(PWC)
0 (one-shot)
1 (reload)
1 (reload)
Reloads TMRLRA and TMRLRB alternately
Stops counting at FFFFH
Reloads TMRLRA
Stops counting at FFFFH
Reloads TMRLRA
* For details, see "● Dual mode (PPG) one-shot operation".
The typical output waveforms that can be output by this timer are shown as below.
Figure 21.6-3 TMO output waveforms in each mode (OUTL=0)
Single mode (timer counter)
one-shot
TMO output
Activation trigger
Single mode (timer counter)
reload
Underflow
TMO output
Capture to TMLRB
Decrement from TMRLRA
(pulse width TMRLRA+1)
Decrement from TMRLRB
(Pulse width TMRLRB+1)
Dual mode (PPG) one-shot
Interrupts can be
generated (UF bit set)
TMO output
Calculation method of pulse width
Pulse width = T × (L+1)
T Cycle of clock for counting
L 16-bit timer reload register A/B
(TMRLRA,TMRLRB)
Dual mode (PPG) reload
TMO output
Compare mode (PWM) reload
TMO output
TMRLRA > TMRLRB
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PWC mode shows capture input, counter value, and the value of capture register.
Figure 21.6-4 Operation in capture mode (PWC)
Capture mode (PWC) reload
Activation trigger
Capture input
(TMI enable edge)
TMI input
Underflow
Counter value
TMRLRA...CNT_a
reload
TMRLRA......
TMRLRA...CNT_b
reload
reload
0
TMRLRA......
CNT_a
TMRLRB register
Decrement from TMRLRA
Interrupts can be generated
(UF bit set)
Interrupts can be generated
(EF bit set)
CNT_b
* When a rising edge is specified as an
enable edge.
● TMI0 to TMI2 pin function settings
Using TRGM1 and TRGM0 bits of the timer control status register (TMCSR0 to TMCSR2) and the
GATE bit, the function of TMI0 to TMI2 pins can be selected from the following list.
Table 21.6-1 shows the combination of bits.
Table 21.6-1 Combination of bits
TRGM1,
TRGM0
508
GATE
Pin Function
00
0
TMI0 to TMI2 pins do not work.
01
0
TMI0 to TMI2 pins operate as the trigger input function.
The effective edge is a rising edge.
10
0
TMI0 to TMI2 pins operate as the trigger input function.
The effective edge is a falling edge.
11
0
TMI0 to TMI2 pins operate as the trigger input function.
The effective edge is both edges.
00/10
1
TMI0 to TMI2 pins operate as the gate input function.
The effective level is "L".
01/11
1
TMI0 to TMI2 pins operate as the gate input function.
The effective level is "H".
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21.6
MB91665 Series
■ Activate
The counter enters the activation trigger wait state when "1" is written to bit1: CNTE bit in TMCSR
register.
•
TMI input is in the trigger input function
In the activation trigger wait state, when "1" is written to bit0:TRG bit in TMCSR register or when an
external trigger is input by TMI input, a clear of a prescaler is generated, and the timer performs
decrementing operation by loading a value from the reload register, TMRLRA.
For TMI input, input a pulse greater than 2×T (T indicates a peripheral clock (PCLK) cycle).
The following figure shows the timer activation.
Figure 21.6-5 Timer activation (when in trigger input function and in selecting rising edge trigger)
Peripheral clock
(PCLK)
CNTE (register)
TMI pin
Effective edge of
TMI pin
Prescaler clear
Prescaler clock
Data load
Counter value
•
TMRLRA
-1
-1
-1
When TMI input is in the gate input function
During the activation trigger wait state, when "1" is written to bit0:TRG bit in TMCSR register, a
clear of a prescaler is generated, and it enters the effective input polarity state. In the effective input
polarity state, when there is a gate input of an effective polarity from TMI input, the timer performs
decrementing operation.
For TMI input, input a pulse greater than 2×T (T indicates a peripheral clock (PCLK) cycle).
Figure 21.6-6 Activation of the timer (in gate input function)
Peripheral clock
(PCLK)
CNTE (register)
TRG (register)
Prescaler clear
Prescaler clock
Data load
TMI pin
Counter value
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■ Operation
● Retrigger
A trigger generated during counting operation of the timer is called a retrigger, and the following
operations are performed.
1. TMO output is initialized when the timer output (TMO) is enabled.
2. The value of the reload register (TMRLRA) is loaded to the counter.
3. The prescaler is cleared.
4. Count operation is continued.
•
TMI input is in trigger input function
Figure 21.6-7 Operation when a retrigger is generated
(TMI is at trigger input, rising edge trigger, and one-shot output)
Count clock
TMI pin
Effective edge
of TTRG pin
Retrigger
TRG
(register)
Trigger
CNTE
(register)
Prescaler
clear
Count value
-1
TMRLRA
-1
TMRLRA
-1
-1
-1
TMO pin
(OUTL=0)
•
TMI input is in gate input function
Figure 21.6-8 Operation when a retrigger is generated
(TMI is at gate input, counting at H level, and one-shot output)
Count clock
TMI pin
CNTE
(register)
Prescaler
clear
Count value
TRG (register)
TMRLRA
-1
-1
-1
TMRLRA
-1
-1
-1
Retrigger
TMO pin
(OUTL=0)
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MB91665 Series
The value of counting is transferred to TMRLRB when a retrigger is generated, and EF bit in TMCSR
register is set only in capture mode.
● Underflow/Reload
When the timer starts decrementing from 0000H, the transition is detected as an underflow. When an
underflow is generated, bit2:UF bit in TMCSR register is set.
The timer generates an underflow when "the setting value of the reload register +1" is counted.
● Generating interrupt requests
Interrupts are generated when bit3:INTE bit in TMCSR register is "1", and when bit2:UF bit/bit7:EF bit
are set.
In interval timer mode, UF bit/EF bit are set under the following conditions.
UF bit is set: When an underflow of the counter is generated.
EF bit is set: When a capture input is generated in capture mode (PWC).
An example of the interrupt request generation is shown below.
Figure 21.6-9 UF interrupt request output operation (bit4:RELD=1, bit3:INTE=1 in TMCSR register)
Count clock
Counter value
0001H
0000H
TMRLRA
-1
-1
-1
Underflow
UF bit
Interrupt
request
● Simultaneous operation of register write and timer operation
The operations to be executed when the register write operation by a user and the timer operation occur at
the same time are shown in the following table.
User operation
Timer operation
Operation to be executed
Clear operation by writing "0"
to UF bit
Setting of UF bit
Setting of UF bit
(writing "0" is ignored)
Clear operation by writing "0"
to EF bit
Setting of EF bit
Setting of EF bit
(writing "0" is ignored)
Write operation to reload
register
Load of timer by retrigger
Reload the old data
(The changed value is reloaded
at next reloading)
The details of operation for each setting are explained below.
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MB91665 Series
● Single mode (timer counter) one-shot operation
When bit15,14:MOD1, MOD0=00, and bit4:RELD=0 in TMCSR register, the timer performs the single
mode (timer counter) one-shot operation, which stops at FFFFH due to generation of an underflow.
The timer performs the following operations when an underflow occurs while single mode (timer counter)
one-shot is set.
•
UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
Counting is stopped at FFFFH
•
TMO output is initialized when the timer output is enabled
•
The timer enters the trigger wait state
In single mode (timer counter) one-shot operation, TMRLRA becomes an initial value of the counter at
reloading.
TMRLRB is not used.
Figure 21.6-10 Underflow operation details (at selecting trigger input and rising edge trigger)
Count clock
TMI pin
Effective edge
of TMI pin
Counter
value
0001H
0000H
FFFFH
TMRLRA
-1
-1
Underflow
UF bit
TMO pin
(OUTL=0)
Reload
Activation
trigger wait
count operation
Figure 21.6-11 Single mode (timer counter) one-shot operation
(at selecting GATE=0:trigger input and rising edge trigger)
Underflow
TMO pin
(OUTL=0)
CNTE
(register)
TMI pin
Effective edge
of TMI pin
Activation
trigger wait
count operation
512
TMRLRA+1
count
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
Figure 21.6-12 Single mode (timer counter) one-shot operation
(GATE=1:gate input, and TRGM:H input period count)
Underflow
TMO pin
(OUTL=0)
CNTE (register)
TMI pin
TRG (register)
activation
trigger wait
Effective gate
input wait count
operation
TMRLRB+1
count
TMRLRB+1
count
● Single mode (timer counter) reload operation
When bit15,14:MOD1,MOD0=00, and bit4:RELD=1 in TMCSR register, single mode (timer counter)
reload is operated.
Single mode (timer counter) reload operation starts decrementing after loading the value from TMRLRA
to the timer by trigger input. When an underflow is generated, the value is reloaded from TMRLRA again
and decrementing is continued. The value of TMRLRA indicates the time that the timer reloads.
TMRLRB register is not used.
While single mode (timer counter) reload is set, the following operations are performed when an
underflow is generated.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
TMRLRA register is loaded to the register
•
TMO output is inverted when the timer output is enabled
•
Decrementing is continued
Figure 21.6-13 Single mode (timer counter) reload operation (GATE=0:trigger input)
Register reloaded
by timer
TMRLRA
TMRLRA
TMRLRA
TMRLRA
TMRLRA
TMRLRA
TMRLRA
Underflow
UF bit
TMO pin
(OUTL=0)
CNTE
(register)
TMRLRA+1
Count
...
...
...
...
TMRLRA+1
Count
TMRLRA+1
Count
TMRLRA+1
Count
TMRLRA+1
Count
...
TMRLRA+1
Count
...
TMRLRA+1
Count
Data load
TRG (register)
Activation trigger
wait count
operation
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Figure 21.6-14 Single mode (timer counter) reload operation
(GATE=1:gate input, TRGM:H input period count)
Register loaded
by timer
TMRLRA
TMRLRA
TMRLRA
TMRLRA TMRLRA
TMRLRA
Underflow
UF bit
...
...
TMRLRA+1
Count
TMO pin
(OUTL=0)
TMRLRA+1
Count
TMRLRA+1
Count
...
TMRLRA+1
Count
... ...
TMRLRA+1
Count
TMRLRA+1
Count
TMI pin
CNTE
(register)
Data load
TRG (register)
Activation trigger wait
Effective gate input
wait count operation
● Dual mode (PPG) one-shot operation
When bit15,14:MOD1,MOD0=01, bit4:RELD=0 in TMCSR register, the timer performs dual mode
(PPG) one-shot operation.
In dual mode (PPG) one-shot operation, the value is loaded to the counter one time each from TMRLRA
and TMRLRB respectively, and each value is decremented, and counting is stopped when the second
underflow occurs.
When bit6:OUTL=0, the value of TMRLRA indicates the time from activation of the timer ("L" level for
TMO output) until TMO output toggles to H, and the value of TMRLRB indicates the time of "H" width
of TMO output.
The pulse shown in the following figure is generated (operates as PPG).
H width=TMRLRB
Trigger
TMO pin
Delay
= TMRLRA
The following operations are performed when the first underflow (UF-A) is generated.
514
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
TMRLRB is loaded to the counter
•
TMO output is inverted
•
Decrementing from TMRLRB is started
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MB91665 Series
The following operations are performed when the second underflow (UF-B) is generated.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
Counting is stopped at FFFFH
•
TMO output is initialized
•
The timer enters in activation wait state
Figure 21.6-15 Dual mode (PPG) one-shot operation (at selecting trigger input and rising edge trigger)
...
Count clock
...
...
UF-A
Underflow
UF bit
...
UF-B
...
UF-A
...
CNTE (register)
TMI pin
Effective edge
of TMI pin
TMO pin
(OUTL=0)
Activation
trigger wait
Register
reloaded by timer
Counter
value
TMRLRA + 1
count
TMRLRB + 1
count
TMRLRA
A:TMRLRA
B:TMRLRB
A -1 . . .
Activation
trigger wait
TMRLRA
TMRLRB
0 B -1 -1 -1 -1 . . .
0
TMRLRB + 1
count
TMRLRA + 1
count
FFFFH
A -1 . . .
TMRLRB
0 B -1 -1
Figure 21.6-16 Dual mode (PPG) one-shot operation (gate input)
Count clock
...
Underflow
...
...
UF-A
UF bit
UF-B
...
...
TMRLRA + 1
TMRLRB + 1
count
count
Activation
trigger wait
UF-A
CNTE
(register)
TRG (register)
TMI pin
TMO pin
(OUTL=1)
Activation
trigger wait
Register loaded
by timer
Counter value
CM71-10158-1E
TMRLRA
A:TMRLRA
B:TMRLRB
A -1 . . .
TMRLRB
0 B -1 -1 -1 -1 . . .
0
TMRLRA + 1
TMRLRA
FFFFH
FUJITSU SEMICONDUCTOR LIMITED
TMRLRB + 1
count
count
A -1 . . .
TMRLRB
0 B
-1
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MB91665 Series
● Dual mode (PPG) reload operation
When bit15,14:MOD1,MOD0=01, and bit4: RELD=1 in TMCSR register, the timer performs dual mode
(PPG) reload operation.
Dual mode (PPG) reload operation is a function to load and decrement TMRLRA and TMRLRB
alternately as follows. TMRLRA is loaded to the counter and decremented, and when an underflow is
generated, TMRLRB is loaded to the counter and decremented, and when the underflow is generated,
TMRLRA is loaded and decremented....
When bit5:OUTL=0, the value of TMRLRA indicates the time from activation of the timer ("L" level for
TMO output) until TMO output toggles to "H", and the value of TMRLRB indicates the time of "H"
width of TMO output.
The following operations are performed when an underflow (UF-A) is generated at decrementing after the
value is loaded from TMRLRA.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
TMRLRB is loaded to the counter
•
TMO output is inverted
•
Decrementing from TMRLRB is started
The following operations are performed when an underflow (UF-B) is generated at decrementing after the
value is loaded from TMRLRB.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
TMRLRA is loaded to the counter
•
TMO output is inverted
•
Decrementing from TMRLRA is started
Figure 21.6-17 Dual mode (PPG) reload operation (GATE=0: trigger input)
Register reloaded
by timer
A:TMRLRA
B:TMRLRB
A
B
A
B
UF-B
Underflow
UF-A
UF bit
...
B
A
B
UF-B
UF-A
...
A
...
A
UF-B
UF-A
... ... ...
UF-A
...
TMO pin
(OUTL=0)
CNTE (register)
Data load
TRG (register)
Activation
trigger wait
Count from TMRLRA
Count from TMRLRB
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MB91665 Series
Figure 21.6-18 Dual mode (PPG) reload operation (GATE=1:gate input and "H" input period count)
Register
reloaded by
timer
Underflow
A:TMRLRA
B:TMRLRB
B
A
A
B
A
B
UF-B
UF-A
...
UF bit
A
UF-B
UF-A
...
UF-A
...
...
TMI pin
(OUTL=0)
TTRG (pin)
CNTE (register)
Data load
TRG (register)
Activation trigger wait
Effective gate input wait
Count from TMRLRA
Count from TMRLRB
● Compare mode (PWM) one-shot operation
When bit15,14:MOD1, MOD0=10, and bit4:RELD=0 in TMCSR register, compare mode (PWM) oneshot operation, which compares the counter value and the value of TMRLRB register in each time of
decrementing. After accepting the trigger, the value in TMRLRA register is loaded and decrementing is
started. TMO output is inverted if the value is decremented from the compare match (TMR = TMRLRB).
When an underflow is generated, the count operation is stopped, TMO output is initialized, and the
counter enters the activation trigger wait state.
The value of TMRLRA indicates the time from activation of the timer until it stops, and the value of
TMRLRB indicates the counter value which starts to output the H width of TMO output. When OUTL=0,
TMO outputs "H" level if TMR < TMRLRB.
The timer can be used as PWM.
Trigger
input
TMRLRB = H width
TMO
pin
TMRLRA = cycle
The following operations are performed from the beginning of decrementing until TMR = TMRLRB
(when TMR ≥ TMRLRB).
•
The timer continues counting
The following operations are performed when a down count is generated from TMR = TMRLRB.
•
CM71-10158-1E
The timer continues counting
(During the compare operation in interval timer mode, bit7:EF bit in TMCSR register is not set.)
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The following operations are performed when an underflow is generated.
•
bit2:UF in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
The timer is stopped at FFFFH
•
The timer enters the activation trigger wait state
The operations of the compare function vary depending on the setting relationship of TMRLRA and
TMRLRB.
•
Setting TMRLRB < TMRLRA
When the relationship of the registers is as above, TMO output is "L" level from loading to the timer
until TMR = TMRLRB. When decrementing from the compare match (TMR = TMRLRB), the level
becomes "H" until inverting the TMO output and an underflow is generated. When the underflow is
generated, TMO output is initialized. The timer stops the counting operation due to the underflow, and
it enters the activation trigger wait state (when OUTL=0).
Figure 21.6-19 Compare mode (PWM) one-shot operation (TMRLRB < TMRLRA)
Count clock
...
...
...
Underflow
UF bit
...
Reload
TMO pin
(OUTL=0)
Activation
trigger
Count from
compare match
Register
reloaded
by timer
518
TMRLRA + 1
count
TMRLRB
count
Activation
trigger wait
TMRLRA
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
•
Setting TMRLRB > TMRLRA
When the relationship of the registers are as above, when loading to the timer is operated, TMO
output becomes "H" level from the activation trigger is generated until an underflow is generated
because TMR < TMRLRB. The timer enters the activation trigger wait state due to generation of the
underflow, and TMO output becomes "L" level (when OUTL=0).
Figure 21.6-20 Compare mode (PWM) one-shot operation (TMRLRB > TMRLRA)
...
Count clock
Register reloaded
by timer
...
TMRLRA
TMRLRA
TMRLRA+1
TMRLRA+1
Underflow
TMO pin
(OUTL=0)
Activation
trigger wait
Activation
trigger
•
Activation
trigger wait
Setting TMRLRB = TMRLRA
When the relationship of the registers is as above, TMO output outputs "L" level for 1 count from
decrementing, and outputs "H" level until an underflow is generated because the relationship becomes
TMR < TMRLRB by counting 1 after loading to the timer. The timer enters the activation trigger wait
state due to generation of the underflow, and TMO output becomes "L" level (OUTL=0).
Figure 21.6-21 Compare mode (PWM) one-shot operation (TMRLRB = TMRLRA)
Register reloaded
by timer
Count clock
TMRLRA
TMRLRA
...
...
Underflow
TMO pin
(OUTL=0)
Activation
trigger
CM71-10158-1E
1 count
1 count
TMRLRA+1
Activation
trigger wait
TMRLRA+1
Activation
trigger wait
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CHAPTER 21 16-bit Reload Timer
21.6
•
MB91665 Series
Setting TMRLRB = 0
When the relationship of the register is as above, TMO output becomes "L" level from the start of
decrementing until generation of an underflow because the relationship does not become TMR <
TMRLRB. The output is continued to be "L" level after the underflow is generated (when OUTL=0).
Figure 21.6-22 Compare mode (PWM) one-shot operation (TMRLRB=0)
Count clock
...
...
Register reloaded
by register
TMRLRA
TMRLRA
Underflow
TMO pin
(OUTL=0)
H
L
Activation
trigger wait
TMRLRA+1
Activation
trigger wait
TMRLRA+1
Activation
trigger wait
Activation
trigger
● Compare mode (PWM) reload operation
When bit15,14:MOD1,MOD0=10, and bit4: RELD=1 the timer compares the counter value (TMR) and
the value of TMRLRB in every decrementing, and it inverts TMO output when decrementing from the
compare match (TMR = TMRLRB). When an underflow is generated, the timer loads the value from
TMRLRA, and performs compare mode (PWM) reload operation, which operates decrementing. Loading
to the counter is from TMRLRA.
The value of TMRLRA indicates the counter cycle from activation of the timer until reloading, and the
value of TMRLRB indicates the "H" level width after TMO output is inverted from "L" level output to
"H" level output.
When TMR +1 = TMRLRB, TMO output is inverted and becomes "H" level (when OUTL=0).
The timer can be used as PWM.
H width = TMRLRB
TMO
pin
Cycle = TMRLRA
The following operations are performed from the beginning of decrementing until TMR = TMRLRB
(when TMR ≥ TMRLRB).
•
Counting is continued
The following operations are performed when decrementing from TMR = TMRLRB.
•
520
Counting is continued
(During the compare operation in interval timer mode, bit7:EF bit in TMCSR register is not set.)
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MB91665 Series
The following operations are performed when an underflow is generated.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
The value is reloaded from TMRLRA
•
The timer continues counting
The operations of the compare operation vary depending on the setting relationship of TMRLRA and
TMRLRB.
•
Setting TMRLRB < TMRLRA
When the relationship of the registers is as follows, TMO output becomes "L" level from loading to
the timer until the relationship becomes TMR = TMRLRB. When decrementing from the compare
match (TMR = TMRLRB), the level becomes "H" until the TMO output is inverted and an underflow
is generated. TMO output is initialized when the underflow occurs. The timer operates reloading from
TMRLRA and the counting operation is continued due to the underflow (when OUTL=0).
Figure 21.6-23 Compare mode (PWM) reload operation (TMRLRB < TMRLRA) trigger input
Count clock
...
...
...
...
...
...
Underflow
UF bit
...
...
...
Reload
TMO pin
(OUTL=0)
TMRLRA + 1
count
TMRLRB
count
TMRLRA + 1
count
TMRLRB
count
TMRLRA + 1
count
TMRLRB
count
...
...
Decrement from
compare match
EF bit
Register
reloaded
by timer
CM71-10158-1E
...
TMRLRA
TMRLRA
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TMRLRA
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CHAPTER 21 16-bit Reload Timer
21.6
•
MB91665 Series
Setting TMRLRB > TMRLRA
When the relationship of the registers is as above, TMO output is "H" level from generation of the
activation trigger until an underflow is generated because the relationship is always TMR <
TMRLRB. Even after the underflow occurs, TMO output is continued to be "H" level. The timer
performs loading from TMRLRA due to the underflow, and continues the count operation (when
OUTL=0).
Figure 21.6-24 Compare mode (PWM) reload operation (TMRLRB > TMRLRA) trigger input
...
Count clock
Register reloaded
by timer
...
TMRLRA
TMRLRA
...
TMRLRA
Underflow
UF bit
TMO pin
(OUTL=0)
TMRLRA+1
...
...
TMRLRA+1
TMRLRA+1
Activation
trigger
•
Setting TMRLRB = TMRLRA
When the relationship of the registers is as above, TMO output outputs "L" level for 1 count of
decrementing, and outputs "H" level until an underflow is generated.
The timer performs loading from TMRLRA due to generation of the underflow, and continues the
counting operation. TMO output becomes "L" level (when OUTL=0).
Figure 21.6-25 Compare mode (PWM) reload operation (TMRLRB = TMRLRA) trigger input
Register reloaded
by timer
Count clock
TMRLRA
...
TMRLRA
TMRLRA
...
...
Underflow
UF bit
TMO pin
(when OUTL=0)
...
1 count
1 count
TMRLRB
1 count
...
1 count
TMRLRB
TMRLRB
TMRLRA+1
TMRLRA+1
TMRLRA+1
...
...
Decrement from
compare match
EF bit
L
Activation
trigger
522
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...
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
•
Setting TMRLRB = 0
When the relationship of the register is as above, TMO output is "L" level from the start of
decrementing until generation of an underflow because the relationship does not become TMR <
TMRLRB after loading to the timer. The output is continued to be "L" level after the underflow is
generated.
Figure 21.6-26 Compare mode (PWM) reload operation (TMRLRB = 0) trigger input
Count clock
...
Register reloaded
by timer
TMRLRA
...
...
TMRLRA
TMRLRA
Underflow
...
UF bit
TMO pin
(OUTL=0)
H
L
TMRLRA+1
...
TMRLRA+1
TMRLRA+1
Activation
trigger
● Capture mode (PWC) operation
When bit15,14:MOD1, MOD0=11 in TMCSR register, the timer operates the capture operation.
When a retrigger is generated, the value of TMR at that point is captured in TMRLRB, and bit7:EF in
TMCSR register is set.
If using TMI input as a gate input (when bit8:GATE=1 in TMCSR register), generate a retrigger by
bit0:TRG in TMCSR register.
Figure 21.6-27 Capture function (RELD=1)
TMI pin
retrigger
TMI pin
trigger input
Counter value
TMRLRA
Capture to
TMRLRB
0
UF interrupt
&
Reload
(from TMRLRA)
EF interrupt
&
Capture (to TMRLRB)
&
Reload (from TMRLRA)
In other mode, a capture is not performed during a retrigger is generated. EF interrupt is not generated
either.
The operations of the timer/ TMO output are same in single mode (timer counter) one-shot function or in
single mode (timer counter) reload function.
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21.6
21.6.2
MB91665 Series
Operations in Event Counter Mode
This section explains the operations for using 16-bit reload timer as an event counter. This section
explains the operation for counting external events.
■ Overview
In event counter mode, external events input from TMI0 to TMI2 pins are counted. It performs a
countdown every time an effective edge is input from TMI0 to TMI2 pins.
For information on cascade mode, see "21.6.3 Operation in Cascade Mode".
■ Setting
● Event counter mode settings
To use the 16-bit reload timer in event counter mode, set CSL2 to CSL0 bits of the timer control status
register (TMCSR0 to TMCSR2) as shown below.
CSL2
CSL1
CSL0
1
1
1
Mode
Count Clock
Event counter mode
External clock
● Operation mode settings
Select the operations when an underflow of the counter is generated by the reload operation enabled bit
(bit4:RELD in TMCSR) and the mode select bit (bit15,14:MOD1, MOD0 in TMCSR register).
For details of the operations in each mode, see the section for operations.
MOD1
MOD0
Mode
RELD
0
0
Single mode
(timer counter)
0 (one-shot)
1 (reload)
Reloads TMRLRA
Dual mode
(PPG)
0 (one-shot)
1. Reloads TMRLRB
1
0
1
Stops counting at FFFFH
*
2. Stops counting at FFFFH
1 (reload)
1
Operations when an underflow is
generated
Compare
(PWM)
0 (one-shot)
Capture mode
(PWC)
0 (one-shot)
1 (reload)
1 (reload)
TMRLRA and TMRLRB are reloaded
alternately
Stops counting at FFFFH
Reloads TMRLRA
Stops counting at FFFFH
Reloads TMRLRA
* For details, see "● Dual mode (PPG) one-shot operation".
See Figure 21.6-1 for the output waveform of TMO0 to TMO2.
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CHAPTER 21 16-bit Reload Timer
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MB91665 Series
● Effective edge settings
The 16-bit reload timer performs a count down every time an effective edge is input from TMI0 to TMI2
pins.
The effective edge can be selected from the following settings of TRGM1 and TRGM0 bits of the timer
control status register (TMCSR0 to TMCSR2).
TRGM1, TRGM0
Pin Function
00
TMI0 to TMI2 pins do not work.
01
Rising edge
10
Falling edge
11
Both edges
■ Activate
The counter enters the activation trigger wait state when "1" is written to bit1:CNTE bit in TMCSR
register.
When "1" is written to bit0:TRG bit in TMCSR register in the activation trigger wait state, the data is
loaded from TMRLRA and the counter value becomes TMRLRA. Then, if there is an effective input to
TMI pin, the counter starts decrementing.
■ Operation
● Count operation
When an effective edge is input from TMI pin, the counter starts decrementing.
The following figure shows the counter operation of each setting of bit13,12:TRGM1, TRGM0 bits in
TMCSR register.
Figure 21.6-28 Operation of the rising edge count (TRGM1, TRGM0=01) (RELD=1, OUTL=0)
Peripheral clock
(PCLK)
TMI pin
Effective edge
of TMI pin
Count value
TMRLRA
-1
-1
-1
TRG (register)
Figure 21.6-29 Operation of the falling edge count (TRGM1, TRGM0=10) (RELD=1, OUTL=0)
Peripheral clock
(PCLK)
TMI pin
Effective edge
of TMI pin
Count value
TMRLRA
-1
-1
-1
TRG (register)
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CHAPTER 21 16-bit Reload Timer
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Figure 21.6-30 Operation of both edge count (TRGM1, TRGM0=11) (RELD=1, OUTL=0)
Peripheral clock
(PCLK)
TMI pin
Effective edge
of TMI pin
Count value
TMRLRA
-1
-1
-1
-1
-1
-1
TRG (register)
● Retrigger
While the counter is operating, the following operations are performed when a trigger is generated by
bit0:TRG bit in TMCSR register.
-
TMO output is initialized when the counter output (TMO) is enabled
-
The value of TMRLRA is loaded to the counter
-
The operation of the counter is continued
● Underflow/Reload
When the value of the counter is decremented from 0000H, the transition is detected as an underflow.
When an underflow is generated, bit2:UF bit in TMCSR register is set. When the value of bit4:RELD
is "1", reloading to the counter occurs.
The timer generates an underflow when "the setting value of the reload register +1" is counted.
● Generating interrupt request
Interrupts are generated when bit3:INTE bit in TMCSR register is "1", and when bit2:UF bit/bit7:EF
bit are set.
In event counter mode, UF bit/EF bit are set under the following conditions.
UF bit is set: When an underflow of the counter is generated.
EF bit is set: 1. When decrementing is generated from TMR = TMRLRB in compare mode.
2. The input of software trigger in capture mode (PWC).
An example of the interrupt request generation due to an underflow is shown below.
Figure 21.6-31 Interrupt request output operation (bit4:RELD=1 and bit3:INTE=1 in TMCSR register)
Event input
Counter value
0002H
0001H
0000H
TMRLRA
-1
-1
-1
-1
Underflow
UF bit
Interrupt request
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Simultaneous operation of register write and timer operation
The operations to be executed when the register write operation by a user and the timer operation
occur at the same time are shown in the following table.
User operation
Timer operation
Operation to be executed
Clear operation by writing "0"
to UF bit
Setting of UF bit
Setting of UF bit
(writing "0" is ignored)
Clear operation by writing "0"
to EF bit
Setting of EF bit
Setting of EF bit
(writing "0" is ignored)
Write operation to reload
register
Load of timer by retrigger
Reload the old data
(The changed value is reloaded
at next reloading)
The operations of each setting are explained.
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Single mode (timer counter) one-shot operation
When bit15,14:MOD1,MOD0=00, and bit4:RELD=0 in TMCSR register, the counter performs the single
mode (timer counter) one-shot operation, which stops at FFFFH due to generation of an underflow.
The timer performs the following operations when an underflow occurs while single mode (timer counter)
one-shot is set.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
Counting is stopped at FFFFH
•
TMO output is initialized when the counter output is enabled
•
The counter enters the activation trigger wait state
Figure 21.6-32 Single mode (timer counter) one-shot operation (details) (rising edge count)
Peripheral clock
(PCLK)
TMI pin
Effective edge
of TMI pin
Counter value
0001H
0000H
FFFFH
TMRLRA
-1
-1
Underflow
UF (register)
TRG (register)
Activation
trigger wait
Data load
Figure 21.6-33 Single mode (timer counter) one-shot operation (counting both edges)
Underflow
UF bit
...
TMO pin
(OUTL=0)
TMO pin
(OUTL=1)
...
TMI pin
...
...
Effective edge of
TMI pin
TRG (register)
Reload
Counter value
TMRLRA
-1
...
FFFFH
TMRLRA
-1
0000H
528
FUJITSU SEMICONDUCTOR LIMITED
...
FFFFH
0000H
CM71-10158-1E
CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Single mode (timer counter) reload operation
When bit15,14:MOD1, MOD0=00, and bit4:RELD=1 in TMCSR register, single mode (timer counter)
reload is operated.
Single mode (timer counter) reload operation starts decrementing after loading the value from TMRLRA
to the counter by trigger input. When an underflow is generated, the value is reloaded from TMRLRA
again and decrementing is continued.
TMRLRB register is not used.
While single mode (timer counter) reload is set, the following operations are performed when an
underflow is generated.
•
UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
The value of TMRLRA is loaded to the counter
•
TMO output is inverted when the counter output (TMO) is enabled
•
Decrementing is continued due to generation of an event input
Figure 21.6-34 Single mode (timer counter) reload operation (counting both edges)
Register reloaded
by timer
TMRLRA
TMRLRA
TMRLRA
TMRLRA
TMRLRA
Underflow
...
UF bit
...
...
...
TMO pin
(OUTL=0)
TMI pin
...
Effective edge
of TMI pin
...
...
...
...
...
...
...
TRG (register)
Data load
Counter value
A:TMRLRA
A
-1 . . .
A -1 . . .
A
-1
...
0000H
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
0000H
A
A
...
-1
0000H
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Dual mode (PPG) one-shot operation
When bit15,14:MOD1,MOD0=01, bit4:RELD=0 in TMCSR register, the counter performs dual mode
(PPG) one-shot operation.
In dual mode (PPG) one-shot operation, the value is loaded to the counter from TMRLRA and
decremented when there is an effective edge input from TMI input. When an underflow is generated, the
value is loaded from TMRLRB, and when an underflow is generated the counter enters the activation
trigger state.
The value of TMRLRA indicates the time from activation of the counter ("L" level for TMO when
bit5:OUTL=0) until TMO output toggles to "H" level, and the value of TMRLRB indicates the time for
outputting "H" level.
The following operations are performed when the first underflow (UF-A) is generated.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
TMRLRB is loaded to the counter
•
TMO output is inverted when the counter output is enabled
•
Decrementing from TMRLRB is started
The following operations are performed when the second underflow (UF-B) is generated.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
Counting is stopped at FFFFH
•
TMO output is initialized when the counter output is enabled
•
The timer enters the activation wait state
Figure 21.6-35 Dual mode (PPG) one-shot operation (counting both edges)
TMI pin
...
...
Effective edge
of TMI pin
Underflow
UF bit
Activation
trigger
UF-B
UF-A
Activation
trigger wait
...
Activation
trigger wait
...
TMO pin
(OUTL=0)
TMRLRB + 1
TMRLRA + 1
count
TMRLRA + 1
count
count
Register reloaded
by timer
Counter
value
530
A:TMRLRA
B:TMRLRB
TMRLRA
TMRLRA
-1
TMRLRA
TMRLRB
...
1
0
TMRLRB
-1
FUJITSU SEMICONDUCTOR LIMITED
...
1
0
FFFFH
TMRLRA
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Dual mode (PPG) reload operation
When bit15,14:MOD1, MOD0=01, and bit4: RELD=1 in dual mode (PPG) reload operation is performed,
which is a function to reload from TMRLRA and TMRLRB alternately.
The value is loaded from the counter from TMRLRA by the activation trigger input, and starts
decrementing by an effective edge input of TMI pin. When an underflow is generated due to
decrementing from TMRLRA (UF-A), the value of TMRLRB is loaded to the counter, and decrementing
operation is continued. When an underflow is generated due to decrementing from TMRLRB (UF-B), the
value is loaded from TMRLRA. Loading to the counter is performed from TMRLRA and TMRLRB
alternately every time underflows occur.
While dual mode (PPG) reload operation is set, the following operations are performed when an
underflow is generated.
The following operations are performed when UF-A, as explained above occurs.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
TMRLRB is loaded to the counter
•
Decrementing from the value of TMRLRB is started due to an event input
The following operations are performed when UF-B, as explained above occurs.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
TMRLRA is loaded to the counter
•
Decrementing from the value of TMRLRA is started due to an event input
Figure 21.6-36 Dual mode (PPG) reload operation (counting both edges)
Register reloaded
by timer
A:TMRLRA
B:TMRLRB
B
A
Underflow
UF-A
UF bit
...
B
A
UF-B
A
UF-A
...
UF-B
...
...
TMO pin
(OUTL=0)
TMI pin
...
...
...
...
Effective edge
of TMI pin
...
...
...
...
TRG (register)
Data load
Counter value
A:TMRLRA
B:TMRLRB
A
-1 . . .
0000H
CM71-10158-1E
B -1 . . .
A
-1
...
0000H
FUJITSU SEMICONDUCTOR LIMITED
B
...
A
-1
0000H
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Compare mode (PWM) one-shot operation
When bit15,14:MOD1, MOD0=10, and bit4:RELD=0 in TMCSR register, compare mode (PWM) oneshot operation, which compares the counter value and the value of TMRLRB register in each time of
decrementing. After loading the value from TMRLRA register by the activation trigger, and decrementing
is started when an effective edge of the TMI pin is input. EF bit is set and TMO output is inverted if the
value is decremented from the compare match (TMR = TMRLRB). When an underflow is generated, the
count operation is stopped, and the counter enters the activation trigger wait state.
The value of TMRLRA indicates the number of count from activation of the counter until an underflow is
generated, and the value of TMRLRB indicates the counter value which starts to output the "H" level
during counting.
When bit5:OUTL=0 is set in TMCSR register, TMO outputs "L" level if TMR ≥ TMRLRB. TMO outputs
"H" level when TMR < TMRLRB.
At comparing in event counter mode, if TMR + 1 = TMRLRB, bit7:EF bit in TMCSR register is set. At
this time, EF interrupt is generated if bit3:INTE bit in TMCSR register is "1".
From the beginning of decrementing, the following operations are performed while TMR ≥ TMRLRB.
•
The counter continues counting (wait for an effective edge input)
The following operations are performed when a decrementing is generated from TMR = TMRLRB.
•
bit7:EF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
The counter continues counting (wait for an effective edge input)
The following operations are performed when an underflow is generated.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
The counter is stopped at FFFFH
•
The counter enters the activation trigger wait state
The operations of the compare function vary depending on the setting relationship of TMRLRA and
TMRLRB.
•
TMRLRB < TMRLRA
When the relationship of the registers is as follows, TMO output becomes "L" level when OUTL =0
from loading to the counter until compare match (TMR ≥ TMRLRB), TMO output becomes "L" level
when OUTL =0.
When decrementing from the compare match (TMR = TMRLRB), TMO output is inverted, and the
level becomes "H" until an underflow is generated. EF bit is set also. TMO output is initialized when
an underflow occurs. The counting operation is stopped due to the underflow, and enters the activation
trigger wait state.
532
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
Figure 21.6-37 Compare mode (PWM) one-shot operation (TMRLRB < TMRLRA) (counting both edges)
TMI pin
...
Effective edge
of TMI pin
...
...
...
...
...
...
...
Underflow
...
UF bit
Reload
TMO pin
(OUTL=0)
Activation
trigger wait
Activation
trigger
TMRLRB
count
TMRLRA + 1
count
TMRLRB
count
TMRLRA + 1
count
Activation
trigger wait
Activation
trigger wait
Compare match from
decrementing
EF bit
...
Register
reloaded by timer
...
TMRLRA
•
TMRLRA
TMRLRB > TMRLRA
When the relationship of the registers is as above, TMO output is "H" level from the state becomes the
effective event input wait until an underflow is generated by the activation trigger because the
relationship is already TMR < TMRLRB. The level becomes "L" due to generation of an underflow.
Figure 21.6-38 Compare mode (PWM) one-shot operation (TMRLRB > TMRLRA) (counting both edges)
Register reloaded
by timer
TMRLRA
...
TMI pin
Effective edge
of TMI pin
TMRLRA
...
...
...
...
...
Underflow
UF bit
EF bit
L
...
...
...
...
TMO pin
(OUTL=0)
Activation
trigger
CM71-10158-1E
TMRLRA+1
Activation
trigger wait
TMRLRA+1
Activation
trigger wait
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Activation
trigger wait
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CHAPTER 21 16-bit Reload Timer
21.6
•
MB91665 Series
TMRLRB = TMRLRA
When the relationship of the registers is as above, TMO output outputs "L" level for 1 count of
decrementing, and outputs "H" level until an underflow is generated because the relationship becomes
TMR < TMRLRB when the counter counts once.
EF flag is set also. TMO output becomes "L" level due to generation of an underflow.
Figure 21.6-39 Compare mode (PWM) one-shot operation (TMRLRB = TMRLRA) (counting both edges)
Register reloaded
by timer
TMRLRA
TMI pin
TMRLRA
...
...
Effective edge
of TMI pin
Underflow
UF bit
...
EF bit
...
TMO pin
(OUTL=0)
1 count
Activation
trigger wait
Activation
trigger
•
1 count
TMRLRA+1
Activation
trigger wait
TMRLRA+1
Activation
trigger wait
TMRLRB = 0
When the relationship of the register is as above, TMO output is "L" level from the start of
decrementing until generation of an underflow because the relationship does not become TMR <
TMRLRB. The output is continued to be "L" level after the underflow is generated.
Figure 21.6-40 Compare mode (PWM) one-shot operation (TMRLRB = 0) (counting both edges)
Register reloaded
by timer
TMI pin
TMRLRA
TMRLRA
...
...
Effective edge
of TMI pin
Underflow
...
UF bit
EF bit
...
H
L
TMO pin
H
(OUTL=0) L
TMRLRA+1
Activation
trigger wait
TMRLRA+1
Activation
trigger wait
Activation
trigger
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CM71-10158-1E
CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Compare mode (PWM) reload operation
When bit15,14:MOD1,MOD0=10, and bit4: RELD=1, the counter loads the value from TMRLRA by the
activation trigger, and decrements every time the effective edge of TMI pin is input. The counter value
(TMR) and the value of TMRLRB are compared every counting operation, TMO output is inverted and
EF bit is set. When an underflow is generated, the timer loads the value from TMRLRA, and performs
compare mode (PWM) reload operation, which operates decrementing. When an underflow is generated,
the value is loaded from TMRLRA again and decrementing is started.
The value of TMRLRA indicates the initial value that the counter operates a downcounter, and the value
of TMRLRB indicates the counter value, which "H" width is started to output during counting. When
TMR < TMRLRB, TMO outputs "H" level (when OUTL=0).
From the beginning of decrementing, the following operations are performed while TMR ≥ TMRLRB.
•
The counter continues counting (wait for an effective edge input)
The following operations are performed when decrementing is generated from TMR = TMRLRB.
•
bit7:EF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
The counter continues counting (wait for an effective edge input)
The following operations are performed when an underflow is generated.
•
bit2:UF bit in TMCSR register is set
•
An interrupt is generated when the interrupt is enabled (bit3:INTE=1 in TMCSR register)
•
The value is reloaded from TMRLRA
•
The counter continues counting (wait for an effective edge input)
The operations of the compare function vary depending on the setting relationship of TMRLRA and
TMRLRB.
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CHAPTER 21 16-bit Reload Timer
21.6
•
MB91665 Series
Setting TMRLRB < TMRLRA
When the relationship of the registers is as above, TMO output is "L" level from loading to the
counter until compare match (TMR = TMRLRB). When decrementing from the compare match (TMR
= TMRLRB) is generated, TMO output is inverted, and the level becomes "H" until an underflow is
generated. When the underflow is generated, TMO output is initialized and becomes "L" level. The
timer reloads from TMRLRA due to an underflow and continues counting.
Figure 21.6-41 Compare mode (PWM) reload operation (TMRLRB < TMRLRA) (counting both edges)
TMI pin
...
...
...
...
...
...
Effective edge
of TMI pin
...
...
...
...
...
...
Underflow
...
UF bit
...
Reload
TMO pin
(OUT=0)
TMRLRB
TMRLRB
count
count
TMRLRA + 1
count
TMRLRB
count
TMRLRA + 1
TMRLRA + 1
count
count
Decrementing from
compare match
...
EF bit
Register
reloaded by
timer
TMRLRA
•
...
...
TMRLRA
TMRLRA
Setting TMRLRB > TMRLRA
When the relationship of the registers are as above, when loading to the counter is operated, TMO
output (when OUTL=0) becomes "H" level from the start of decrementing until an underflow is
generated because the relationship is already TMR < TMRLRB. The counter loads the value from
TMRLRA due to generation of an underflow, and continues counting. TMO output is continued to be
"H" level. When the relationship of the registers is as above, EF bit is not set.
Figure 21.6-42 Compare mode (PWM) reload operation (TMRLRB > TMRLRA) (counting both edges)
TMI pin
...
...
...
Effective edge
of TMI pin
...
...
...
Register
loaded by timer
TMRLRA
TMRLRA
TMRLRA
Underflow
...
UF bit
TMO pin
(OUTL=0)
TMRLRA+1
TMRLRA+1
...
TMRLRA+1
EF bit
Activation trigger
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CM71-10158-1E
CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
•
Setting TMRLRB = TMRLRA
When the relationship of the registers is as above, TMO output outputs "L" level for 1 count from
decrementing, and outputs "H" level until an underflow is generated because the relationship becomes
TMR < TMRLRB by counting once after loading to the counter. EF bit is set also. The counter loads
the value from TMRLRA due to generation of the underflow, and continues counting. TMO output
becomes "L" level.
Figure 21.6-43 Compare mode (PWM) reload operation (TMRLRB = TMRLRA) (counting both edges)
Register reloaded
by timer
TMRLRA
TMRLRA
TMRLRA
TMI pin
...
...
...
Effective edge
of TMI pin
...
...
...
Underflow
UF bit
...
TMO pin
(OUTL=0)
1 count
1 count
TMRLRA+1
TMRLRB
1 count
TMRLRA+1
TMRLRB
...
...
TMRLRA+1
TMRLRB
Decrementing from
compare match
EF bit
Activation
trigger
•
Setting TMRLRB = 0
When the relationship of the register is as above, TMO output becomes "L" level from the start of
decrementing until generation of an underflow because the relationship does not become TMR <
TMRLRB. The output is continued to be "L" level after the underflow is generated.
Figure 21.6-44 Compare mode (PWM) reload operation (TMRLRB=0) (counting both edges)
TMI pin
...
...
...
Effective edge
of TMI pin
...
...
...
Register
reloaded by timer
TMRLRA
TMRLRA
TMRLRA
Underflow
...
UF bit
TMO pin
(OUTL=0)
H
L
TMRLRA+1
TMRLRA+1
...
TMRLRA+1
Activation
trigger
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
● Capture mode (PWC) operation
When bit15,14:MOD1,MOD0=11 in TMCSR register, the counter operates the capture operation, which
captures the counter value when a retrigger is generated.
To use capture input in event counter mode, write "1" to bit0:TRG in TMCSR register.
When a retrigger is generated during counting, the value of TMR at this time is captured to TMRLRB
register, and bit7:EF in TMCSR register is set. Capturing can be operated either reload or one-shot mode
is selected.
For operations when an underflow is generated, see "• Single mode (timer counter) one-shot operation" or
"• Single mode (timer counter) reload operation".
Figure 21.6-45 Capture operation
TMI pin retrigger input
Counter value
TMI pin input
TMRLRA
Underflow
Capture TMR to
TMRLRB
0
UF interrupt
&
Reload (TMRLRA)
538
Underflow
EF interrupt
&
Capture (TMRLRB)
&
Reload (TMRLRA)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
21.6.3
Operation in Cascade Mode
In cascade mode, ch.1 can count the outputs from ch.0 of the 16-bit reload timer, and ch.2 can count
the outputs from ch.1. This section explains the operations in cascade mode.
■ Operation
The following shows the count operation when cascade mode is selected with the CSL2 to CSL0 bits
(CSL2 to CSL0 = 110) of the timer control status register (TMCSR0 to TMCSR2).
•
When ch.1 is connected in cascade mode
It counts the outputs from ch.0. Figure 21.6-46 shows the I/O operation when ch.1 is used in cascade
mode.
Figure 21.6-46 I/O operation when ch.1 is used in cascade mode
TMI0 pin
ch.0
TMO0 pin
TMI1 pin
ch.1
TMO1 pin
•
When ch.2 is connected in cascade mode
It counts the outputs from ch.1. Figure 21.6-47 shows the I/O operation when ch.2 is used in cascade
mode.
Figure 21.6-47 I/O operation when ch.2 is used in cascade mode
TMI1 pin
ch.1
TMO1 pin
TMI2 pin
ch.2
TMO2 pin
<Note>
In cascade mode, use the CSL2 to CSL0 bits of the timer control status register (TMCSR0 to
TMCSR2) to set the timer mode as shown below.
•
Lower number channel
Select interval timer mode or external clock (CSL2 to CSL0 = other than 110)
•
Higher number channel
Set cascade mode (CSL2 to CSL0 = 110)
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CHAPTER 21 16-bit Reload Timer
21.6
MB91665 Series
■ Underflow cycle
This section explains the calculation of the underflow cycles of ch.1 and ch.2.
•
When ch.1 is connected in cascade mode
T × (TMRLRA0 value + 1) × (TMRLRA1 value + 1)
T: Cycle of the count clock for ch.0
TMRLRA0: 16-bit timer reload register A0 (TMRLRA0)
TMRLRA1: 16-bit timer reload register A1 (TMRLRA1)
•
When ch.2 is connected in cascade mode
T × (TMRLRA1 value + 1) × (TMRLRA2 value + 1)
T: Cycle of the count clock for ch.1
TMRLRA1: 16-bit timer reload register A1 (TMRLRA1)
TMRLRA2: 16-bit timer reload register A2 (TMRLRA2)
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CHAPTER 21 16-bit Reload Timer
21.7
MB91665 Series
21.7 Notes on Use
Note the following points on using the 16-bit reload timer.
■ Notes on interrupts
If an underflow interrupt request flag is cleared at the same time that it is set to "1", the clearing of the
underflow interrupt request flag is ignored and the underflow interrupt request flag remains "1".
■ Operations for simultaneous activations
If more than one of the events used to determine the operating state of the 16-bit reload timer occur
simultaneously, the priority order of these events is shown below.
1. Register reading
2. Trigger input
3. Underflow
4. Clock count input
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CHAPTER 21 16-bit Reload Timer
21.7
542
MB91665 Series
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CM71-10158-1E
CHAPTER 22 Base Timer I/O Select
Function
This chapter explains the I/O select function of the base
timer.
22.1
22.2
22.3
22.4
22.5
CM71-10158-1E
Overview
Configuration
Pins
Registers
I/O Mode
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CHAPTER 22 Base Timer I/O Select Function
22.1
MB91665 Series
22.1 Overview
The I/O select function of the base timer determines the I/O method of the signals (external clock/
external activation trigger/wave form) to/from the base timer by setting the I/O mode.
In addition, the base timer can be used separately by channel as either of the following timers by
switching the timer function.
• 16-bit PWM timer
• 16-bit PPG timer
• 16/32-bit reload timer
• 16/32-bit PWC timer
Be sure to use the base timer after reading both this chapter and the chapter on the timer function to
be used.
■ Overview
The I/O mode can be selected from among the 9 types of modes for each 2 channels.
•
I/O mode 0: 16-bit timer standard mode
This mode operates the base timer individually, one channel at a time.
•
I/O mode 1: Timer full mode
In this mode, signals of the even-numbered channel of the base timer are allocated to the external pins
separately to operate the timer.
•
I/O mode 2: External trigger shared mode
In this mode, the external activation trigger can be input to the 2 channels of base timers at the same
time. This mode enables activating 2 channels of base timers at the same time.
•
I/O mode 3: Other channel trigger shared mode
In this mode, the external signal from other channels is input as an external activation trigger to
activate the timer. This mode cannot be set for ch.0 and ch.1.
•
I/O mode 4: Timer activation/stop mode
This mode controls activation/stop of the odd-numbered channel by using the even-numbered channel.
The odd-numbered channel is activated at the rising edge of the output signal from the evennumbered channel and stops at the falling edge.
•
I/O mode 5: Same time software activation mode
This mode activates multiple channels at the same time using the software.
•
I/O mode 6: Software activation timer activation/stop mode
This mode controls activation/stop of the odd-numbered channel by using the even-numbered channel.
The even-numbered channel is activated through software. The odd-numbered channel is activated at
the rising edge of the output signal from the even-numbered channel and stops at the falling edge.
•
I/O mode 7: Timer activation mode
This mode controls activation of the odd-numbered channel by using the even-numbered channel.
The odd-numbered channel is activated at the rising edge of the output signal from the even-numbered
channel.
•
I/O mode 8: Other channel trigger shared timer activation/stop mode
In this mode, the external signal from other channels is input as an external activation trigger to
activate the timer. This mode cannot be set for ch.0 and ch.1.
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22.2
MB91665 Series
22.2 Configuration
The base timer I/O select function consists of the following blocks:
■ Block diagram of the base timer I/O select function
Figure 22.2-1 is a block diagram of the base timer I/O select function.
Figure 22.2-1 Block diagram of base timer I/O select function
Register block
TIOB3
Peripheral bus
Base Timer
ch.3
I/O selection block
TIOA3
TIOB2
Base Timer
ch.2
TIOA2
TIOB1
Base Timer
ch.1
Base Timer
ch.0
TIOA1
TIOB0
TIOA0
•
I/O selection block
This circuit selects the I/O mode of the base timer for each channel.
•
Base timer (ch.0 to ch.3)
ch.0 to ch.3 of the base timer.
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22.3
MB91665 Series
22.3 Pins
This section explains the pins for setting the I/O mode using the base timer I/O select function.
■ Overview
The base timer has 2 types of external pins and 5 types of internal signals for each channel.
By connecting the external pins and internal signals, signals that correspond to the connection destination
(external clock (ECK signal)/external activation trigger (TGIN signal)/wave form (TIN signal)) are input
to or output from the base timer.
The external pins and internal signals are connected by setting the I/O mode of the base timer. The pins
that are used and the signals to be input/output vary depending on the I/O mode.
● External pin
•
TIOA0 to TIOA3 pins
These pins are used to output the wave form of the base timer (TOUT signal) or input the external
activation trigger (TGIN signal).
These pins are multiplexed pins. To use them as TIOA0 to TIOA3 pins of the base timer, see "2.4
Setting Method for Pins".
•
TIOB0 to TIOB3 pins
These pins are used to input the external activation trigger (TGIN signal)/external clock (ECK signal)/
wave form of another channel (TIN signal).
These pins are multiplexed pins. To use them as TIOB0 to TIOB3 pins of the base timer, see "2.4
Setting Method for Pins".
● Internal signal
By connecting these pins to the above mentioned external pins or by inputting the output signal from
another channel, signals is input to or output from the base timer.
•
TOUT signal
Output wave form of the base timer. (It is not used in the 16/32-bit PWC timer.)
•
ECK signal
External clock of the base timer. (It is not used in the 16/32-bit PWC timer.)
This signal is input when the external clock is selected for the count clock.
•
TGIN signal
External activation trigger of the base timer. (It is not used in the 16/32-bit PWC timer.)
When the effective edge of the external activation trigger is selected, the edge of this signal is detected
to activate the base timer.
•
TIN signal
The wave form to be measured. (It is used only in the 16/32-bit PWC timer.)
•
DTRG signal
The base timer stops operation at the falling edge of this signal.
•
COUT signal
Output signal to other channels.
•
CIN signal
Signal that is input from other channels.
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● Connection of the external pins and internal signals
The external pins and internal signals are connected by setting the I/O mode of the base timer. Table
22.3-1 outlines the relationship between the I/O mode and pin connections.
Table 22.3-1 Relationship between the I/O mode and pin connections
I/O
Mode
TIOAn
(Even-numbered
Channel)
Connection
Destination
I/O
TIOBn
(Even-numbered
Channel)
Connection
Destination
I/O
TIOAn+1
(Odd-numbered
Channel)
Connection
Destination
I/O
TIOBn+1
(Odd-numbered
Channel)
Connection
Destination
I/O
0
ch.n’s TOUT
Output
ch.n’s ECK/
TGIN/TIN
Input
ch.n+1’s
TOUT
Output
ch.n+1’s
ECK/TGIN/
TIN
Input
1
ch.n’s TOUT
Output
ch.n’s ECK
Input
ch.n’s TGIN
Input
ch.n’s TIN
Input
2
ch.n’s TOUT
Output
ch.n/ch.n+1’s
ECK/TGIN/
TIN*1
Input
ch.n+1’s
TOUT
Output
Not used
3
ch.n’s TOUT
Output
Not used
ch.n+1’s
TOUT
Output
4
ch.n’s TOUT
Output
ch.n’s ECK/
TGIN/TIN
ch.n+1’s
TOUT
Output
5
ch.n’s TOUT
Output
Not used
ch.n+1’s
TOUT
Output
6
ch.n’s TOUT
Output
ch.n+1’s
TOUT
Output
7
ch.n’s TOUT
Output
ch.n’s ECK/
TGIN/TIN
ch.n+1’s
TOUT
Output
8
ch.n’s TOUT
Output
Not used
ch.n+1’s
TOUT
Output
ch.n
Input
Input
even-numbered channel
ch.n+1 odd-numbered channel
n = 0, 2
*1
Synchronize with the peripheral clock (PCLK)
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22.4
MB91665 Series
22.4 Registers
This section explains the configuration and functions of registers used in the base timer I/O select
function.
■ List of registers of the base timer I/O select function
Table 22.4-1 lists registers of the base timer I/O select function.
Table 22.4-1 Registers of the base timer I/O select function
Channel
548
Abbreviated
Register
Name
Register Name
Reference
Common
BTSSSR
Base timer same time soft start register
22.4.2
Common to 0 to 3
BTSEL0123
Base timer io select register for ch.0/1/2/3
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22.4
MB91665 Series
22.4.1
Base Timer IO Select Register for Ch.0/1/2/3
(BTSEL0123)
This register sets the I/O mode of ch.0 to ch.3 of the base timer.
Figure 22.4-1 shows the bit configuration of the base timer io select register for ch.0/1/2/3 (BTSEL0123).
Figure 22.4-1 Bit configuration of base timer io select register for ch.0/1/2/3 (BTSEL0123)
bit
7
6
5
4
3
2
1
0
SEL23_3
SEL23_2
SEL23_1
SEL23_0
SEL01_3
SEL01_2
SEL01_1
SEL01_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
<Note>
Change this register after setting the base timer to reset mode in FMD2 to FMD0 bits (FMD2 to
FMD0 = 000) of the base timer x timer control register (BTxTMCR).
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[bit7 to bit4]: SEL23_3 to SEL23_0 (I/O select bit for ch.2/ch.3)
These bits set the I/O mode for ch.2 and ch.3 of the base timer.
SEL23_3
SEL23_2
SEL23_1
SEL23_0
Explanation
0
0
0
0
I/O mode 0
(16-bit timer standard mode)
0
0
0
1
I/O mode 1
(timer full mode)
0
0
1
0
I/O mode 2
(external trigger shared mode)
0
0
1
1
I/O mode 3
(other channel trigger shared mode)
0
1
0
0
I/O mode 4
(timer activation/stop mode)
0
1
0
1
I/O mode 5
(same time software activation mode)
0
1
1
0
I/O mode 6
(software activation timer activation/stop
mode)
0
1
1
1
I/O mode 7
(timer activation mode)
1
0
0
0
I/O mode 8
(other channel trigger shared timer activation/
stop mode)
<Note>
Setting the values other than above is prohibited.
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[bit3 to bit0]: SEL01_3 to SEL01_0 (I/O select bit for ch.0/ch.1)
These bits set the I/O mode of ch.0 and ch.1 of the base timer.
ch.0 and ch.1 are the lowest channels of the base timer so that modes that use signals from the lower side
channels cannot be used in these channels. Therefore, the setting of the following modes is prohibited.
•
I/O mode 3 (other channel trigger shared mode)
•
I/O mode 8 (other channel trigger shared timer activation/stop mode)
SEL01_3
SEL01_2
SEL01_1
SEL01_0
Explanation
0
0
0
0
I/O mode 0
(16-bit timer standard mode)
0
0
0
1
I/O mode 1
(timer full mode)
0
0
1
0
I/O mode 2
(external trigger shared mode)
0
0
1
1
Setting prohibited
0
1
0
0
I/O mode 4
(timer activation/stop mode)
0
1
0
1
I/O mode 5
(same time software activation mode)
0
1
1
0
I/O mode 6
(software activation timer activation/stop
mode)
0
1
1
1
I/O mode 7
(timer activation mode)
1
0
0
0
Setting prohibited
<Note>
Setting the values other than above is prohibited.
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22.4
22.4.2
MB91665 Series
Base Timer Same Time Soft Start Register (BTSSSR)
This register simultaneously activates the base timers using the software.
Up to 16 channels corresponding to the bits in which "1" is written can be simultaneously activated.
Figure 22.4-2 shows the bit configuration of the base timer same time soft start register (BTSSSR).
Figure 22.4-2 Bit configuration of base timer same time soft start register (BTSSSR)
bit
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Attribute
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
SSSR3
SSSR2
SSSR1
SSSR0
Attribute
W
W
W
W
W
W
W
W
Initial value
X
X
X
X
X
X
X
X
bit
W: Write only
X: Undefined
<Notes>
•
Do not write to this register when the modes other than the following are set.
- I/O mode 5 (same time software activation mode)
- I/O mode 6 (software activation timer activation/stop mode) (only for even-numbered
channels)
•
For channels that are activated using this register, set the trigger input edge to the rising edge in
the EGS1 and EGS0 bits (EGS1, EGS 0 = 01) of the base timer x timer control register
(BTxTMCR).
[bit15 to bit4]: Reserved bits
Write "0" to this (these) bit (bits).
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[bit3]: SSSR3 (Same time software start bit for ch.3)
This bit activates the ch.3 of the base timer.
Written Value
Explanation
0
Ignored
1
Activates the ch.3 of the base timer.*
* Only when the I/O mode is set to "5" (same time software activation mode) in SEL23_3 to SEL23_0
bits of the base timer io select register for ch.0/1/2/3 (BTSEL0123) (SEL23_3 to SEL23_0 = 0101)
[bit2]: SSSR2 (Same time software start bit for ch.2)
This bit activates the ch.2 of the base timer.
Written Value
Explanation
0
Ignored
1
Activates the ch.2 of the base timer.*
* Only when the I/O mode is set to either of the following modes in the SEL23_3 to SEL23_0 bits of
the base timer io select register for ch.0/1/2/3 (BTSEL0123)
- "5" (Same time software activation mode) (SEL23_3 to SEL23_0 = 0101)
- "6" (Software activation timer activation/stop mode) (SEL23_3 to SEL23_0 = 0110)
[bit1]: SSSR1 (Same time software start bit for ch.1)
This bit activates the ch.1 of the base timer.
Written Value
Explanation
0
Ignored
1
Activates the ch.1 of the base timer.*
* Only when the I/O mode is set to "5" (same time software activation mode) in SEL01_3 to SEL01_0
bits of the base timer io select register for ch.0/1/2/3 (BTSEL0123) (SEL01_3 to SEL01_0 = 0101)
[bit0]: SSSR0 (Same time software start bit for ch.0)
This bit activates the ch.0 of the base timer.
Written Value
Explanation
0
Ignored
1
Activates the ch.0 of the base timer.*
* Only when the I/O mode is set to either of the following modes in the SEL01_3 to SEL01_0 bits of
the base timer io select register for ch.0/1/2/3 (BTSEL0123)
- "5" (Same time software activation mode) SEL01_3 to SEL01_0)
- "6" (Software activation timer activation/stop mode) (SEL01_3 to SEL01_0)
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22.5
MB91665 Series
22.5 I/O Mode
Operations of the external pins and activation/stop timing of the base timer vary depending on the I/O
mode set in the base timer io select register (BTSEL0123).
22.5.1
I/O Mode 0 (16-bit Timer Standard Mode)
In this mode, each channel of the base timer is used separately.
Table 22.5-1 lists the external pins used when this mode is set.
Table 22.5-1 External Pins Used
Even-numbered Channel
Odd-numbered Channel
Input pin
1
1
Output pin
1
1
Table 22.5-2 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-2 Connection Destinations of the External Pins and I/O Signals
External Pin
I/O
Connection
Destination
(Internal Signal)
I/O Signal
TIOA0 to TIOA3
Output
TOUT
Output wave form the base timer
TIOB0 to TIOB3
Input
ECK/TGIN/TIN*
Use the signals that have been input as one
of the following:
- External clock (ECK signal)
- External activation trigger (TGIN signal)
- Measured wave form (TIN signal)
* Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register
(BTxTMCR) setting.
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Figure 22.5-1 is a block diagram of I/O mode 0 (16-bit timer standard mode), taking ch.0 as an example.
Figure 22.5-1 Block Diagram of I/O Mode 0 (16-bit Timer Standard Mode)
Base Timer
ch.n+1
Base Timer
ch.n
ECK
TGIN
TIN
TOUT
TIOBn+1
ECK
TGIN
TIN
TOUT
TIOBn
TIOAn+1
TIOAn
Table 22.5-3 lists the connections for I/O mode 0.
Table 22.5-3 Connections for I/O Mode 0
Connection Source
Connection Destination
TOUT signal of ch.n
Output from the TIOAn pin
Input signal from the TIOBn pin
Input to ch.n as TIN/TGIN/ECK
TOUT signal of ch.n+1
Output from the TIOAn+1 pin
Input signal from the TIOBn+1 pin
Input to ch.n+1 as TIN/TGIN/ECK
n=0, 2
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22.5
22.5.2
MB91665 Series
I/O Mode 1 (Timer Full Mode)
In this mode, signals from the even-numbered channels are allocated to all the external pins
separately to operate the timer.
Table 22.5-4 lists the external pins used when this mode is set.
Table 22.5-4 External Pins Used
Even-numbered Channel
Input pin
3
Output pin
1
Table 22.5-5 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-5 Connection Destinations of the External Pins and I/O Signals
External
Pin
I/O
Connection
Destination
(Internal Signal)
I/O Signal
TIOAn
Output
TOUT of an evennumbered channel
Output the wave form of an even-numbered
channel
TIOBn
Input
ECK of the evennumbered channel
Input the external clock (ECK signal) to the evennumbered channel
TIOAn+1
Input
TGIN of the evennumbered channel
Input the external activation trigger (TGIN signal)
to the even-numbered channel
TIOBn+1
Input
TIN of the evennumbered channel
Input the measured wave form (TIN signal) in the
even-numbered channel
n=0, 2
Figure 22.5-2 is a block diagram of I/O mode 1 (timer full mode).
Figure 22.5-2 Example of Block Diagram of I/O Mode 1 (Timer Full Mode)
TIOBn+1
Base Timer
ch.n+1
TIOAn+1
(During 32-bit mode operation)
Base Timer
ch.n
556
ECK
TGIN
TIN
TOUT
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TIOBn
TIOAn
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Table 22.5-6 lists the connections for I/O mode 1.
Table 22.5-6 Connections for I/O Mode 1
Connection Source
Connection Destination
TOUT signal of ch.n
Output from the TIOAn pin
Input signal from the TIOBn pin
Input to ch.n as an ECK signal
Input signal from the TIOAn+1 pin
Input to ch.n as a TGIN signal
Input signal from the TIOBn+1 pin
Input to ch.n as a TIN signal
n=0, 2
<Note>
If this mode is set, set the TIOAn pins (TIOA1, TIOA3) corresponding to the odd-numbered channel
to the port input mode in the port function register (PFR). For details of the setting of pins, see "2.4
Setting Method for Pins".
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22.5
22.5.3
MB91665 Series
I/O Mode 2 (External Trigger Shared Mode)
In this mode, input signals to the base timer (ECK/TGIN/TIN) are shared by 2 channels.
Table 22.5-7 lists the external pins used when this mode is set.
Table 22.5-7 External Pins Used
Even-numbered Channel
Input pin
1 (shared by 2 channels)
Output pin
1
Odd-numbered Channel
1
Table 22.5-8 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-8 Connection Destinations of the External Pins and I/O Signals
External
pin
I/O
Connection
Destination
(Internal Signal)
I/O Signal
TIOAn
Output
TOUT of an evennumbered channel
Output the wave form of an even-numbered
channel
TIOAn+1
Output
TOUT of an oddnumbered channel
Output the wave form of an odd-numbered
channel
TIOBn
Input
ECK/TGIN/TIN of the
even/odd-numbered
channel*
Input to both of the even/odd-numbered channels
(synchronized with the peripheral clock (PCLK))
and use it as one of the following:
- External clock (ECK signal)
- External activation trigger (TGIN signal)
- Measured wave form (TIN signal)
TIOBn+1
-
-
Not used
n=0, 2
* Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register
(BTxTMCR) setting.
Figure 22.5-3 is a block diagram of I/O mode 2 (external trigger shared mode).
Figure 22.5-3 Block Diagram of I/O Mode 2 (External Trigger Shared Mode)
Base Timer
ch.n+1
Base Timer
ch.n
558
ECK
TGIN
TIN
TOUT
COUT
ECK
TGIN
TIN
TOUT
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TIOBn+1
TIOAn+1
TIOBn
TIOAn
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Table 22.5-9 lists the connections for I/O mode 2.
Table 22.5-9 Connections for I/O Mode 2
Connection
Source
Connection Destination
TOUT signal of ch.n
Output from the TIOAn pin
Input signal from the
TIOBn pin
- Input to ch.n and ch.n+1 as TIN/TGIN/ECK
signals
- Output to another channel as the COUT
signal
TOUT signal of
ch.n+1
Output from the TIOAn+1 pin
Remarks
Synchronization with the
peripheral clock (PCLK)
n=0, 2
<Note>
If the upper 2 channels (n + 2, n + 3) of those that have been set to this mode are set to I/O mode 3
(other channel trigger shared mode), the input signals (ECK/TGIN/TIN) can be input to 4 channels
at the same time.
(Example: If this mode is set for ch.0 and ch.1 and I/O mode 3 is set for ch.2 and ch.3, the input
signals (ECK/TGIN/TIN) can be input to all 4 channels of ch.0 to ch.3 at the same time.)
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22.5.4
MB91665 Series
I/O Mode 3 (Other Channel Trigger Shared Mode)
In this mode, the COUT signal of the channel that is lower by 2 channels is input as a CIN signal to be
used as the ECK/TGIN/TIN signal.
Table 22.5-10 lists the external pins used when this mode is set.
Table 22.5-10 External Pins Used
Even-numbered Channel
Input pin
Not used
Output pin
1
Odd-numbered Channel
1
Table 22.5-11 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-11 Connection Destinations of the External Pins and I/O Signals
External pin
I/O
Connection Destination
(Internal Signal)
I/O Signal
TIOAn
Output
TOUT of an even-numbered
channel
Output the wave form of an evennumbered channel
TIOAn+1
Output
TOUT of an odd-numbered
channel
Output the wave form of an oddnumbered channel
TIOBn, TIOBn+1
-
-
Not used
n=2
Figure 22.5-4 is a block diagram of I/O mode 3 (other channel trigger shared mode).
Figure 22.5-4 Block Diagram of I/O Mode 3 (Other Channel Trigger Shared Mode)
Base Timer
ch.n+1
Base Timer
ch.n
ECK
TGIN
TIN
TOUT
COUT
TIOBn+1
TIOAn+1
ECK
TGIN
TIN
TOUT
TIOBn
TIOAn
CIN
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Table 22.5-12 lists the connections for I/O mode 3.
Table 22.5-12 Connections for I/O Mode 3
Connection Source
Connection Destination
TOUT signal of ch.n
Output from the TIOAn pin
CIN signal*
- Input to ch.n and ch.n+1 as the TIN/TGIN/ECK signal
- Output to another channel as the COUT signal
TOUT signal of ch.n+1
Output from the TIOAn+1 pin
n=2
* Input the COUT signal of the other channel as the CIN signal.
The signals of ch.n-2/n-1 that can be input to ECK, TGIN and TIN of ch.n/n+1 are as below.
•
The signal that synchronized TIOBn-2 input of input/output mode 2 with peripheral clock.
•
The trigger signal input from ch.n-4/n-3 of input/output mode 3.
•
TIONAn-2 output of input/output mode 4.
•
TIONAn-2 output of input/output mode 6.
•
TIONAn-2 output of input/output mode 7.
•
The trigger signal input from ch.n-4/n-3 of input/output mode 8.
<Notes>
•
Set the trigger input edge to the rising edge in EGS1 and EGS0 bits (EGS1, EGS0=01) of the
base timer x timer control register (BTxTMCR).
•
Channels that have been set to this mode use the COUT signal of the channels (n - 2, n - 1) that
are lower by 2 channels, as the CIN signal input.
(Example: If ch.2 and ch.3 are set to this mode, they use the COUT signal of ch.0 and ch.1.)
Therefore, ch.0 and ch.1 cannot be set to this mode.
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22.5
22.5.5
MB91665 Series
Operations in I/O Mode 4 (Timer Activation/Stop Mode)
This mode enables control of activation/stop of the odd-numbered channel by using the evennumbered channel.
The odd-numbered channel is activated at the rising edge of the output wave form (TOUT signal) of
the even-numbered channel and stops at the falling edge.
Table 22.5-13 lists the external pins used when this mode is set.
Table 22.5-13 External Pins Used
Even-numbered Channel
Odd-numbered Channel
Input pin
1
Not used
Output pin
1
1
Table 22.5-14 lists the functions of pins.
Table 22.5-14 Functions of Pins
External Pin
I/O
Connection Destination
(Internal Signal)
I/O Signal
TIOAn
Output
TOUT of an even-numbered
channel
Output the wave form of an evennumbered channel
TIOAn+1
Output
TOUT of an odd-numbered
channel
Output the wave form of an odd-numbered
channel
TIOBn
Input
ECK/TGIN/TIN of the evennumbered channel*
Input to the even-numbered channel and
use as one of the following.
- External clock (ECK signal)
- External activation trigger (TGIN signal)
- Measured wave form (TIN signal)
TIOBn+1
-
-
Not used
n=0, 2
* Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register
(BTxTMCR) setting.
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
Figure 22.5-5 is a block diagram of I/O mode 4 (timer activation/stop mode).
Figure 22.5-5 Block Diagram of I/O Mode 4 (Timer Activation/Stop Mode)
COUT
Base Timer
ch.n+1
Base Timer
ch.n
DTRG
ECK
TGIN
TIN
TOUT
TIOBn+1
TIOAn+1
ECK
TGIN
TIN
TOUT
TIOBn
TIOAn
Table 22.5-15 lists the connections for I/O mode 4.
Table 22.5-15 Connections for I/O Mode 4
Connection Source
Connection Destination
TOUT signal of ch.n
- Output from the TIOAn pin
- Input to ch.n+1 as the TIN/TGIN/ECK signal and DTRG signal
- Output to another channel as the COUT signal
Input signal from the TIOBn
pin
Input to ch.n as the TIN/TGIN/ECK signal
TOUT signal of ch.n+1
Output from the TIOAn+1 pin
n=0, 2
<Notes>
•
Set the trigger input edge of the odd-numbered channel to the rising edge in the EGS1 and
EGS0 bits (EGS1, EGS0 = 01) of the base timer x timer control register (BTxTMCR).
•
The odd-numbered channel stops operation when the falling edge is detected in the DTRG
signal.
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
Figure 22.5-6 shows the operation when I/O mode 4 (timer activation/stop mode) is set, taking as an
example the case where ch.0 and ch.1 are used as the PWM timer.
Setting
Value
Register (ch.0)
Setting
Value
Register (ch.1)
Base timer 0 cycle setting register
(BT0PCSR)
0010H
Base timer 1 cycle setting register
(BT1PCSR)
0002H
Base timer 0 duty setting register
(BT0PDUT)
0009H
Base timer 1 duty setting register
(BT1PDUT)
0001H
Base timer 0 timer control register
(BT0TMCR)
0013H
Base timer 1 timer control register
(BT1TMCR)
0112H
Figure 22.5-6 Example of Operations of I/O Mode 4 (Timer Activation/Stop Mode)
Peripheral clock
(PCLK)
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
TIOA0
6
TIOA1
ch.1 operation period
ch.1 activated
564
FUJITSU SEMICONDUCTOR LIMITED
7
8
ch.1 maintains the
timer value at the
time of stop.
ch.1 stops
CM71-10158-1E
CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
22.5.6
Operations in I/O Mode 5 (Same Time Software
Activation Mode)
This mode enables activating multiple channels at the same time by using the base timer same time
soft start register (BTSSSR).
All channels corresponding to the bits in which "1" is written in the base timer same time soft start
register (BTSSSR) are activated at the same time.
Table 22.5-16 lists the external pins used when this mode is set.
Table 22.5-16 External Pins Used
Even-numbered Channel
Input pin
Not used
Output pin
1
Odd-numbered Channel
1
Table 22.5-17 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-17 Connection Destinations of the External Pins and I/O Signals
External Pin
Connection Destination
(Internal Signal)
I/O
I/O Signal
TIOAn
Output
TOUT of an even-numbered
channel
Output the wave form of an
even-numbered channel
TIOAn+1
Output
TOUT of an odd-numbered
channel
Output the wave form of an oddnumbered channel
TIOBn, TIOBn+1
-
-
Not used
n=0, 2
Figure 22.5-7 is a block diagram of I/O mode 5 (same time software activation mode).
Figure 22.5-7 Block Diagram of I/O Mode 5 (Same Time Software Activation Mode)
Software
activation signal
(SSSRn+1 bit)
Base Timer
ch.n+1
Software
activation signal
(SSSRn bit)
Base Timer
ch.n
CM71-10158-1E
ECK
TGIN
TIN
TOUT
TIOBn+1
ECK
TGIN
TIN
TOUT
TIOBn
FUJITSU SEMICONDUCTOR LIMITED
TIOAn+1
TIOAn
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
Table 22.5-18 lists the connections for I/O mode 5.
Table 22.5-18 Connections for I/O Mode 5
Connection Source
Connection Destination
TOUT signal of ch.n
Output from the TIOAn pin
Software activation signal
(Writing "1" in SSSRn bit of BTSSSR)
Input to ch.n as the TIN/TGIN/ECK signal
TOUT signal of ch.n+1
Output from the TIOAn+1 pin
Software activation signal
(Writing "1" in SSSRn+1 bit of BTSSSR)
Input to ch.n+1 as the TIN/TGIN/ECK signal
n=0, 2
BTSSSR: Base timer same time soft start register (BTSSSR)
If "1" is written in the base timer same time soft start register (BTSSSR), the rising edge is input (ECK/
TGIN/TIN signal) in the channels that correspond to the written bits.
<Note>
Set the trigger input edge to the rising edge in EGS1 and EGS0 bits (EGS1, EGS0 = 01) of the
base timer x timer control register (BTxTMCR).
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
22.5.7
Operations in I/O Mode 6 (Software Activation Timer
Activation/Stop Mode)
This mode enables control of activation/stop of the odd-numbered channel by using the evennumbered channel.
The even-numbered channel is activated by writing "1" in the base timer same time soft start register
(BTSSSR).
The odd-numbered channel is activated when the rising edge is detected in the output wave form
(TOUT signal) of the even-numbered channel and stops when the falling edge is detected.
Table 22.5-19 lists the external pins used when this mode is set.
Table 22.5-19 External Pins Used
Even-numbered Channel
Input pin
Not used
Output pin
1
Odd-numbered Channel
1
Table 22.5-20 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-20 Connection Destinations of the External Pins and I/O Signals
Pin
Connection Destination
(Internal Signal)
I/O
I/O Signal
TIOAn
Output
TOUT of an even-numbered
channel
Output the wave form of an evennumbered channel
TIOAn+1
Output
TOUT of an odd-numbered
channel
Output the wave form of an oddnumbered channel
TIOBn, TIOBn+1
-
-
Not used
n=0, 2
Figure 22.5-8 is a block diagram of I/O mode 6 (software activation timer activation/stop mode).
Figure 22.5-8 Block Diagram of I/O Mode 6 (Software Activation Timer Activation/Stop Mode)
COUT
Base Timer
ch.n+1
Software
activation signal
(SSSRn bit)
Base Timer
ch.n
CM71-10158-1E
DTRG
ECK
TGIN
TIN
TOUT
ECK
TGIN
TIN
TOUT
FUJITSU SEMICONDUCTOR LIMITED
TIOBn+1
TIOAn+1
TIOBn
TIOAn
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
Table 22.5-21 lists the connections for I/O mode 6.
Table 22.5-21 Connections for I/O Mode 6
Connection Source
Connection Destination
TOUT signal of ch.n
- Output from the TIOAn pin
- Input to ch.n+1 as the TIN/TGIN/ECK/DTRG signal
- Output to another channel as the COUT signal
Software activation signal
(Writing "1" in SSSRn bit of BTSSSR)
Input to ch.n as the TIN/TGIN/ECK signal
TOUT signal of ch.n+1
Output from the TIOAn+1 pin
n=0, 2
BTSSSR Base timer same time soft start register (BTSSSR)
If "1" is written in the bits of the base timer same time soft start register (BTSSSR) that correspond to the
even-numbered channels to be activated, the rising edge is input (ECK, TGIN, TIN signal) in the
corresponding channels.
Start-up and stop timing of ch.n are same as input/output mode4.
<Notes>
568
•
Set the trigger input edge to the rising edge in EGS1 and EGS0 bits (EGS1, EGS0 = 01) of the
base timer x timer control register (BTxTMCR).
•
The odd-numbered channel stops operation when the falling edge is detected in the DTRG
signal.
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
22.5.8
Operations in I/O Mode 7 (Timer Activation Mode)
In this mode, the output wave form (TOUT signal) of the even-numbered channel is used as input
signals (ECK/TGIN/TIN signal) of the odd-numbered channel.
Table 22.5-22 lists the external pins used when this mode is set.
Table 22.5-22 External Pins Used
Even-numbered Channel
Odd-numbered Channel
Input pin
1
Not used
Output pin
1
1
Table 22.5-23 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-23 Connection Destinations of the External Pins and I/O Signals
External Pin
I/O
Connection Destination
(Internal Signal)
I/O Signal
TIOAn
Output
TOUT of an even-numbered
channel
Output the wave form of an evennumbered channel
TIOAn+1
Output
TOUT of an odd-numbered
channel
Output the wave form of an odd-numbered
channel
TIOBn
Input
ECK/TGIN/TIN of the evennumbered channel*
Input to the even-numbered channel and
use as one of the following.
- External clock (ECK signal)
- External activation trigger (TGIN signal)
- Measured wave form (TIN signal)
TIOBn+1
-
-
Not used
n=0, 2
* Input signals (ECK/TGIN/TIN signals) are used according to the base timer x timer control register
(BTxTMCR) setting.
Figure 22.5-9 is a block diagram of I/O mode 7 (timer activation mode).
Figure 22.5-9 Block Diagram of I/O Mode 7 (Timer Activation Mode)
COUT
Base Timer
ch.n+1
Base Timer
ch.n
CM71-10158-1E
ECK
TGIN
TIN
TOUT
TIOBn+1
ECK
TGIN
TIN
TOUT
TIOBn
FUJITSU SEMICONDUCTOR LIMITED
TIOAn+1
TIOAn
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
Table 22.5-24 lists the connection for I/O mode 7.
Table 22.5-24 Connection for I/O Mode 7
Connection Source
Connection Destination
TOUT signal of ch.n
- Output from the TIOAn pin
- Input to ch.n+1 as the TIN/TGIN/ECK signal
- Output to another channel as the COUT signal
Input signal from the TIOBn pin
Input to ch.n as the TIN/TGIN/ECK signal
TOUT signal of ch.n+1
Output from the TIOAn+1 pin
n=0, 2
Start-up timing of ch.n is same as input/output mode4.
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
22.5.9
Operations in I/O Mode 8 (Other Channel Trigger Shared
Timer Activation/Stop Mode)
In this mode, the COUT signal of the channel that is lower by 2 channels is input as the CIN signal to
be used as the external activation trigger (TGIN signal).
Table 22.5-25 lists the external pins used when this mode is set.
Table 22.5-25 External Pins Used
Even-numbered
Channel
Input pin
Not used
Output pin
1
Odd-numbered
Channel
1
Table 22.5-26 lists the connection destinations of the external pins used and I/O signals.
Table 22.5-26 Connection Destinations of the External Pins and I/O Signals
External Pin
Connection Destination
(Internal Signal)
I/O
I/O Signal
TIOAn
Output
TOUT of an even-numbered
channel
Output the wave form of an evennumbered channel
TIOAn+1
Output
TOUT of an odd-numbered
channel
Output the wave form of an oddnumbered channel
TIOBn, TIOBn+1
-
-
Not used
n=2
Figure 22.5-10 is a block diagram of I/O mode 8 (other channel trigger shared timer activation/stop
mode).
Figure 22.5-10 Block Diagram of I/O Mode 8 (Other Channel Trigger Shared Timer Activation/Stop Mode)
COUT
Base Timer
ch.n+1
Base Timer
ch.n
DTRG
ECK
TGIN
TIN
TOUT
TIOBn+1
TIOAn+1
DTRG
ECK
TGIN
TIN
TOUT
TIOBn
TIOAn
CIN
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CHAPTER 22 Base Timer I/O Select Function
22.5
MB91665 Series
Table 22.5-27 lists the connections for I/O mode 8.
Table 22.5-27 Connections for I/O Mode 8
Connection Source
Connection Destination
TOUT signal of ch.n
Output from the TIOAn pin
CIN signal*
- Input to ch.n and ch.n+1 as the TIN/TGIN/ECK signal and DTRG signal
- Output to another channel as the COUT signal
n=2
* Input the COUT signal of the other channel as the CIN signal.
The signals of ch.n-2/n-1 that can be input to ECK, TGIN and TIN of ch.n/n+1 are as below.
•
The signal that synchronized TIOBn-2 input of input/output mode 2 with peripheral clock.
•
The trigger signal input from ch.n-4/n-3 of input/output mode 3.
•
TIONAn-2 output of input/output mode 4.
•
TIONAn-2 output of input/output mode 6.
•
TIONAn-2 output of input/output mode 7.
•
The trigger signal input from ch.n-4/n-3 of input/output mode 8.
<Notes>
•
Channels that have been set to this mode use the COUT signal of the channels (n - 2, n - 1)
that are lower by 2 channels, as the CIN signal input.
(Example: If ch.2 and ch.3 are set to this mode, they use the COUT signal of ch.0 and ch.1.)
Therefore, ch.0 and ch.1 cannot be set to this mode.
•
For the channels that are set to this mode, set the trigger input edge to the rising edge in EGS1
and EGS0 bits (EGS1, EGS0 = 01) of the base timer x timer control register (BTxTMCR).
However, the above setting does not apply to the case where the timer function is set to 16/32bit PWC timer in the FMD2 to FMD0 bits (FMD2 to FMD0 = 100) of the base timer x timer
control register (BTxTMCR).
•
572
The odd-numbered channel stops operation when the falling edge is detected in the DTRG
signal.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
This chapter provides an overview of the base timer,
summarizes its register configuration and functions, and
describes its operations.
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
CM71-10158-1E
Overview of the Base Timer
Block Diagrams of the Base Timer
Base Timer's Registers
Operations of the Base Timer
32-bit Mode Operations
Notes of Using the Base Timer
Base Timer Interrupts
Base Timer Description by Function Mode
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CHAPTER 23 Base Timer
23.1
MB91665 Series
23.1 Overview of the Base Timer
The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its
timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload
timer, and 16/32-bit PWC timer. This section outlines the base timer in each function mode available.
This series is equipped with 16 channels.
■ Function Mode Bit Settings and Timer Function Modes Assigned
FMD2/FMD1/FMD0 bit Settings
Timer Function Mode
000B
Reset mode
001B
16-bit PWM timer
010B
16-bit PPG timer
011B
16/32-bit reload timer
100B
16/32-bit PWC timer
■ Reset Mode
Placing the base timer in this mode resets its macro (with each register reset to the initial value). Place the
base timer in this mode once before changing its function mode or T32 bit setting. After a reset, however,
the base timer can set its function mode and the T32 bit without entering the reset mode in advance.
■ 16-bit PWM Timer
The 16-bit PWM timer mainly consists of a 16-bit down counter, a 16-bit data register buffered for period
setting, a 16-bit compare register buffered for duty cycle setting, and a pin controller.
Period data and duty cycle data can be updated during timer operation as they are held in their buffered
respective registers.
The count clock for the 16-bit down counter can be selected from among five different internal clocks
(available by frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256) and three
different external events (rising edge, falling edge and both edge detection).
The PWM timer can select one-shot mode in which stops counting on an underflow or continuous mode
in which repeats counting by reloading.
For activation, the PWM timer can select a software trigger or one of three different external events
(rising-edge detection, falling-edge detection, and both-edge detection).
■ 16-bit PPG Timer
The 16-bit PPG timer mainly consists of a 16-bit down counter, a 16-bit data register for "H"-width
setting, a 16-bit data register for "L"-width setting, and a pin controller.
The count clock for the 16-bit down counter can be selected from among five different internal clocks
(available by frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256) and three
different external events (rising edge, falling edge and both edge detection).
The PPG timer can select one-shot mode in which stops counting on an underflow or continuous mode in
which repeats counting by reloading.
For activation, the PPG timer can select a software trigger or one of three different external events (risingedge detection, falling-edge detection, and both-edge detection).
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CHAPTER 23 Base Timer
23.1
MB91665 Series
■ 16/32-bit Reload Timer
The 16/32-bit reload timer mainly consists of a 16-bit down counter, a 16-bit reload register, and a pin
controller.
The count clock for the 16-bit down counter can be selected from among five different internal clocks
(available by frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256) and three
different external events (rising edge, falling edge and both edge detection).
The reload timer can select one-shot mode in which stops counting on an underflow or continuous mode
in which repeats counting by reloading.
For activation, the reload timer can select a software trigger or one of three different external events
(rising-edge detection, falling-edge detection, and both-edge detection).
■ 16/32-bit PWC Timer
The 16/32-bit PWC timer mainly consists of a 16-bit up counter, a measurement input pin, and control
registers.
The PWC timer measures the time between arbitrary events based on the pulse input from an external
source.
The reference count clock can be selected from among five different internal clocks (available by
frequency-dividing the peripheral clock (PCLK) by 1, 4, 16, 128, and 256).
Measurement modes "H" pulse width (↑ to ↓) / "L" pulse width (↓ to ↑ )
Rising period (↑ to ↑ ) / Falling period (↓ to ↓)
Inter-edge measurement (↑ or ↓ to ↓ or ↑ )
The PWC timer can generate an interrupt request upon completion of measurement.
The PWC timer can select one-shot measurement or continuous measurement.
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CHAPTER 23 Base Timer
23.2
MB91665 Series
23.2 Block Diagrams of the Base Timer
This section provides a block diagram of the base timer in each function mode.
■ Block Diagram of 16-bit PWM Timer
Figure 23.2-1 Block Diagram of 16-bit PWM Timer
BTxPDUT
BTxPCSR
Load
BTxPDUT
Writing
Buffer
CKS
Buffer
OSEL
3
16
16
20
Peripheral
clock
(PCLK)
Match detection
Division
circuit 27
External clock
28
(ECK signal)
From base timer
I/O selection block
Count clock
16
PMSK
16-bit down counter
Edge
detection
Counting
enabled
Invert control
Load
To base timer
I/O selection block
Toggle
generation
Underflow
Wave form output
(TOUT signal)
EGS
2
UDIE
STRG
External
activation trigger
(TGIN signal)
Edge
detection
From base timer
I/O selection block
CTEN
Counting
enabled
MDSE
DTIE Underflow/Duty
match interrupt
request
Interrupt
source
generation
Trigger
Timer enabled
CTEN
TGIE
Trigger interrupt
request
BTxPCSR: Base timer x cycle setting register (BTxPCSR)
BTxPDUT: Base timer x duty setting register (BTxPDUT)
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FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.2
MB91665 Series
■ Block Diagram of 16-bit PPG Timer
Figure 23.2-2 Block Diagram of 16-bit PPG Timer
Reload data
settings
CKS
BTxPRLL
16
Buffer
3
Peripheral
clock
(PCLK)
From base timer
I/O selection block
External clock
(ECK signal)
2
Division
circuit
BTxPRLH
0
Count clock
27
28
Load
OSEL invert control
PPG output
Down counter
Edge
detection
Counting
enabled
EGS
(TOUT Signal)
Underflow
Toggle
generation
2
To base timer
I/O selection block
PMSK
UDIE
STRG CTEN
External
activation
trigger
(TGIN signal)
From base timer
I/O selection block
Counting
enabled
MDSE
CTEN
Edge
detection
Interrupt
source
generation
Underflow
interrupt request
Trigger interrupt
request
Trigger
Timer enabled
TGIE
BTxPRLL: Base timer xL width setting (BTxPRLL)
BTxPRLH: Base timer xH width setting (BTxPRLH)
BTxTMR: Base timer x timer register (BTxTMR)
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CHAPTER 23 Base Timer
23.2
MB91665 Series
■ Block Diagram of 16/32-bit Reload Timer (ch.1, ch.0)
Figure 23.2-3 Block Diagram of 16/32-bit Reload Timer (ch.1, ch.0)
16-bit mode
T32 = 0
OSEL
BTxPCSR
Invert control
CKS
Peripheral
clock
(PCLK)
20
Division
circuit
External clock
(ECK signal)
From base timer
I/O selection block
Toggle
generation
16
3
Output wave form
(TOUT signal)
To base timer
I/O selection block
Count clock
27
28
Load
Down counter
(BTxTMR)
Edge
detection
Counting
enabled
Underflow
T32
EGS
2
External activation
edge
(TGIN signal)
From base timer
I/O selection block
MDSE
UDIE
Counting
enabled
STRG
Trigger
CTEN
Edge
detection
CTEN
Underflow
interrupt request
Interrupt
source
generation
Trigger interrupt
request
Timer
TGIE
BTxPCSR: Base timer x cycle setting register (BTxPCSR)
BTxTMR: Base timer x timer register (BTxTMR)
(Continued)
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CM71-10158-1E
CHAPTER 23 Base Timer
23.2
MB91665 Series
(Continued)
32-bit mode
ch.1
BT1PCSR
16
Count clock
Load
Down counter
(BT1TMR)
Counting
enabled
Underflow
T32 = 0
T32 = 1
ch.0
OSEL
Output wave form
(TOUT signal)
BT0PCSR
Invert control
CKS
3
To base timer
I/O selection block
2
Peripheral
clock
(PCLK)
Division
circuit 27
External clock
28
(ECK signal)
From base timer
I/O selection block
Toggle
generation
16
0
Count clock
Load
Down counter
(BT0TMR)
Edge
detection
Counting
enabled
Underflow
T32
EGS
2
MDSE
Counting
enabled
External activation
trigger
(TGIN signal)
From base timer
I/O selection block
UDIE
Underflow
interrupt request
STRG
Trigger
Edge
detection
CTEN
CTEN
Interrupt
source
generation
Trigger interrupt
request
Timer
TGIE
BT1PCSR: Base timer 1 cycle setting register (BT1PCSR)
BT1TMR: Base timer 1 timer register (BT1TMR)
BT0PCSR: Base timer 0 cycle setting register (BT0PCSR)
BT0TMR: Base timer 0 timer register (BT0TMR)
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CHAPTER 23 Base Timer
23.2
MB91665 Series
<Notes>
580
•
The reload timer can operate in 32 bits only between ch.0 and ch.1 and between ch.2 and ch.3.
No 32-bit operation is applicable to any other combination of channels.
•
This function supports simultaneous activation. For details, see "CHAPTER 22 Base Timer I/O
Select Function".
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.2
MB91665 Series
■ Block Diagram of 16/32-bit PWC Timer (ch.1, ch.0)
Figure 23.2-4 Block Diagram of 16/32-bit PWC Timer (ch.1, ch.0)
16-bit mode
BTxDTBF
T32 = 0
CKS
3
Peripheral
clock
(PCLK)
16
20
Division
circuit 27
28
Count clock
Clearing
Up counter
Counting
enabled
Overflow
MDSE
MDSE
T32
EGS
3
Wave form to
be measured
(TIN signal)
CTEN
Edge
detection
From base
timer
I/O selection
block
Overflow
OVIE Interrupt
Request
Counting
enabled
Interrupt
source
generation
End of measuring
Interrupt Request
Activation detection
CTEN
Edge
detection
Stop detection
EDIE
BTxDTBF: Base timer x data buffer register (BTxDTBF)
(Continued)
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CHAPTER 23 Base Timer
23.2
MB91665 Series
(Continued)
32-bit mode
ch.1
BT1DTBF
16
Clearing
Count
clock
Up counter
(BT1TMR)
Counting
enabled
Overflow
T32 = 0
T32 = 1
BT0DTBF
ch.0
CKS
3
Peripheral
clock
(PCLK)
16
20
Division
circuit
Count clock
27
28
Clearing
Up counter
(BT0TMR)
Counting
enabled
Overflow
MDSE
MDSE
T32
EGS
3
Wave form to
be measured
(TIN signal)
Overflow
interrupt
request
CTEN
Interrupt
source
generation
Edge
detection
From base
timer
I/O selection
block
OVIE
Counting
enabled
End of measuring
Interrupt Request
Activation detection
CTEN
Edge
detection
Stop detection
EDIE
BT0DTBF: Base timer 0 data buffer register (BT0DTBF)
BT1DTBF: Base timer 1 data buffer register (BT1DTBF)
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CHAPTER 23 Base Timer
23.2
MB91665 Series
<Notes>
•
The PWC timer can operate in 32 bits only between ch.0 and ch.1 and between ch.2 and ch.3.
No 32-bit operation is applicable to any other combination of channels.
•
This function supports simultaneous activation. For details, see "CHAPTER 22 Base Timer I/O
Select Function".
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CHAPTER 23 Base Timer
23.3
MB91665 Series
23.3 Base Timer's Registers
This section lists the registers used for the base timer and their bit configurations in each timer
function mode.
■ List of Base Timer's Registers
Table 23.3-1 Registers used for 16-bit PWM timer
Channel
Register Name
Reference
Common
BTSSSR
Base timer same time soft start register
22.4.2
Common to 0 to 3
BTSEL0123
Base timer io select register for ch.0/1/2/3
22.4.1
0
BT0TMCR
Base timer 0 timer control register
23.8.1.1
BT0STC
Base timer 0 status control register
23.8.1.1
BT0PCSR
Base timer 0 cycle setting register
23.8.1.2
BT0PDUT
Base timer 0 duty setting register
23.8.1.3
BT0TMR
Base timer 0 timer register
23.8.1.4
BT1TMCR
Base timer 1 timer control register
23.8.1.1
BT1STC
Base timer 1 status control register
23.8.1.1
BT1PCSR
Base timer 1 cycle setting register
23.8.1.2
BT1PDUT
Base timer 1 duty setting register
23.8.1.3
BT1TMR
Base timer 1 timer register
23.8.1.4
BT2TMCR
Base timer 2 timer control register
23.8.1.1
BT2STC
Base timer 2 status control register
23.8.1.1
BT2PCSR
Base timer 2 cycle setting register
23.8.1.2
BT2PDUT
Base timer 2 duty setting register
23.8.1.3
BT2TMR
Base timer 2 timer register
23.8.1.4
BT3TMCR
Base timer 3 timer control register
23.8.1.1
BT3STC
Base timer 3 status control register
23.8.1.1
BT3PCSR
Base timer 3 cycle setting register
23.8.1.2
BT3PDUT
Base timer 3 duty setting register
23.8.1.3
BT3TMR
Base timer 3 timer register
23.8.1.4
1
2
3
584
Abbreviated
Register
Name
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CHAPTER 23 Base Timer
23.3
MB91665 Series
Table 23.3-2 Registers for the 16-bit PPG timer
Channel
Register Name
Reference
Common
BTSSSR
Base timer same time soft start register
22.4.2
Common to 0 to 3
BTSEL0123
Base timer io select register for ch.0/1/2/3
22.4.1
0
BT0TMCR
Base timer 0 timer control register
23.8.2.1
BT0STC
Base timer 0 status control register
23.8.2.1
BT0PRLL
Base timer 0 L width setting register
23.8.2.2
BT0PRLH
Base timer 0 H width setting register
23.8.2.3
BT0TMR
Base timer 0 timer register
23.8.2.4
BT1TMCR
Base timer 1 timer control register
23.8.2.1
BT1STC
Base timer 1 status control register
23.8.2.1
BT1PRLL
Base timer 1 L width setting register
23.8.2.2
BT1PRLH
Base timer 1 H width setting register
23.8.2.3
BT1TMR
Base timer 1 timer register
23.8.2.4
BT2TMCR
Base timer 2 timer control register
23.8.2.1
BT2STC
Base timer 2 status control register
23.8.2.1
BT2PRLL
Base timer 2 L width setting register
23.8.2.2
BT2PRLH
Base timer 2 H width setting register
23.8.2.3
BT2TM
Base timer 2 timer register
23.8.2.4
BT3TMCR
Base timer 3 timer control register
23.8.2.1
BT3STC
Base timer 3 status control register
23.8.2.1
BT3PRLL
Base timer 3 L width setting register
23.8.2.2
BT3PRLH
Base timer 3 H width setting register
23.8.2.3
BT3TMR
Base timer 3 timer register
23.8.2.4
1
2
3
CM71-10158-1E
Abbreviated
Register
Name
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CHAPTER 23 Base Timer
23.3
MB91665 Series
Table 23.3-3 Registers for the 16/32-bit reload timer
Channel
Register Name
Reference
Common
BTSSSR
Base timer same time soft start register
22.4.2
Common to 0 to 3
BTSEL0123
Base timer io select register for ch.0/1/2/3
22.4.1
0
BT0TMCR
Base timer 0 timer control register
23.8.3.1
BT0STC
Base timer 0 status control register
23.8.3.1
BT0PCSR
Base timer 0 cycle setting register
23.8.3.2
BT0TMR
Base timer 0 timer register
23.8.3.3
BT1TMCR
Base timer 1 timer control register
23.8.3.1
BT1STC
Base timer 1 status control register
23.8.3.1
BT1PCSR
Base timer 1 cycle setting register
23.8.3.2
BT1TMR
Base timer 1 timer register
23.8.3.3
BT2TMCR
Base timer 2 timer control register
23.8.3.1
BT2STC
Base timer 2 status control register
23.8.3.1
BT2PCSR
Base timer 2 cycle setting register
23.8.3.2
BT2TMR
Base timer 2 timer register
23.8.3.3
BT3TMCR
Base timer 3 timer control register
23.8.3.1
BT3STC
Base timer 3 status control register
23.8.3.1
BT3PCSR
Base timer 3 cycle setting register
23.8.3.2
BT3TMR
Base timer 3 timer register
23.8.3.3
1
2
3
586
Abbreviated
Register
Name
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CM71-10158-1E
CHAPTER 23 Base Timer
23.3
MB91665 Series
Table 23.3-4 List of registers used for 16/32-bit PWC timer
Channel
Register Name
Reference
Common
BTSSSR
Base timer same time soft start register
22.4.2
Common to 0 to 3
BTSEL0123
Base timer io select register for ch.0/1/2/3
22.4.1
0
BT0TMCR
Base timer 0 timer control register
23.8.4.1
BT0STC
Base timer 0 status control register
23.8.4.1
BT0DTBF
Base timer 0 data buffer register
23.8.4.2
BT1TMCR
Base timer 1 timer control register
23.8.4.1
BT1STC
Base timer 1 status control register
23.8.4.1
BT1DTBF
Base timer 1 data buffer register
23.8.4.2
BT2TMCR
Base timer 2 timer control register
23.8.4.1
BT2STC
Base timer 2 status control register
23.8.4.1
BT2DTBF
Base timer 2 data buffer register
23.8.4.2
BT3TMCR
Base timer 3 timer control register
23.8.4.1
BT3STC
Base timer 3 status control register
23.8.4.1
BT3DTBF
Base timer 3 data buffer register
23.8.4.2
1
2
3
CM71-10158-1E
Abbreviated
Register
Name
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CHAPTER 23 Base Timer
23.4
MB91665 Series
23.4 Operations of the Base Timer
This section introduces how the base timer operates in each timer function mode.
■ Operations of the Base Timer
● Reset mode
Placing the base timer in this mode resets its macro (with each register reset to the initial value). Place the
base timer in this mode once before changing its function mode or T32 bit setting. After a reset, however,
the base timer can set its function mode and the T32 bit without entering the reset mode in advance. If
you set this mode for even-numbered channels in 32-bit mode, odd-numbered channels are reset as well at
the same time. Thus you do not have to set the reset mode for odd-numbered channels.
● 16-bit PWM timer
The 16-bit PWM timer starts decrementing its counter by the value set as a period when triggered to start.
The PWM timer then sets the output to the "L" level first and, if the 16-bit down counter value matches
the value set in the duty setting register, inverts the output to the "H" level. Then it inverts the output back
to the "L" level when the counter causes an underflow subsequently. This generates a waveform with an
arbitrary period and duty cycle.
● 16-bit PPG timer
The 16-bit PPG timer starts decrementing its counter by the value set in the "L"-width setting reload
register when triggered to start. The PPG timer then sets the output to the "L" level first and inverts the
output back to the "H" level when the counter causes an underflow. The PPG timer continuously
decrements the counter by the value set in the "H"-width setting reload register and inverts the output
level to "L" when the counter causes an underflow. This generates a waveform with arbitrary "L" and "H"
widths.
● 16-bit reload timer
The 16-bit reload timer starts decrementing its 16-bit down counter by the value set as a period when
triggered to start. When the down counter causes an underflow, the interrupt flag is set. Depending on the
MDSE bit setting, the output level either toggles, or is inverted, between "H" and "L" each time the
counter causes an underflow or becomes "H" when the counter starts counting and "L" when it causes an
underflow.
● 32-bit reload timer
The 32-bit reload timer is the same in basic operation as the 16-bit reload timer, except that it works as a
32-bit version using a pair of even-numbered and odd-numbered channels. Although the even-numbered
and odd-numbered channels then operate as the lower 16-bit and upper 16-bit timers, respectively,
interrupt control and output wave control follow their respective settings for the even-numbered channel.
To set the period, write the value to the upper register (odd-numbered channel) first and then to the lower
register (even-numbered channel).
To obtain the timer value, read the lower register (even-numbered channel) first and then the upper
register (odd-numbered channel).
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CHAPTER 23 Base Timer
23.4
MB91665 Series
<Notes>
•
The reload timers can operate in 32 bits only between ch.0 and ch.1 and between ch.2 and
ch.3. No 32-bit operation is applicable to any other combination of channels.
•
This function supports simultaneous activation. For details, see "CHAPTER 22 Base Timer I/O
Select Function".
● 16-bit PWC timer
The 16-bit PWC timer starts the 16-bit up counter upon input of a pre-set measurement start edge and
stops the counter upon detection of a measurement stop edge. The count value between the two edges is
written to the data buffer register as a pulse width.
● 32-bit PWC timer
The 32-bit PWC timer is the same in basic operation as the 16-bit PWC timer, except that it works as a
32-bit version using a pair of even-numbered and odd-numbered channels. Although the even-numbered
and odd-numbered channels then operate as the lower 16-bit and upper 16-bit counters, respectively,
interrupt control follows the setting for the even-numbered channel. To obtain the measured value or
count value, read the lower register (even-numbered channel) first and then the upper register (oddnumbered channel).
<Notes>
•
The PWC timer can operate in 32 bits only between ch.0 and ch.1 and between ch.2 and ch.3.
No 32-bit operation is applicable to any other combination of channels.
•
This function supports simultaneous activation. For details, see "CHAPTER 22 Base Timer I/O
Select Function".
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CHAPTER 23 Base Timer
23.5
MB91665 Series
23.5 32-bit Mode Operations
The reload timer and PWC timer can operate in 32-bit mode using a pair of channels. This section
describes the basic functions and operations of 32-bit mode.
■ Functions of 32-bit Mode
The 32-bit mode combines two channels of base timer into a 32-bit data reload timer or PWC timer.
Either 32-bit timer allows the timer/counter value to be read even during operation as it takes the upper
16-bit timer/counter value of the odd-numbered channel also when reading the lower 16-bit timer/counter
value of the even-numbered channel.
■ Setting the 32-bit Mode
First, set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register for the even-numbered channel to
"000B" to reset in reset mode. Then, select the reload timer or PWC timer and set its operations in the
same way as in 16-bit mode. At this time, write "1" to the T32 bit in the BTxTMCR register to enter the
32-bit operation mode. The T32 bit for the odd-numbered channel must be left containing "0". Neither the
reset mode setting is required for the odd-numbered channel. To use the base timer as the reload timer, set
the period setting register for the odd-numbered channel to the upper 16-bit reload value among 32 bits
and set the period setting register for the even-numbered channel to the lower 16-bit reload value.
As the transition to 32-bit operation mode takes place the moment is written to the T32 bit, the setting
must be changed with counting halted on both of the channels.
To switch from 32-bit mode to 16-bit mode, set the FMD2, FMD1, and FMD0 bits in the BTxTMCR
register for the even-numbered channel to "000B" to reset the states of both of the even-numbered and
odd-numbered channels in reset mode. Then set each channel for operation in 16-bit mode.
■ Operations in 32-bit Mode
When the reload timer or PWC timer is started in 32-bit mode under control of the even-numbered
channel, the timer/counter of the even-numbered channel operates as the lower 16-bit timer/counter and
the timer/counter of the odd-numbered channel operates as the upper 16-bit one.
In 32-bit mode, the base timer follows the settings for the even-numbered channel while ignoring those
for the odd-numbered channel (except the period setting register when serving as the reload timer). Even
for the timer start, waveform output, and interrupt signal settings, the even-numbered channel overrides
the odd-numbered channel (odd-numbered channel is always masked at "L").
The following example shows a PWC configuration using ch.0 and ch.1.
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CHAPTER 23 Base Timer
23.5
MB91665 Series
ch. 1
Underflow
Overflow
ch.0
Interrupt
Upper 16-bit
timer/counter
Upper 16-bit
reload value
T32=0
Underflow
Overflow
Lower 16-bit
timer/counter
Waveform output
Read/write signals
Lower 16-bit
reload value
PWC measured waveform/
external trigger
T32=1
<Notes>
•
The reload timer or PWC timer can operate in 32 bits only between ch.0 and ch.1 and between
ch.2 and ch.3. No 32-bit operation is applicable to any other combination of channels.
•
This function supports simultaneous activation. For details, see "CHAPTER 22 Base Timer I/O
Select Function".
CM71-10158-1E
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CHAPTER 23 Base Timer
23.6
MB91665 Series
23.6 Notes of Using the Base Timer
This section summarizes the notes on using the base timer.
■ Common Notes on Using Each Type of Timer
● Notes on setting through programming
•
The following bits in the BTxTMCR register must not be updated during operation. Be sure to update
them before starting the base timer or after stopping it.
[bit14, bit13, bit12]
CKS2, CKS1, CKS0 : Clock select bits
[bit10, bit9, bit8]
EGS2, EGS1, EGS0
: Measurement edge select bits
[bit7]
T32
: 32-bit timer select bit
(Used with the reload timer or PWC timer selected)
[bit6, bit5,bit4]
FMD2, FMD1, FMD0 : Timer function mode select bits
[bit2]
MDSE
: Measurement mode (one-shot/continuous) select bit
•
If you set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register to "000B" to enter the reset
mode, all the registers of the base timer are initialized and thus they must be set all over again.
•
If you set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register to "000B" to enter the reset
mode, the other bits in the BTxTMCR register are initialized with their settings ignored.
■ Notes on Using the 16-bit PWM/PPG/Reload Timer
● Notes on setting through programming
592
•
When the interrupt request flag is attempted to be set and cleared at the same timing, the flag set action
overrides the flag clear action.
•
When the down counter is attempted to load and count at the same timing, the load action overrides the
count action.
•
Set the FMD2, FMD1, and FMD0 bits in the BTxTMCR register to select the timer function mode
before setting the period, duty cycle, "H" width, and "L" width.
•
If a restart is detected when counting is completed in one-shot mode, the counter is restarted with the
count value reloaded.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.6
MB91665 Series
■ Notes on Using the PWC Timer
● Notes on setting through programming
•
Writing "1" to the counting enable bit (CTEN) clears the counter, nullifying the data existing in the
counter before counting is enabled.
•
If you set the PWC mode (FMD = 100B) after a system reset or in reset mode and enables measurement
(CTEN = 1) at the same time, the timer may operate according to the immediately preceding
measurement signal.
•
If a measurement start edge is detected the moment a restart is set in continuous measurement mode,
the timer immediately starts counting from "0001H".
•
An attempt to restart the timer after starting counting can result as follows, depending on that timing:
-
If the attempt is made at a measurement end edge in one-shot pulse width measurement mode:
Although the timer is restarted and waits for an measurement start edge, the measurement end flag
(EDIR) is set.
-
If the attempt is made at a measurement end edge in continuous pulse width measurement mode:
Although the timer is restarted and waits for a measurement start edge, the measurement end flag
(EDIR) is set and the current measurement result is transferred to the BTxDTBF register.
When restarting the timer during operation, control interrupts while paying attention to the behaviors of
flags.
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CHAPTER 23 Base Timer
23.7
MB91665 Series
23.7 Base Timer Interrupts
This section lists the interrupt request flags, interrupt enable bits, and interrupt factors for the base
timer in each timer function mode.
■ Interrupt Control Bits and Interrupt Factors by Timer Function Mode
Table 23.7-1 lists the interrupt control bits and interrupt factors for the base timer in each timer function
mode.
Table 23.7-1 Interrupt Control Bits and Interrupt Factors in Each Timer Function Mode
Status control register (BTxSTC)
Interrupt request
flag bits
Interrupt request
enable bits
Interrupt factors
IRQ
UDIR: bit0
UDIE: bit4
Underflow detection
IRQ0
DTIR: bit1
DTIE: bit5
Duty match detection
TGIR: bit2
TGIE: bit6
Timer start trigger detection
IRQ1
PPG timer
function
UDIR: bit0
UDIE: bit4
Underflow detection
IRQ0
TGIR: bit2
TGIE: bit6
Timer start trigger detection
IRQ1
Reload timer
function
UDIR: bit0
UDIE: bit4
Underflow detection
IRQ0
TGIR: bit2
TGIE: bit6
Timer start trigger detection
IRQ1
PWC timer
function
OVIR: bit0
OVIE: bit4
Overflow detection
IRQ0
EDIR: bit2
EDIE: bit6
Measurement end detection
IRQ1
PWM timer
function
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8 Base Timer Description by Function Mode
This section describes each function of the base timer.
■ Base Timer Function
•
PWM function
•
PPG function
•
Reload timer function
•
PWC function
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CHAPTER 23 Base Timer
23.8
23.8.1
MB91665 Series
PWM Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its
timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload
timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the
PWM timer.
596
•
Timer Control Register (BTxTMCR) for PWM Timer
•
PWM Period Setting Register (BTxPCSR)
•
PWM Duty Setting Register (BTxPDUT)
•
Timer Register (BTxTMR)
•
16-bit PWM Timer Operation
•
One-shot Operation
•
Interrupt Factors and Timing Chart
•
Output Waveforms
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.1.1
Timer Control Register (BTxTMCR) for PWM Timer
The timer control register (BTxTMCR) controls the PWM timer. Keep in mind that the register contains
bits which cannot be updated with the PWM timer operating.
■ Timer Control Register (BTxTMCR Upper Byte)
Figure 23.8-1 Timer Control Register (BTxTMCR Upper Byte)
bit15
-
bit14
bit13
bit12
bit11
bit10
R/W
R/W
R/W
R/W
0
R/W
: Readable/writable
: Initial value
R/W
Initial value:
-0000000B (At reset)
R/W
Trigger input edge select bits
0
Disable trigger input
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
PMSK
Pulse output mask bit
0
Normal output
1
Fixed to "L"-level output
RTGEN
Restart enable bit
0
Disables restarting
1
Enable restarting
CKS2 CKS1 CKS0
CM71-10158-1E
bit8
CKS2 CKS1 CKS0 RTGEN PMSK EGS1 EGS0
EGS1 EGS0
R/W
bit9
Count clock select bits
0
0
0
φ
0
0
1
φ/4
0
1
0
φ/16
0
1
1
φ/128
1
0
0
φ/256
1
0
1
External clock (rising edge event)
1
1
0
External clock (falling edge event)
1
1
1
External clock (both edge event)
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-1 Timer Control Register (BTxTMCR Upper Byte)
Bit name
bit15
598
Function
Undefined bit
•
The read value of this bit is undefined.
•
Write to this bit takes no effect.
Select the count clock for the 16-bit down counter.
The count clock promptly reflects any changes made to its
setting. CKS2 to CKS0 must therefore be updated while counting
is stopped (CTEN = 0). Note, however, that you can change their
setting at the same time as writing "1" to the CTEN bit.
bit14
to
bit12
CKS2, CKS1, CKS0:
Count clock select
bits
•
•
bit11
RTGEN:
Restart enable bit
Enables restarting with a software trigger or trigger input.
bit10
PMSK:
Pulse output mask bit
•
•
•
bit9,
bit8
EGS1, EGS0:
Trigger input edge
select bits
•
Controls the PWM output waveform level.
When this bit is "0", the PWM waveform is output as it is.
When the bit is "1", the PWM output is masked to the "L" level
irrespective of the period and duty cycle.
Note:
Setting the PMSK bit to "1" with the OSEL bit (bit3) set for
inverted output masks the PWM output to the "H" level.
Select the effective edge of the input waveform as an external
trigger to set the trigger condition.
• When these bits are set to the initial value or "00B", no effective
edge of the input waveform is selected, preventing the timer from
being triggered by the external waveform.
Note:
Writing "1" to the STRG bit enables the software trigger
irrespective of the settings of EGS1 and EGS0.
• EGS1 and EGS0 must be updated while counting is stopped
(CTEN = 0). Note, however, that you can change their setting at
the same time as writing "1" to the CTEN bit.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
■ Timer Control Register (BTxTMCR Lower Byte)
Figure 23.8-2 Timer Control Register (BTxTMCR Lower Byte)
bit7
R/W
bit6
bit5
bit4
bit3
bit2
bit1
FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
00000000B (At reset)
STRG
Software trigger bit
0
Disable software trigger
1
Start with software trigger
CTEN
Counting enable bit
0
Disables counting
1
Enables counting
MDSE
Mode select bit
0
Continuous operation
1
One-shot operation
OSEL
Output polarity select bit
0
Normal polarity
1
Inverted polarity
FMD2 FMD1 FMD0
R/W
-
bit0
Timer function select bits
0
0
0
Reset mode
0
0
1
Selects PWM function mode
0
1
0
Selects PPG function mode
0
1
1
Selects reload timer function mode
1
0
0
Selects PWC function mode
: Readable/writable
: Undefined bit
1
0
1
1
1
0
: Initial value
1
1
1
CM71-10158-1E
FUJITSU SEMICONDUCTOR LIMITED
Setting not allowed
599
CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-2 Timer Control Register (BTxTMCR Lower Byte)
Bit name
bit7
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit6
to
bit4
FMD2, FMD1,
FMD0:
Timer function select
bits
•
•
These bits select the timer function mode.
Setting the FMD2, FMD1, and FMD0 bits to "001B" selects the
PWM function mode.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
bit3
600
Function
OSEL:
Output polarity select
bit
•
Selects the polarity of PWM output.
Polarity
After reset
Normal
"L" output
Inverted
"H" output
Duty match
Underflow
bit2
MDSE:
Mode select bit
•
•
Selects continuous pulse output or one-shot pulse output.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
bit1
CTEN:
Counting enable bit
•
•
This bit enables the down counter.
Writing "0" to the CTEN bit with the counter enabled (CTEN = 1)
stops the counter.
bit0
STRG:
Software trigger bit
•
Writing "1" to the STRG bit with the CTEN bit containing "1"
generates a software trigger.
Note:
Writing "1" to the CTEN and STRG bits at the same time also
generates a software trigger.
• The value read from the STRG bit is always "0".
Note:
Writing "1" to the STRG bit enables the software trigger
irrespective of the settings of the EGS1 and EGS0 bits.
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CHAPTER 23 Base Timer
23.8
MB91665 Series
■ Status Control Register (BTxSTC)
Figure 23.8-3 Status Control Register (BTxSTC)
R/W
-
bit7
bit6
bit5
bit4
bit3
-
TGIE
DTIE
UDIE
-
R/W
R/W
R/W
R/W
R/W
: Readable/writable
: Undefined bit
bit2
bit1
bit0
TGIR DTIR UDIR
R/W
R/W
R/W
Initial value:
00000000B (At
reset)
UDIR
Underflow interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
DTIR
Duty match interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
TGIR
Trigger interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
UDIE
Underflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
DTIE
Duty match interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
TGIE
Trigger interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
: Initial value
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CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-3 Status Control Register (BTxSTC)
Bit name
bit7
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit6
TGIE:
Trigger interrupt
request enable bit
•
•
Controls bit2: TGIR interrupt requests.
Setting the TGIR bit (bit2) with the TGIE bit enabling trigger
interrupt requests generates an interrupt request to the CPU.
bit5
DTIE:
Duty match
interrupt request
enable bit
•
•
Controls bit1: DTIR interrupt requests.
Setting the DTIR bit (bit1) with the DTIE bit enabling duty match
interrupt requests generates an interrupt request to the CPU.
bit4
UDIE:
Underflow
interrupt request
enable bit
•
•
Controls bit0: UDIR interrupt requests.
Setting the UDIR bit (bit0) with the UDIE bit enabling underflow
interrupt requests generates an interrupt request to the CPU.
bit3
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit2
TGIR:
Trigger interrupt
request bit
•
The TGIR bit is set to "1" upon detection of a software trigger or
trigger input.
Writing "0" to the TGIR bit clears it.
Writing "1" to the TGIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit always
returns "1" irrespective of the current bit value.
DTIR:
Duty match
interrupt request bit
•
bit1
bit0
602
Function
UDIR:
Underflow
interrupt request bit
•
•
•
•
•
•
•
•
•
•
The DTIR bit is set to "1" when the count value matches the duty
cycle setting.
Writing "0" to the DTIR bit clears it.
Writing "1" to the DTIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit always
returns "1" irrespective of the current bit value.
The UDIR bit is set to "1" when a count value underflow occurs from
0000H to FFFFH.
Writing "0" to the UDIR bit clears it.
Writing "1" to the UDIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit always
returns "1" irrespective of the current bit value.
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.1.2
PWM Period Setting Register (BTxPCSR)
The PWM period setting register (BTxPCSR) is a buffered register for setting the PWM period.
Transfer to the timer register takes place when the counter is started and when it causes an underflow.
■ Bit Configuration of the PWM Period Setting Register (BTxPCSR)
Figure 23.8-4 shows the bit configuration of the PWM period setting register (BTxPCSR).
Figure 23.8-4 Bit Configuration of the PWM Period Setting Register (BTxPCSR)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTxPCSR register is a buffered register for setting the PWM period. Transfer to the timer register
takes place when the counter is started and when it causes an underflow.
After writing to the period setting register to initially set or update it, be sure to write to the duty setting
register.
•
Access the BTxPCSR register using 16-bit data.
•
Set the PWM period using the BTxPCSR register after selecting the PWM function mode using the
FMD2, FMD1, and FMD0 bits in the BTxTMCR register.
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CHAPTER 23 Base Timer
23.8
23.8.1.3
MB91665 Series
PWM Duty Setting Register (BTxPDUT)
The PWM duty setting register (BTxPDUT) is a buffered register for setting the PWM duty cycle.
Transfer from the buffer takes place when an underflow occurs.
■ Bit Configuration of the PWM Duty Setting Register (BTxPDUT)
Figure 23.8-5 shows the bit configuration of the PWM duty setting register (BTxPDUT).
Figure 23.8-5 Bit Configuration of the PWM Duty Setting Register (BTxPDUT)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB
(At reset)
Initial value:
XXXXXXXXB
(At reset)
R/W : Readable/writable
X
: Undefined value
The BTxPDUT register is a buffered register for setting the PWM duty cycle. Transfer from the buffer
takes place when an underflow occurs.
If you set the period setting and duty setting registers to the same value, the output level is all "H" in
normal polarity or all "L" in inverted polarity.
Do not set the BTxPDUT register to a value greater than the value of the BTxPSCR register, or PWM
output will be undefined.
604
•
Access the BTxPDUT register using 16-bit data.
•
Set the PWM duty cycle using the BTxPDUT register after selecting the PWM function mode using the
FMD2, FMD1, and FMD0 bits in the BTxTMCR register.
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.1.4
Timer Register (BTxTMR)
The timer register (BTxTMR) allows the value of the 16-bit down counter to be read from.
■ Bit Configuration of the Timer Register (BTxTMR)
Figure 23.8-6 shows the bit configuration of the PWM timer register (BTxTMR).
Figure 23.8-6 Bit Configuration of the Timer Register (BTxTMR)
bit15
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
bit14
R
R
R
R
R
R
R
Initial value:
00000000B
(At reset)
Initial value:
00000000B
(At reset)
: Read only
The BTxTMR register allows the value of the 16-bit down counter to be read from.
<Note>
Access the BTxTMR register using 16-bit data.
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CHAPTER 23 Base Timer
23.8
23.8.1.5
MB91665 Series
16-bit PWM Timer Operation
In PWM timer mode, a waveform having a specified period can be output either in single shots or
continuously after detection of a trigger.
The period of output pulses can be controlled by changing the BTxPCSR value.
The duty ratio can be controlled by changing the BTxPDUT value. After writing data to the BTxPCSR
register, be sure to write to the BTxPDUT register as well.
■ Continuous Operation
● When restarting is disabled (RTGEN = 0)
Figure 23.8-7 PWM Operation Timing Chart (Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
O
PWM
output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
T
m
n
: Count clock cycle
: BTxPCSR value
: BTxPDUT value
● When restarting is enabled (RTGEN = 1)
Figure 23.8-8 PWM Operation Timing Chart (Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
O
PWM output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
606
T
m
n
: Count clock cycle
: BTxPCSR value
: BTxPDUT value
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.1.6
One-shot Operation
In one-shot operation mode, single pulses with an arbitrary width can be output by trigger. When
restarting is enabled, the counter is reloaded upon detection of a trigger edge during operation.
■ One-shot Operation
● When restarting is disabled (RTGEN = 0)
Figure 23.8-9 One-shot Operation Timing Chart (Trigger Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
O
PWM output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
T
m
n
: Count clock cycle
: BTxPCSR value
: BTxPDUT value
● When restarting is enabled (RTGEN = 1)
Figure 23.8-10 One-shot Operation Timing Chart (Trigger Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
O
PWM output
waveform
(1)
(2)
(1) = T(n+1) ms
(2) = T(m+1) ms
CM71-10158-1E
T
m
n
: Count clock cycle
: BTxPCSR value
: BTxPDUT value
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CHAPTER 23 Base Timer
23.8
23.8.1.7
MB91665 Series
Interrupt Factors and Timing Chart
This section provides the interrupt factors and timing chart.
■ Interrupt Factors and Timing Chart (PWM Output: Normal Polarity)
A software trigger requires T and an external trigger requires 2T to 3T (T: peripheral clock (PCLK) cycle)
until the counter value is loaded after the input of the trigger.
Figure 23.8-11 shows the interrupt factors and timing chart, assuming "period setting" = 3 and
"duty value" = 1.
Figure 23.8-11 PWM Timer Interrupt Factors and Timing Chart
Trigger
2T to 3T (external trigger)
Load
Count clock
Count value
XXXXH
0003H
0002H
0001H
0000H
0003H
0002H
PWM output waveform
Interrupt
Start edge
TGIR
608
Duty match
DTIR
Underflow
UDIR
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.1.8
Output Waveforms
This section illustrates PWM output.
■ PWM Output at All "L" or All "H" Level
Figure 23.8-12 and Figure 23.8-13 illustrate how to provide PWM output at all "L" and all "H" levels,
respectively.
Figure 23.8-12 Example of PWM Output at All "L" Level
Underflow interrupt
Duty value
0002H
0001H
0000H
XXXXH
PWM output waveform
Decrease the
duty value.
Use the underflow interrupt to set PMSK to "1".
The output waveform has all "L" level from the
current period.
Figure 23.8-13 Example of PWM Output at All "H" Level
Duty match interrupt
PWM output
waveform
Increase the
duty value.
Use the duty match interrupt to set the duty value
to the same as the period setting, and the output
waveform has all "H" level in the next period.
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CHAPTER 23 Base Timer
23.8
23.8.2
MB91665 Series
PPG Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its
timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload
timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the
PPG timer.
610
•
Timer Control Register (BTxTMCR) for PPG Timer
•
"L"-width Setting Reload Register (BTxPRLL)
•
"H"-width Setting Reload Register (BTxPRLH)
•
Timer Register (BTxTMR)
•
16-bit PPG Timer Operation
•
Continuous Operation
•
One-shot Operation
•
Interrupt Factors and Timing Chart
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.2.1
Timer Control Register (BTxTMCR) for PPG Timer
The timer control register (BTxTMCR) controls the PPG timer. Keep in mind that the register contains
bits which cannot be updated with the PPG timer operating.
■ Timer Control Register (BTxTMCR Upper Byte)
Figure 23.8-14 Timer Control Register (BTxTMCR Upper Byte)
bit15
-
bit14
bit13
bit12
bit11
bit10
R/W
R/W
R/W
R/W
R/W
R/W
0
0
Disable trigger input
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
Pulse output mask bit
0
Normal output
1
Fixed to "L"-level output
RTGEN
Restart enable bit
0
Disables restarting
1
Enable restarting
CKS2 CKS1 CKS0
: Readable/writable
: Initial value
R/W
Initial value:
-0000000B (At reset)
Trigger input edge select bits
PMSK
CM71-10158-1E
bit8
CKS2 CKS1 CKS0 RTGEN PMSK EGS1 EGS0
EGS1 EGS0
R/W
bit9
Count clock select bits
0
0
0
φ
0
0
1
φ/4
0
1
0
φ/16
0
1
1
φ/128
1
0
0
φ/256
1
0
1
External clock (rising edge event)
1
1
0
External clock (falling edge event)
1
1
1
External clock (both edge event)
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CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-4 Timer Control Register (BTxTMCR Upper Byte)
Bit name
612
Function
bit15
Undefined bit
•
•
The read value of this bit is undefined.
Write to this bit takes no effect.
bit14
to
bit12
CKS2, CKS1,
CKS0:
Count clock select
bits
•
•
Select the count clock for the 16-bit down counter.
The count clock promptly reflects any changes made to its
setting.
CKS2 to CKS0 must therefore be updated while counting is
stopped (CTEN = 0). Note, however, that you can change their
setting at the same time as writing "1" to the CTEN bit.
bit11
RTGEN:
Restart enable bit
This bit enables restarting with a software trigger or trigger input.
bit10
PMSK:
Pulse output mask bit
•
•
•
bit9,
bit8
EGS1, EGS0:
Trigger input edge
select bits
•
Controls the PPG output waveform level.
When this bit is "0", the PPG waveform is output as it is.
When the bit is "1", the PPG output is masked to the "L" level
irrespective of the "H" and "L" width settings.
Note:
Setting the PMSK bit to "1" with the OSEL bit (bit3) set for
inverted output masks the PPG output to the "H" level.
Select the effective edge of the input waveform as an external
trigger to set the trigger condition.
• When these bits are set to the initial value or "00B", no effective
edge of the input waveform is selected, preventing the timer
from being triggered by the external waveform.
Note:
Writing "1" to the STRG bit enables the software trigger
irrespective of the settings of EGS1 and EGS0.
• EGS1 and EGS0 must be updated while counting is stopped
(CTEN = 0). Note, however, that you can change their setting at
the same time as writing "1" to the CTEN bit.
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CHAPTER 23 Base Timer
23.8
MB91665 Series
■ Timer Control Register (BTxTMCR Lower Byte)
Figure 23.8-15 Timer Control Register (BTxTMCR Lower Byte)
bit7
R/W
bit6
bit5
bit4
bit3
bit2
bit1
FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
R/W
R/W
R/W
R/W
R/W
R/W
: Readable/writable
: Undefined bit
R/W
Initial value:
00000000B (At reset)
STRG
Software trigger bit
0
Disable software trigger
1
Start with software trigger
CTEN
Counting enable bit
0
Disables counting
1
Enables counting
MDSE
Mode select bit
0
Continuous operation
1
One-shot operation
OSEL
Output polarity select bit
0
Normal polarity
1
Inverted polarity
FMD2 FMD1 FMD0
R/W
-
bit0
Timer function select bits
0
0
0
Reset mode
0
0
1
Select PWM function mode
0
1
0
Select PPG function mode
0
1
1
Select reload timer function mode
1
0
0
Select PWC function mode
1
0
1
1
1
0
1
1
1
Setting not allowed
: Initial value
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CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-5 Timer Control Register (BTxTMCR Lower Byte)
Bit name
bit7
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit6
to
bit4
FMD2, FMD1,
FMD0:
Timer function
select bits
•
•
These bits select the timer function mode.
Setting the FMD2, FMD1, and FMD0 bits to "010B" selects the
PPG function mode.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
bit3
614
Function
OSEL:
Output polarity
select bit
•
Selects the polarity of PPG output.
Polarity
After
reset
Normal
"L" output
Inverted
"H" output
End of "L"width
counting
End of "H"width
counting
bit2
MDSE:
Mode select bit
•
•
Selects continuous pulse output or one-shot pulse output.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
bit1
CTEN:
Counting enable bit
•
•
This bit enables the down counter.
Writing "0" to the CTEN bit with the counter enabled (CTEN = 1)
stops the counter.
bit0
STRG:
Software trigger bit
•
Writing "1" to the STRG bit with the CTEN bit containing "1"
generates a software trigger.
Note:
Writing "1" to the CTEN and STRG bits at the same time also
generates a software trigger.
• The value read from the STRG bit is always "0".
Note:
Writing "1" to the STRG bit enables the software trigger
irrespective of the settings of the EGS1 and EGS0 bits.
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CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
■ Status Control Register (BTxSTC)
Figure 23.8-16 Status Control Register (BTxSTC)
R/W
-
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
TGIE
-
UDIE
-
TGIR
-
UDIR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
00000000B (At reset)
UDIR
Underflow interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
TGIR
Trigger interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
UDIE
Underflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
TGIE
Trigger interrupt request enable bit
: Readable/writable
: Undefined bit
0
Disables interrupt requests
: Initial value
1
Enables interrupt requests
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CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-6 Status Control Register (BTxSTC)
Bit name
Function
bit7
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit6
TGIE:
Trigger interrupt
request enable bit
•
•
Controls bit2: TGIR interrupt requests.
Setting the TGIR bit (bit2) with the TGIE bit enabling trigger
interrupt requests generates an interrupt request to the CPU.
bit5
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit4
UDIE:
Underflow interrupt
request enable bit
•
•
Controls bit0: UDIR interrupt requests.
Setting the UDIR bit (bit0) with the UDIE bit enabling underflow
interrupt requests generates an interrupt request to the CPU.
bit3
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit2
TGIR:
Trigger interrupt
request bit
•
The TGIR bit is set to "1" upon detection of a software trigger or
trigger input.
Writing "0" to the TGIR bit clears it.
Writing "1" to the TGIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit
always returns "1" irrespective of the current bit value.
•
•
•
bit1
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit0
UDIR:
Underflow interrupt
request bit
•
The UDIR bit is set to "1" when a count value underflow occurs
from 0000H to FFFFH during counting from the value set as the
"H" width.
Writing "0" to the UDIR bit clears it.
Writing "1" to the UDIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit
always returns "1" irrespective of the current bit value.
•
•
•
616
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.2.2
"L"-width Setting Reload Register (BTxPRLL)
The "L"-width setting reload register (BTxPRLL) is used to set the "L" width of PPG output waveforms.
Transfer to the timer register takes place upon detection of a start trigger or when an underflow occurs
at the end of "H"-width counting.
■ Bit Configuration of the "L"-width Setting Reload Register (BTxPRLL)
Figure 23.8-17 shows the bit configuration of the "L"-width setting reload register (BTxPRLL).
Figure 23.8-17 Bit Configuration of the "L"-width Setting Reload Register (BTxPRLL)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTxPRLL register is used to set the "L" width of PPG output waveforms. Transfer to the timer
register takes place upon detection of a start trigger or when an underflow occurs at the end of "H"-width
counting.
•
Access the BTxPRLL register using 16-bit data.
•
Set the "L" width using the BTxPRLL register after selecting the PPG function mode using the FMD2,
FMD1, and FMD0 bits in the BTxTMCR register.
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CHAPTER 23 Base Timer
23.8
23.8.2.3
MB91665 Series
"H"-width Setting Reload Register (BTxPRLH)
The "H"-width setting reload register (BTxPRLH) is a buffered register for setting the "H" width of PPG
output waveforms. Transfer from the BTxPRLH register to the buffer register takes place upon
detection of a start trigger or when an underflow occurs at the end of "H"-width counting. Transfer from
the buffer register to the timer register takes place when an underflow occurs at the end of "L" width
counting.
■ Bit Configuration of the "H"-width Setting Reload Register (BTxPRLH)
Figure 23.8-18 shows the bit configuration of the "H"-width setting reload register (BTxPRLH).
Figure 23.8-18 Bit Configuration of the "H"-width Setting Reload Register (BTxPRLH)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTxPRLH register is used to set the "H" width of PPG output waveforms. Transfer from the
BTxPRLH register to the buffer register takes place upon detection of a start trigger or when an
underflow occurs at the end of "H"-width counting. Transfer from the buffer register to the timer register
takes place when an underflow occurs at the end of "L" width counting.
618
•
Access the BTxPRLH register using 16-bit data.
•
Set the "H" width using the BTxPRLH register after selecting the PPG function mode using the FMD2,
FMD1, and FMD0 bits in the BTxTMCR register.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.2.4
Timer Register (BTxTMR)
The timer register (BTxTMR) allows the value of the 16-bit down counter to be read from.
■ Bit Configuration of the Timer Register (BTxTMR)
Figure 23.8-19 shows the bit configuration of the PPG timer register (BTxTMR).
Figure 23.8-19 Bit Configuration of the Timer Register (BTxTMR)
bit15
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
bit14
R
R
R
R
R
R
R
Initial value:
00000000B (At reset)
Initial value:
00000000B (At reset)
: Read only
The BTxTMR register allows the value of the 16-bit down counter to be read from.
<Note>
Access the BTxTMR register using 16-bit data.
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CHAPTER 23 Base Timer
23.8
23.8.2.5
MB91665 Series
16-bit PPG Timer Operation
In PPG timer mode, an arbitrary output pulse can be controlled by setting its "L" and "H" widths in their
respective reload registers.
■ Principles of Operation
The PPG timer has two 16-bit reload registers for setting the "L" and "H" widths respectively and one "H"
width setting buffer (BTxPRLL, BTxPRLH, BTxPRLHB).
In response to the start trigger, the 16-bit down counter loads the BTxPRLL value and the BTxPRLH
value is transferred to the BTxPRLHB buffer at the same time. The counter is decremented every count
clock with the PPG output at the "L" level. When an underflow is detected, the counter reloads the
BTxPRLHB value and is decremented with the PPG output waveform inverted. When an underflow is
detected again, the PPG output waveform is inverted, the counter reloads the BTxPRLL set value, and the
BTxPRLH set value is transferred to the BTxPRLHB buffer.
Through these steps, the output waveform becomes the pulse output with the "L" and "H" widths
corresponding to their respective reload register values.
■ Reload Register Write Timing
Data is written to the BTxPRLL and BTxPRLH reload registers upon detection of a start trigger and
between when the underflow interrupt request bit (UDIR) is set and when the next period begins. The
data set then becomes the setting for the next period. The BTxPRLL and BTxPRLH settings are
automatically transferred to the BTxTMR and BTxPRLHB, respectively, upon detection of a start trigger
and when an underflow occurs at the end of "H" width counting. The data transferred to the BTxPRLHB
is automatically reloaded to the BTxTMR when an underflow occurs at the end of "L" width counting.
Rising edge detected
Trigger
IRQ1 (TGIR source)
IRQ0 (UDIR source)
Set the L width and H width of the next cycle to registers.
BTnPRLL
L0
L1
L2
L3
BTnPRLH
H0
H1
H2
H3
BTnPRLHB
xxxx
BTnTMR
xxxx
H1
H0
L0 to 0000
H2
H0 to
0000
L1 to 0000
H1 to
0000
H0
L1
H1
L2 to 0000
H2 to
0000
PPG output waveforms
L0
620
FUJITSU SEMICONDUCTOR LIMITED
L2
H2
CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.2.6
Continuous Operation
In continuous operation mode, an arbitrary pulse can be output continuously by updating the "L" and
"H" widths at the set timing of each interrupt. When restarting is enabled, the counter is reloaded upon
detection of a trigger edge during operation.
■ Continuous Operation
● When restarting is disabled (RTGEN = 0)
Figure 23.8-20 PPG Operation Timing Chart (Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
O
PPG output waveform
(1)
(2)
Interrupt
Start edge
TGIR
Underflow
UDIR
Underflow
UDIR
(1) = T(m+1) ms
(2) = T(n+1) ms
T : Count clock cycle
m : BTxPRLL value
n : BTxPRLH value
● When restarting is enabled (RTGEN = 1)
Figure 23.8-21 PPG Operation Timing Chart (Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
O
PPG output waveform
(2)
(1) = T(m+1) ms
(2) = T(n+1) ms
CM71-10158-1E
(1)
T : Count clock cycle
m : BTxPRLL value
n : BTxPRLH value
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23.8
23.8.2.7
MB91665 Series
One-shot Operation
In one-shot operation mode, single pulses with an arbitrary width can be output by trigger. When
restarting is enabled, the counter is reloaded upon detection of a trigger edge during operation.
■ One-shot Operation
● When restarting is disabled (RTGEN = 0)
Figure 23.8-22 One-shot Operation Timing Chart (Trigger Restarting Disabled)
Rising edge detected
Trigger is ignored.
Trigger
m
n
O
PPG output waveform
(1)
(2)
(1) = T(m+1) ms
(2) = T(n+1) ms
T : Count clock cycle
m : BTxPRLL value
n : BTxPRLH value
● When restarting is enabled (RTGEN = 1)
Figure 23.8-23 One-shot Operation Timing Chart (Trigger Restarting Enabled)
Rising edge detected
Restarted by trigger
Trigger
m
n
O
PPG output waveform
(1)
(2)
(1) = T(m+1) ms
(2) = T(n+1) ms
622
T : Count clock cycle
m : BTxPRLL value
n : BTxPRLH value
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CHAPTER 23 Base Timer
23.8
MB91665 Series
■ Relationship between Reload Value and Pulse Width
The output pulse width is obtained by adding 1 to the value written in the 16-bit reload register and
multiplying the result by the count clock cycle. When the reload register value is 0000H, therefore, the
output has a pulse width of one count clock cycle. When the reload register value is FFFFH, the output
has a pulse width of 65536 count clock cycles. The pulse width is calculated from the following equation.
PL = T × (L+1)
PH = T × (H+1)
CM71-10158-1E
PL : "L" pulse width
PH : "H" pulse width
T
: Count clock cycle
L
: BTxPRLL value
H
: BTxPRLH value
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CHAPTER 23 Base Timer
23.8
23.8.2.8
MB91665 Series
Interrupt Factors and Timing Chart
This section provides the interrupt factors and timing chart.
■ Interrupt Factors and Timing Chart (PPG Output: Normal Polarity)
A software trigger requires T and an external trigger requires 2T to 3T (T: peripheral clock (PCLK) cycle)
until the counter value is loaded after the trigger is generated.
Interrupt factors are set when the PPG start trigger is detected and when an underflow is detected during
"H" level output.
Figure 23.8-24 shows the interrupt factors and timing chart, assuming "L" width setting = 1 and "H"
width setting = 1.
Figure 23.8-24 PPG Timer Interrupt Factors and Timing Chart
Trigger
2T to 3T (external trigger)
Load
Count clock
Count value
XXXXH
0001H
0000H
0001H
0000H
0001H
0000H
PPG output waveform
Interrupt
Start edge
TGIR
624
Underflow
UDIR
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.3
Reload Timer Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its
timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload
timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the
reload timer.
•
Timer Control Register (BTxTMCR) for Reload Timer
•
Period Setting Register (BTxPCSR)
•
Timer Register (BTxTMR)
•
16-bit Reload Timer Operation
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CHAPTER 23 Base Timer
23.8
23.8.3.1
MB91665 Series
Timer Control Register (BTxTMCR) for Reload Timer
The timer control register (BTxTMCR) controls the reload timer.
■ Timer Control Register (BTxTMCR Upper Byte)
Figure 23.8-25 Timer Control Register (BTxTMCR Upper Byte)
bit15
-
bit14
bit13
bit12
CKS2 CKS1 CKS0
R/W
R/W
R/W
bit11
bit10
-
-
-
-
bit9
bit8
EGS1 EGS0
R/W
R/W
EGS1 EGS0
0
Trigger edge select bits
0
Disable trigger input
0
1
External trigger (rising edge)
1
0
External trigger (falling edge)
1
1
External trigger (both edges)
CKS2 CKS1 CKS0
R/W
-
626
Initial value:
00000000B (At reset)
Count clock select bits
φ
0
0
0
0
0
1
φ/4
0
1
0
φ/16
0
1
1
φ/128
1
0
0
φ/256
: Readable/writable
: Undefined bit
1
0
1
External clock (rising edge event)
1
1
0
External clock (falling edge event)
: Initial value
1
1
1
External clock (both edge event)
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-7 Timer Control Register (BTxTMCR Upper Byte)
Bit name
CM71-10158-1E
Function
bit15
Undefined bit
•
•
The read value of this bit is undefined.
Write to this bit takes no effect.
bit14
to
bit12
CKS2, CKS1,
CKS0:
Count clock select bits
•
•
Select the count clock for the 16-bit down counter.
The count clock promptly reflects any changes made to its
setting. CKS2 to CKS0 must therefore be updated while
counting is stopped (CTEN = 0). Note, however, that you can
change their setting at the same time as writing "1" to the
CTEN bit.
bit11,
bit10
Undefined bits
•
•
The value read is "0"
When writing to these bits, write "0".
bit9,
bit8
EGS1, EGS0:
Trigger edge select bits
•
Select the effective edge of the input waveform as an external
trigger to set the trigger condition.
• When these bits are set to the initial value or "00B", no
effective edge of the input waveform is selected, preventing
the timer from being triggered by the external waveform.
Note:
Writing "1" to the STRG bit enables the software trigger
irrespective of the settings of EGS1 and EGS0.
• EGS1 and EGS0 must be updated while counting is stopped
(CTEN = 0). Note, however, that you can change their setting
at the same time as writing "1" to the CTEN bit.
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MB91665 Series
■ Timer Control Register (BTxTMCR Lower Byte)
Figure 23.8-26 Timer Control Register (BTxTMCR Lower Byte)
bit7
T32
R/W
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STRG
Software trigger bit
0
Disable software trigger
1
Start with software trigger
CTEN
Counting enable bit
0
Disables counting
1
Enables counting
MDSE
Mode select bit
0
Reload mode
1
One-shot mode
OSEL
Output polarity select bit
0
Normal polarity
1
Inverted polarity
FMD2 FMD1 FMD0
R/W
: Readable/writable
: Initial value
628
Initial value:
00000000B (At reset)
Timer function select bits
0
0
0
Reset mode
0
0
1
Select PWM function mode
0
1
0
Select PPG function mode
0
1
1
Select reload timer function mode
1
0
0
Select PWC function mode
1
0
1
1
1
0
1
1
1
Setting not allowed
T32
32-bit timer select bit
0
16-bit timer mode
1
32-bit timer mode
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CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-8 Timer Control Register (BTxTMCR Lower Byte)
Bit name
bit7
Function
T32:
32-bit timer select bit
•
•
•
bit6
to
bit4
bit3
bit2
FMD2, FMD1,
FMD0:
Timer function select
bits
OSEL:
Output polarity select
bit
MDSE:
Mode select bit
•
•
•
•
•
•
•
•
CM71-10158-1E
bit1
CTEN:
Counting enable bit
•
•
bit0
STRG:
Software trigger bit
•
This bit selects the 32-bit timer mode.
When the FMD2, FMD1, and FMD0 bits contain "011B" to select
the reload timer, setting the T32 bit to "1" places the timer in 32-bit
timer mode.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
→See Section "23.5 32-bit Mode Operations".
These bits select the timer function mode.
Setting the FMD2, FMD1, and FMD0 bits to "011B" selects the
reload timer function mode.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
Selects the timer output at normal level or inverted level.
The output waveform is generated as follows depending on the
combination with the MDSE bit (bit2):
MDSE
OSEL
Output Waveforms
0
0
Toggle output of "L" at the count start
0
1
Toggle output of "H" at the count start
1
0
Rectangular wave of "H" during count
1
1
Rectangular wave of "L" during count
Setting the MDSE bit to "0" selects reload mode, in which the
counter loads the reload register value to continue counting the
moment a count value underflow occurs from 0000H to FFFFH.
Setting the MDSE bit to "1" selects one-shot mode, in which the
counter stops operation the moment a count value underflow
occurs from 0000H to FFFFH.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
This bit enables the down counter.
Writing "0" to the CTEN bit with the counter enabled (CTEN = 1)
stops the counter.
Writing "1" to the STRG bit with the CTEN bit containing "1"
generates a software trigger.
Note:
Writing "1" to the CTEN and STRG bits at the same time also
generates a software trigger.
• The value read from the STRG bit is always "0".
Note:
Writing "1" to the STRG bit enables the software trigger
irrespective of the settings of the EGS1 and EGS0 bits.
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23.8
MB91665 Series
■ Status Control Register (BTxSTC)
Figure 23.8-27 Status Control Register (BTxSTC)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
TGIE
-
UDIE
-
TGIR
-
UDIR
-
R/W
-
R/W
-
R/W
-
R/W
UDIR
R/W
-
630
: Readable/writable
: Undefined bit
: Initial value
Initial value:
00000000B (At reset)
Underflow interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
TGIR
Trigger interrupt request bit
0
Clears interrupt factor
1
Indicates that interrupt factor has been detected
UDIE
Underflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
TGIE
Trigger interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
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CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
Table 23.8-9 Status Control Register (BTxSTC)
Bit name
CM71-10158-1E
Function
bit7
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit6
TGIE:
Trigger interrupt
request enable bit
•
•
Controls bit2:TGIR interrupt requests.
Setting the TGIR bit (bit2) with the TGIE bit enabling trigger
interrupt requests generates an interrupt request to the CPU.
bit5
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit4
UDIE:
Underflow interrupt
request enable bit
•
•
Controls bit0:UDIR interrupt requests.
Setting the UDIR bit (bit0) with the UDIE bit enabling underflow
interrupt requests generates an interrupt request to the CPU.
bit3
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit2
TGIR:
Trigger interrupt
request bit
•
The TGIR bit is set to "1" upon detection of a software trigger or
trigger input.
Writing "0" to the TGIR bit clears it.
Writing "1" to the TGIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit
always returns "1" irrespective of the current bit value.
bit1
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit0
UDIR:
Underflow interrupt
request bit
•
The UDIR bit is set to "1" when a count value underflow occurs
from 0000H to FFFFH.
Writing "0" to the UDIR bit clears it.
Writing "1" to the UDIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit
always returns "1" irrespective of the current bit value.
•
•
•
•
•
•
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CHAPTER 23 Base Timer
23.8
23.8.3.2
MB91665 Series
Period Setting Register (BTxPCSR)
The period setting register (BTxPCSR) holds the initial count value. In 32-bit mode, the register holds
the initial count value of the lower 16 bits for the even-numbered channel or the initial count value of
the upper 16 bits for the odd-numbered channel. The initial value immediately after a reset is
undefined. To access this register, be sure to use a 16-bit data transfer instruction.
■ Bit Configuration of the Period Setting Register (BTxPCSR)
Figure 23.8-28 shows the bit configuration of the period setting register (BTxPCSR).
Figure 23.8-28 Bit Configuration of the Period Setting Register (BTxPCSR)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
R/W : Readable/writable
X
: Undefined value
The BTxPCSR register is used to set the period. Transfer to the timer register takes place when an
underflow occurs.
632
•
Access the BTxPCSR register using 16-bit data.
•
Set the period using the BTxPCSR register after selecting the reload timer function mode using the
FMD2, FMD1, and FMD0 bits in the BTxTMCR register.
•
To write data to the BTxPCSR register in 32-bit mode, access its upper 16-bit data (data for the oddnumbered channel) first and then the lower 16-bit data (data for the even-numbered channel).
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.3.3
Timer Register (BTxTMR)
The timer register (BTxTMR) allows the count value of the timer to be read from. In 32-bit mode, the
register holds the count value of the lower 16 bits for the even-numbered channel or the count value
for the upper 16 bits for the odd-numbered channel. The initial value is undefined.
To read this register, be sure to use a 16-bit data transfer instruction.
■ Bit Configuration of the Timer Register (BTxTMR)
Figure 23.8-29 shows the bit configuration of the timer register (BTxTMR).
Figure 23.8-29 Bit Configuration of the Timer Register (BTxTMR)
bit15
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
bit14
R
R
R
R
R
R
R
Initial value:
00000000B (At reset)
Initial value:
00000000B (At reset)
: Read only
The BTxTMR register allows the value of the 16-bit down counter to be read from.
<Notes>
•
Access the BTxTMR register using 16-bit data.
•
To read data from the BTxTMR register in 32-bit mode, access its lower 16-bit data (data for the
even-numbered channel) first and then the upper 16-bit data (data for the odd-numbered
channel).
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CHAPTER 23 Base Timer
23.8
23.8.3.4
MB91665 Series
16-bit Reload Timer Operation
In reload timer mode, the timer decrements the counter from the value set in the period setting
register in synchronization with the count clock, and finishes counting when the count value reaches
"0" or continues operation with the period setting loaded automatically until the counter stops being
decremented.
■ Counting with the Internal Clock Selected
To start counting the moment counting is enabled, write "1" to both of the CTEN and STRG bits in the
timer control register. The STRG bit maintains the trigger input always enabled irrespective of the
operation mode as long as the timer is active (CNTE = 1).
Enable counting and start the timer using a software trigger or external trigger, and the timer loads the
period setting register value to the counter to start decrementing the counter.
It takes 1T (T: peripheral clock (PCLK) cycle) for data in the period setting register to be loaded into the
counter after the counter start trigger is set.
Figure 23.8-30 illustrates how the counter is started by the software trigger and operates.
Figure 23.8-30 Counting with the Internal Clock Selected
Load
Count clock
Count value
XXXXH
Reload value
-1
-1
CTEN (register)
1T
STRG (register)
■ Underflow Operation
When the counter value changes from "0000H" to "FFFFH", the transition is detected as an underflow.
When the counter counts [period setting register value + 1], therefore, an underflow occurs.
When an underflow occurs, the content of the period setting register (BTxPCSR) is loaded into the
counter, and the counter continues counting if the MDSE bit in the timer control register (BTxTMCR) is
"0". If the MDSE bit is "1", the counter stops operation with the loaded counter value left unchanged.
When an underflow occurs, the UDIR bit in the status control register (BTxSTC) is set and an interrupt
request occurs if the UDIE bit is "1".
634
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CHAPTER 23 Base Timer
23.8
MB91665 Series
Figure 23.8-31 is a timing chart of underflow operation.
Figure 23.8-31 Underflow Operation Timing Chart
[MDSE=0]
Load
Count clock
Count value
0000H
Reload value
-1
-1
Underflow set
UDIR
[MDSE=1]
Load
Count clock
Count value
Reload value
0000H
Underflow set
UDIR
■ Input Pin Operation
The TGIN pin can be used as a trigger input. When the effective edge is input to the TGIN pin, the
counter loads the content of the period setting register and starts counting. It takes 2T or 3T (T: peripheral
clock (PCLK) cycle) for the counter value to be loaded after the trigger is applied.
Figure 23.8-32 illustrates the trigger input operation with the rising edge selected as the effective edge.
Figure 23.8-32 Trigger Input Operation
TGIN
2T to 3T (External trigger)
Load
Count clock
Count value
0000H
Reload value
-1
-1
■ Output Pin Operation
The TOUT pin functions as a toggle output to be inverted at each underflow in reload mode and as a
pulse output to indicate that counting is in process in one-shot mode. The output polarity can be set by the
OSEL bit in the timer control register (BTxTMCR). When the OSEL bit is "0", the initial value of the
toggle output is "0" and that of the one-shot pulse output is "1" (indicating that counting is in process).
Setting the OSEL bit to "1" inverts the output waveform.
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Figure 23.8-33 is a timing chart of output pin operation.
Figure 23.8-33 Output Pin Operation Timing Chart
[MDSE=0, OSEL=0]
CTEN
Inverted with OSEL = 1
TOUT
Trigger
Underflow
[MDSE=1, OSEL=0]
CTEN
Inverted with OSEL = 1
TOUT
Trigger
Underflow
Waiting for trigger start
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MB91665 Series
23.8.4
PWC Function
The base timer can assign itself, according to the settings of the FMD2, FMD1, and FMD0 bits in its
timer control register, to serve as only one of the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload
timer, and 16/32-bit PWC timer. This section describes the functions of the base timer assigned as the
PWC timer.
•
Timer Control Register (BTxTMCR) for PWC Timer
•
Data Buffer Register (BTxDTBF)
•
PWC Operation
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23.8.4.1
MB91665 Series
Timer Control Register (BTxTMCR) for PWC Timer
The timer control register (BTxTMCR) controls the PWC timer.
■ Timer Control Register (BTxTMCR Upper Byte)
Figure 23.8-34 Timer Control Register (BTxTMCR Upper Byte)
bit15
R/W
bit14
bit13
bit12
CKS2 CKS1 CKS0
R/W
R/W
R/W
bit11
R/W
bit10
bit9
bit8
EGS2 EGS1 EGS0
R/W
R/W
R/W
EGS2 EGS1 EGS0
0
0
Initial value:
00000000B (At reset)
Measurement edge select bits
0
Measure "H" pulse width (↑ to ↓)
0
0
1
Measure period between rising edges
(↑ to ↑ )
0
1
0
Measure period between falling edges
(↓ to ↓)
0
1
1
Measure pulse widths between all edges
(↑ or ↓ to ↓ or ↑ )
1
0
0
Measure "L" pulse width (↓ to ↑ )
1
0
1
1
1
0
1
1
1
CKS2 CKS1 CKS0
R/W
-
: Readable/writable
: Undefined bit
: Initial value
638
Setting not allowed
Count clock select bits
0
0
0
φ
0
0
1
φ/4
0
1
0
φ/16
0
1
1
φ/128
1
0
0
φ/256
1
0
1
Setting not allowed
1
1
0
1
1
1
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Table 23.8-10 Timer Control Register (BTxTMCR Upper Byte)
Bit name
CM71-10158-1E
Function
bit15
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit14
to
bit12
CKS2, CKS1,
CKS0:
Count clock select
bits
•
•
Select the count clock for the 16-bit up counter.
The count clock promptly reflects any changes made to its setting.
CKS2 to CKS0 must therefore be updated while counting is
stopped (CTEN = 0). Note, however, that you can change their
setting at the same time as writing "1" to the CTEN bit.
bit11
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit10
to
bit8
EGS2, EGS1, EGS0:
Measurement edge
select bits
•
•
Set the measurement edge condition.
EGS2, EGS1, and EGS0 must be updated while counting is
stopped (CTEN = 0). Note, however, that you can change their
setting at the same time as writing "1" to the CTEN bit.
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■ Timer Control Register (BTxTMCR Lower Byte)
Figure 23.8-35 Timer Control Register (BTxTMCR Lower Byte)
bit7
T32
R/W
bit6
bit5
bit4
FMD2 FMD1 FMD0
R/W
R/W
R/W
bit3
R/W
bit2
bit1
MDSE CTEN
R/W
R/W
bit0
Initial value:
00000000B (At reset)
R/W
CTEN
Counting enable bit
0
Halt
1
Enables operation
MDSE
Mode select bit
0
Continuous measurement mode
1
One-shot measurement mode
FMD2 FMD1 FMD0 Timer function mode select bits
0
R/W
-
: Readable/writable
: Undefined bit
0
0
Reset mode
0
0
1
PWM function mode
0
1
0
PPG function mode
0
1
1
Reload timer function mode
1
0
0
PWC function mode
1
0
1
1
1
0
1
1
1
Setting not allowed
T32
32-bit timer select bit
0
16-bit timer mode
1
32-bit timer mode
: Initial value
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Table 23.8-11 Timer Control Register (BTxTMCR Lower Byte)
Bit name
bit7
Function
T32:
32-bit timer select bit
•
•
•
bit6
to
bit4
FMD2, FMD1,
FMD0:
Timer function mode
select bits
•
•
•
These bits select the timer function mode.
Setting the FMD2, FMD1, and FMD0 bits to "100B" selects the
PWC timer function mode.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
bit3
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit2
MDSE:
Mode select bit
•
Selects measurement mode as follows.
bit1
CTEN:
Counting enable bit
bit0
Undefined bit
MDSE
Mode
Operation
0
Continuous measurement
Continuous measurement:
buffer register enabled
1
One-shot measurement
Halts after each
measurement
•
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
•
•
This bit enables the starting or restarting of the up counter.
Writing "1" to this bit with the counter enabled for operation
(CTEN bit = 1) causes a restart, resulting in the counter cleared
and waiting for the measurement start edge.
Writing "0" to the bit with the counter enabled for operation
(CTEN bit = 1 stops the counter.
•
CM71-10158-1E
This bit selects the 32-bit timer mode.
When the FMD2, FMD1, and FMD0 bits contain "100B" to select
the PWC timer, setting the T32 bit to "1" places the timer in 32-bit
PWC mode.
The setting must be changed with the timer stopped (CTEN = 0).
Note, however, that you can change the setting at the same time as
writing "1" to the CTEN bit.
→See Section "23.5 32-bit Mode Operations".
•
•
The value read is "0"
When writing to this bit, write "0".
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■ Status Control Register (BTxSTC)
Figure 23.8-36 Status Control Register (BTxSTC)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ERR
EDIE
-
OVIE
-
EDIR
-
OVIR
R
R/W
R/W
R/W
R/W
R
R/W
R/W
OVIR
Initial value:
00000000B (At reset)
Overflow interrupt request bit
0
Clears interrupt request
1
Indicates that interrupt factor has been detected
EDIR
Measurement end interrupt request bit
0
Reads measurement result (BTxDTBF)
1
Indicates that interrupt factor has been detected
OVIE
Overflow interrupt request enable bit
0
Disables interrupt requests
1
Enables interrupt requests
EDIE Measurement end interrupt request enable bit
R/W
R
-
: Readable/writable
: Read only
: Undefined bit
0
Disables interrupt requests
1
Enables interrupt requests
ERR
Error flag bit
0
Normal state
1
Unread measurement result has been overwritten with
next measurement result
: Initial value
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Table 23.8-12 Status Control Register (BTxSTC)
Bit name
bit7
Function
ERR:
Error flag bit
•
•
•
•
bit6
EDIE:
Measurement end
interrupt request
enable bit
•
•
Controls bit2: EDIR interrupt requests.
Setting the EDIR bit (bit2) with the EDIE bit enabling measurement
end interrupt requests generates an interrupt request to the CPU.
bit5
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit4
OVIE:
Overflow interrupt
request enable bit
•
•
Controls bit0: OVIR interrupt requests.
Setting the OVIR bit (bit0) with the OVIE bit enabling overflow
interrupt requests generates an interrupt request to the CPU.
bit3
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit2
EDIR:
Measurement end
interrupt request bit
•
Indicates that measurement has been completed. The flag is set to
"1" upon completion.
The EDIR bit is cleared by reading the measurement result
(BTxDTBF).
The EDIR bit can only be read; an attempt to write to it has no effect
on the bit value.
•
•
CM71-10158-1E
This flag indicates that the next measurement has been completed
before reading the current measurement result from the BTxDTBF
register in continuous measurement mode. In this case, the
BTxDTBF register is updated with the new measurement result,
discarding the preceding measurement result.
Measurement continues irrespective of the ERR bit value.
The ERR bit can only be read; an attempt to write to it has no effect
on the bit value.
The ERR bit is cleared by reading the measurement result
(BTxDTBF).
bit1
Undefined bit
•
•
The value read is "0"
When writing to this bit, write "0".
bit0
OVIR:
Overflow interrupt
request bit
•
The flag is set to "1" when a count value overflow occurs from
FFFFH to 0000H.
Writing "0" to the OVIR bit clears it.
Writing "1" to the OVIR bit has no effect on the bit value.
When read by a read modify write (RMW) instruction, the bit always
returns "1" irrespective of the current bit value.
•
•
•
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23.8.4.2
MB91665 Series
Data Buffer Register (BTxDTBF)
The data buffer register (BTxDTBF) allows the measured value or count value of the PWC timer to be
read from. In 32-bit mode, the register holds the value of the lower 16 bits for the even-numbered
channel or the value of the upper 16 bits for the odd-numbered channel.
To read this register, be sure to use a 16-bit data transfer instruction.
■ Bit Configuration of the Data Buffer Register (BTxDTBF)
Figure 23.8-37 shows the bit configuration of the data buffer register (BTxDTBF).
Figure 23.8-37 Bit Configuration of the Data Buffer Register (BTxDTBF)
bit15
644
bit13
bit12
bit11
bit10
bit9
bit8
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R
R
bit14
R
R
R
R
R
R
R
Initial value:
XXXXXXXXB (At reset)
Initial value:
XXXXXXXXB (At reset)
: Read only
•
The BTxDTBF register can only be read in both of the continuous and one-shot measurement modes.
An attempt to write to the register makes no change to the register value.
•
In continuous measurement mode (BTxTMCR: bit3 MDSE = 1), the BTxDTBF register serves as a
buffer register holding the preceding measurement result.
•
In one-shot measurement mode (BTxTMCR: bit3 MDSE = 0), the BTxDTBF register directly accesses
the up counter. Even during counting, the count value can be read from this register. When the
measurement is completed, the register preserved the measurement result as it is.
•
Access the BTxDTBF register using 16-bit data.
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CHAPTER 23 Base Timer
23.8
MB91665 Series
23.8.4.3
PWC Operation
The PWC timer has a pulse width measurement feature, capable of selecting the count clock from
among five types and measuring the time between arbitrary events of the input pulse and their cycle.
The following outlines the basic functions and operations of the pulse width measurement feature.
■ Pulse Width Measurement Feature
When started, the timer clears the counter to "0000H" but does not perform counting until the pre-set
measurement start edge is input. Upon detection of the measurement start edge, the timer increments the
counter from "0001H". Upon detection of the measurement end edge, the timer stops the counter. The
timer saves the count value between the two events as the pulse width to the register.
An interrupt request can be generated upon completion of measurement or when an overflow occurs.
After measurement, the timer acts as follows depending on the measurement mode:
•
In one-shot measurement mode:The timer stops operation.
•
In continuous measurement mode:The timer transfers the counter value to the buffer register and stops
counting until the measurement start edge is input again.
Figure 23.8-38 Pulse Width Measurement Operation
(One-shot Measurement Mode/"H" Width Measurement)
PWC input measured pulse
CTEN
Count value
FFFFH
Count
cleared
0000H
Start
triggered
Counting
stopped
(Solid line indicates count values.)
Counting 0001H
started
Time
EDIR flag set (Measurement completed)
Figure 23.8-39 Pulse Width Measurement Operation
(Continuous Measurement Mode/"H" Width Measurement)
PWC input measured pulse
CTEN
(Solid line indicates
count values.)
Count value
FFFFH
Overflow
Data transfer to BTxDTBF
Data transfer to BTxDTBF
Count
cleared
0000H
Start
triggered
Counting
stopped
Counting
stopped
Counting 0001H
started
Counting 0001H
restarted
Counting
continued
Time
EDIR flag set (Measurement completed)
CM71-10158-1E
OVIR flag set
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EDIR flag set
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■ Selecting the Count Clock
The count clock for the counter can be selected from among five types, depending on the settings of the
CKS2 (bit6), CKS1 (bit5), and CKS0 (bit4) in the BTxTMCR registers.
The following count clocks can be selected:
BTxTMCR Register
Internal count clock selected
CKS2, CKS1, CKS0 bits
000B
Peripheral clock (PCLK) [Initial value]
001B
Peripheral clock (PCLK) divided by 4
010B
Peripheral clock (PCLK) divided by 16
011B
Peripheral clock (PCLK) divided by 128
100B
Peripheral clock (PCLK) divided by 256
101B
Setting not allowed
110B
111B
The initial value immediately after a reset selects the peripheral clock (PCLK).
Note: Be sure to select the count clock before starting the counter.
■ Selecting the Operation Mode
Operation and measurement modes are selected depending on their settings in the BTxTMCR register.
Operation mode setting . . . . . . BTxTMCR bit10 to bit8: EGS2, EGS1. EGS0
(Selecting the measurement edge)
Measurement mode setting. . . . BTxTMCR bit2: MDSE
(Selecting one-shot/continuous measurement)
Listed below are the selectable operation modes and their respective bit settings.
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.
Operation mode
↑ to ↓ "H" pulse width measurement
↑ to ↑ measurement of period
between rising edges
↓ to ↓ measurement of period
between falling edges
↑ or ↓ to ↓ or ↑ measurement
between all edges
↓ to ↑ "L" pulse width measurement
MDSE
EGS2
EGS1
EGS0
Continuous measurement:
Buffer enabled
0
0
0
0
One-shot measurement:
Buffer disabled
1
0
0
0
Continuous measurement:
Buffer enabled
0
0
0
1
One-shot measurement:
Buffer disabled
1
0
0
1
Continuous measurement:
Buffer enabled
0
0
1
0
One-shot measurement:
Buffer disabled
1
0
1
0
Continuous measurement:
Buffer enabled
0
0
1
1
One-shot measurement:
Buffer disabled
1
0
1
1
Continuous measurement:
Buffer enabled
0
1
0
0
One-shot measurement:
Buffer disabled
1
1
0
0
0
1
0
1
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
Setting not allowed
The initial value immediately after a reset selects "H" pulse width/one-shot measurement mode.
Be sure to select the operation mode before starting the counter.
■ Starting and Stopping Pulse Width Measurement
Each type of measurement can be started, restarted, and aborted by the CTEN bit (bit1) in the BTxTMCR
register.
You can start/restart pulse width measurement by writing "1" to the CTEN bit. You can abort it by
writing "0" to the CTEN bit.
CTEN
Function
1
Starts/restarts pulse width measurement
0
Aborts pulse width measurement
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■ Operation after being Started
The timer operation after the pulse width measurement mode has been started does not start counting until
the measurement start edge is input. Upon detection of the measurement start edge, the 16-bit up counter
starts counting from "0001H".
■ Restarting
Restarting the timer means starting the timer during operation again while it has already been started (by
writing "1" again to the CTEN bit already containing "1"). When restarted, the timer behaves as follows:
•
If restarted the timer waiting for the measurement start edge: No effect on its operation.
•
If restarted during measurement:The timer clears the counter to "0000H" and waits for the
measurement start edge again. If the restart and measurement end edge detection occur at the same
time, the measurement end flag (EDIR) is set. In continuous measurement mode, the measurement
result is transferred to the BTxDTBF register.
■ Stopping
In one-shot measurement mode, the timer stops counting automatically when the counter causes an
overflow or when measurement is completed, requiring no special attention. To stop the timer either in
continuous measurement mode or before it stops automatically, you have to abort it.
■ Clearing the Counters and Their Initial Values
The 16-bit up counter is cleared to "0000H" when:
•
a reset occurs
•
"1" is written to the CTEN bit (bit1) in the BTxTMCR register (including the case of restarting).
The 16-bit up counter is initialized to "0001H" when measurement start edge is detected.
■ Details of Pulse Width Measurement Operation
● One-shot measurement and continuous measurement
There are two modes of pulse width measurement: one is to perform measurement only once and the
other is to perform measurement continuously. Each mode is selected by using the MDSE bit in the
BTxTMCR register (see "■ Selecting the Operation Mode" in "23.8.4.3 PWC Operation"). The two
modes have the following differences:
One-shot measurement mode:
When the measurement end edge is input once, the counter stops counting and the measurement end
flag (EDIR) in the BTxSTC register is set, finishing the current measurement session. If the counter is
restarted at the same time, however, it waits for the measurement start edge.
Continuous measurement mode:
When the measurement end edge is input, the counter stops counting, the measurement end flag
(EDIR) in the BTxSTC register is set, and the counter remains idle until the measurement start edge is
input again. Next time the measurement start edge is input, the counter is initialized to "0001H" to
start measurement. Upon completion of measurement, the measurement result in the counter is
transferred to the BTxDTBF register.
Be sure to select or change the measurement mode with the counter stopped.
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● Measurement result data
The one-shot measurement and continuous measurement modes are different in the handling of
measurement results and counter values and the BTxDTBF function. The differences in measurement
results between the two modes are as follows:
One-shot measurement mode:
When the BTxDTBF register is read during operation, the count value being measured can be
obtained.
When the BTxDTBF register is read after measurement is completed, measurement result data is
obtained.
Continuous measurement mode:
When measurement is completed, the measurement result in the counter is transferred to the
BTxDTBF register.
When the BTxDTBF register is read, the last measurement result is obtained. During measurement
operation, the BTxDTBF register holds the result of preceding measurement. The count value being
measured cannot be read.
If the current measurement is completed before the preceding measurement result is read in
continuous measurement mode, the preceding measurement result is overwritten by the new
measurement result. In this case, the error flag (ERR) in the BTxSTC register is set. The error flag
(ERR) is cleared automatically when the BTxDTBF register is read.
■ Measurement Mode and Counting
Measurement mode can be selected from among five types, depending on what part of the input pulse is
measured. The following table summarizes each measurement mode and its target.
Measurement mode
EGS2, EGS1, EGS0
"H" pulse width measurement
000B
Measurement target (W: Pulse width to be measured)
W
↑ Start
counting
W
↓ Stop
counting
↓
Stop
↑
Start
Measure the width of "H" period.
Start counting (measurement) : upon detection of rising edge
Stop counting (measurement) : upon detection of falling edge
Measurement of period
between rising edges
001B
W
↑ Start
counting
W
W
↑ Stop counting
↑ Start
Measure the period between rising edges.
Start counting (measurement) : upon detection of rising edge
Stop counting (measurement) : upon detection of rising edge
Measurement of period
between falling edges
010B
W
↓ Start
counting
W
W
↓ Stop counting
↓ Start
↓ Stop
↓ Start
Measure the period between falling edges.
Start counting (measurement) : upon detection of falling edge
Stop counting (measurement) : upon detection of falling edge
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Measurement mode
EGS2, EGS1, EGS0
Measurement of pulse
widths between all
edges
011B
Measurement target (W: Pulse width to be measured)
W
↑ Start
counting
W
W
↓ Stop counting
↓ Start
↑ Stop
↑ Start
Measure the width between continuously input edges.
Start counting (measurement) : upon detection of edge
Stop counting (measurement) : upon detection of edge
Measurement of "L"
pulse width
100B
W
W
↓ Start
counting
↑ Stop
counting
↓
Start
↑
Stop
Measure the width of the "L" period.
Start counting (measurement) : upon detection of falling edge
Stop counting (measurement) : upon detection of rising edge
In any measurement mode, the counter started for measurement is cleared to "0000H" and remains idle
without counting until the measurement start edge is input. When the measurement start edge is input, the
counter is incremented every count clock until the measurement end edge is input.
When measurement of pulse widths between all edges or period measurement is performed in continuous
measurement mode, the end edge becomes the next measurement start edge.
● Pulse width/period calculation method
The following equation can be used to calculate the measured pulse width/period from measurement
result data obtained from the BTxDTBF register after measurement is completed:
TW = n × t [ms]
TW : Measured pulse width/period [ms]
n
: Measurement result data in BTxDTBF
t
: Count clock cycle [ms]
● Generating interrupt requests
Interrupt requests can be generated in two ways.
•
Interrupt request in response to counter overflow
When the counter is incremented to cause an overflow during measurement, the overflow flag (OVIR)
is set and generates an interrupt request if overflow interrupt requests have been enabled.
•
Interrupt request upon completion of measurement
When the measurement end edge is detected, the measurement end flag (EDIR) in the BTxSTC
register is set and generates an interrupt request if measurement end interrupt requests have been
enabled.
The measurement end flag (EDIR) is cleared automatically when the measurement result is read from
the BTxDTBF register.
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23.8
MB91665 Series
■ Pulse Width Measurement Operation Flow
Various settings
Figure 23.8-40 Pulse Width Measurement Operation Flow
Select PWC mode
Select count clock
Select operation/
measurement modes
Clear interrupt flag
Enable interrupts
Start with CTEN bit
Restart
Clear counter
Continuous measurement
mode
One-shot measurement
mode
Measurement start edge
detected
Measurement start edge
detected
Start counting
Start counting
Increment
Increment
Overflow caused
→ Set OVIR flag
Measurement end edge
detected
→ Set EDIR flag
CM71-10158-1E
Overflow caused
→ Set OVIR flag
Measurement end edge
detected
→ Set EDIR flag
Stop counting
Stop counting
Transfer count value to
BTxDTBF
Stop operation
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CHAPTER 24 Up/Down Counter
This chapter explains the functions and operations of the
up/down counter.
24.1 Overview
24.2 Configuration
24.3 Pins
24.4 Registers
24.5 Interrupt
24.6 An Explanation of Operations and Setting Procedure
Examples
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CHAPTER 24 Up/Down Counter
24.1
MB91665 Series
24.1 Overview
The up/down counter counts upward or downward depending on the setting.
By using only the lower byte of the 16-bit up/down counter, you can use it as an 8-bit up/down counter.
The counter can perform a count in a range of "00H" to "FFH" when used as an 8-bit up/down counter,
and "0000H" to "FFFFH" when used as a 16-bit up/down counter.
This series microcontroller has 4 built-in channels for the 16-bit up/down counter. However, because
only the lower byte can be used as an 8-bit up/down counter, you can use a total of 4 channels for
both cases of using it as an 8-bit and a 16-bit counter.
■ Overview
•
Counter mode: You can select the use of the counter either as an 8-bit up/down counter (8-bit mode),
or as a 16-bit up/down counter (16-bit mode).
•
Operation mode: One of the following three modes (4 types) can be selected.
-
Timer mode
The counter counts downward by synchronizing with the count clock.
The internal clock (peripheral clock) which is generated by dividing the peripheral clock (PCLK)
by 2 or 8 by the prescaler is used as a count clock.
-
Up/Down count mode
The counter counts upward/counts downward signals that are input from the 2 external signal input
pins. You can select which edge to count from among the rising edge, falling edge, or both edges.
-
Phase difference count mode
The counter counts upward/counts downward the phase difference of the signals that are input
from the 2 external signal input pins.
Phase difference count mode is appropriate for counting for the encoder of the motor and the like.
Rotation angle and rotation number can be easily counted with high accuracy by inputting Aphase, B-phase, and Z-phase outputs respectively from the encoder.
There are two phase difference count modes: one multiplied by 2-mode and one multiplied by 4mode. The counting method for each of these modes differs from the other.
Table 24.1-1 outlines the operation mode of the up/down counter.
Table 24.1-1 Operation mode of the up/down counter
Operation Mode
654
Count Timing
Count Direction
Timer mode
Internal clock
(peripheral clock)
Count downward
Up/Down count mode
External clock
Count upward/Count downward
Phase difference count mode
(Multiplied by 2/Multiplied by
4)
Phases of the input signals from
the external signal input pins
Count upward/Count downward
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CHAPTER 24 Up/Down Counter
24.1
MB91665 Series
•
Reload/compare clear function: One of the following three types can be selected.
-
Compare clear function
Clears the counter at the next up count timing when the specified value matches the counter value.
-
Reload function
If an underflow occurs, the reload value is loaded to continue counting.
-
Reload compare clear function
Compare clear function and reload function can be combined for use.
•
Count direction: The last count direction (count upward/count downward) can be verified.
•
Interrupt request: Can be generated in the following cases:
CM71-10158-1E
-
The count direction is inverted
-
The value of the counter matches the previously set value.
-
An overflow occurs
-
An underflow (reload) occurs
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CHAPTER 24 Up/Down Counter
24.2
MB91665 Series
24.2 Configuration
This section shows the configuration of the up/down counter.
■ Block diagram of the up/down counter
Figure 24.2-1 is a block diagram of the up/down counter, taking ch.0 as an example.
Figure 24.2-1 Block diagram of the up/down counter
Peripheral bus
8 bits
CGE1
ZIN1 pin
CGE0
To upper byte
CGSC
M16E
RCRL
CTUT
Reload
UCRE
RLDE
Carry
Edge/Level detection
UDCC
Counter
clearing
8 bits
CES1
CES0
CMS1
CMS0
UDCRL
CMPF
UDFF
AIN1 pin
BIN1 pin
OVFF
Count clock
Count clock
selection
CSTR
UDF1
UDIE
UDF0
CDCF
Prescaler
CITE
CLKS
UFIE
Interrupt output
RCRL : Reload compare register lower (RCRL1)
UDCRL : Up-down count register lower (UDCRL1)
•
Reload compare register (RCR1)
This register sets the reload value and the compare value of the up/down counter.
It is divided into the upper 8 bits and lower 8 bits as follows:
The lower bits are used when the counter is used in 8-bit mode.
656
-
Reload compare register upper (RCRH1)
-
Reload compare register lower (RCRL1)
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CHAPTER 24 Up/Down Counter
24.2
MB91665 Series
•
Up-down count register (UDCR1)
This register operates as a counter of the up/down counter.
It is divided into the upper 8 bits and lower 8 bits as follows:
The lower bits are used when the counter is used in 8-bit mode.
-
Up-down count register upper(UDCRH1)
-
Up-down count register lower (UDCRL1)
•
Counter control register (CCR1)
•
Counter status register (CSR1)
This register controls the up/down counter.
This register verifies the state of the up/down counter and controls interrupt requests.
•
Count clock selection circuit
This circuit is used to select the count clock for the up/down counter.
•
Prescaler
This is used to select the division rate of the peripheral clock (PCLK) when the up/down counter is
used in timer mode.
■ Clock
Table 24.2-1 shows the clock used by the up/down counter.
Table 24.2-1 Clock used by the up/down counter
Clock Name
CM71-10158-1E
Description
Remarks
Operation clock
Peripheral clock (PCLK)
-
Count clock
Internal clock (peripheral clock)
Generated through division of the
peripheral clock (PCLK).
Counts inputs from the external pins
Inputs from AIN1 pin and BIN1 pin
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CHAPTER 24 Up/Down Counter
24.3
MB91665 Series
24.3 Pins
This section explains the pins of the up/down counter.
■ Overview
The up/down counter has the following three types of pins.
•
AIN1 pin
These are the external signal input pins of the up/down counter In up/down count mode, signals are
counted upward if an effective edge is detected in these pins. In phase difference count mode
(multiplied by 2/multiplied by 4), the phase difference between these pins and BIN1 pin is counted.
These pins are multiplexed pins. To use them as AIN1 pin of the up/down counter, see "2.4 Setting
Method for Pins".
•
BIN1 pin
These are the external signal input pins of the up/down counter In up/down count mode, signals are
counted downward if an effective edge is detected in these pins. In phase difference count mode
(multiplied by 2/multiplied by 4), the phase difference between these pins and AIN1 pin is counted.
These pins are multiplexed pins. To use them as BIN1 pin of the up/down counter, see "2.4 Setting
Method for Pins".
•
ZIN1 pin
These are the external signal input pins of the up/down counter They are used to clear the counter or
for gate input.
These pins are multiplexed pins. To use them as ZIN1 pin of the up/down counter, see "2.4 Setting
Method for Pins".
■ Relationship between pins and channels
Table 24.3-1 outlines the relationship between channels and pins.
Table 24.3-1 Relationship between Channels and Pins
Channel
1
658
External Signal Input Pin
AIN1
BIN1
ZIN1
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
24.4 Registers
This section explains the configuration and functions of registers used by the up/down counter.
■ List of registers for the up/down counter
Table 24.4-1 lists the registers used by the up/down counter.
Table 24.4-1 Registers for the up/down counter
Channel
1
CM71-10158-1E
Abbreviated
Register Name
Register Name
Reference
RCRL1
Reload compare register lower 1
24.4.1
RCRH1
Reload compare register upper 1
24.4.1
UDCRL1
Up-down count register lower 1
24.4.2
UDCRH1
Up-down count register upper 1
24.4.2
CCR1
Counter control register 1
24.4.3
CSR1
Counter status register 1
24.4.4
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CHAPTER 24 Up/Down Counter
24.4
24.4.1
MB91665 Series
Reload Compare Register (RCR1)
This register sets the reload value and the compare value of the up/down counter.
The reload value is a starting value to count downward with, and the compare value is a value to be
compared with the counted value when counting upward (i.e., counting up is performed until the
counted value reaches the compare value). The reload value and the compare value are the same.
This register is divided into upper byte and lower byte as follows:
•
Reload compare register upper (RCRH1)
•
Reload compare register lower (RCRL1)
In 16-bit mode, both the upper and lower byte values are used, while in 8-bit mode, the lower byte value
is used.
By transferring the value that is written in this register to the up-down count register (UDCR1), the up/
down counter performs the count in a range from "0000H" (for 8-bit mode, "00H") to the value that has
been set for this register.
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
Figure 24.4-1 shows the bit configuration of the reload compare register (RCR1).
Figure 24.4-1 Bit configuration of the reload compare register (RCR1)
Reload compare register upper (RCRH1)
bit
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
Attribute
W
W
W
W
W
W
W
W
Initial value
0
0
0
0
0
0
0
0
Reload compare register lower (RCRL1)
bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Attribute
W
W
W
W
W
W
W
W
Initial value
0
0
0
0
0
0
0
0
W: Write only
<Notes>
•
By writing "1" to the CTUT bit of the counter control register (CCR1), the value that has been set
for this register can be transferred to the up-down count register (UDCR1). However, note that
the CTUT bit of the counter control register (CCR1) should be written while the up-down counter
is stopped.
•
If 16-bit mode is set in M16E bit (M16E = 1) of the counter control register (CCR1), this register
must be written in half word.
•
If 8-bit mode is set in M16E bit (M16E = 0) of the counter control register (CCR1), the reload
compare register lower (RCRL1) must be written in byte notation.
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CHAPTER 24 Up/Down Counter
24.4
24.4.2
MB91665 Series
Up-Down Count Register (UDCR1)
This register operates as a counter of the up/down counter. Also, the register can be read to verify the
counter value.
This register is divided into upper byte and lower byte as follows:
•
Up-down count register upper (UDCRH1)
•
Up-down count register lower (UDCRL1)
In 8-bit mode, the upper byte value is invalid. Read the value of the up-down count register lower
(UDCRL1).
Figure 24.4-2 shows the bit configuration of the up-down count register (UDCR1).
Figure 24.4-2 Bit configuration of the up-down count register (UDCR1)
Up-down count register upper (UDCRH1)
bit
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Up-down count register lower (UDCRL1)
bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Attribute
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
R: Read only
<Notes>
•
This register is read-only. To set a value to this register, transfer the value of the reload
compare register (RCR1) to this register by using the following procedure.
1. Write a value in the reload compare register (RCR1).
2. Write "0" to the CSTR bit of the counter status register (CSR1).
3. Write "1" to the CTUT bit of the counter control register (CCR1).
662
•
If 16-bit mode is set in M16E bit (M16E = 1) of the counter control register (CCR1), this register
must be read in half word.
•
If 8-bit mode is set in the M16E bit (M16E = 0) of the counter control register (CCR1), the value
of the up-down count register lower (UDCRL1) must be read.
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
24.4.3
Counter Control Register (CCR1)
This register controls operation of the up/down counter.
Figure 24.4-3 shows the bit configuration of the counter control register (CCR1).
Figure 24.4-3 Bit configuration of the counter control register (CCR1)
bit
15
14
13
12
11
10
9
8
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Reserved
CTUT
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
0
0
0
1
0
0
0
Attribute
Initial value
bit
Attribute
Initial value
R/W: Read/Write
R: Read only
[bit15]: M16E (16-bit mode selection bit)
This bit selects whether to use the up/down counter in 8-bit or 16-bit mode.
Written Value
CM71-10158-1E
Explanation
0
Uses the up/down counter in 8-bit mode (1 channel).
1
Uses the up/down counter in 16-bit mode (1 channel).
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
[bit14]: CDCF (Count direction change flag bit)
This bit indicates that the count direction is inverted from counting downward to counting upward or
from counting upward to downward one or more times.
If the CFIE bit is set to "1" when this bit is "1", a count direction change interrupt request is generated.
CDCF
In Case of Reading
In Case of Writing
0
The count direction has not been inverted.
This bit is cleared to "0".
1
The count direction has been inverted one
or more times.
Ignored
<Notes>
•
If the counter reset occurs, the count direction is set to counting downward. Therefore, if
counting upward is performed immediately after the reset, this bit changes to "1".
•
If the count direction consecutively changes in a short period of time, the count direction may
return to the original one with UDF1 and UDF0 bits of the counter status register (CSR1)
unchanged.
[bit13]: CFIE (Count direction change interrupt enable bit)
This bit sets whether to generate the count direction change interrupt request if the count direction is
inverted (CDCF = 1).
Written Value
Explanation
0
Disables generation of count direction change interrupt requests.
1
Enables generation of count direction change interrupt requests.
[bit12]: CLKS (Internal clock division selection bit)
This bit sets the division rate of the peripheral clock (PCLK) that is used as a count clock when timer
mode is selected.
Written Value
Explanation
0
Peripheral clock (PCLK) divided by 2
1
Peripheral clock (PCLK) divided by 8
<Note>
This bit is enabled only when timer mode is set for the operation mode by setting the CMS1 and
CMS0 bits (CMS1, CMS0 = 00). The setting of this bit is ignored if other operation modes are
selected.
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24.4
MB91665 Series
[bit11, bit10]: CMS1, CMS0 (Operation mode selection bit)
These bits select the operation mode of the up/down counter from among the following options.
•
Timer mode
•
Up/Down count mode
The counter counts downward by synchronizing with the count clock.
The counter counts upward/counts downward signals that are input from the 2 external signal input
pins.
•
Phase difference count mode
The counter counts upward/counts downward the phase difference between the 2 external signal input
pins. There are two phase difference count modes: one multiplied by 2-mode and one multiplied by 4mode. The counting method for each of these modes differs from the other.
CMS1
CMS0
Operation Mode
0
0
Timer mode
0
1
Up/Down count mode
1
0
Phase difference count mode (multiplied by 2)
1
1
Phase difference count mode (multiplied by 4)
[bit9, bit8]: CES1, CES0 (Count clock edge selection bit)
These bits select the detection edge for the AIN1 pin and BIN1 pin.
When up/down count mode is selected, the count operation is performed every time if the edge that has
been selected for this bit is detected.
CES1
CES0
Detection Edge
0
0
Edge detection disabled
0
1
Falling edge
1
0
Rising edge
1
1
Both edges
<Note>
This bit is enabled only when up/down count mode is set for the operation mode by setting the
CMS1 and CMS0 bits (CMS1, CMS0 = 01). The setting of this bit is ignored if other operation
modes are selected.
[bit7]: Reserved bit
CM71-10158-1E
In Case of Writing
Always write "0" to this (these) bit (bits).
In Case of Reading
"0" is read.
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
[bit6]: CTUT (Counter write bit)
Transfers the values that have been set in the reload compare register (RCR1) to the up-down count
register (UDCR1).
CTUT
In Case of Writing
0
Ignored
1
Transfers the value.
In Case of Reading
"0" is read.
<Note>
The value of the reload compare register (RCR1) is transferred at the time when "1" is written to
this bit. Therefore do not change this bit to "1" while the CSTR bit of the counter status register
(CSR1) is "1" (the counter is active).
[bit5]: UCRE (Counter clear enable bit)
This bit controls the clear operation of the counter by compare function.
If this bit is enabled, it clears the counter at the next up count timing when the counter value matches the
value specified to the reload compare register (RCR1).
Written Value
Explanation
0
Disables compare clear function.
1
Enables compare clear function.
<Note>
This bit can control only the compare clear function. It does not affect comparison result match
interrupt.
The following clear operations cannot be controlled by this bit.
•
Clear operation by resetting this device
•
Clear operation by effective edge inputs from the ZIN1 pin (when CGSC bit = 0)
•
Clear operation by writing "0" to the UDCC bit (clear by software)
[bit4]: RLDE (Reload enable bit)
This bit enables/disables use of the reload function.
The reload function reloads to the counter the value that has been set in the reload compare register
(RCR1) when the counter underflows during count downward, and continues counting.
Written Value
666
Explanation
0
Disables use of the reload function.
1
Enables use of the reload function.
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
[bit3]: UDCC (Counter clear bit)
This bit clears the counter value to "0000H".
UDCC
In Case of Writing
0
Clears the counter value.
1
Ignored
In Case of Reading
"1" is read.
[bit2]: CGSC (Counter clear/Gate selection bit)
This bit selects the function for ZIN1 pin from among the following options.
•
Counter clear function
The counter value is cleared to "0000H" if the effective edge is input from the ZIN1 pin.
•
Gate function
The counter operates only while the effective level is input from ZIN1 pin.
Written Value
Explanation
0
Counter clear function
1
Gate function
<Note>
The ZIN1 pin operate by combining settings of this bit and CGE1 and CGE0 bits. Be sure to also
set CGE1 and CGE0 bits.
[bit1, bit0]: CGE1, CGE0 (Edge/Level selection bit)
These bits select the effective edge/effective level for the ZIN1 pin. The meaning and function of these
bits vary depending on the CGSC bit setting.
•
When the counter clear function is selected in the CGSC bit (CGSC = 0)
Selects the effective edge.
The counter value is cleared to "0000H" if the edge selected in this bit is detected in the ZIN1 pin.
•
When the gate function is selected in the CGSC bit (CGSC = 1)
Selects the effective level.
The counter operates only while the level selected in this bit is input from the ZIN1 pin.
CGE1
CM71-10158-1E
CGE0
When the Counter Clear
Function Is Selected
(CGSC = 0)
When the Gate Function Is
Selected
(CGSC = 1)
0
0
Edge detection disabled
Level detection disabled (count
disabled)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting prohibited
Setting prohibited
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CHAPTER 24 Up/Down Counter
24.4
24.4.4
MB91665 Series
Counter Status Register (CSR1)
This register verifies the state of the up/down counter and controls interrupt requests.
Figure 24.4-4 shows the bit configuration of the counter status register (CSR1).
Figure 24.4-4 Bit configuration of the counter status register (CSR1)
bit
7
6
5
4
3
2
1
0
CSTR
CITE
UDIE
CMPF
OVFF
UDFF
UDF1
UDF0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
R: Read only
[bit7]: CSTR (Count activation bit)
This bit activates/stops the up/down counter.
Written Value
Explanation
0
Stops count operation.
1
Activates the up/down counter.
[bit6]: CITE (Compare result match interrupt enable bit)
This bit sets whether to generate the comparison result match interrupt request if the counter value
matches the value that has been set in the reload compare register (RCR1) (CMPF = 1).
Written Value
Explanation
0
Disables generation of comparison result match interrupt requests.
1
Enables generation of comparison result match interrupt requests.
[bit5]: UDIE (Overflow/Underflow interrupt enable bit)
This bit sets whether to generate the overflow/underflow interrupt request when the up/down counter
overflows/underflows (OVFF/UDFF = 1).
Written Value
668
Explanation
0
Disables generation of overflow/underflow interrupt requests.
1
Enables generation of overflow/underflow interrupt requests.
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
[bit4]: CMPF (Compare result match detection flag bit)
This bit indicates that the counter value matches the value that has been set in the reload compare register
(RCR1).
If the CITE bit is set to "1" when this bit is "1", the comparison result match interrupt request is
generated.
CMPF
In Case of Reading
In Case of Writing
0
Values are not matched.
This bit is cleared to "0".
1
Values are matched.
Ignored
<Note>
The bit is changed to "1" in any of the following cases:
•
The value matches during count upward.
•
The value of the reload compare register (RCR1) is reloaded to the counter.
•
Values are already matched when the up/down counter is activated.
[bit3]: OVFF (Overflow detection flag bit)
This bit indicates that the up/down counter overflows.
If the UDIE bit is set to "1" when this bit is "1", an overflow interrupt request is generated.
OVFF
In Case of Reading
In Case of Writing
0
No overflow occurred.
This bit is cleared to "0".
1
An overflow occurred.
Ignored
An overflow occurs when the counter value is "FFFFH" and the counter attempts to count upward.
[bit2]: UDFF (Underflow detection flag bit)
This bit indicates that the up/down counter underflows.
If the UDIE bit is set to "1" when this bit is "1", an underflow interrupt request is generated.
UDFF
In Case of Reading
In Case of Writing
0
No underflow occurred.
This bit is cleared to "0".
1
An underflow occurred.
Ignored
An underflow occurs when the counter value is "0000H" and the counter attempts to count downward.
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CHAPTER 24 Up/Down Counter
24.4
MB91665 Series
[bit1, bit0]: UDF1, UDF0 (Up-down flag bit)
This bit indicates the last count direction.
This bit is updated each time the up/down counter performs a count operation.
UDF1
670
UDF0
Explanation
0
0
No input
0
1
Count downward
1
0
Count upward
1
1
Count upward/count downward concurrently
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CHAPTER 24 Up/Down Counter
24.5
MB91665 Series
24.5 Interrupt
An interrupt request is generated in any of the following cases.
• The count direction is inverted (count direction change interrupt request)
• The counter value matches the value that has been set in the reload compare register (RCR1)
(comparison result match interrupt request)
• An overflow occurs (overflow interrupt request)
• An underflow occurs (underflow interrupt request)
The generated interrupt request varies depending on the operation mode of the up/down counter.
Table 24.5-1 outlines the relationship between the operation modes and interrupt requests.
Table 24.5-1 Relationship between the operation modes and interrupt requests
Interrupt Request
Timer Mode
Up/Down count
mode
Phase difference
count mode
(Multiplied by 2/
multiplied by 4)
Count direction change interrupt
request
x
O
O
Comparison result match
interrupt request
O
O
O
Overflow interrupt request
x
O
O
Underflow interrupt request
O
O
O
Table 24.5-2 outlines the interrupts that can be used with the up/down counter.
Table 24.5-2 Interrupts of the up/down counter
Interrupt Request
Interrupt Request
Flag
Interrupt Request
Enabled
Clearing an
Interrupt Request
Count direction change
interrupt request
CDCF = 1 for CCR
CFIE = 1 for CCR
Write "0" to the CDCF
bit in the CCR.
Comparison result match
interrupt request
CMPF = 1 for CSR
CITE = 1 for CSR
Write "0" to the CMPF
bit in the CSR.
Overflow interrupt
request
OVFF = 1 for CSR
UDIE = 1 for CSR
Write "0" to the OVFF
bit in the CSR.
Underflow interrupt
request
UDFF = 1 for CSR
UDIE = 1 for CSR
Write "0" to the UDFF
bit in the CSR.
CCR: Counter control register (CCR1)
CSR: Counter status register (CSR1)
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<Notes>
•
The CMPF bit of the counter control register (CCR1) changes to "1" not only if the counted up
value matches but also if the value has already been matched when the value of the reload
compare register (RCR1) is reloaded or when the up/down counter is activated.
•
For details of how to clear the counter and the reload timing, see "■ Clear event" and "■ Reload
event" in "24.6 An Explanation of Operations and Setting Procedure Examples".
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests.
- Clears interrupt requests before enabling the generation of interrupt requests.
- Clears interrupt requests simultaneously with interrupts enabled.
672
•
For details of the interrupt vector number of the respective interrupt request, see "APPENDIX C
Interrupt Vectors".
•
Use the interrupt control register (ICR00 to ICR47) to set the interrupt level corresponding to the
interrupt vector number. For interrupt level settings, see "CHAPTER 10 Interrupt Controller".
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MB91665 Series
24.6 An Explanation of Operations and Setting
Procedure Examples
This section explains the operation of the up/down counter. Also, examples of procedures for setting
the operating state are shown.
■ Overview
● Counter mode
The up/down counter can be used both as a 16-bit up/down counter and as an 8-bit up/down counter,
depending on the setting.
This can be set in the M16E bit in the counter control register (CCR1).
•
8-bit mode (M16E = 0)
Only the up-down count register lower (UDCRL1) is used. Write the reload value and compare value
only in the reload compare register lower (RCRL1) in byte notation.
•
16-bit mode (M16E = 1)
Both the upper and lower bytes of the up-down count register (UDCR1) are used. Write the reload
value and compare value in the reload compare register (RCR1) in half word.
● Operation mode
One of the following three modes (4 types) can be selected for the operation mode of the up/down counter
by using the CMS1 and CMS0 bit of the counter control register (CCR1).
•
Timer mode (CMS1, CMS0 = 00)
In this mode, counting downward is performed starting from the previously set value by
synchronizing with the count clock.
The count clock is generated by dividing the peripheral clock (PCLK) by 2 or 8 with the prescaler.
•
Up/Down count mode (CMS1, CMS0 = 01)
In this mode, signals that are input from the external signal input pins are counted upward or
downward.
•
Phase difference count mode (multiplied by 2) (CMS1, CMS0 = 10)/Phase difference count mode
(multiplied by 4) (CMS1, CMS0 = 11)
In this mode, phase difference between the signals that are input from the external signal input pins
are counted upward or downward. By inputting A-phase of the encoder from the AIN1 pin, B-phase
from the BIN1 pin, and Z-phase from the ZIN1 pin, rotation angle and rotation number can be counted
and rotation direction can be detected with high accuracy, making it appropriate for counting for the
encoder of motors and the like.
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■ Functions that can be used
● Reload/Compare clear function
8/16-bit up/down counter can enable and disable the reload function and compare clear function by using
the RLDE bit and UCRE bit in the counter control register (CCR1).
•
Reload function
This function reloads the value that has been set in the reload compare register (RCR1) if an
underflow occurs during count downward, and performs count downward again. For details of this
operation, see "■ Count operation" in "24.6.1 Operation in Timer Mode".
•
Compare clear function
In this function, if an attempt is made to further count upward while the value of the up/down counter
matches the value that has been set in the reload compare register (RCR1) (comparison result match),
the value of the up/down counter is cleared to "0000H" to start counting upward again. For details of
this operation, see "■ Count operation" in "24.6.2 Operations in Up/Down Count Mode".
This function cannot be used in timer mode.
•
Reload compare clear function
this is a function used by combining the reload function and compare clear function. In this function,
counting of any range is possible because counting upward/downward is performed between the
values of "0000 H" and the value set in the reload compare register (RCR1). See "■ Count operation"
in "24.6.2 Operations in Up/Down Count Mode".
This function cannot be used in timer mode.
Table 24.6-1shows how to set the reload function/compare clear function.
Table 24.6-1 Setting the reload/compare clear function
RLDE bit
UCRE bit
Explanation
0
0
Disable reload function/compare clear function
0
1
Disable reload function
Enable compare clear function
1
0
Enable reload function
Disable compare clear function
1
1
Enable reload function/compare clear function
● Function of the ZIN1 pin
One of the following functions can be selected for the ZIN1 pin using the CGSC bit of the counter control
register (CCR1).
•
Count clear function (CGSC = 0)
The counter value is cleared to "0000H" if an effective edge is input from the ZIN1 pin during count
operation.
•
Gate function (CGSC = 1)
The counter operates only when the effective level is being input from the ZIN1 pin.
When the counter clear function is selected, select the effective edge. When the gate function is selected,
select the effective level. Make these selections by using the CGE1 and CGE0 bits of the counter control
register (CCR1).
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MB91665 Series
CGE1
CGE0
When the Counter Clear
Function Is Selected
(CGSC = 0)
When the Gate Function Is
Selected
(CGSC = 1)
0
0
Edge detection disabled
Level detection disabled (count
disabled)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting prohibited
Setting prohibited
■ Clear event
The counter value is cleared to "0000H" in one of the following cases:
•
This device is reset.
•
The effective edge is input from the ZIN1 pin.
(When the counter clear function for the ZIN1 pin is set in the CGSC bit (CGSC =0) of the counter
control register (CCR1).
•
Software clear
"0" is written to the UDCC bit of the counter control register (CCR1).
•
Clear with the compare clear function
The counter value matches the value set in the reload compare register (RCR1) and the counter further
attempts to count upward.
(The count value is not cleared if counting downward is performed or the counter is stopped.)
•
Clear with an overflow generation
Timing of count upward/count downward after the counter value reaches "FFFFH" (in 8-bit mode,
"FFH")
The timing of clearing the counter value to "0000H" depends on the operation state of the up/down
counter as follows.
•
When a clear event occurs during count operation
The value is cleared by synchronizing with the count clock.
Figure 24.6-1 shows the timing for the clear event to occur.
Figure 24.6-1 Clear event generation timing
UDCR
0065H
0066H
0000H
0001H
Synchronize with this clock
Clear event
Count clock
UDCR: Up-down count register (UDCR1)
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•
MB91665 Series
When a clear event occurs during count operation and the count operation is stopped before the next
count clock is input (CSTR bit = 0, in the counter status register (CSR1))
The value is cleared at the point where the up/down counter stops.
Figure 24.6-2 shows the clear event generation timing.
Figure 24.6-2 Clear event generation timing
UDCR
0065H
0066H
0000H
Clear event
Count clock
Disabled
Counting enabled
Enabled
UDCR: Up-down count register (UDCR1)
■ Reload event
The value of the up/down counter is reloaded in any of the following cases.
•
"1" is written to the CTUT bit of the counter control register (CCR1)
•
The value is reloaded by the reload function
The timing at which the value of the up/down counter is reloaded is listed below, which depends on the
operation state of the up/down counter.
•
When the reload event occurs during count operation
The value is reloaded by synchronizing with the count clock.
•
When the reload event occurs while counting is stopped
The value is reloaded at the time when the reload event occurs.
<Notes>
676
•
Do not write "1" to the CTUT bit of the counter control register (CCR1) during count operation.
•
If the reload event and clear event occur at the same time, the clear event has priority.
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CHAPTER 24 Up/Down Counter
24.6
MB91665 Series
24.6.1
Operation in Timer Mode
This section explains operations in timer mode.
■ Overview
In this mode, counting downward is performed starting from the value that has been set in the reload
compare register (RCR1). The peripheral clock (PCLK) is used as a count clock by dividing it with the
prescaler.
You can also use the reload function, which reloads the value of the reload compare register (RCR1)
when the counter underflows to restart counting downward.
■ Count operation
● Normal operation
1. Set the reload value/compare value in the reload compare register (RCR1).
2. Write "1" to the CTUT bit of the counter control register (CCR1).
The set value is transferred to the up-down count register (UDCR1).
3. Enable operation of the up/down counter by setting the CSTR bit (CSTR = 1) of the counter status
register (CSR1).
Counting downward starts from the value that has been set in the reload compare register (RCR1).
If the counter underflows, the UDFF bit of the counter status register (CSR1) changes to "1". At this
point, if the UDIE bit of the counter status register is set to "1", the underflow interrupt request is
generated.
If the gate function is set in the ZIN1 pin by use of the CGSC bit (CGSC = 1) of a counter control register
(CCR1), the counting is performed only when the effective level, which was set in the CGE1 and CGE0
bits, is input from the ZIN1 pin.
For details of effective level settings, see "24.4.3 Counter Control Register (CCR1)".
<Note>
The minimum pulse width required for the ZIN1 pin is 2T (T: period of the peripheral clock (PCLK)).
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● Operation when the reload function is used
If the counter underflows while counting downward, the UDFF bit of the counter status register (CSR1)
changes to "1". The value of the reload compare register (RCR1) is reloaded at the next timing of
underflow occurrence and counting down is restarted. At this point, if the UDIE bit of the counter status
register (CSR1) is set to "1", the underflow interrupt request is generated.
Figure 24.6-3 shows the operations when the reload function is used.
Figure 24.6-3 Operation when the reload function is used
(0FFFFH)
FFH
Reload (underflow interrupt
request is generated)
Reload (underflow interrupt
request is generated)
RCR
00H
Underflow
Underflow
RCR: Reload compare register (RCR1)
<Note>
The value of the reload compare register (RCR1) is a reload value as well as a compare value.
Therefore, if the value of the reload compare register (RCR1) is reloaded, the CMPF bit of the
counter status register (CSR1) also changes to "1".
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CHAPTER 24 Up/Down Counter
24.6
MB91665 Series
24.6.2
Operations in Up/Down Count Mode
This section explains operations in the up/down count mode.
■ Overview
In this mode, the external signals that are input from the AIN1 pin and BIN1 pin are counted upward/
downward as a count clock.
Signals are counted upward if the external signals are input from the AIN1 pin and counted downward if
input from the BIN1 pin.
One of the following edges can be selected for counting the external signals by setting the CES1 and
CES0 bits of the counter control register (CCR1).
•
Falling edge (CES1, CES0 = 01)
•
Rising edge (CES1, CES0 = 10)
•
Both edges (CES1, CES0 = 11)
In up/down count mode, the following three functions can be used.
•
Reload function
•
Compare clear function
•
Reload compare clear function
■ Count operation
● Normal operation
While the counter is enabled, if the effective edge is input from the AIN1 pin, signals are counted upward,
and if the effective edge is input from the BIN1 pin, signals are counted downward.
If the count direction is inverted such as from count up to count down or from count down to count up,
the CDCF bit of the counter control register (CCR1) changes to "1". At this point, if "1" is set for the
CFIE bit of the counter control register (CCR1), a count direction change interrupt request is generated.
If the gate function is set in the ZIN1 pin by use of the CGSC bit (CGSC = 1) of a counter control register
(CCR1), the counting is performed only when the effective level, which was set in the CGE1 and CGE0
bits, is input from the ZIN1 pin.
For details of effective level settings, see "24.4.3 Counter Control Register (CCR1)".
<Note>
The minimum pulse width required for the AIN1 pin, BIN1 pin, and ZIN1 pin is 2T (T: period of the
peripheral clock (PCLK)).
● Operation when the reload function is used
The operation is the same as that in timer mode. See "■ Count operation" in "24.6.1 Operation in Timer
Mode".
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● Operations when the compare clear function is used
If the value of the up/down counter matches the value that has been set for the reload compare register
(RCR1), the CMPF bit of the counter status register (CSR1) changes to "1". At this point, if CITE bit of
the counter status register (CSR1) is set to "1", the comparison result match interrupt request is generated.
In this state, if an attempt to further count upward is performed, the value of the up/down counter is
cleared to "0000H" to restart counting upward.
Figure 24.6-4 shows the operations when the compare clear function is used.
Figure 24.6-4 Operations when the compare clear function is used
(0FFFFH)
FFH
RCR
Comparison results
matched
Comparison results
matched
00H
Counter clearing
(Comparison result
match interrupt request
generation)
Counter clearing
(Comparison result
match interrupt
request generation)
RCR: Reload compare register (RCR1)
<Note>
When the compare clear function is used, the value of the up/down counter is cleared to "0000H" if
the following conditions are met.
•
The value of the up/down counter and the value that has been set in the reload compare
register (RCR1) match (comparison result match)
•
After that, another count has been performed.
However, the value of the up/down counter is not cleared in the following cases even if the
comparison result matches.
680
•
The next operation is counting downward
•
The up/down counter is stopped.
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MB91665 Series
● Operations when the reload compare clear function is used
During count downward, the reload function is used, and during count upward, the compare clear
function is used.
Figure 24.6-5 shows the operations when the reload compare clear function is used.
Figure 24.6-5 Operations when the reload compare clear function is used
FFH
Comparison
results matched
Comparison
results matched
Reload
Reload
Reload
Comparison
results matched
RCR
00H
Underflow
Counter clearing
Counter clearing
Underflow
Underflow
Counter clearing
RCR: Reload compare register (RCR1)
■ Verifying the count direction
In this mode, both count upward and downward are performed. Therefore, the count direction can be
verified with the UDF1 and UDF0 bits of the counter status register (CSR1). As these bits are rewritten
each time counting is performed, they can be used to verify the current count direction. This is helpful if
you want to know the rotation direction such as for controlling the motor.
Table 24.6-2 shows the count directions indicated with the UDF1 and UDF0 bits.
Table 24.6-2 Relationship between the UDF1 and UDF0 bits and count direction
UDF1
UDF0
Count Direction
0
0
No input
0
1
Count downward
1
0
Count upward
1
1
Count upward/count downward concurrently
If the count direction is inverted one or more times such as from count downward to count upward or
from count upward to count downward, the CDCF bit of the counter control register (CCR1) changes to
"1". At the time when this bit is changed, the count direction change interrupt request can also be
generated. Thus, you can verify whether the count direction has been inverted by using the CDCF bit and
generation of the count direction change interrupt request.
<Note>
If the count direction consecutively changes in a short period of time, the count direction may return
to the original one with the UDF1 and UDF0 bits of the counter status register (CSR1) indicating
the same direction as one indicated before the CDCF bit changed to "1".
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CHAPTER 24 Up/Down Counter
24.6
24.6.3
MB91665 Series
Operations in Phase Difference Count Mode
(Multiplied by 2)
This section explains operations in phase difference count mode (multiplied by 2).
■ Overview
In this mode, phase difference between the signals that are input from the 2 external signal input pins is
counted. This mode is appropriate for counting phase difference between the A-phase and B-phase of the
encoder output.
When the rising edge or falling edge is detected from the BIN1 pin, the input level of the AIN1 pin is
verified to perform counting upward/downward the phase difference between the BIN1 pin and AIN1 pin.
If the A-phase leads the B-phase, the counter counts upward; if the A-phase falls behind the B-phase, the
counter counts downward.
Whether the counter counts upward or downward depends on the detection edge of the BIN1 pin and
input level of the AIN1 pin.
Table 24.6-3 lists how to count.
Table 24.6-3 Counting method
BIN1 pin
AIN1 pin
Rising edge
Falling edge
Count Direction
"H" level
Count upward
"L" level
Count downward
"H" level
Count downward
"L" level
Count upward
In phase difference count mode (multiplied by 2), the following three functions can be used.
682
•
Reload function
•
Compare clear function
•
Reload compare clear function
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CHAPTER 24 Up/Down Counter
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MB91665 Series
■ Count operation
● Normal operation
While the counter is enabled, if the rising edge/falling edge is input from the BIN1 pin, the input level of
the AIN1 pin is detected to perform counting upward/downward.
Figure 24.6-6 shows the operations in phase difference count mode (multiplied by 2).
Figure 24.6-6 Operations in phase difference count mode (multiplied by 2)
AIN1 pin
BIN1 pin
Count value
0
+1
1
+1
2
+1
3
+1
4
+1
5
-1
4
+1
5
-1
4
-1
3
-1
2
-1
1
-1
0
If the gate function is set in the ZIN1 pin by use of the CGSC bit (CGSC = 1) of a counter control register
(CCR1), the counting is performed only when the effective level, which was set in the CGE1 and CGE0
bits, is input from the ZIN1 pin.
For details of effective level settings, see "24.4.3 Counter Control Register (CCR1)".
<Note>
The minimum pulse width required for the AIN1 pin, BIN1 pin, and ZIN1 pin is 2T (T: period of the
peripheral clock (PCLK)).
● Operation when the reload function is used
The operation is the same as that in timer mode. See "■ Count operation" in "24.6.1 Operation in Timer
Mode".
● Operations when the compare clear function is used
The operation is the same as that in up/down count mode. See "■ Count operation" in "24.6.2 Operations
in Up/Down Count Mode".
● Operations when the reload compare clear function is used
The operation is the same as that in up/down count mode. See "■ Count operation" in "24.6.2 Operations
in Up/Down Count Mode".
■ Verifying the count direction
The method is the same as that for the up/down count mode. See "■ Verifying the count direction" in
"24.6.2 Operations in Up/Down Count Mode".
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CHAPTER 24 Up/Down Counter
24.6
24.6.4
MB91665 Series
Operations in Phase Difference Count Mode
(Multiplied by 4)
This section explains operations in phase difference count mode (multiplied by 4).
■ Overview
In this mode, the phase difference between the signals that are input from the 2 external signal input pins
is counted. This mode is appropriate for counting phase difference between the A-phase and B-phase of
the encoder output.
When the rising edge or falling edge is detected from the AIN1 pin or from the BIN1 pin, the input level
of the other pins is verified to perform counting upward/downward the phase difference between the
BIN1 pin and AIN1 pin.
Whether the counter counts upward or downward depends on the combination of the detected edge and
input level.
Table 24.6-4 shows how to count.
Table 24.6-4 Counting method
Edge Detection
Pin
BIN1 pin
Detected Edge
Rising edge
Level
Verification Pin
AIN1 pin
Falling edge
AIN1 pin
Rising edge
BIN1 pin
Falling edge
Input Level
Count
Direction
"H" level
Count upward
"L" level
Count downward
"H" level
Count downward
"L" level
Count upward
"H" level
Count downward
"L" level
Count upward
"H" level
Count upward
"L" level
Count downward
In phase difference count mode (multiplied by 4), the following three functions can be used.
684
•
Reload function
•
Compare clear function
•
Reload compare clear function
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MB91665 Series
■ Count operation
● Normal operation
While the counter is enabled, if the rising edge/falling edge is input from the AIN1 pin or from the BIN1
pin, input level of the other pins is detected to perform counting upward/downward.
Figure 24.6-7 shows the operations in phase difference count mode (multiplied by 4).
Figure 24.6-7 Operations in phase difference count mode (multiplied by 4)
AIN1 pin
BIN1 pin
Count value
0
+1+1
1 2
+1+1
3 4
+1+1
5 6
+1+1
7 8
+1+1
9 10
-1
9
+1
10
-1
9
-1-1
8 7
-1-1
6 5
-1-1
4 3
-1-1
2 1
If the gate function is set in the ZIN1 pin by use of the CGSC bit (CGSC = 1) of a counter control register
(CCR1), the counting is performed only when the effective level, which was set in the CGE1 and CGE0
bits, is input from the ZIN1 pin.
For details of effective level settings, see "24.4.3 Counter Control Register (CCR1)".
<Note>
The minimum pulse width required for the AIN1 pin, BIN1 pin, and ZIN1 pin is 2T (T: period of the
peripheral clock (PCLK)).
● Operation when the reload function is used
The operation is the same as that in timer mode. See "■ Count operation" in "24.6.1 Operation in Timer
Mode".
● Operations when the compare clear function is used
The operation is the same as that in up/down count mode. See "■ Count operation" in "24.6.2 Operations
in Up/Down Count Mode".
● Operations when the reload compare clear function is used
The operation is the same as that in up/down count mode. See "■ Count operation" in "24.6.2 Operations
in Up/Down Count Mode".
■ Verifying the count direction
The method is the same as that for the up/down count mode. See "■ Verifying the count direction" in
"24.6.2 Operations in Up/Down Count Mode".
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CHAPTER 25 10-Bit A/D Converter
This chapter explains the functions and operations of the
10-bit A/D converter.
25.1
25.2
25.3
25.4
Overview
Configuration
Pins
Registers
25.5 Interrupts
25.6 Explanation of Operations and Setting Procedure
Examples
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25.1
MB91665 Series
25.1 Overview
The 10-bit A/D converter is a device for converting analog signals to 10-bit digital signals.
This series microcontroller has 10-bit A/D converters. Analog inputs are assigned to 12 channels
(MB91F669 (64 pins)) or 10 channels (MB91F668 (48 pins)) and converted.
■ Overview
•
Conversion time: 1.2 μs per channel, minimum (33 MHz peripheral clock (PCLK))
•
Comparison/conversion method: RC-type successive comparison and conversion with sample-and-hold
circuits
•
Conversion mode: The modes that can be used are categorized into the following two types:
-
A/D scan conversion
An optional conversion channel is selected from 24 channels and made subject to conversion.
Two conversion modes are available: single conversion mode and repeat conversion mode. In
single conversion mode, signals from the selected channel are converted only once. In repeat
conversion mode, signals from the selected channel are converted repeatedly.
-
A/D priority conversion
Once an activation trigger for high-priority A/D conversion is generated, that conversion is
performed soon afterward by stopping A/D scan conversion in progress. There are two priority
levels.
•
Activation trigger: Activation triggers vary depending on the A/D conversion mode:
-
A/D scan conversion
Conversion is activated by software or at detection of a rising edge of the TOUT signal of base
timer ch.0.
-
A/D priority conversion (priority 1)
Conversion is triggered by input of a falling edge from an external trigger input pin.
-
A/D priority conversion (priority 2)
Conversion is activated by software or at detection of a rising edge of the TOUT signal of base
timer ch.2.
•
FIFO functionality: There 16 FIFO levels for A/D scan conversion and 4 FIFO levels for A/D priority
conversion.
•
Conversion result compare function: A/D conversion results can be compared.
•
Independent control of channels: One of two kinds of sampling time can be set for each channel.
•
Conversion results: A/D conversion results can specified to be stored left-justified (MSB side) or rightjustified (LSB side).
•
Interrupt request: Can be issued in the following cases:
•
688
-
Data has been stored in the predetermined number of stages in the FIFO used during A/D scan
conversion.
-
Data has been stored in the predetermined number of stages in the FIFO used during A/D priority
conversion.
-
A FIFO overrun occurred.
-
The comparison function is used to determine whether conversion results satisfy the interrupt
request generation conditions.
DMA transfer activation: Generation of an interrupt request can be used for DMA transfer of
conversion results.
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CHAPTER 25 10-Bit A/D Converter
25.2
MB91665 Series
25.2 Configuration
This section explains the configuration of the 10-bit A/D converter.
■ Block diagram of the 10-bit A/D converter
Figure 25.2-1 shows a block diagram of the 10-bit A/D converter.
Figure 25.2-1 Block diagram of the 10-bit A/D converter
Base timer ch.0
Base timer ch.2
ADTRG0 pins
A/D conversion result comparison interrupt request
FIFO overrun interrupt request
Scan conversion interrupt request
Priority conversion interrupt request
Channel and status controller
Controller
S/H
A/D converter
Comparator
D/A converter
AN10
4 FIFO levels for A/D priority
conversion
AN7
MPX
AN9
AN6
Peripheral bus
16 FIFO levels for A/D scan
conversion
AN11
AN8
Buffer
AN5
AN4
AN3
AN2
AN1
AN0
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (AN10 and AN11 are not existed.)
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CHAPTER 25 10-Bit A/D Converter
25.2
•
MB91665 Series
A/D scan conversion FIFO
This is the FIFO for A/D scan conversion. There are 16 FIFO levels.
•
A/D priority conversion FIFO
•
Controller
This is the FIFO for A/D priority conversion. There are four FIFO levels.
This controller controls conversion operations.
•
Channel and status controller
This controller controls the channels and status of the 10-bit A/D converter.
•
MPX (analog multiplexer)
The MPX selects (switches to), from multiple analog input signals, the analog signal to be converted.
■ Clocks
Table 25.2-1 lists the clocks used for the 10-bit A/D converter.
Table 25.2-1 Clock used for the 10-bit A/D converter
Clock Name
Operation clock
690
Description
Peripheral clock (PCLK)
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CHAPTER 25 10-Bit A/D Converter
25.3
MB91665 Series
25.3 Pins
This section explains the pins used for the 10-bit A/D converter.
■ Overview
The 10-bit A/D converter has the following pins:
•
AVCC pin
•
AVRH pin
10-bit A/D converter analog power input pin
10-bit A/D converter reference voltage input pin
•
AVSS pin
10-bit A/D converter GND pin
•
AN0 to AN11 pins
10-bit A/D converter analog input pins
These pins are multiplexed pins. For details of using these pins as the AN0 to AN11 (AN0 to AN9 for
MB91F668 (48 pins)) pins of the 10-bit A/D converter, see "14.4.6 A/D Channel Enable Register
(ADCHE)".
•
ADTRG0 pins
10-bit A/D converter external trigger input pins
These pins are multiplexed pins. For details of using these pins as the ADTRG0 pins of the 10-bit A/
D converter, see "2.4 Setting Method for Pins".
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CHAPTER 25 10-Bit A/D Converter
25.3
MB91665 Series
■ Relationship between pins and channels
Table 25.3-1 shows the relationship between channels and pins.
Table 25.3-1 Relationship between channels and pins
Channel
0
Analog Power
Input Pin
Reference
Voltage Input
Pin
AVCC
AVRH
GND Pin
AVSS
Analog
Input Pin
AN0
1
AN1
2
AN2
3
AN3
4
AN4
5
AN5
6
AN6
7
AN7
8
AN8
9
AN9
10
AN10
11
AN11
External
Trigger Input
Pin
ADTRG0
-
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (AN10 and AN11 are not existed.)
692
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4 Registers
This section explains the configurations and functions of the registers used for the 10-bit A/D
converter.
■ List of registers for the 10-bit A/D converter
Table 25.4-1 lists the registers used for the 10-bit A/D converter.
Table 25.4-1 Registers for the 10-bit A/D converter
Abbreviated
Register Name
CM71-10158-1E
Register Name
Reference
ADCHE
A/D channel enable register
14.4.6
ADCR0
A/DC control register 0
25.4.1
ADSR0
A/DC status register 0
25.4.2
SCCR0
Scan conversion control register 0
25.4.3
SFNS0
Scan conversion FIFO number setting register 0
25.4.4
SCIS00
Scan conversion input select register 00
25.4.6
SCIS10
Scan conversion input select register 10
25.4.6
SCIS20
Scan conversion input select register 20
25.4.6
SCFD0
Scan conversion FIFO data register 0
25.4.5
PCCR0
Priority conversion control register 0
25.4.7
PFNS0
Priority conversion FIFO number setting register 0
25.4.8
PCIS0
Priority conversion input select register 0
25.4.10
PCFD0
Priority conversion FIFO data register 0
25.4.9
CMPD0
A/D comparison data setting register 0
25.4.11
CMPCR0
A/D comparison control register 0
25.4.12
ADSS00
Sampling time select register 00
25.4.14
ADSS10
Sampling time select register 10
25.4.14
ADSS20
Sampling time select register 20
25.4.14
ADST00
Sampling time setting register 00
25.4.13
ADST10
Sampling time setting register 10
25.4.13
ADCT0
Compare time setting register 0
25.4.15
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CHAPTER 25 10-Bit A/D Converter
25.4
25.4.1
MB91665 Series
A/DC Control Registers (ADCR0)
These registers control interrupt requests.
Figure 25.4-1 shows the bit configuration of the A/DC control registers (ADCR0).
Figure 25.4-1 Bit configuration of the A/DC control registers (ADCR0)
bit
Attribute
Initial value
7
6
5
4
3
2
1
0
SCIF
PCIF
CMPIF
Undefined
SCIE
PCIE
CMPIE
OVRIE
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
0
0
0
X
0
0
0
0
R/W: Read/Write
-: Undefined
X: Undefined
[bit7]: SCIF (Scan conversion interrupt request flag bit)
This bit indicates that A/D scan conversion results have been stored in the number of stages in the FIFO
as specified by the SFS3 to SFS0 bits in a scan conversion FIFO number setting register (SFNS0).
If the SCIE bit is set to "1" when this bit is "1", a scan conversion interrupt request is generated.
SCIF
In Case of Reading
In Case of Writing
0
The number of stages storing
conversion results has not reached the
specified number of stages.
This bit is cleared to "0".
1
The number of stages storing
conversion results has reached the
specified number of stages.
Ignored
<Note>
When a read-modify-write instruction is used, "1" is read.
694
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit6]: PCIF (Priority conversion interrupt request flag bit)
This bit indicates that A/D priority conversion results have been stored up to the number of stages in the
FIFO as specified by the PFS1 and PFS0 bits in a priority conversion FIFO number setting register
(PFNS0).
If the PCIE bit is set to "1" when this bit is "1", a priority conversion interrupt request is generated.
PCIF
In Case of Reading
In Case of Writing
0
The number of stages storing
conversion results has not reached the
specified number of stages.
This bit is cleared to "0".
1
The number of stages storing
conversion results has reached the
specified number of stages.
Ignored
<Note>
When a read-modify-write instruction is used, "1" is read.
[bit5]: CMPIF (Conversion result comparison interrupt request flag bit)
The A/D conversion result compare function is used when conversion results are compared with the data
in the A/D comparison data setting registers (CMPD0).
This bit indicates that a conversion result satisfies the requirements set in an A/D comparison data setting
register (CMPD0) and an A/D comparison control register (CMPCR0).
If the CMPIE bit is set to "1" when this bit is "1", a conversion result comparison interrupt request is
generated.
CMPIF
In Case of Reading
In Case of Writing
0
The requirements are not satisfied.
This bit is cleared to "0".
1
The requirements are satisfied.
Ignored
<Note>
When a read-modify-write instruction is used, "1" is read.
[bit4]: Undefined bit
CM71-10158-1E
In case of writing
Ignored
In case of reading
A value is undefined.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit3]: SCIE (Scan conversion interrupt enable bit)
This bit specifies whether to generate a scan conversion interrupt request when the number of stages
storing A/D scan conversion results reaches the number of FIFO stages (SCIF bit = 1) specified in the
SFS3 to SFS0 bits in a scan conversion FIFO number setting register (SFNS0).
Written Value
Explanation
0
Disables generation of scan conversion interrupt requests.
1
Enables generation of scan conversion interrupt requests.
[bit2]: PCIE (Priority conversion interrupt enable bit)
This bit specifies whether to generate a priority conversion interrupt request when the number of stages
storing A/D priority conversion results reaches the number of FIFO stages (PCIF bit = 1) specified in the
PFS1 and PFS0 bits in a priority conversion FIFO number setting register (PFNS0).
Written Value
Explanation
0
Disables generation of priority conversion interrupt requests.
1
Enables generation of priority conversion interrupt requests.
[bit1]: CMPIE (Conversion result comparison interrupt enable bit)
The A/D conversion result compare function is used when conversion results are compared with the data
in the A/D comparison data setting registers (CMPD0).
This bit specifies whether to generate a conversion result comparison interrupt request when a conversion
result satisfies the requirements (CMPIF bit = 1) set in an A/D comparison control register (CMPCR0).
Written Value
Explanation
0
Disables generation of conversion result comparison
interrupt requests.
1
Enables generation of conversion result comparison interrupt
requests.
[bit0]: OVRIE (FIFO overrun interrupt enable bit)
This bit specifies whether to generate a FIFO overrun interrupt request when the SOVR bit in a scan
conversion control register (SCCR0) or the POVR bit in a priority conversion control register (PCCR0)
changes to "1".
If an attempt is made to write to a full FIFO, the SOVR bit in the scan conversion control register
(SCCR0) or the POVR bit in the priority conversion control register (PCCR0) changes to "1".
Written Value
696
Explanation
0
Disables generation of FIFO overrun interrupt requests.
1
Enables generation of FIFO overrun interrupt requests.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.2
A/DC Status Registers (ADSR0)
These registers indicate the A/D conversion status.
Figure 25.4-2 shows the bit configuration of the A/DC status registers (ADSR0).
Figure 25.4-2 Bit configuration of the A/DC status registers (ADSR0)
bit
7
6
5
4
3
2
1
0
ADSTP
FDAS
Undefined
Undefined
Undefined
PCNS
PCS
SCS
R/W
R/W
-
-
-
R
R
R
0
0
X
X
X
0
0
0
Attribute
Initial value
R/W: Read/Write
R: Read only
-: Undefined
X: Undefined
[bit7]: ADSTP (A/D conversion abort bit)
This bit forcibly stops A/D conversion.
ADSTP
In Case of Writing
0
Ignored
1
Forcibly stops A/D conversion.
In Case of Reading
"0" is read.
<Notes>
•
Writing "1" to this bit stops A/D conversion in either A/D scan conversion mode or A/D priority
conversion mode.
•
Writing "1" to this bit to forcibly stop A/D conversion clears the PCNS, PCS, and SCS bits to "0".
However, it does not affect other registers.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit6]: FDAS (FIFO data allocation select bit)
This bit specifies the mode of bit allocation to the scan conversion FIFO data registers (SCFD0) and
priority conversion FIFO data registers (PCFD0).
•
Left-justify: Conversion results (with channel information, with priority A/D activation trigger
information (priority conversion only)) are left-justified.
•
Right-justify: Conversion results (without channel information, without priority A/D activation trigger
information (priority conversion only)) are shifted 6 bits to the LSB side to right-justify the results.
Conversion results are allocated to bit9 to bit0.
Written Value
698
Explanation
0
Allocates conversion results left-justified.
1
Allocates conversion results right-justified.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
Figure 25.4-3 shows the relationship between this bit and the scan conversion FIFO data registers
(SCFD0) and the relationship between this bit and the priority conversion FIFO data registers (PCFD0).
Figure 25.4-3 Relationship between FDAS and the scan conversion FIFO data registers (SCFD0)/
priority conversion FIFO data registers (PCFD0)
Scan conversion FIFO data registers (SCFD0)
For FDAS = 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
SC4
SC3
SC2
SC1
SC0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
For FDAS = 1
Priority conversion FIFO data registers (PCFD0)
For FDAS = 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
RS
PC4
PC3
PC2
PC1
PC0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
For FDAS = 1
<Notes>
•
If "1" is written to this bit to select right-justification, conversion results are shifted six bits to the
LSB side, which consequently leads to a loss of converted information on channels (the SC4 to
SC0 bits/PC4 to PC0 bits in Figure 25.4-3). Right-justification is used only when channel
information is not required in conversion results, such as when conversion involves only 1
channel.
•
If "1" is written to this bit to select right-justification in A/D priority conversion mode, (the RS bit
of Figure 25.4-3 ) activation trigger information on A/D priority conversion is lost. Rightjustification is used only when either priority 1 or 2 of A/D priority conversion mode is used.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit5 to bit3]: Undefined bits
In case of writing
Ignored
In case of reading
A value is undefined.
[bit2]: PCNS (Priority conversion pending flag bit)
This bit indicates that A/D priority conversion of priority 2 is pending.
If A/D priority conversion of priority 2 is activated during execution of A/D priority conversion of
priority 1 or vice versa, the bit is changed to "1".
Read Value
Explanation
0
A/D priority conversion of priority 2 is not pending.
1
A/D priority conversion of priority 2 is pending.
[bit1]: PCS (Priority conversion status flag bit)
This bit indicates that A/D priority conversion of priority 1 or 2 is in progress.
Read Value
Explanation
0
A/D priority conversion is stopped.
1
A/D priority conversion is in progress.
[bit0]: SCS (Scan conversion status flag bit)
This bit indicates that A/D scan conversion is in progress.
Read Value
700
Explanation
0
A/D scan conversion is stopped.
1
A/D scan conversion is in progress.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.3
Scan Conversion Control Registers (SCCR0)
These registers are used to control the operation of A/D scan conversion.
Figure 25.4-4 shows the bit configuration of the scan conversion control registers (SCCR0).
Figure 25.4-4 Bit configuration of the scan conversion control registers (SCCR0)
bit
7
6
5
4
3
2
1
0
SEMP
SFUL
SOVR
SFCLR
Undefined
RPT
SHEN
SSTR
Attribute
R
R
R/W
R/W
-
R/W
R/W
R/W
Initial value
1
0
0
0
X
0
0
0
R/W: Read/Write
R: Read only
-: Undefined
X: Undefined
<Note>
Do not perform word access to these registers.
The scan conversion FIFO data register (SCFD0) needs to be read when the SEMP bit is "0".
[bit7]: SEMP (Scan conversion FIFO empty flag bit)
This bit indicates that the FIFO for A/D scan conversion is empty.
Read Value
Explanation
0
The FIFO for A/D scan conversion contains data.
1
The FIFO for A/D scan conversion is empty.
This bit is cleared to "0" when data is stored in a scan conversion FIFO data register (SCFD0).
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit6]: SFUL (Scan conversion FIFO full bit)
This bit indicates that the FIFO for A/D scan conversion is full.
Read Value
Explanation
0
The FIFO for A/D scan conversion has free space.
1
The FIFO for A/D scan conversion is full.
This bit is cleared to "0" when "1" is written to the SFCLR bit or a scan conversion FIFO data register
(SCFD0) is read.
[bit5]: SOVR (Scan conversion overrun flag bit)
The bit indicates that an attempt has been made to write to a full A/D scan conversion FIFO (an overrun
has occurred).
If the OVRIE bit in an A/DC control register (ADCR0) is set to "1" when this bit is "1", a FIFO overrun
interrupt request is generated.
SOVR
In Case of Reading
In Case of Writing
0
No overrun occurred.
This bit is cleared to "0".
1
An overrun occurred.
Ignored
<Notes>
•
When a read-modify-write instruction is used, "1" is read.
•
When an attempt is made to write data to a full FIFO, the conversion data in the FIFO is not
overwritten.
[bit4]: SFCLR (Scan conversion FIFO clear bit)
This bit is used to clear the A/D scan conversion FIFO.
SFCLR
In Case of Writing
0
Ignored
1
Clears the A/D scan conversion
FIFO.
In Case of Reading
"0" is read.
<Note>
Writing "1" to this bit empties the FIFO for A/D scan conversion. Accordingly, the SEMP bit
changes to "1".
702
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit3]: Undefined bit
In case of writing
Ignored
In case of reading
A value is undefined.
[bit2]: RPT (Scan conversion repeat bit)
This bit specifies the A/D scan conversion mode.
•
Single conversion mode: Signals from the channel specified by a scan conversion input select register
(SCIS20 to SCIS00) are converted only once.
•
Repeat conversion mode: Signals from the channel specified by a scan conversion input select register
(SCIS20 to SCIS00) are converted repeatedly.
Written Value
Explanation
0
Single conversion mode
1
Repeat conversion mode
<Notes>
•
If "0" is written to this bit during conversion in repeat conversion mode, the conversion operation
is stopped after the signals from the channel specified by the scan conversion input select
register (SCIS20 to SCIS00) are converted.
•
To enable repeat conversion mode, write "1" to this bit after checking the SCS bit in the A/DC
status registers (ADSR0) and confirming that A/D scan conversion is stopped
(SCS = 0).
However, to start A/D scan conversion (with SSTR = 1) while simultaneously enabling repeat
conversion mode, the SSTR bit can be written at the same time as this bit.
[bit1]: SHEN (Scan conversion timer activation enable bit)
This bit specifies whether to activate A/D scan conversion upon detection of the rising edge of a TOUT
signal of base timer ch.0.
Written Value
Explanation
0
Disables A/D scan conversion activation based on a base timer (ch.0).
1
Enables A/D scan conversion activation based on a base timer (ch.0).
<Notes>
•
If "1" is written to the SSTR bit, A/D scan conversion is activated regardless of the setting of this
bit.
•
After "1" is written to this bit, "1" may be written to the SSTR bit at the same time that activation
is triggered by a base timer (ch.0). In this event, activation by software is given priority, and
activation triggered by the base timer is ignored.
•
For details of the TOUT signal, see "CHAPTER 23 Base Timer".
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit0]: SSTR (Scan conversion start bit)
This bit is used to activate A/D scan conversion by software.
Writing "1" to the bit during conversion stops and restarts the conversion.
SSTR
704
In Case of Writing
0
Ignored
1
Activates or reactivates A/D scan
conversion.
In Case of Reading
"0" is read.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.4
Scan Conversion FIFO Number Setting Register
(SFNS0)
These registers specify the maximum number of stages in the A/D scan conversion FIFO. A scan
conversion interrupt request can be issued when the number of stages storing conversion results
reaches that maximum number during A/D scan conversion.
Figure 25.4-5 shows the bit configuration of the scan conversion FIFO number setting registers (SFNS0).
Figure 25.4-5 Bit configuration of the scan conversion FIFO number setting registers (SFNS0)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
Undefined
Undefined
SFS3
SFS2
SFS1
SFS0
Attribute
-
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
0
0
0
0
R/W: Read/Write
-: Undefined
X: Undefined
<Note>
Do not perform word access to these registers.
[bit7 to bit4]: Undefined bits
CM71-10158-1E
In case of writing
Ignored
In case of reading
A value is undefined.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit3 to bit0]: SFS3 to SFS0 (Scan conversion FIFO number setting bits)
These bits specify the maximum number of stages in the A/D scan conversion FIFO. A scan conversion
interrupt request can be issued when the number of stages storing conversion results reaches that
maximum number during A/D scan conversion.
The SCIF bit in an A/DC control register (ADCR0) changes to "1" when the number of stages storing
such data reaches the maximum number of FIFO stages specified by these bits.
706
SFS3
SFS2
SFS1
SFS0
Explanation
0
0
0
0
First level
0
0
0
1
Second level
0
0
1
0
Third level
0
0
1
1
Fourth level
0
1
0
0
Fifth level
0
1
0
1
Sixth level
0
1
1
0
Seventh level
0
1
1
1
Eighth level
1
0
0
0
Ninth level
1
0
0
1
Tenth level
1
0
1
0
Eleventh level
1
0
1
1
Twelfth level
1
1
0
0
Thirteenth level
1
1
0
1
Fourteenth level
1
1
1
0
Fifteenth level
1
1
1
1
Sixteenth level
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.5
Scan Conversion FIFO Data Registers (SCFD0)
These registers store A/D scan conversion results. Each register consists of 16 FIFO stages.
FIFO data can be read sequentially from the registers.
The bit configuration of these registers varies depending on the setting of the FDAS bit in the A/DC
status registers (ADSR0).
<Notes>
•
One of these registers must always be read after the SEMP bit in a scan conversion control
register (SCCR0) is checked to determine whether data remains in the A/D scan conversion
FIFO (SEMP = 0).
If this register is read when the A/D scan conversion FIFO is empty (SEMP = 1), it is impossible
to determine whether the read data is valid. For details, see "■ Operation of A/D scan
conversion" in "25.6.3 FIFO Operations".
•
Do not perform word access to these registers.
•
In byte access to these registers, the low-order byte (bit7 to bit0) must be accessed before the
high-order byte (bit15 to bit8). FIFO data is shifted after the high-order bytes is read.
■ Left-justify (FDAS = 0)
Figure 25.4-6 shows the bit configuration of the scan conversion FIFO data registers (SCFD0) when the
FDAS bit in an A/DC status register (ADSR0) specifies left-justification (FDAS = 0).
Figure 25.4-6 Bit configuration of the scan conversion FIFO data registers (SCFD0)
bit
15
14
13
12
11
10
9
8
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
Attribute
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
SD1
SD0
Undefined
SC4
SC3
SC2
SC1
SC0
Attribute
R
R
-
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit
R: Read only
-: Undefined
X: Undefined
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit15 to bit6]: SD9 to SD0 (A/D scan conversion result bits)
These bits store A/D scan conversion results.
[bit5]: Undefined bit
"0" is read.
[bit4 to bit0]: SC4 to SC0 (Conversion channel bits)
These bits indicate the channel from which analog input has been converted and stored in the SD9 to SD0
bits.
SC4
SC3
SC2
SC1
SC0
Explanation
0
0
0
0
0
ch.0 (AN0 pin)
0
0
0
0
1
ch.1 (AN1 pin)
0
0
0
1
0
ch.2 (AN2 pin)
0
0
0
1
1
ch.3 (AN3 pin)
0
0
1
0
0
ch.4 (AN4 pin)
0
0
1
0
1
ch.5 (AN5 pin)
0
0
1
1
0
ch.6 (AN6 pin)
0
0
1
1
1
ch.7 (AN7 pin)
0
1
0
0
0
ch.8 (AN8 pin)
0
1
0
0
1
ch.9 (AN9 pin)
0
1
0
1
0
ch.10 (AN10 pin)
0
1
0
1
1
ch.11 (AN11 pin)
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
Setting prohibited
708
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
SC4
SC3
SC2
SC1
SC0
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
Explanation
Setting prohibited
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (Setting prohibited for AN10 and AN11 because they
are not existed.)
■ Right-justify (FDAS = 1)
Figure 25.4-7 shows the bit configuration of the scan conversion FIFO data registers (SCFD0) when the
FDAS bit in an A/DC status register (ADSR0) specifies right-justification
(FDAS = 1).
Figure 25.4-7 Bit configuration of the scan conversion FIFO data registers (SCFD0)
bit
15
14
13
12
11
10
9
8
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
SD9
SD8
Attribute
-
-
-
-
-
-
R
R
Initial value
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Attribute
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit
R: Read only
-: Undefined
X: Undefined
[bit15 to bit10]: Undefined bits
"0" is read.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit9 to bit0]: SD9 to SD0 (A/D scan conversion result bits)
These bits store A/D scan conversion results.
<Note>
Information on converted channels is not stored in right-justify mode. Right-justification is used
only when channel information is not required in conversion results, such as when conversion
involves only one channel.
710
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.6
Scan Conversion Input Select Registers
(SCIS20 to SCIS00)
These registers are used to select the channel to be subject to A/D scan conversion.
Figure 25.4-8 shows the bit configuration of the scan conversion input select registers (SCIS20 to
SCIS00).
Figure 25.4-8 Bit configuration of the scan conversion input select registers (SCIS20 to SCIS00)
Scan conversion input select register 20 (SCIS20)
bit
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
Scan conversion input select register 10 (SCIS10)
bit
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
AN11
AN10
AN9
AN8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
Scan conversion input select register 00 (SCIS00)
bit
Attribute
Initial value
7
6
5
4
3
2
1
0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
R/W: Read/Write
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (Reserved bits for AN10 and AN11 because they are not existed.)
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
SCIS20 to SCIS00: AN11 to AN0 (analog input select bits)
The channel corresponding to a bit that is set to "1" is made subject to conversion.
The AN11 bit corresponds to ch.11 (AN11 pin), the AN10 bit corresponds to ch.10 (AN10 pin), ... the
AN1 bit corresponds to ch.1 (AN1 pin), and the AN0 bit corresponds to ch.0 (AN0 pin).
If multiple channels are selected with these registers, they are made subject to conversion sequentially in
ascending order of channel number. For example, if "1" is written to the AN3, AN5, AN10, and AN11
bits, the corresponding channels are made subject to conversion in the following sequence:
ch.3 →ch.5 →ch.10 →ch.11
<Notes>
712
•
Write to these registers while A/D conversion is stopped.
•
Always write "0" to the reserved bits.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.7
Priority Conversion Control Registers (PCCR0)
These registers are used to control the operation of A/D priority conversion. Two priority levels can be
selected.
Figure 25.4-9 shows the bit configuration of the priority conversion control registers (PCCR0).
Figure 25.4-9 Bit configuration of the priority conversion control registers (PCCR0)
bit
7
6
5
4
3
2
1
0
PEMP
PFUL
POVR
PFCLR
Reserved
PEEN
PHEN
PSTR
Attribute
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
1
0
0
0
0
0
0
0
R/W: Read/Write
R: Read only
<Note>
Do not perform word access to these registers.
The priority conversion FIFO data register (PCFD0) needs to be read when the SEMP bit is "0".
[bit7]: PEMP (Priority conversion FIFO empty flag bit)
This bit indicates that the FIFO for A/D priority conversion is empty.
Read Value
Explanation
0
The FIFO for A/D priority conversion contains data.
1
The FIFO for A/D priority conversion is empty.
This bit is cleared to "0" when data is stored in the priority conversion FIFO data register (PCFD0).
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit6]: PFUL (Priority conversion FIFO full bit)
This bit indicates that the FIFO for A/D priority conversion is full.
Read Value
Explanation
0
The A/D priority conversion FIFO has free space.
1
The A/D priority conversion FIFO is full.
This bit is cleared to "0" when "1" is written to the PFCLR bit or a priority conversion FIFO data register
(PCFD0) is read.
[bit5]: POVR (Priority conversion overrun flag bit)
This bit indicates that an attempt has been made to write to a full A/D priority conversion FIFO (an
overrun has been occurred).
If the OVRIE bit in an A/DC control register (ADCR0) is set to "1" when this bit is "1", a FIFO overrun
interrupt request is generated.
POVR
In Case of Reading
In Case of Writing
0
Overrun has not been occurred
This bit is cleared to "0".
1
Overrun has been occurred
Ignored
<Notes>
•
When a read-modify-write instruction is used, "1" is read.
•
Even if an attempt is made to write data to a full FIFO, the conversion data in the FIFO is not
overwritten.
[bit4]: PFCLR (Priority conversion FIFO clear bit)
This bit is used to clear the A/D priority conversion FIFO.
PFCLR
In Case of Writing
0
Ignored
1
Clears the A/D priority conversion
FIFO.
In Case of Reading
"0" is read.
<Note>
Writing "1" to this bit empties the FIFO for A/D priority conversion. Accordingly, the PEMP bit
changes to "1".
714
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit3]: Reserved bit
In case of writing
Always write "0" to this (these) bit (bits).
In case of reading
A value is undefined.
[bit2]: PEEN (Priority conversion external activation enable bit)
This bit specifies whether to activate A/D priority conversion of priority level 1 upon detection of a
falling edge from the ADTRG0 pin. Priority 1 has the highest priority because priority 1 > priority 2.
Written Value
Explanation
0
Disables activation of A/D priority conversion of priority 1.
1
Enables activation of A/D priority conversion of priority 1.
<Note>
The microcontroller provides four pins that can be used as an ADTRG0 pin. Specify a pin as the
ADTRG0 pin.
For details of how to set the pin, see "CHAPTER 14 I/O Ports".
[bit1]: PHEN (Priority conversion timer activation enable bit)
This bit specifies whether to activate A/D priority conversion of priority 2 upon detection of the rising
edge of a TOUT signal of base timer ch.2. Priority 2 < priority 1.
Written Value
Explanation
0
Disables activation of A/D priority conversion of priority 2.
1
Enables activation of A/D priority conversion of priority 2.
<Notes>
•
If "1" is written to the PSTR bit, A/D priority conversion of priority 2 is activated regardless of
the setting of this bit.
•
For details of the TOUT signal, see "CHAPTER 23 Base Timer".
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit0]: PSTR (Priority conversion start bit)
This bit enables software to activate A/D priority conversion of priority 2. Priority 2 < priority 1.
PSTR
In Case of Writing
0
Ignored
1
Activates A/D priority conversion of
priority 2.
In Case of Reading
"0" is read.
<Note>
Even if "1" is written to this bit during A/D conversion, the A/D conversion cannot be reactivated.
716
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.8
Priority Conversion FIFO Number Setting Registers
(PFNS0)
These registers specify the maximum number of stages in the A/D priority conversion FIFO. A priority
conversion interrupt request can be issued when the number of stages storing conversion results
reaches that maximum number during A/D priority conversion.
Figure 25.4-10 shows the bit configuration of the priority conversion FIFO number setting registers
(PFNS0).
Figure 25.4-10 Bit configuration of the Priority conversion FIFO number setting registers (PFNS0)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
PFS1
PFS0
Attribute
-
-
-
-
-
-
R/W
R/W
Initial value
X
X
X
X
X
X
0
0
R/W: Read/Write
-: Undefined
X: Undefined
<Note>
Do not perform word access to these registers.
The priority conversion FIFO data register (PCFD0) needs to be read when the PEMP bit is "0".
[bit7 to bit2]: Undefined bits
CM71-10158-1E
In case of writing
Ignored
In case of reading
A value is undefined.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit1, bit0]: PFS1, PFS0 (Priority conversion FIFO number setting bits)
These bits specify the maximum number of stages in the A/D priority conversion FIFO. A priority
conversion interrupt request can be issued when the number of stages storing conversion results reaches
that maximum number during A/D priority conversion.
The PCIF bit in an A/DC control register (ADCR0) changes to "1" when the number of stages storing
such data reaches the maximum number of FIFO stages specified by these bits.
718
PFS1
PFS0
Explanation
0
0
First level
0
1
Second level
1
0
Third level
1
1
Fourth level
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.9
Priority Conversion FIFO Data Registers (PCFD0)
These registers store A/D priority conversion results. Each register consists of 4 FIFO stages. FIFO
data can be read sequentially from the registers.
The bit configuration of these registers varies depending on the setting of the FDAS bit in the A/DC
status registers (ADSR0).
<Notes>
•
One of these registers must always be read after the PEMP bit in a priority conversion control
register (PCCR0) is checked to determine whether data remains in the A/D priority conversion
FIFO (PEMP = 0).
If this register is read when the A/D priority conversion FIFO is empty (PEMP = 1), it is
impossible to determine whether the read data is valid. For details, see "■ Operation of A/D
priority conversion" in "25.6.3 FIFO Operations".
•
Do not perform word access to these registers.
•
In byte access to these registers, the low-order byte (bit7 to bit0) must be accessed before the
high-order byte (bit15 to bit8). FIFO data is shifted after the high-order byte is read.
■ Left-justify (FDAS = 0)
Figure 25.4-11 shows the bit configuration of the priority conversion FIFO data registers (PCFD0) when
the FDAS bit in an A/DC status register (ADSR0) specifies left-justification (FDAS = 0).
Figure 25.4-11 Bit configuration of the priority conversion FIFO data registers (PCFD0)
bit
15
14
13
12
11
10
9
8
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
Attribute
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
PD1
PD0
RS
PC4
PC3
PC2
PC1
PC0
Attribute
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit
R: Read only
X: Undefined
[bit15 to bit6]: PD9 to PD0 (A/D priority conversion result bits)
These bits store A/D priority conversion results.
CM71-10158-1E
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit5]: RS (Priority A/D activation trigger bit)
This bit indicates whether the data stored in the PD9 to PD0 bits has been converted with priority 1 or 2
(activation trigger for A/D priority conversion).
Read Value
Explanation
0
Priority 2 (activation by software/base timer)
1
Priority 1 (activation by an external trigger)
<Note>
The activation trigger for A/D priority conversion of priority 2 cannot be distinguished as software or
a base timer.
[bit4 to bit0]: PC4 to PC0 (Conversion channel bits)
These bits indicate the channel from which analog input has been converted and stored in the PD9 to PD0
bits.
PC4
720
PC3
PC2
PC1
PC0
Explanation
0
0
0
0
0
ch.0 (AN0 pin)
0
0
0
0
1
ch.1 (AN1 pin)
0
0
0
1
0
ch.2 (AN2 pin)
0
0
0
1
1
ch.3 (AN3 pin)
0
0
1
0
0
ch.4 (AN4 pin)
0
0
1
0
1
ch.5 (AN5 pin)
0
0
1
1
0
ch.6 (AN6 pin)
0
0
1
1
1
ch.7 (AN7 pin)
0
1
0
0
0
ch.8 (AN8 pin)
0
1
0
0
1
ch.9 (AN9 pin)
0
1
0
1
0
ch.10 (AN10 pin)
0
1
0
1
1
ch.11 (AN11 pin)
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
Setting prohibited
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
PC4
PC3
PC2
PC1
PC0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
Explanation
Setting prohibited
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (Setting prohibited for AN10 and AN11 because they
are not existed.)
<Note>
A/D priority conversion of priority 1 can be performed only for ch.0 to ch.7.
CM71-10158-1E
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
■ Right-justify (FDAS = 1)
Figure 25.4-12 shows the bit configuration of the priority conversion FIFO data registers (PCFD0) when
the FDAS bit in an A/DC status register (ADSR0) specifies right-justification (FDAS = 1).
Figure 25.4-12 Bit configuration of the Priority conversion FIFO data registers (PCFD0)
bit
15
14
13
12
11
10
9
8
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
PD9
PD8
Attribute
-
-
-
-
-
-
R
R
Initial value
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Attribute
R
R
R
R
R
R
R
R
Initial value
X
X
X
X
X
X
X
X
bit
R: Read only
-: Undefined
X: Undefined
[bit15 to bit10]: Undefined bits
In case of writing
Ignored
In case of reading
A value is undefined.
[bit9 to bit0]: PD9 to PD0 (A/D priority conversion result bits)
These bits store A/D priority conversion results.
<Note>
The activation trigger (priority) for A/D priority conversion and information on the converted channel
are not stored in right-justify mode. Right-justification is used only when only either priority 1 or 2 of
A/D priority conversion mode is used and when the converted result does not need the channel
information, such as a conversion with 1 channel.
722
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.10
Priority Conversion Input Select Registers (PCIS0)
These registers are used to select the channel to be subject to A/D priority conversion.
1 channel subject to conversion with priority 2 is selected from the 24 channels, and 1 channel subject
to conversion with priority 1 is selected from ch.0 to ch.7.
Figure 25.4-13 shows the bit configuration of the priority conversion input select registers (PCIS0).
Figure 25.4-13 Bit configuration of the priority conversion input select registers (PCIS0)
bit
7
6
5
4
3
2
1
0
P2A4
P2A3
P2A2
P2A1
P2A0
P1A2
P1A1
P1A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
CM71-10158-1E
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit7 to bit3]: P2A4 to P2A0 (Priority 2 analog input select bit)
These bits select the channel to be subject to A/D priority conversion of priority 2. Priority 2 < priority 1.
P2A4
P2A3
P2A2
P2A1
P2A0
Explanation
0
0
0
0
0
ch.0 (AN0 pin)
0
0
0
0
1
ch.1 (AN1 pin)
0
0
0
1
0
ch.2 (AN2 pin)
0
0
0
1
1
ch.3 (AN3 pin)
0
0
1
0
0
ch.4 (AN4 pin)
0
0
1
0
1
ch.5 (AN5 pin)
0
0
1
1
0
ch.6 (AN6 pin)
0
0
1
1
1
ch.7 (AN7 pin)
0
1
0
0
0
ch.8 (AN8 pin)
0
1
0
0
1
ch.9 (AN9 pin)
0
1
0
1
0
ch.10 (AN10 pin)
0
1
0
1
1
ch.11 (AN11 pin)
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
Setting prohibited
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (Setting prohibited for AN10 and AN11 because they
are not existed.)
724
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit2 to bit0]: P1A2 to P1A0 (Priority 1 analog input select bit)
These bits select the channel to be subject to A/D priority conversion of priority 1. A/D priority
conversion of priority 1 can be performed only for ch.0 to ch.7. Priority 2 < priority 1.
CM71-10158-1E
P1A2
P1A1
P1A0
Explanation
0
0
0
ch.0 (AN0 pin)
0
0
1
ch.1 (AN1 pin)
0
1
0
ch.2 (AN2 pin)
0
1
1
ch.3 (AN3 pin)
1
0
0
ch.4 (AN4 pin)
1
0
1
ch.5 (AN5 pin)
1
1
0
ch.6 (AN6 pin)
1
1
1
ch.7 (AN7 pin)
FUJITSU SEMICONDUCTOR LIMITED
725
CHAPTER 25 10-Bit A/D Converter
25.4
25.4.11
MB91665 Series
A/D Comparison Data Setting Registers (CMPD0)
These registers are used to set the value that is compared with A/D conversion results when the
comparison function is used. The eight high-order bits of the conversion results are compared with a
value set in the registers. If the comparison result satisfies the requirements set in an A/D
comparison control register (CMPCR0), the CMPIF bit in an A/DC control register (ADCR0) changes
to "1".
Figure 25.4-14 shows the bit configuration of the A/D comparison data setting registers (CMPD0).
Figure 25.4-14 Bit configuration of the A/D comparison data setting registers (CMPD0)
bit
7
6
5
4
3
2
1
0
CMAD9
CMAD8
CMAD7
CMAD6
CMAD5
CMAD4
CMAD3
CMAD2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
<Note>
A value that is set in these registers is compared with the eight high-order bits (bit9 to bit2) of A/D
conversion results. The two bits (bit1, bit0) on the LSB side of A/D conversion results are not used
for the comparison.
726
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.12
A/D Comparison Control Registers (CMPCR0)
These registers control the comparison function. The comparison function is used when an A/D
conversion result is compared with the value set in an A/D comparison data setting register (CMPD0).
If the comparison result satisfies the requirements set in that register, the CMPIF bit in an
A/DC control register (ADCR0) changes to "1".
Figure 25.4-15 shows the bit configuration of the A/D comparison control registers (CMPCR0).
Figure 25.4-15 Bit configuration of the A/D comparison control registers (CMPCR0)
bit
7
6
5
4
3
2
1
0
CMPEN
CMD1
CMD0
CCH4
CCH3
CCH2
CCH1
CCH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
[bit7]: CMPEN (Comparison function operation enable bit)
This bit specifies whether to enable the comparison function.
Written Value
Explanation
0
Disables the comparison function.
1
Enables the comparison function.
[bit6]: CMD1 (Comparison mode 1 bit)
This bit sets the conversion interrupt request generation conditions.
Written Value
CM71-10158-1E
Explanation
0
A conversion result interrupt request is generated when the A/D conversion
result is smaller than the value set in an A/D comparison data setting register
(CMPD0).
1
A conversion result interrupt request is generated when the A/D conversion
result is equal to or greater than the value set in an A/D comparison data
setting register (CMPD0).
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit5]: CMD0 (Comparison mode 0 bit)
This bit selects one of the following comparison modes:
•
Comparing the conversion result of the channel specified by the CCH4 to CCH0 bits with the value set
in an A/D comparison data setting register (CMPD0)
•
Comparing the conversion results of all channels with the value set in an A/D comparison data setting
register (CMPD0)
Written Value
Explanation
0
Compares the conversion result of the channel specified by the CCH4 to CCH0
bits.
1
Compares the conversion results of all channels.
<Note>
Writing "1" to this bit invalidates the settings of the CCH4 to CCH0 bits.
728
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit4 to bit0]: CCH4 to CCH0 (Comparison target analog input channel bits)
These bits specify the channel to be compared with the value set in an A/D comparison data setting
register (CMPD0) when the CMD0 bit is "0".
CCH4
CCH3
CCH2
CCH1
CCH0
Explanation
0
0
0
0
0
ch.0 (AN0 pin)
0
0
0
0
1
ch.1 (AN1 pin)
0
0
0
1
0
ch.2 (AN2 pin)
0
0
0
1
1
ch.3 (AN3 pin)
0
0
1
0
0
ch.4 (AN4 pin)
0
0
1
0
1
ch.5 (AN5 pin)
0
0
1
1
0
ch.6 (AN6 pin)
0
0
1
1
1
ch.7 (AN7 pin)
0
1
0
0
0
ch.8 (AN8 pin)
0
1
0
0
1
ch.9 (AN9 pin)
0
1
0
1
0
ch.10 (AN10 pin)
0
1
0
1
1
ch.11 (AN11 pin)
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
Setting prohibited
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
CCH4
CCH3
CCH2
CCH1
CCH0
1
1
1
1
0
1
1
1
1
1
Explanation
Setting prohibited
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (Setting prohibited for AN10 and AN11 because they
are not existed.)
<Note>
If the CMD0 bit is set to "1" to compare the conversion results of all channels, the settings of these
bits are ignored.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
25.4.13
Sampling Time Setting Registers (ADST00, ADST10)
These registers specify the sampling time, that is, the period from the start of A/D conversion until the
beginning of input voltage sampling when the sampled voltage is held in the sample-and-hold circuit.
The A/D conversion time is the total of the sampling time and compare time.
2 ADST registers are provided to set the sampling time. After the sampling time is set in each
register, the sampling time select registers (ADSS20 to ADSS00) can be used to specify the register
that has the set sampling time to be used for each channel.
Figure 25.4-16 shows the bit configuration of the sampling time setting registers (ADST00, ADST10).
Figure 25.4-16 Bit configuration of the sampling time setting registers (ADST00, ADST10)
Sampling time setting registers 00 (ADST00)
bit
15
14
13
12
11
10
9
8
STX01
STX00
ST05
ST04
ST03
ST02
ST01
ST00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
0
0
Attribute
Initial value
Sampling time setting registers 10 (ADST10)
bit
7
6
5
4
3
2
1
0
STX11
STX10
ST15
ST14
ST13
ST12
ST11
ST10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
0
0
Attribute
Initial value
R/W: Read/Write
<Notes>
•
Write to these registers while A/D conversion is stopped.
•
For details of the sampling time, see "■ A/D conversion time" in "25.6 Explanation of
Operations and Setting Procedure Examples".
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25.4
MB91665 Series
● Sampling time setting registers 00 (ADST00)
These registers set the first sampling time.
[bit15, bit14]: STX01, STX00 (Sampling time Nx setting bit)
These bits set a value (N) by which a value set in the ST05 to ST00 bits is multiplied.
STX01
STX00
Explanation
0
0
Multiplies the value by 1.
0
1
Multiplies the value by 4.
1
0
Multiplies the value by 8.
1
1
Multiplies the value by 16.
[bit13 to bit8]: ST05 to ST00 (Sampling time setting bit)
These bits set the value used to determine the sampling time.
A value that is set in these bits is used to determine the sampling time based on the following formula:
Sampling time = peripheral clock (PCLK) period × (ST + 1) × STX
ST: Value set in the ST05 to ST00 bits
STX: N (multiplier) set in the STX01 and STX00 bits
Example: ST05 to ST00 = 9, STX01, STX00 = 01 (multiply by 4), peripheral clock (PCLK) = 20 MHz
(50 ns)
Sampling time = 50 ns × (9 + 1) × 4 = 2 μs
<Notes>
732
•
If "00" (multiply the setting value by 1) is set in the STX01 and STX00 bits, set "3" or a higher
number in the ST05 to ST00 bits.
•
For details of the sampling time, see "■ A/D conversion time" in "25.6 Explanation of
Operations and Setting Procedure Examples".
•
Sampling time setting registers 00 (ADST00) must be set such that the sampling time in the
electrical characteristics is satisfied. For details of the electrical characteristics, see "Data
Sheet".
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
● Sampling time setting register 10 (ADST10)
These registers set the second sampling time.
[bit7, bit6]: STX11, STX10 (Sampling time Nx setting bit)
These bits set a value (N) by which a value set in the ST15 to ST10 bits is multiplied.
STX11
STX10
Explanation
0
0
Multiplies the value by 1.
0
1
Multiplies the value by 4.
1
0
Multiplies the value by 8.
1
1
Multiplies the value by 16.
[bit5 to bit0]: ST15 to ST10 (Sampling time setting bit)
These bits set the value used to determine the sampling time.
A value that is set in these bits is used to determine the sampling time based on the following formula:
Sampling time = peripheral clock (PCLK) period × (ST + 1) × STX
ST: Value set in the ST15 to ST10 bits
STX: N (multiplier) set in the STX11 and STX10 bits
Example: ST15 to ST10 = 9, STX11, STX10 = 01 (multiply by 4), peripheral clock (PCLK) = 20 MHz
(50 ns)
Sampling time = 50 ns × (9 + 1) × 4 = 2 μs
<Notes>
•
If "00" (multiply the setting value by 1) is set in the STX11 and STX10 bits, set "3" or a higher
number in the ST15 to ST10 bits.
•
For details of the sampling time, see "■ A/D conversion time" in "25.6 Explanation of
Operations and Setting Procedure Examples".
•
Sampling time setting registers 10 (ADST10) must be set such that the sampling time in the
electrical characteristics is satisfied. For details of the electrical characteristics, see "Data
Sheet".
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CHAPTER 25 10-Bit A/D Converter
25.4
25.4.14
MB91665 Series
Sampling Time Select Registers (ADSS20 to ADSS00)
These registers are used to select the A/D sampling time.
The sampling time to be used for each channel can be selected from that set in sampling time setting
registers 00 (ADST00) or that set in sampling time setting registers 10 (ADST10).
Figure 25.4-17 shows the bit configuration of the sampling time select registers (ADSS20 to ADSS00).
Figure 25.4-17 Bit configuration of the sampling time select registers (ADSS20 to ADSS00)
Sampling time select registers 20 (ADSS20)
bit
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Attribute
Initial value
Sampling time select registers 10 (ADSS10)
bit
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
TS11
TS10
TS9
TS8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
5
4
3
2
1
0
Attribute
Initial value
Sampling time select registers 00 (ADSS00)
bit
Attribute
Initial value
7
6
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
R/W: Read/Write
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (TS10, and TS11 are reserved bits because AN10 and AN11 are not
existed.)
<Notes>
734
•
Write to these registers while A/D conversion is stopped.
•
Always write "0" to the reserved bits.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
ADSS10 to ADSS00: TS11 to TS0 (Sampling time selection bits)
These bits specify for each channel whether to use the sampling time that is set in one of sampling time
setting registers 00 (ADST00) or sampling time setting registers 10 (ADST10).
Written Value
Explanation
0
Use a sampling time that is set in sampling time setting registers 00 (ADST00).
1
Use a sampling time that is set in sampling time setting registers 10 (ADST10).
The TS11 bit corresponds to ch.11 (AN11 pin), the TS10 bit corresponds to ch.10 (AN10 pin), ... the TS1
bit corresponds to ch.1 (AN1 pin), and the TS0 bit corresponds to ch.0 (AN0 pin).
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (TS10, and TS11 are reserved bits because AN10 and AN11 are not
existed.)
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CHAPTER 25 10-Bit A/D Converter
25.4
25.4.15
MB91665 Series
Compare Time Setting Registers (ADCT0)
These registers set the compare time in the A/D conversion time. The A/D conversion time is the total
of the sampling time and compare time.
Figure 25.4-18 shows the bit configuration of the compare time setting registers (ADCT0).
Figure 25.4-18 Bit configuration of the compare time setting registers (ADCT0)
bit
7
6
5
4
3
2
1
0
Undefined
Undefined
Undefined
Undefined
Undefined
CT2
CT1
CT0
Attribute
-
-
-
-
-
R/W
R/W
R/W
Initial value
X
X
X
X
X
1
1
1
R/W: Read/Write
-: Undefined
X: Undefined
<Note>
Write to this register while A/D conversion is stopped.
[bit7 to bit3]: Undefined bits
736
In case of writing
Ignored
In case of reading
A value is undefined.
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CHAPTER 25 10-Bit A/D Converter
25.4
MB91665 Series
[bit2 to bit0]: CT2 to CT0 (Compare time setting bits)
These bits set the value used to determine the compare time.
A value that is set in these bits is used to determine the compare time based on the following formula:
Compare time = { (CT + 1) × 10 + 4} × peripheral clock (PCLK) period
CT: Value set in these bits
Example: CT = 1, peripheral clock (PCLK) = 20 MHz (50 ns)
Compare time = {(1 + 1) × 10 + 4} × 50 ns = 1.2 μs
<Note>
For details of the compare time, see "■ A/D conversion time" in "25.6 Explanation of Operations
and Setting Procedure Examples",
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CHAPTER 25 10-Bit A/D Converter
25.5
MB91665 Series
25.5 Interrupts
An interrupt request can be generated in the following case(s):
• Data has been stored in the predetermined number of stages in the FIFO during A/D scan
conversion. (Scan conversion interrupt request)
• Data has been stored in the predetermined number of stages in the FIFO during A/D priority
conversion. (Priority conversion interrupt request)
• An attempt has been made to save the next conversion result to a full FIFO. (FIFO overrun interrupt
request)
• The conversion result satisfies the interrupt request generation conditions when the comparison
function is used. (Conversion result comparison interrupt request)
■ A/D scan conversion interrupt request
Table 25.5-1 outlines the interrupt requests of A/D scan conversion.
Table 25.5-1 Interrupt requests of A/D scan conversion
Interrupt Request
Interrupt Request
Flag
Interrupt Request
Enabled
Clearing of
Interrupt Request
Scan conversion
interrupt request
SCIF bit = 1 in an
ADCR
SCIE bit = 1 in an
ADCR
Write "0" to the SCIF
bit in the ADCR.
FIFO overrun
interrupt request
SOVR bit = 1 in an
SCCR
OVRIE bit = 1 in an
ADCR
Write "0" to the
SOVR bit in the
SCCR.
Conversion result
comparison interrupt
request
CMPIF bit = 1 in an
ADCR
CMPIE bit = 1 in an
ADCR
Write "0" to the
CMPIF bit in the
ADCR.
ADCR: A/DC control register (ADCR0)
SCCR: Scan conversion control register (SCCR0)
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CHAPTER 25 10-Bit A/D Converter
25.5
MB91665 Series
■ A/D priority conversion interrupt request
Table 25.5-2 outlines the interrupt requests of A/D priority conversion.
Table 25.5-2 Interrupt requests of A/D priority conversion
Interrupt Request
Interrupt Request
Flag
Interrupt Request
Enabled
Clearing of
Interrupt Request
Priority conversion
interrupt request
PCIF bit = 1 in an
ADCR
PCIE bit = 1 in an
ADCR
Write "0" to the PCIF
bit in the ADCR.
FIFO overrun
interrupt request
POVR bit = 1 in a
PCCR
OVRIE bit = 1 in an
ADCR
Write "0" to the
POVR bit in the
PCCR.
Conversion result
comparison interrupt
request
CMPIF bit = 1 in an
ADCR
CMPIE bit = 1 in an
ADCR
Write "0" to the
CMPIF bit in the
ADCR.
ADCR: A/DC control register (ADCR0)
PCCR: Priority conversion control register (PCCR0)
<Notes>
•
If generation of interrupt requests is enabled while the interrupt request flag is "1", an interrupt
request is generated at the same time.
Execute any of the following processing when enabling the generation of the interrupt requests:
- Clear interrupt requests before enabling the generation of interrupt requests.
- Clear interrupt requests simultaneously with interrupts enabled.
•
For the interrupt vector number of each interrupt request, see "APPENDIX C Interrupt Vectors".
•
Use the interrupt control registers (ICR00 to ICR47) to set the interrupt level corresponding to
the interrupt vector number. For details of the setting of interrupt levels, see "CHAPTER 10
Interrupt Controller".
■ Activating DMA transfer upon an interrupt
DMA transfer can be activated when one of the following interrupt requests is generated:
•
Scan conversion interrupt request
•
Priority conversion interrupt request
For details of DMA transfer, see "25.6.4 Activating the DMA Controller (DMAC)".
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
25.6 Explanation of Operations and Setting
Procedure Examples
This section explains the operations of the 10-bit A/D converter. Also, examples of procedures for
setting the operating state are shown.
■ Overview
The 10-bit A/D converter enables A/D conversion by allowing analog signal input from the pin
corresponding to each bit in the A/D channel enable register (ADCHE).
For details of the A/D channel enable register (ADCHE), see "14.4.6 A/D Channel Enable Register
(ADCHE)" in "CHAPTER 14 I/O Ports".
The 10-bit A/D converter performs the following two types of conversion:
•
A/D scan conversion
Any selected channel is converted.
Two conversion modes are available. One is single conversion mode in which the signals from the
selected channel are converted only once, and the other is repeat conversion mode in which the signals
from the selected channel are converted repeatedly.
•
A/D priority conversion
High-priority A/D conversion is performed soon after an activation trigger for the conversion is
generated, because the trigger stops A/D scan conversion. The two priority levels are priority 1 and
priority 2. Priority 1 > priority 2.
Table 25.6-1 summarizes the differences between A/D scan conversion and A/D priority conversion.
Table 25.6-1 Differences between A/D scan conversion and A/D priority conversion
A/D Scan Conversion
A/D Priority Conversion
Priority 1
Priority 2
Supported
channels
Up to 11 channels are
selected arbitrarily from
all 11 channels.
1 channel is selected
from ch.0 to ch.7
1 channel is selected
from the 11 channels.
Conversion
activation
trigger
Software
Detection of a rising
edge of the TOUT signal
of base timer ch.0
Detection of a falling
edge at the ADTRG0
pin
Software
Detection of a rising
edge of the TOUT
signal of base timer
ch.2
Restart
Enabled
Disabled
FIFO
16 levels
4 levels
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (AN10 and AN11 are not existed.)
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
■ Priority and state transition
Table 25.6-2 lists A/D conversion priorities.
Table 25.6-2 A/D conversion priority
Priority
A/D Conversion Type
1
A/D priority conversion of priority 1
2
A/D priority conversion of priority 2
3
A/D scan conversion
If A/D conversion of a different priority is activated while A/D conversion is already in progress,
operations are performed as follows:
•
The A/D conversion activated while A/D conversion is already in progress has a higher priority.
The A/D conversion in progress is stopped and the A/D conversion of the higher priority is executed.
After the higher-priority conversion is completed, the stopped A/D conversion is restarted.
Example: An A/D priority conversion activation trigger is generated during A/D scan conversion
The A/D scan conversion is interrupted, and A/D priority conversion begins. After the A/D
priority conversion is completed, the A/D scan conversion resumes from the channel at which it
interrupted.
Example: An activation trigger for A/D priority conversion of priority 1 is generated during A/D
priority conversion of priority 2.
The A/D priority conversion of priority 2 is interrupted, and the A/D priority conversion of priority
1 begins. After the A/D priority conversion of priority 1 is completed, the A/D priority conversion
of priority 2 resumes.
•
The A/D conversion activated while A/D conversion is already in progress has a lower priority.
The activation trigger for the A/D conversion of a lower priority is held, and the A/D conversion in
progress is executed continuously.
After the A/D conversion in progress is completed, the A/D conversion whose activation trigger has
been held begins automatically.
Example: An activation trigger for A/D priority conversion of priority 2 is generated during A/D
priority conversion of priority 1.
The activation trigger for the A/D priority conversion of priority 2 is held, and the A/D priority
conversion of priority 1 is executed continuously.
After the A/D priority conversion of priority 1 is completed, the A/D priority conversion of
priority 2 begins automatically.
Example: An activation trigger for A/D scan conversion is generated during A/D priority
conversion of priority 1.
The activation trigger for the A/D scan conversion is held, and the A/D priority conversion of
priority 1 is executed continuously.
After the A/D priority conversion of priority 1 is completed, the A/D scan conversion begins
automatically.
Example: An activation trigger for A/D scan conversion is generated during A/D priority
conversion of priority 2.
The activation trigger for the A/D scan conversion is held, and the A/D priority conversion of
priority 2 is executed continuously.
After the A/D priority conversion of priority 2 is completed, the A/D scan conversion begins
automatically.
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CHAPTER 25 10-Bit A/D Converter
25.6
•
MB91665 Series
The A/D conversion activated during A/D priority conversion has the same priority.
An activation trigger with the same priority is ignored. (The ignored activation trigger will not be
reactivated.)
Figure 25.6-1 show state transitions of the 10-bit A/D converter.
Figure 25.6-1 State transitions of the 10-bit A/D converter
000
Waiting for conversion
Scan conversion request
End of scan conversion
001
A/D scan conversion
in progress
Priority conversion request
End of priority conversion
A/D priority conversion
in progress
Scan conversion request
Priority conversion request
End of priority conversion
010
011
A/D priority conversion in
progress
A/D scan conversion
suspended
End of priority 1
conversion
End of priority 1
conversion
110
Priority 1 conversion in
progress
Priority 2 conversion
suspended
Priority
conversion
request
111
Priority 1 conversion in progress
Priority 2 conversion suspended
A/D scan conversion suspended
Priority
conversion
request
Scan conversion
request
As shown in Figure 25.6-1, the states of the 10-bit A/D converter can be checked with the PCNS, PCS,
and SCS bits in the A/DC status registers (ADSR0).
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
Table 25.6-3 shows the relationship between bits and operating states.
Table 25.6-3 Relationship between bits and operating states
PCNS
PCS
SCS
Explanation
0
0
0
Waiting for conversion
0
0
1
A/D scan conversion in progress
0
1
0
A/D priority conversion in progress
0
1
1
A/D priority conversion in progress, with A/D scan
conversion suspended
1
1
0
Priority 1 A/D priority conversion in progress, with priority
2 conversion suspended
1
1
1
Priority 1 A/D priority conversion in progress, with priority
2 conversion and scan conversion suspended
■ Operation using the A/D comparison function
The A/D comparison function compares the eight high-order bits (bit9 to bit2) of A/D conversion results
with a preset value in the A/D comparison data setting registers (CMPD0). If the comparison result
satisfies the requirements set in an A/D comparison control register (CMPCR0), the function generates a
conversion result comparison interrupt request.
The CMPEN bit must be set to "1" in the A/D comparison control register (CMPCR0) to enable the
comparison function before conversion is started.
The comparison function can be used even with a full FIFO because a comparison is made before A/D
conversion results are stored in the FIFO.
For details of the comparison function, see "25.4.11 A/D Comparison Data Setting Registers (CMPD0)",
and "25.4.12 A/D Comparison Control Registers (CMPCR0)".
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CHAPTER 25 10-Bit A/D Converter
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MB91665 Series
■ A/D conversion time
The A/D conversion time is the total of the sampling time and compare time.
To determine the A/D conversion time, add the sampling time and compare time.
● Sampling time
The sampling time can be set in each of the sampling time setting registers (ADST00, ADST10).
The sampling time select register (ADSS20 to ADSS00) can be used to specify the register that has the
set sampling time to be used for each channel. Therefore, the sampling time can be set individually for
channels with different external impedances.
The formula for calculating the sampling time is as follows:
Sampling time = peripheral clock (PCLK) period × (ST + 1) × STX
ST:
Value that is set in the ST05 to ST00/ST15 to ST10 bits in a sampling time setting
register (ADST00, ADST10)
STX: Multiplier that is set in the STX01, STX00/STX11, and STX10 bits in a sampling
time setting register (ADST00, ADST10)
<Notes>
744
•
If "00" (multiply the setting value by 1) is set in the STX01 and STX00 bits, set "3" or a higher
number in the ST05 to ST00/ST15 to ST10 bits.
•
Sampling time setting registers 00 (ADST00) must be set so that the sampling time in the
electrical characteristics is satisfied. For details of the electrical characteristics, see "Data
Sheet".
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
Table 25.6-4 and Table 25.6-5 show sampling time setting examples.
Table 25.6-4 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 00)
(1 / 2)
Register value (N)
CM71-10158-1E
Sampling Time [µs]
STx5 to STx0
PCLK=30MHz
PCLK=32MHz
PCLK=33MHz
0
Setting prohibited
Setting prohibited
Setting prohibited
1
Setting prohibited
Setting prohibited
Setting prohibited
2
Setting prohibited
Setting prohibited
Setting prohibited
3
Setting prohibited
Setting prohibited
Setting prohibited
4
Setting prohibited
Setting prohibited
Setting prohibited
5
Setting prohibited
Setting prohibited
Setting prohibited
6
Setting prohibited
Setting prohibited
Setting prohibited
7
Setting prohibited
Setting prohibited
Setting prohibited
8
Setting prohibited
Setting prohibited
Setting prohibited
9
Setting prohibited
Setting prohibited
Setting prohibited
10
Setting prohibited
Setting prohibited
Setting prohibited
11
0.400
Setting prohibited
Setting prohibited
12
0.433
0.406
Setting prohibited
13
0.467
0.438
0.424
14
0.500
0.469
0.455
15
0.533
0.500
0.485
16
0.567
0.531
0.515
17
0.600
0.563
0.545
18
0.633
0.594
0.576
19
0.667
0.625
0.606
20
0.700
0.656
0.636
...
...
...
...
36
1.233
1.156
1.121
37
1.267
1.188
1.152
38
1.300
1.219
1.182
...
...
...
...
42
1.433
1.344
1.303
43
1.467
1.375
1.333
...
...
...
...
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
Table 25.6-4 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 00)
(2 / 2)
Register value (N)
STx5 to STx0
Sampling Time [µs]
PCLK=30MHz
PCLK=32MHz
PCLK=33MHz
52
1.767
1.656
1.606
53
1.800
1.688
1.636
...
...
...
...
62
2.100
1.969
1.909
63
2.133
2.000
1.939
PCLK : peripheral clock (PCLK) frequency
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MB91665 Series
Table 25.6-5 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 10)
(1 / 2)
Register Value (N)
STx5 to STx0
PCLK=30MHz
PCLK=32MHz
PCLK=33MHz
0
Setting prohibited
Setting prohibited
Setting prohibited
1
0.533
0.500
0.485
2
0.800
0.750
0.727
3
1.067
1.000
0.970
4
1.333
1.250
1.212
5
1.600
1.500
1.455
6
1.867
1.750
1.697
7
2.133
2.000
1.939
8
2.400
2.250
2.182
9
2.667
2.500
2.424
10
2.933
2.750
2.667
11
3.200
3.000
2.909
12
3.467
3.250
3.152
13
3.733
3.500
3.394
14
4.000
3.750
3.636
15
4.267
4.000
3.879
16
4.533
4.250
4.121
17
4.800
4.500
4.364
18
5.067
4.750
4.606
19
5.333
5.000
4.848
20
5.600
5.250
5.091
...
...
...
...
36
9.867
9.250
8.970
37
10.133
9.500
9.212
38
10.400
9.750
9.455
...
...
...
...
42
11.467
10.750
10.424
43
11.733
11.000
10.667
...
52
CM71-10158-1E
Sampling Time [µs]
...
14.133
FUJITSU SEMICONDUCTOR LIMITED
...
13.250
...
12.848
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25.6
MB91665 Series
Table 25.6-5 Sampling time setting examples (for STX01, STX00/STX11, STX10 bits = 10)
(2 / 2)
Register Value (N)
Sampling Time [µs]
STx5 to STx0
PCLK=30MHz
PCLK=32MHz
PCLK=33MHz
53
14.400
13.500
13.091
...
...
...
...
62
16.800
15.750
15.273
63
17.067
16.000
15.515
PCLK : peripheral clock (PCLK) frequency
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● Compare time
The compare time setting registers (ADCT0) specify the compare time.
The formula for calculating the compare time is as follows:
Compare time = { (CT + 1) × 10 + 4} × peripheral clock (PCLK) period
CT: Value that is set in the CT2 to CT0 bits in a compare time setting register (ADCT0)
Table 25.6-6 shows a compare time setting example.
Table 25.6-6 Compare time setting example
Register Value (N)
CT2 to CT0
Compare Time
PCLK = 30 MHz
PCLK = 32 MHz
PCLK = 33 MHz
0
Setting prohibited
Setting prohibited
Setting prohibited
1
0.80 μs
0.75 μs
0.73 μs
2
1.13 μs
1.06 μs
1.03 μs
3
1.47 μs
1.38 μs
1.33 μs
4
1.80 μs
1.69 μs
1.64 μs
5
2.13 μs
2.00 μs
1.94 μs
6
2.47 μs
2.31 μs
2.24 μs
7 (initial value)
2.80 μs
2.63 μs
2.55 μs
PCLK peripheral clock (PCLK) frequency
* This table covers only compare time data.
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25.6
25.6.1
MB91665 Series
Operation of A/D Scan Conversion
Channels are selected by the scan conversion input select registers (SCIS20 to SCIS00) sequentially.
■ Overview
A/D scan conversion is performed in one of the following two conversion modes:
•
Single conversion mode
The channel specified by a scan conversion input select register (SCIS20 to SCIS00) is converted only
once.
•
Repeat conversion mode
The channel specified by a scan conversion input select register (SCIS20 to SCIS00) is converted
repeatedly.
Also, the operation that is performed varies depending on whether only one channel is selected or
multiple channels are selected with a scan conversion input select register (SCIS20 to SCIS00).
Table 25.6-7 shows the order of conversion in each conversion mode.
Table 25.6-7 Conversion mode and order of conversion
Conversion Mode
Selected Channel
Conversion Order
Single conversion mode
(RPT bit = 0 in an SCCR)
ch.3
ch.3 →conversion stopped
ch.3, ch.5, ch.10
ch.3 → ch.5 → ch.10 →
conversion stopped
Repeat conversion mode
(RPT bit = 1 in an SCCR)
ch.3
ch.3 → ch.3 → ch.3 → ch.3
↑
↓
ch.3 ← ch.3 ← ch.3 ← ch.3
ch.3, ch.5, ch.10
ch.3 → ch.5 → ch.10
↑
↓
ch.10 ← ch.5 ← ch.3
SCCR: scan conversion control register (SCCR0)
<Note>
The 10-bit A/D converter enables A/D conversion by allowing analog signal input with the A/D
channel enable register (ADCHE).
For details of the A/D channel enable register (ADCHE), see "14.4.6 A/D Channel Enable Register
(ADCHE)" in "CHAPTER 14 I/O Ports".
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25.6
MB91665 Series
■ Operation in single conversion mode
Writing "0" to the RPT bit in a scan conversion control register (SCCR0) sets single conversion mode.
In this mode, the channel specified by a scan conversion input select register (SCIS20 to SCIS00) is
converted only once.
● Activation
The channel to be converted is selected with the scan conversion input select register (SCIS20 to SCIS00)
in one of the following ways, and the 10-bit A/D converter is then activated:
•
Write "1" to the SSTR bit in a scan conversion control register (SCCR0).
•
Set the SHEN bit in a scan conversion control register (SCCR0) to enable timer activation (SHEN = 1),
and input the rising edge of a TOUT signal of base timer ch.0.
If either of the above activation operations is performed during A/D scan conversion, the A/D scan
conversion is immediately stopped/initialized, and the A/D scan conversion resumes later (reactivated).
● Single-channel conversion
Only one channel to be converted is selected with a scan conversion input select register (SCIS20 to
SCIS00).
When started, the 10-bit A/D converter activates the conversion operation for the selected channel, and
the SCS bit in an A/DC status register (ADSR0) changes to "1".
After the conversion of the selected channel is completed, the conversion result and information on the
converted channel are stored in the first level of the A/D scan conversion FIFO, and the conversion
operation is then stopped. Then, the SCS bit in the A/DC status register (ADSR0) is cleared to "0".
The conversion results stored in the FIFO can be read from a scan conversion FIFO data register
(SCFD0).
● Multichannel conversion
Two or more channels to be converted are selected with a scan conversion input select register (SCIS20 to
SCIS00).
When started, the 10-bit A/D converter begins converting the selected channels in ascending order of
channel number. The SCS bit in an A/DC status register (ADSR0) then changes to "1".
After the conversion of one channel is completed, the conversion results and information on the converted
channel are stored in the first level of the A/D scan conversion FIFO, and the converter then begins
converting the next channel.
The channels not selected by the scan conversion input select register (SCIS20 to SCIS00) remain
unconverted.
In the A/D scan conversion FIFO, the number of stages storing conversion results and information on
each converted channel is changed every time the channel subject to conversion changes.
The 10-bit A/D converter stops operating after converting on all the channels selected by the scan
conversion input select register (SCIS20 to SCIS00). Then, the SCS bit in the A/DC status register
(ADSR0) is cleared to "0".
The conversion results stored in the FIFO can be read sequentially from a scan conversion FIFO data
register (SCFD0). For details of reading, see "■ Operation of A/D scan conversion" in "25.6.3 FIFO
Operations".
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
■ Operation in repeat conversion mode
Writing "1" to the RPT bit in a scan conversion control register (SCCR0) enables single conversion mode.
In this mode, the channel specified by a scan conversion input select register (SCIS20 to SCIS00) is
converted repeatedly.
As in single conversion mode, to activate the 10-bit A/D converter, select a channel.
● Single-channel conversion
Only one channel to be converted is selected with a scan conversion input select register (SCIS20 to
SCIS00).
When started, the 10-bit A/D converter activates the conversion operation for the selected channel, and
the SCS bit in an A/DC status register (ADSR0) changes to "1".
After the conversion of the selected channel is completed, the conversion results and information on the
converted channel are stored in the first level of the A/D scan conversion FIFO, and conversion of the
same channel is then repeated.
To stop conversion, write "0" to a scan conversion control register (SCCR0).
The conversion results stored in the FIFO can be read sequentially from a scan conversion FIFO data
register (SCFD0). For details of reading conversion results, see "■ Operation of A/D scan conversion" in
"25.6.3 FIFO Operations".
● Multichannel conversion
Two or more channels to be converted are selected with a scan conversion input select register (SCIS20 to
SCIS00).
When activated, the 10-bit A/D converter begins converting on the selected channels sequentially in
ascending order of channel number. The SCS bit in an A/DC status register (ADSR0) then changes to "1".
After the conversion of one channel is completed, the conversion results and information on the converted
channel are stored in the first level of the A/D scan conversion FIFO, and the converter then begins
converting the next channel.
The channels not selected by the scan conversion input select register (SCIS20 to SCIS00) remain
unconverted.
After conversion of all the selected channels is completed, the second round of conversion begins for the
channels sequentially in ascending order of channel number.
To stop conversion, write "0" in the RPT bit of the scan conversion control register (SCCR0).
Conversion stops when all channels selected by the scan conversion input select register (SCIS20 to
SCIS00) have been converted.
Figure 25.6-2 shows the stop timing in multichannel conversion.
Figure 25.6-2 Stop timing in multichannel conversion
RPT bit
SSTR bit
Conversion
channel
Stop
ch.0
ch.4
ch.8
ch.10
ch.0
ch.4
ch.8
ch.10
Stop
The conversion results stored in the FIFO can be read sequentially from a scan conversion FIFO data
register (SCFD0). For details of reading, see "■ Operation of A/D scan conversion" in "25.6.3 FIFO
Operations".
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
25.6.2
Operation of A/D Priority Conversion
High-priority A/D conversion is performed soon after an activation trigger for the conversion is
generated, because the trigger stops A/D scan conversion. There are two priority levels.
■ Overview
Two priority levels can be selected depending on the activation trigger. Priority 1 has a higher priority
than priority 2.
The channels that can be set vary depending on the priority.
Table 25.6-8 shows the relationship among priorities, channels, and activation triggers.
Table 25.6-8 Relationship among, priorities, channels, and activation triggers
Priority 1
Priority 2
Priority
1
2
Supported channel
1 channel is selected from ch.0 to ch.7
1 channel is selected from the 11
channels.
Activation trigger
Detection of a falling edge at the
ADTRG0 pin
Software
Detection of a rising edge of the TOUT
signal of base timer ch.2
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (AN10 and AN11 are not existed.)
<Notes>
•
The 10-bit A/D converter enables A/D conversion by allowing analog signal input with the A/D
channel enable register (ADCHE).
For details of the A/D channel enable register (ADCHE), see "14.4.6 A/D Channel Enable
Register (ADCHE)" in "CHAPTER 14 I/O Ports".
•
A/D conversion can be reactivated regardless of priority after A/D priority conversion.
•
Only one channel can be converted in A/D priority conversion.
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CHAPTER 25 10-Bit A/D Converter
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■ Conversion with priority 1
This conversion has the highest priority. When an activation trigger with priority 1 is generated, any A/D
scan conversion or A/D priority conversion that is in progress is immediately stopped, and the conversion
with priority 1 begins.
● Selecting a channel
Only one channel is selected from ch.0 to ch.7 and set in the P1A2 to P1A0 bits in a priority conversion
input select register (PCIS0).
● Conversion
An activation trigger for A/D priority conversion of priority 1 is generated when a falling edge is detected
at the ADTRG0 pin after the PEEN bit in a priority conversion control register (PCCR0) is set to "1" to
enable external activation.
If A/D scan conversion or A/D priority conversion of priority 2 is in progress, it is immediately
interrupted, and conversion of the specified channel with priority 1 begins. The PCS bit in an A/DC
status register (ADSR0) then changes to "1".
After the conversion is completed, the conversion results and information on the channel subject to
conversion are stored in the FIFO for A/D priority conversion, and the PCS bit in the A/DC status register
(ADSR0) is cleared to "0". The interrupted conversion is then restarted.
The A/D priority conversion results stored in the FIFO can be read from a priority conversion FIFO data
register (PCFD0). For details of reading, see "■ Operation of A/D priority conversion" in "25.6.3 FIFO
Operations".
For details of the operation performed when an activation trigger with a different priority is generated
while A/D priority conversion of priority 1 is in progress, see "■ Priority and state transition in "25.6
Explanation of Operations and Setting Procedure Examples".
<Note>
If an activation trigger for A/D conversion of the same level (priority 1) is generated while A/D
priority conversion of priority 1 is in progress, the conversion in progress is continued and the new
activation trigger is ignored.
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CHAPTER 25 10-Bit A/D Converter
25.6
■ Conversion with priority 2
This conversion has the second highest priority. When an activation trigger of priority 2 is generated, any
A/D scan conversion in progress is immediately stopped, and the conversion with priority 2 begins.
● Selecting a channel
Only one channel to be converted is selected from all 11 channels and set in the P2A4 to P2A0 bits in a
priority conversion input select register (PCIS0).
* MB91F669 (64 pins): AN0 to AN11
MB91F668 (48 pins): AN0 to AN9 (AN10 and AN11 are not existed.)
● Conversion
An activation trigger with priority 2 is generated in one of the following ways:
•
Write "1" to the PSTR bit in a priority conversion control register (PCCR0).
•
A rising edge of the TOUT signal of base timer ch.2 is detected after the PHEN bit in the priority
conversion control register (PCCR0) is set to "1" to enable timer activation.
When an activation trigger is generated, A/D priority conversion of priority 2 is activated and the PCS bit
in an A/DC status register (ADSR0) changes to "1" as follows:
•
If the 10-bit A/D converter is not activated: The 10-bit A/D converter is activated to start conversion of
the specified channel with priority 2.
•
If A/D scan conversion is in progress: The A/D scan conversion in progress is immediately interrupted,
and conversion of the specified channel with priority 2 begins.
•
If A/D priority conversion of priority 1 is in progress: The activation trigger with priority 2 is held, and
A/D priority conversion of priority 2 is started after A/D priority conversion of priority 1 is completed.
After A/D priority conversion of priority 2 is completed, the conversion results and information on the
channel subject to conversion are stored in the FIFO for A/D priority conversion, and the PCS bit in an
A/DC status register (ADSR0) is cleared to "0". The interrupted conversion is then restarted.
The A/D priority conversion results stored in the FIFO can be read from a priority conversion FIFO data
register (PCFD0). For details of reading, see "■ Operation of A/D priority conversion" in "25.6.3 FIFO
Operations".
For details of the operation performed when an activation trigger with a different priority is generated
while A/D priority conversion of priority 2 is in progress, see "■Priority and state transition in "25.6
Explanation of Operations and Setting Procedure Examples".
<Note>
No conversion operation can be reactivated during A/D priority conversion. If an activation trigger
for A/D conversion of the same level (priority 2) is generated while A/D priority conversion of priority
2 is in progress, the conversion in progress is continued and the new activation trigger is ignored.
Example: The rising edge of a TOUT signal of base timer ch.2 may be detected after A/D
priority conversion of priority 2 is activated by software. Even in this event, the
conversion operation in progress is continued.
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CHAPTER 25 10-Bit A/D Converter
25.6
25.6.3
MB91665 Series
FIFO Operations
The 10-bit A/D converter provides 16 FIFO stages for A/D scan conversion and 4 FIFO levels for A/D
priority conversion. A scan conversion interrupt request/priority conversion interrupt request can be
generated when the number of stages storing the respective data reaches the predetermined number
of FIFO stages.
This section explains FIFO operations and generation of interrupt requests.
■ Operation of A/D scan conversion
● Operation during A/D conversion
The SEMP bit in a scan conversion control register (SCCR0) is "1", because the FIFO for A/D scan
conversion contains no data (empty) after a reset is released.
The SEMP bit changes to "0" when A/D scan conversion begins, and conversion results for 1 channel are
stored in the first FIFO stage.
After conversion of the next data is completed, the conversion results are stored in the second FIFO stage.
Every time that conversion of 1 channel is completed after that, the conversion results are stored in the
subsequent FIFO stage.
After conversion results are written to all 16 FIFO levels, the A/D scan conversion FIFO becomes full
and the SFUL bit in the scan conversion control register (SCCR0) changes to "1".
If A/D scan conversion is performed again in this state, an overrun occurs and the SOVR bit in the scan
conversion control register (SCCR0) changes to "1". In this event, the conversion results are not stored in
the FIFO but abandoned.
● Read operation
Data stored in the A/D scan conversion FIFO can be read sequentially through reading with a scan
conversion FIFO data register (SCFD0).
A scan conversion FIFO data register (SCFD0) must always be read after the SEMP bit in a scan
conversion control register (SCCR0) is checked to determine whether data remains in the A/D scan
conversion FIFO (SEMP = 0).
If an empty A/D scan conversion FIFO is read (SEMP = 1), it is difficult to determine whether the read
data is valid, and valid data may be abandoned. (This is because conversion results may be stored in a
scan conversion FIFO data register (SCFD0) immediately before the FIFO is read.)
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25.6
MB91665 Series
Figure 25.6-3 shows the relationship between the SEMP bit and read data.
Figure 25.6-3 Relationship between the SEMP bit and read data
SEMP bit
Peripheral bus
Valid FIFO stage
number
SEMP bit
reading
SCFD
reading
It is possible to determine
that the read data is valid
because the value read from
the previous SEMP bit is "0".
1
SEMP bit
reading
0
SCFD
reading
1
It is impossible to determine
whether the read data is valid
because the value read from
the previous SEMP bit is "1".
0
New FIFO data is stored.
SCFD: A/D scan conversion FIFO data register (SCFD0)
<Notes>
•
The registers listed below are located at adjacent addresses. If these registers are accessed at
one time by word access, the registers are read regardless of the setting of the SEMP bit in a
scan conversion control register (SCCR0). Do not execute word access to these registers.
- Scan conversion control register (SCCR0)
- Scan conversion FIFO number setting register (SFNS0)
- Scan conversion FIFO data register (SCFD0)
•
The scan conversion FIFO data registers (SCFD0) can be byte-accessed. FIFO data is shifted
after the high-order byte (bit15 to bit8) is read. FIFO data will not be shifted by reading of the
lower-order byte (bit7 to bit0).
● Clear operation
Writing "1" to the SFCLR bit in a scan conversion control register (SCCR0) clears the FIFO for A/D
scanning conversion and changes the SEMP bit in the scan conversion control register (SCCR0) to "1".
● Scan conversion interrupt request
A scan conversion interrupt request can be generated when the number of stages storing conversion
results reaches the specified number of FIFO stages (SCIF bit = 1 in an A/DC control register (ADCR0)).
To generate an A/D scan conversion interrupt request, perform the following processing:
•
Decide the number of FIFO stages at which an interrupt request is generated, and set the number in the
SFS3 to SFS0 bits in a scan conversion FIFO number setting register (SFNS0).
•
Set the SCIE bit in an A/DC control register (ADCR0) to "1" to enable generation of scan conversion
interrupt requests.
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
Figure 25.6-4 shows FIFO operations.
Figure 25.6-4 FIFO operations
Valid FIFO stage number
FIFO stage number
setting
SFS3 to SFS0 = 0101 (6 stages)
SFS3 to SFS0 = 0011
(4 stages)
Interrupt request
clearing
Scan conversion
interrupt request
Interrupt request
clearing
FIFO reading
A/D conversion
Stop
1 2 3 4 5 6
Stop
1 2 3 4 5 6
Stop
1
Stop
The interrupt request generation examples shown below indicate the number of FIFO stages that is set for
each conversion mode. The number of FIFO stages must be set in the SFS3 to SFS0 bits in a scan
conversion FIFO number setting register (SFNS0).
•
Single channel conversion in single conversion mode
If the number of FIFO stages at which a scan conversion interrupt request is generated is set at 1
(SFS3 to SFS0 = 0000), a scan conversion interrupt request is generated when conversion is
completed. If the number of FIFO stages is set at 2 or more (SFS3 to SFS0 = 0001 or higher), an
interrupt request is not generated even after conversion of the specified channel is completed.
•
Multichannel conversion in single conversion mode
If the set number of FIFO stages is the same as the number of channels to be subject to conversion, a
scan conversion interrupt request is generated at the end of conversion.
Example: Generation of a scan conversion interrupt request after conversion of 3 channels
Set 3 (SFS3 to SFS0 = 0010) for the number of FIFO stages at which a scan conversion interrupt
request is generated.
Settings can be made such that a scan conversion interrupt request is generated at a number of FIFO
stages that is less than the number of the channels to be subject to conversion. In such cases, a scan
conversion interrupt request can be generated at any time before the end of A/D scan conversion.
•
Single channel conversion in repeat conversion mode
If the number of FIFO stages at which a scan conversion interrupt request is generated is set at 1
(SFS3 to SFS0 = 0000), a scan conversion interrupt request is generated when the first round of
conversion is completed.
To generate a scan conversion interrupt request after converting on the specified channel a certain
number of times, match the conversion count to the number of FIFO stages.
Example: Generation of a scan conversion interrupt request after conversion on a single channel
is performed 4 times
Set 4 (SFS3 to SFS0 = 0011) for the number of FIFO stages at which a scan conversion interrupt
request is generated.
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
•
Multichannel conversion in repeat conversion mode
The desired generation time for scan conversion interrupt requests can be selected as shown below.
Example: Conversion of 8 channels in repeat conversion mode
-
Generate a scan conversion interrupt request after the end of the first round of conversion.
Set 8 (SFS3 to SFS0 = 0111) for the number of FIFO stages at which a scan conversion interrupt
request is generated.
-
Generate an interrupt request after the end of the second round of conversion.
Set 16 (twice the number of channels to be subject to conversion) (SFS3 to SFS0 = 1111) for the
number of FIFO stages at which a scan conversion interrupt request is generated.
<Note>
DMA transfer of the data in the FIFO can be performed when a scan conversion interrupt request is
generated. For details of DMA transfer, see "25.6.4 Activating the DMA Controller (DMAC)".
● FIFO overrun interrupt request
When data has been stored in all 16 FIFO levels and the FIFO becomes full, the SFUL bit in a scan
conversion control register (SCCR0) changes to "1".
Also, the OVRIE bit in an A/DC control register (ADCR0) can be set to enable generation of FIFO
overrun interrupt requests (OVRIE = 1). In this state, if an attempt is made to store the next conversion
result in the FIFO when the SFUL bit is "1", an overrun interrupt is generated.
<Notes>
•
The data in the FIFO cannot be rewritten, even by the attempt to store the next conversion
result in the full FIFO. The conversion result to be stored in this attempt is abandoned.
•
The FIFO is emptied and the SEMP bit in a scan conversion control register (SCCR0) changes
to "1" when the SFCLR bit in the scan conversion control register (SCCR0) is set to "1" to clear
the FIFO.
■ Operation of A/D priority conversion
● Operation during A/D conversion
The PEMP bit in an A/D priority conversion control register (PCCR0) is "1", because the FIFO for A/D
scan conversion contains no data (empty) after a reset is released.
The PEMP bit changes to "0" when A/D priority conversion begins, and conversion results for 1 channel
are stored in the first FIFO stage.
After the next A/D priority conversion is completed, the conversion results are stored in the second FIFO
level. Every time that A/D priority conversion is completed after that, the conversion results are stored in
the subsequent FIFO stage.
After conversion results are written to all 4 FIFO levels, the FIFO for A/D priority conversion becomes
full and the PFUL bit in the priority conversion control register (PCCR0) changes to "1".
If A/D priority conversion is performed again in this state, an overrun occurs and the POVR bit in the
priority conversion control register (PCCR0) changes to "1". In this event, the conversion results are not
stored in the FIFO but abandoned.
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
● Read operation
Data stored in the A/D priority conversion FIFO can be read sequentially through reading with a priority
conversion FIFO data register (PCFD0).
A priority conversion FIFO data register (PCFD0) must always be read after the PEMP bit in a priority
conversion control register (PCCR0) is checked to determine whether data remains in the A/D priority
conversion FIFO (PEMP = 0).
If an empty A/D priority conversion FIFO is read (PEMP = 1), it is difficult to determine whether the read
data is valid, and valid data may be abandoned. (This is because conversion results may be stored in a
priority conversion FIFO data register (PCFD0) immediately before the FIFO is read.)
Figure 25.6-5 shows the relationship between the PEMP bit and read data.
Figure 25.6-5 Relationship between the PEMP bit and read data
PEMP bit
Peripheral bus
Valid FIFO stage
number
PEMP bit
reading
PCFD
reading
It is possible to determine
that the read data is valid
because the value read from
the previous PEMP bit is "0".
1
PEMP bit
reading
0
PCFD
reading
1
It is impossible to determine
whether the read data is valid
because the value read from
the previous PEMP bit is "1".
0
New FIFO data is stored.
PCFD: A/D priority conversion FIFO data register (PCFD0)
<Notes>
•
The registers listed below are located at adjacent addresses. If these registers are accessed at
one time by word access, the registers are read regardless of the setting of the PEMP bit in a
priority conversion control register (PCCR0). Do not execute word access to these registers.
- Priority conversion control register (PCCR0)
- Priority conversion FIFO number setting register (PFNS0)
- Priority conversion FIFO data register (PCFD0)
•
760
The priority conversion FIFO data registers (PCFD0) can be byte accessed. FIFO data is
shifted after the high-order byte (bit15 to bit8) is read. FIFO data will not be shifted by reading
of the low-order byte (bit7 to bit0).
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
● Clear operation
Writing "1" to the PFCLR bit in a priority conversion control register (PCCR0) clears the A/D priority
conversion FIFO and changes the PEMP bit in an A/D priority conversion control register (PCCR0).
● Priority conversion interrupt request
A priority conversion interrupt request can be generated when the number of stages storing conversion
results reaches the specified number of FIFO stages (PCIF bit = 1 in an A/DC control register (ADCR0)).
To generate an A/D priority conversion interrupt request, perform the following processing:
•
Decide the number of FIFO stages at which an interrupt request is generated, and set the number in the
PFS1 and PFS0 bits in the priority conversion FIFO number setting register (PFNS0).
•
Set the PCIE bit in the A/DC control register (ADCR0) to "1" to enable generation of priority
conversion interrupt requests.
If the number of FIFO stages at which a priority conversion interrupt request is generated is set to "1"
(PFS1, PFS0 = 00), a priority conversion interrupt request is generated when the conversion is completed.
<Notes>
•
If the number of FIFO stages at which a priority interrupt request is generated is set at 2 or more
(PFS1, PFS0 = 01 or higher), no priority conversion interrupt request is generated even after A/
D priority conversion is completed.
•
DMA transfer of the data in the FIFO can be performed when a priority conversion interrupt
request is generated. For details of DMA transfer, see "25.6.4 Activating the DMA Controller
(DMAC)".
● FIFO overrun interrupt request
The PFUL bit in a priority conversion control register (PCCR0) changes to "1" when data has been stored
in all of 4 FIFO levels and the FIFO becomes full.
Also, the OVRIE bit in an A/DC control register (ADCR0) can be set to enable generation of FIFO
overrun interrupt requests (OVRIE = 1). In this state, if an attempt is made to store the next conversion
result in FIFO when the PFUL bit is "1", an overrun interrupt is generated.
<Notes>
•
The data in the FIFO cannot be rewritten, even by the attempt to store the next conversion
result in the full FIFO. The conversion result to be stored in this attempt is abandoned.
•
The FIFO is emptied and the PEMP bit in a priority conversion control register (PCCR0)
changes to "1" when the PFCLR bit in the priority conversion control register (PCCR0) is set to
"1" to clear the FIFO.
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CHAPTER 25 10-Bit A/D Converter
25.6
25.6.4
MB91665 Series
Activating the DMA Controller (DMAC)
DMA transfer of FIFO data is possible through scan conversion interrupt requests and priority
conversion interrupt requests generated by the 10-bit A/D converter.
If the same value is set for the number of FIFO stages at which a scan conversion interrupt request/
priority conversion interrupt request is generated and the byte number for DMA transfer, DMA transfer of
FIFO data can be performed in synchronization with A/D scan conversion. For details of setting the byte
number for DMA transfer, see "CHAPTER 31 DMA Controller (DMAC)".
•
In single conversion mode
To perform DMA transfer, set the same value to the DMA block size and the interrupt generation
FIFO stage number, and perform the next A/D activation after DMA is completed.
•
In repeat conversion mode
To perform DMA transfer, set 1 to the DMA block size, and 1 for the interrupt generation FIFO stage
number.
Figure 25.6-6 shows the DMA transfer operation.
Figure 25.6-6 DMA transfer operation (through scan conversion interrupt requests)
Valid FIFO stage number
Block transfer when the block size is
6 and the transfer count is 1
Block transfer when the block size is
8 and the transfer count is 1.
SFS3 to SFS0=0111(8 stages)
FIFO stage
number setting
SFS3 to SFS0=0101(6 stages)
Scan conversion
interrupt request
(DMA activation
request)
Clearing by
DMAC
Clearing by
DMAC
FIFO reading
(DMA transfer)
A/D conversion
Stop
1 2 3 4 5 6
Stop
1 2 3 4 5 6 7 8
Stop
A/D activation
DMA normal end
interrupt
<Note>
Set the same value to the DMA block size and the interrupt generation FIFO stage number.
Perform the next A/D activation after performing DMA transfer of all FIFO data.
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CHAPTER 25 10-Bit A/D Converter
25.6
MB91665 Series
However, note that the event described below may occur while A/D conversion is repeated, such as in
repeat conversion mode. In such cases, even after DMA transfer of data by the specified number of the
bytes, the FIFO may still store more data corresponding to stages exceeding the number of stages at
which a scan conversion interrupt request/priority conversion interrupt request is generated.
•
A/D conversion of the signals from the next channel begins before DMA transfer of conversion results
is completed.
(Examples are when another DMA transfer is activated and DMA transfer of conversion results in
progress is made to wait)
For this reason, if the FIFO is storing more data corresponding to stages exceeding the number of stages
at which an interrupt request is generated, a clear operation by the DMA controller (DMAC) is ignored
and DMA transfer is performed again.
Figure 25.6-7 shows the DMA retransfer operation.
Figure 25.6-7 DMA retransfer operation
Block transfer when block size is 1 and transfer count is 4
Valid FIFO stage number
FIFO stage
number setting
Scan conversion
interrupt request
Clearing by DMAC
is ignored.
SFS3 to SFS0=0000
(1 stage)
Clearing by
DMAC
(DMA activation
request)
Waiting for DMA transfer
FIFO reading
(DMA transfer)
A/D conversion
Stop
1
2
3
4
1
2
3
4
1
2
3
4
Stop
A/D activation
RPT bit
DMA normal
end interrupt
<Note>
Set 1 to block size of DMA, and 1 for the interrupt generation FIFO stage number.
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CHAPTER 25 10-Bit A/D Converter
25.6
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FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 26 Multi-function Serial
Interface
This chapter describes the functions and operations of the
multi-function serial interface.
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
Characteristics of Multi-function Serial Interface
UART (Asynchronous Serial Interface)
Overview of UART (Asynchronous Serial Interface)
Registers of UART (Asynchronous Serial Interface)
Interrupts of UART
Operation of UART
Dedicated Baud Rate Generator
Setup Procedure and Program Flow for Operation
Mode 0 (Asynchronous Normal Mode)
26.9 Setup Procedure and Program Flow for Operation
Mode 1 (Asynchronous Multi-processor Mode)
26.10 Notes on UART Mode
26.11 CSIO (Clock Synchronous Serial Interface)
26.12 Overview of CSIO (Clock Synchronous Serial Interface)
26.13 Registers of CSIO (Clock Synchronous Serial Interface)
26.14 Interrupts of CSIO (Clock Synchronous Serial Interface)
26.15 Operation of CSIO (Clock Synchronous Serial Interface)
26.16 Dedicated Baud Rate Generator
26.17 Setup Procedure and Program Flow for CSIO (Clock
Synchronous Serial Interface)
26.18 Notes on CSIO Mode
26.19 I2C Interface
26.20 Overview of I2C Interface
26.21 Registers of I2C Interface
26.22 Interrupts of I2C Interface
26.23 Dedicated Baud Rate Generator
26.24 Notes on I2C Mode
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CHAPTER 26 Multi-function Serial Interface
26.1
26.1
MB91665 Series
Characteristics of Multi-function Serial
Interface
This multi-function serial interface has the following characteristics.
■ Interface Mode
The following interface modes are selectable for the multi-function serial interface depending on the
operation mode settings.
•
UART0 (Asynchronous normal serial interface)
•
UART1 (Asynchronous multi-processor serial interface)
•
CSIO (Clock synchronous serial interface) (SPI can be supported)
•
I2C (I2C bus interface)
■ Switching the Interface Mode
To communicate through each serial interface, the serial mode registers (SMR) shown in Table 26.1-1
should be used to set the operation mode before starting the communication.
Table 26.1-1 Switching Interface Mode
MD2
MD1
MD0
Interface mode
0
0
0
UART0 (Asynchronous normal serial interface)
0
0
1
UART1 (Asynchronous multi-processor serial interface)
0
1
0
CSIO (Clock synchronization serial interface) (SPI can be supported)
1
0
0
I2C (I2C bus interface)
Note: Settings other than above are prohibited.
<Notes>
•
Transmission and reception cannot be guaranteed when the operation mode is switched while
one of the serial interfaces is still in use for transmission or reception operation.
•
The operation mode must be set first. Otherwise, the part of registers of the same channel will
be initialized when the operation mode is changed. For the registers to be initialized, see the
notes for serial mode register (SMR) of each operation mode.
■ Number of Channels
This product has 4 built-in channels for multi-function serial interface.
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CHAPTER 26 Multi-function Serial Interface
26.2
MB91665 Series
26.2
UART (Asynchronous Serial Interface)
Among all the functions of the multi-function serial interface, this section describes those supported in
operation modes 0 and 1.
•
UART (Asynchronous Serial Interface)
•
Overview of UART (Asynchronous Serial Interface)
•
Registers of UART (Asynchronous Serial Interface)
•
-
Serial Control Register (SCR)
-
Serial Mode Register (SMR)
-
Serial Status Register (SSR)
-
Extended Serial Control Register (ESCR)
-
Reception Data Register/Transmission Data Register (RDR/TDR)
-
Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
Interrupts of UART
-
Occurrence of Reception Interrupts and Flag Set Timing
-
Occurrence of Transmission Interrupts and Flag Set Timing
•
Operation of UART
•
Dedicated Baud Rate Generator
-
Setting Baud Rate
•
Setup Procedure and Program Flow for Operation Mode 0 (Asynchronous Normal Mode)
•
Setup Procedure and Program Flow for Operation Mode 1 (Asynchronous Multi-processor Mode)
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CHAPTER 26 Multi-function Serial Interface
26.3
26.3
MB91665 Series
Overview of UART (Asynchronous Serial
Interface)
UART (asynchronous serial interface) is a general-purpose serial data communication interface to
perform asynchronous communication (start-stop synchronization) with an external unit. The UART
supports a two-way communication function (normal mode) and a master/slave communication
function (multi-processor mode: the master and slaves both supported).
■ Functions of UART (Asynchronous Serial Interface)
Function
1
Data
2
Serial input
3
Transfer system
4
Baud rate
Full-duplex double buffer
Oversampling is performed for three times to determine the reception
value by the majority of the sampling values achieved.
Asynchronous
•
•
5
Data length
5 to 9 bits (in normal mode), 7 or 8 bits (in multi-processor mode)
6
Signaling system
NRZ (Non Return to Zero), inverted NRZ
7
Start bit detection
•
•
Synchronized with the falling edge of a start bit (NRZ)
Synchronized with the rising edge of a start bit (inverted NRZ)
8
Reception error detection
•
•
•
Framing error
Overrun error
Parity error
9
Interrupt request
•
Reception interrupt
(completion of reception, framing error, overrun error, parity
error)*
Transmission interrupt (transmission data empty, transmission
bus idle)
DMA transfer support function for transmission and reception
•
•
10
Master/slave communication
function (multi-processor
mode)
*:
768
Dedicated baud rate generator (15-bit reload counter
configuration)
The reload counter can be used to adjust the external clock input.
Communication between 1 (master) and n (slaves) is enabled.
(The master and slave systems are both supported.)
The detection of a parity error is enabled only in normal mode.
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 26 Multi-function Serial Interface
26.4
MB91665 Series
26.4
Registers of UART (Asynchronous Serial
Interface)
This section lists the registers of UART (asynchronous serial interface).
■ List of Registers of UART (Asynchronous Serial Interface)
Table 26.4-1 List of Registers of UART (Asynchronous Serial Interface) (1 / 2)
Reference
Abbreviated
Register Name
0
SCR0
Serial control register 0
26.4.1
SMR0
Serial mode register 0
26.4.2
ESCR0
Extended serial control register 0
26.4.4
BGR0
Baud rate generator register 0
26.4.6
SSR0
Serial status register 0
26.4.3
RDR0
Received data register 0
26.4.5
TDR0
Transmitted data register 0
26.4.5
SCR1
Serial control register 1
26.4.1
SMR1
Serial mode register 1
26.4.2
ESCR1
Extended serial control register 1
26.4.4
BGR1
Baud rate generator register 1
26.4.6
SSR1
Serial status register 1
26.4.3
RDR1
Received data register 1
26.4.5
TDR1
Transmitted data register 1
26.4.5
SCR2
Serial control register 2
26.4.1
SMR2
Serial mode register 2
26.4.2
ESCR2
Extended serial control register 2
26.4.4
BGR2
Baud rate generator register 2
26.4.6
SSR2
Serial status register 2
26.4.3
RDR2
Received data register 2
26.4.5
TDR2
Transmitted data register 2
26.4.5
1
2
CM71-10158-1E
Register Name
Channel
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CHAPTER 26 Multi-function Serial Interface
26.4
MB91665 Series
Table 26.4-1 List of Registers of UART (Asynchronous Serial Interface) (2 / 2)
Register Name
Reference
Channel
Abbreviated
Register Name
6
SCR6
Serial control register 6
26.4.1
SMR6
Serial mode register 6
26.4.2
ESCR6
Extended serial control register 6
26.4.4
BGR6
Baud rate generator register 6
26.4.6
SSR6
Serial status register 6
26.4.3
RDR6
Received data register 6
26.4.5
TDR6
Transmitted data register 6
26.4.5
Table 26.4-2 Bit Assignment of UART (Asynchronous Serial Interface)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
SCR/SMR UPCL
SSR/
ESCR
REC
-
-
RIE
TIE
TBIE
-
PE
FRE
ORE
RDRF TDRE
RDR/TDR
BGR1/
BGR0
RXE
-
EXT
B14
B13
-
B12
B11
B10
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TXE
MD2
MD1
MD0
-
SBL
BDS
SCKE
SOE
TBI
-
ESBL
INV
PEN
P
L2
L1
L0
D8
(AD)
D7
D6
D5
D4
D3
D2
D1
D0
B8
B7
B6
B5
B4
B3
B2
B1
B0
B9
-
-
■ Operation Mode
The UART (asynchronous serial interface) operates in two different modes. The mode selection is
determined by MD2, MD1 and MD0 in the serial mode register (SMR).
Table 26.4-3 Operation Modes of UART (Asynchronous Serial Interface)
770
Operation
mode
MD2
MD1
MD0
Type
0
0
0
0
UART0 (asynchronous normal mode)
1
0
0
1
UART1 (asynchronous multi-processor mode)
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 26 Multi-function Serial Interface
26.4
MB91665 Series
26.4.1
Serial Control Register (SCR)
The serial control register (SCR) enables or disables transmission/reception, transmission/reception
interrupts, and transmission bus idle interrupts. SCR can also reset the UART.
■ Serial Control Register (SCR)
Figure 26.4-1 shows the bit structure of the serial control register (SCR), and Table 26.4-4 describes the
function of each bit.
Figure 26.4-1 Bit Structure of Serial Control Register (SCR)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
UPCL
-
-
RIE
TIE
TBIE
RXE
TXE
R/W
-
-
R/W
R/W
R/W
R/W
R/W
.........................................
bit7
bit0
(SMR)
Initial value
0--00000B
TXE
0
1
Transmission enable bit
Disables transmission
Enables transmission
RXE
0
1
Reception enable bit
Disables reception
Enables reception
TBIE
Transmission bus idle interrupt enable bit
Disables transmission bus idle interrupt
0
1
Enables transmission bus idle interrupt
TIE
0
1
Transmission interrupt enable bit
Disables transmission interrupt
Enables transmission interrupt
RIE
0
1
Reception interrupt enable bit
Disables reception interrupt
Enables reception interrupt
Undefined bits
Read: undefined value. Write: no effect.
UPCL
R/W
: Readable/Writable
: Initial value
-
0
1
Programmable clear bit
Write
Read
No effect
"0" is always read.
Programmable clear operation
: Undefined
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CHAPTER 26 Multi-function Serial Interface
26.4
MB91665 Series
Table 26.4-4 Functional Description of Each Bit of Serial Control Register (SCR)
Bit name
bit15
UPCL:
Programmable
clear bit
This bit is used to initialize the internal state of the UART.
Setting the bit to "1":
• The UART will be reset directly (software reset). The register setting,
however, will be retained. In this case, communication of the data which
is being transmitted or received will be cut off immediately.
• The baud rate generator will reload the value set in BGR1/BGR0
registers, and then restart the operation.
• All the transmission/reception interrupt sources (PE, FRE, ORE, RDRF,
TDRE and TBI) will be initialized (000011B).
Setting the bit to "0": No effect on the operation
Reading this bit always returns "0".
Note:
Execute the programmable clear operation after disabling interrupts.
bit14,
bit13
Undefined bits
Read: undefined value
Write: no effect
bit12
RIE:
Reception
interrupt enable
bit
•
bit11
•
This bit is used to enable/disable the output of reception interrupt
requests to the CPU.
A reception interrupt request is output when the RIE bit and the
reception data flag bit (RDRF) are set to "1", or when any of the error
flag bits (PE, ORE or FRE) is set to "1".
TIE:
Transmission
interrupt enable
bit
•
TBIE:
Transmission
bus idle
interrupt enable
bit
•
bit9
RXE:
Reception
enable bit
This bit is used to enable/disable UART reception operation.
• Setting the bit to "0" disables the reception operation.
• Setting the bit to "1" enables the reception operation.
Note:
Even when the reception operation is enabled (RXE = 1), such operation
does not start until the falling edge of a start bit (in NRZ format: INV =
0) is input. (When the inverted NRZ format is selected (INV = 1), the
reception operation does not start until the rising edge is input.)
If the reception operation is disabled (RXE = 0) during the reception, the
operation will be terminated immediately.
bit8
TXE:
Transmission
enable bit
This bit is used to enable/disable UART transmission operation.
• Setting the bit to "0" disables the transmission operation.
• Setting the bit to "1" enables the transmission operation.
Note:
If the transmission operation is disabled (TXE = 0) during the
transmission, the operation will be terminated immediately.
bit10
772
Function
•
•
This bit is used to enable/disable the output of transmission interrupt
requests to the CPU.
A transmission interrupt request is output when the TIE and TDRE bits
are set to "1".
This bit is used to enable/disable the output of transmission bus idle
interrupt requests to the CPU.
A transmission bus idle interrupt request is output when the TBIE and
TBI bits are set to "1".
FUJITSU SEMICONDUCTOR LIMITED
CM71-10158-1E
CHAPTER 26 Multi-function Serial Interface
26.4
MB91665 Series
26.4.2
Serial Mode Register (SMR)
The serial mode register (SMR) sets the operation mode, selects the transfer direction, data length
and stop bit length, and enables or disables the output to the seri