Migration from Atmel AT25DF SPI Flash Memories to Spansion® S25FL2-K Application Note 1. Introduction This document provides a hardware and software migration guide for users of the Atmel® AT25DFXX1A family serial flash memory product interested in evaluating the Spansion® S25FL2-K product family as a possible replacement. S25FL2-K flash is a cost optimized serial peripheral interface (SPI) non-volatile NOR flash family manufactured on a 90 nm floating gate process technology node. The S25FL2-K family is composed of (among others): 512 kB (4 Mbit) S25FL204K 1 MB (8 Mbit) S25FL208K S25FL2-K flash can directly replace AT25DF041A and AT25DF081A flash in many applications. In applications that do not rely on complex protection schemes, the migration is very straightforward. A few features and performance attributes supported by AT25DFxx1A are not supported by S25FL2-K, and others work differently. This application note discusses the specification differences that must be considered when migrating to S25FL2-K from a like density AT25DFxx1A. 2. Feature Comparison and Differences While all members of the FL2_K family support essentially the same feature set, differing only in the size of the data array, Atmel designed the AT25DFXX1A family so that memories with larger array sizes also support more features. A design that uses only features common to all members of the AT25DFXX1A family will require minimal changes in software in order to migrate to the S25FL2-K family. The S25FL2-K family supports a similar set of features to those supported by AT25DFxx1A. Table 2.1 summarizes the feature similarities and differences between AT25DFXX1A and S25FL2-K. The principal feature differences are related to identification and security options. Differences are discussed in more detail in later sections. Publication Number Migrate_AT25DF_to_S25FL2-K_AN Revision 01 Issue Date December 19, 2012 A pplication Note Table 2.1 High Level Feature Support Comparison Feature / Parameter (1) AT25DF041A AT25DF081A FL2-K √ √ √ 4-Mbit Density Option √ 8-Mbit Density Option Standard Single IO Operation yes yes yes Dual Output Operation no yes yes 256B Program Page Buffer Depth yes yes yes 4-kB Sector Erase Granularity yes yes yes 32-kB Block Erase Granularity yes yes no 64-kB Block Erase Granularity yes yes yes HOLD# and WP# Inputs yes yes yes Single IO Normal Read SCK Frequency (max) 33 MHz 50 MHz 44 MHz Single/Dual Fast Read SCK Frequency (max) 70 MHz 85,100 MHz (4) 86-104 MHz (2) no no no Program and Erase Suspend/ Resume Function Fractional Block Protection (BP) yes yes yes yes (3) yes (3) no Unique Serial Number no yes (5) no One Time Programmable Region(s) no yes no Deep Power Down Mode yes yes yes SOIC 8 (150- and 208-mil) Package Options yes yes yes Complement Block Protection Notes: 1. All comparisons apply to operation with VCC = 2.7 to 3.6V and Temperature = -40 to +85°C. 2. Single and Dual Output Fast Read maximum frequency varies by density: S25FL204K - 86 MHz, S25FL208K - 104 MHz. 3. Each sector may be independently protected. 4. 100 MHz available with SPI master controller implementing proprietary Atmel protocol. 5. Serial number in OTP must be programmed by customer. 2.1 Commands S25FL2-K support all basic read, program, erase, identification, and mode control commands that are supported by AT25DFXX1A. Table 2.2 summarizes the commands supported by both S25FL2-K and AT25DFXX1A. Table 2.3 lists the commands that are supported by AT25DFXX1A but not S25FL2-K. Migration from AT25DFXX1A to S25FL2-K can only be accomplished without driver changes provided none of the opcodes listed in Table 2.3 are used by existing drivers. 2 Migrate_AT25DF_to_S25FL2-K_AN_01 December 19, 2012 App l ic atio n No t e Table 2.2 Commands Supported by Both S25FL2-K and AT25DFXX1A Command Description Opcode Read Operations READ Read Data Bytes 03h FAST_READ Read Data Bytes at Higher Speed 0Bh DOR Dual Output Read 3Bh RDID Read Identification JEDEC 9Fh Write Control WRDI Write Disable 04h WREN Write Enable 06h PP Page Program Program and Erase Operations 02h P4E 4-kB Sector Erase 20h BE Bulk Erase 60h / C7h SE 64-kB Block Erase D8h Power Saving Mode RES DP Release from Deep Power-Down and Read Electronic Signature (1) ABh Deep Power Down B9h Status and Configuration Register Operations WRR Write (Status and Configuration) Register 01h RDSR Read Status Register 05h Note: 1. Atmel parts do not implement Read Electronic Signature bytes of RES (ABh) command. As noted before, AT24DFxx1A supports a more elaborate security and protection scheme, with several commands implementing them. For applications requiring more elaborate protection and security, Spansion S25FL-K family parts are more appropriate. The 1B Read opcode works with a proprietary protocol to achieve 100 MHz with the AT24DF081A. Spansion's same-density S25FL208K achieves 104 MHz without requiring such a protocol. December 19, 2012 Migrate_AT25DF_to_S25FL2-K_AN_01 3 A pplication Note Table 2.3 AT24DFxx1A Commands Not Supported by S25FL-2K Supported by: Command Description Opcode AT24DF041A AT24DF081A Read Operations Read Array (fastest, proprietary protocol needed) √ 1Bh Program and Erase Operations Dual-Input Byte/Page Program (1 to 256 Bytes) √ A2h 32-kB Block Erase 52h √ Sequential Program Mode ADh √ Sequential Program Mode AFh √ √ Status and Configuration Register Operations Write Status Register Byte 2 √ 31h Protection Commands Protect Sector 36h √ √ Unprotect Sector 39h √ √ 3Ch √ √ Read Sector Protection Registers Security Commands Sector Lockdown 33h √ Freeze Sector Lockdown State 34h √ Read Sector Lockdown Registers 35h √ Program OTP Security Register 9Bh √ Read OTP Security Register 77h √ Others Reset 2.2 F0h √ √ Modes of Operation S25FL2-K and AT25DFXX1A support the standard SPI Mode 0 (0,0) and Mode 3 (1,1) modes of operation utilizing a single IO. See data sheets for full details of supported modes of operation and related commands. 2.2.1 Dual Output / Dual Input All S25FL2-K family members and AT25DF081A (but not AT25DF041A) support Dual Output mode and the Fast Read Dual Output (3Bh) command (3Bh opcode), which uses single IO channel for both command and address input. Unlike AT25DF081A, S25FL2-K does not support Dual Input mode and the Dual-Input Byte/ Page Program command (A2h opcode). In most applications, Dual Input yields only a very small improvement in performance unless the SPI clock rate is unusually low, due to the fact that program times for any flash part are much greater than the data transfer time. 4 Migrate_AT25DF_to_S25FL2-K_AN_01 December 19, 2012 App l ic atio n 2.3 No t e Device Identification S25FL2-K and AT25DFXX1A both support JEDEC RDID (9Fh) device identification command methods, as shown in Table 2.4 below, which shows the values returned by each memory Table 2.4 Product Identification - Read JEDEC ID (Opcode 9Fh) 2.4 Device Read JEDEC ID Manufacturer ID Byte 0 (MF7-MF0) Read JEDEC ID Memory Type Byte 1 (ID15-ID8) Read JEDEC ID Memory Type Byte 2 (ID7-ID0) [Optional to read] Extended Device Information (EDI) String Length [Optional to read] EDI Byte 1 AT25DF041A 1Fh 44h 01h 01h 00h AT25DF081A 1Fh 45h 01h 01h 00h S25FL204K 01h 40h 13h 00h S25FL208K 01h 40h 14h 00h Status Register S25FL2-K and AT25DF041A both have an 8-bit Status Register(R0-R7) that is read accessed using the use the Read Status Register command (05h opcode) and write accessed using the Write Enable command (06h opcode) and the Write Status Register command (01h opcode). AT25DF081A has a 16-bit Status Register (S0-S15). Read access to register is via the same Read Status Register command (05h opcode) utilized by S25FL2-K. Reading the upper byte (S8-S15) is optional, so the same 8-bit read will work for this chip as well. Write access to Status Register utilizes the same Write Enable command (06h opcode) and the Write Status Register command (01h opcode) utilized by S25FL2-K. Additionally, AT25DFX81A supports the Write Status Register Byte 2 command (31h opcode) which allows writing of the high-order byte of the status register. This feature is not supported by S25FL2-K. The status registers of S25FL2-K and AT25DFXX1A differ substantially. The S25FL2-K status register is not functionally compatible with the Status Register Lower Byte of AT25DFXX1A. The BUSY (R0/S0 bit), WEL (R1/S1 bit have identical functionality. Driver changes will be required if other bits are used by the driver. In particular, S25FL2-K family does not implement the EPE Erase/Program Error functionality. Table 2.5 highlights the differences in Status Register bit definitions. Table 2.5 Status Register Comparison AT25DF041A Reg Bit Bit Function S0 RDY/BSY Ready/Busy Status S1 WEL Write Enable Latch SWP Software Protection Status S2 S3 December 19, 2012 AT25DF081A Bit Name Reg Bit Functionally Compatible Bit Name Bit Function S0 RDY/BSY Ready/Busy Status yes 1S WEL Write Enable Latch SWP Software Protection Status S2 S3 S25FL2-K Reg Bit Bit Name Bit Function R0 BUSY Erase/Write in Progress yes R1 WEL Write Enable Latch no R2 BP0 Block Protect Bit no R3 BP1 Block Protect Bit S4 WPP Write Protect (WP) Pin Status S4 WPP Write Protect (WP) Pin Status no R4 BP2 Block Protect Bit S5 EPE Erase/Program Error S5 EPE Erase/Program Error no R5 BP3 Block Protect Bit S6 SPM Sequential Program Mode Status S6 RES Reserved for future use no R6 Reserved Undefined S7 SPRL Sector Protection Registers Locked S7 SPRL Sector Protection Registers Locked no R7 SRP Status Reg Protect Migrate_AT25DF_to_S25FL2-K_AN_01 5 A pplication 2.5 Note Security and Write Protection S25FL2-K has a limited security feature set. It does support standard write protection features, such as the need to set WEL bit in the Status Register prior to array, or Status Register changes and the need for all commands that change data to conclude with the correct byte oriented clock cycles. 2.5.1 Block Protection S25FL2-K supports a reduced number of options to set the granularity and location of array read-only protection compared to AT25DFXX1A. S25FL2-K uses four Block Protection bits (BP3-BP0) to define which portions of the array are erase/write protected in Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Table 2.6 provides the mapping of BP3-BP0 bits to the limited set of protected address range options for S25FL2-K. Table 2.6 S25FL2-K Block Protection Options S25FL204K S25FL208K BP[3:0] 2.5.2 Protected Addresses Protected Size Protected Addresses 0000b None 0 kB None Protected Size 0 kB 0001b 070000h-07FFFFh 64 kB 0F0000h-0FFFFFh 64 kB 0010b 060000h-07FFFFh 128 kB 0E0000h-0FFFFFh 128 kB 0011b 040000h-07FFFFh 256 kB 0C0000h-0FFFFFh 256 kB 0100b 000000h-07FFFFh 512 kB 080000h-0FFFFFh 512 kB 0101b 000000h-07FFFFh 512 kB 000000h-0FFFFFh 1024 kB 0110b 000000h-07FFFFh 512 kB 000000h-0FFFFFh 1024 kB 0111b 000000h-07FFFFh 512 kB 000000h-0FFFFFh 1024 kB 1000b None 0 kB None 0 kB 1001b 000000h-07EFFFh 504 kB 000000h-07EFFFh 504 kB 1010b 000000h-07DFFFh 496 kB 000000h-07DFFFh 496 kB 1011b 000000h-07BFFFh 480 kB 000000h-07BFFFh 480 kB 1100b 000000h-077FFFh 448 kB 000000h-077FFFh 448 kB 1101b 000000h-05FFFFh 384 kB 000000h-05FFFFh 384 kB 1110b 000000h-03FFFFh 256 kB 000000h-03FFFFh 256 kB 1111b 000000h-07FFFFh 512 kB 000000h-07FFFFh 1024 kB Other Security Options S25FL2-K does not have a One Time Programmable (OTP) region feature. AT25DFX081A, does, but AT25DFX041A does not. 6 Migrate_AT25DF_to_S25FL2-K_AN_01 December 19, 2012 App l ic atio n 2.6 No t e DC and AC Parameter Table 2.7 provides a comparison of DC parameters for AT25DFXX1A and S25FL2-K. Table 2.8 and Table 2.9 provide comparisons of AC parameters for AT25DFXX1A and S25FL2-K by density. While most parameter differences should not cause performance issues when migrating from AT25DFXX1A to S25FL2-K, it is highly recommended that the user carefully review all parameter differences for potential impact. Table 2.7 DC Parameter Differences DC Parameter Type Units AT24DF041A AT24DF081A S25FL2-K VCC: Core Source Voltage min/max V 2.7 / 3.6 2.7 / 3.6 2.7 / 3.6 VIL: Input Low Voltage min/max V -0.6V / 0.3x VCC -0.6V / 0.3x VCC -0.5 / 0.3x VCC VOL: Output Low Voltage max V 0.4 0.4 0.4 ICC1: Standby Current typ/max µA 25 / 35 10 / 25 15 / 25 ICC2: Power Down Current typ/max µA 15 / 20 25/50 15 / 25 8 / 12 13/16 10 / 15 16 20 25 ICC3: Read Data Current - Single IO, 33MHz typ/max mA ICC3: Read Data Current - Dual IO, 33MHz typ/max mA ICC3: Read Data Current - Single IO, FSCK_MAX (1) max mA ICC3: Read Data Current - Dual IO, FSCK_MAX (1) max mA ICC4/5: Write Status Register Current typ/max mA ICC5/4: Page Program Current typ/max mA 12 / 18 25 10 / 18 12 / 18 10 / 15 15 / 20 Note: 1. S25FL-K FSCK_MAX = 80 MHz; S25FL2-K FSCK_MAX = 100 MHz. Table 2.8 AC Parameter Differences — 4 Mbit Density Parameter Type Units AT25DF041A S25FL204K fSCK,R: SCK Frequency - Read Data Instruction (03h) (1) max MHz 33 44 fSCK,R: SCK Frequency - All Other Commands (1) max MHz 50 86 tCLH, tCLL, tCRLH, tCRLL: Clock High/Low Time - Read (03h) min ns 6.4 4 tWH, tCH, tWL, tCL: Clock High/Low Time - All Other Commands min ns 6.4 4 tSU-DAT: Data Input Setup to SCK min ns 2 4 tCS: CS# High Time Between Read Instructions min ns 10 50 tCS: CS# High Time Between Erase/Program and Status Read min ns 50 100 tDIS: Output Disable Time max ns 6 6 tv: SCK low to Output Valid - Except Read ID Commands max ns 6 10 tV2: SCK low to Output Valid - Read ID Commands max ns 7.5 10 200 ns 15 ms ms 1.2 / 5 1.5 / 5 tW: WRR Write Time max tPP: Page Program Time typ / max tSE: Sector Erase Time (4 kB) typ / max ms 50 / 200 50 / 300 tBE: Block Erase Time (64 kB) typ / max s .4 / .95 0.5 / 2 tCE: Chip Erase Time typ / max s 3/7 3.5 / 7 Note: 1. SCLK specifications for VCC = 2.7 - 3.6 V operation. December 19, 2012 Migrate_AT25DF_to_S25FL2-K_AN_01 7 A pplication Note Table 2.9 AC Parameter Differences — 8 Mbit Density Parameter Type Units fSCK,R: SCK Frequency - Read Data Instruction (03h) (1) max MHz AT25DF041A 50 S25FL204K 44 fSCK,R: SCK Frequency - All Other Commands (1) max MHz 80 104 tCLH, tCLL, tCRLH, tCRLL: Clock High/Low Time - Read (03h) min ns 8 4 tSU-DAT: Data Input Setup to SCK min ns 2 4 tCSH: CS# Active Hold from SCK min ns 5 3 tCS: CS# High Time Between Read Instructions min ns 10 50 tCS: CS# High Time Between Erase/Program and Status Read min ns 50 100 tDIS: Output Disable Time max ns 7 6 tv: SCK low to Output Valid - Except Read ID Commands max ns 7 8 tV2: SCK low to Output Valid - Read ID Commands max ns 8.5 8 tW: WRR Write Time max 200 ns 15 ms tSE: Sector Erase Time (4 kB) typ / max ms 30 / 200 50 / 300 tBE: Block Erase Time (64 kB) typ / max s 0.15 / 1 0.5 / 2 tCE: Chip Erase Time typ / max s 3 / 10 12 / 25 Note: 1. SCLK specifications for VCC = 2.7 - 3.6 V operation. 3. Conclusion Migration from AT25DFXX1A to S25FL2-K is straightforward for those applications that do not require 32-kB erase granularity and do not require elaborate security. Careful attention should be paid to differences in status register, JEDEC density code, and clock rates. The maximum clock rate for slow read is slightly lower for the 8-Mb Spansion parts (though for fast read, is a little higher.) 8 Migrate_AT25DF_to_S25FL2-K_AN_01 December 19, 2012 App l ic atio n No t e 4. Revision History Section Description Revision 01 (December 19, 2012) Initial release December 19, 2012 Migrate_AT25DF_to_S25FL2-K_AN_01 9 A pplication Note Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2012 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 10 Migrate_AT25DF_to_S25FL2-K_AN_01 December 19, 2012