Designing a Serial Peripheral Interface Application Note by Eric Lin 1. What is a Serial Peripheral Interface (SPI)? A serial peripheral interface (SPI) has a simple 4-wire synchronous interface protocol that enables controllers and peripheral devices to intercommunicate. An SPI Bus consists of 4 signal wires. See Figure 1.1. 1. Master Out Slave In (MOSI) — MOSI signal is generated by Master, recipient is the Slave. 2. Master In Slave Out (MISO) — MISO signals are generated by Slaves, recipient is the Master. 3. Serial Clock (SCLK or SCK) — SCLK signal is generated by the Master to synchronize data transfers. 4. Slave Select (SS#) from master to Chip Select (CS#) of slave — SS# signal is generated by Master to select individual Slave devices. Figure 1.1 SPI Bus Master Slaves MOSI SI MISO SO SCLK SCK SS# CS# SPI Flash Controller Publication Number Designing_an_SPI_Interface_AN Revision 01 Issue Date March 4, 2008 Ap pl ic atio n No t e 2. SPI Bus Modes CPHA = Clock Phase CPOL = Clock Polarity The following values define how the serial SPI bits are latched. SPI Mode CPHAS CPOL Description 0 0 0 When CPOL is inactive low, rising edge latches SPI data 1 1 0 When CPOL is inactive low, falling edge latches SPI data 2 0 1 When CPOL is inactive high, falling edge latches SPI data 3 1 1 When CPOL is inactive high, rising edge latches SPI data Spansion SPI Flash supports SPI Mode 0 and Mode 3. 3. Spansion® SPI Product Input/Output Description March 4, 2008 SCK Serial Clock Input (always driven by the master) SI Serial Data Input (used to transfer data into the SPI device) SO Serial Data Output (used to transfer data out of the SPI device) CS# Chip Select Input (for enabling device operation) W# Write Protect Input (used to guard against program/erase instructions) HOLD# Hold Input (to pause SPI transaction) Vcc Supply Voltage GND Ground Designing a Serial Peripheral Interface 2 A pplication Note GND 4. Spansion SPI Flash Command Set Table 4.1 SPI Flash Command Set Instruction Description One-Byte Instruction Code WREN Write Enable 06h (0000 0110) 0 WRDI Write Disable 04h (0000 0100) 0 WRSR Write to Status Register 01h (0000 0001) RDSR Read from Status Register 05h (0000 0101) Address Bytes Dummy Bytes Data Bytes Total Bytes 0 0 1 0 0 1 0 0 1 2 0 0 1 to Infinity 2+ Status Register Operations Read Operations READ Read 03h (0000 0011) 3 0 1 to Infinity 5+ FAST_READ Fast Read 0Bh (0000 1011) 3 1 1 to Infinity 6+ RDID(1) Manuf & Device ID Read 9Fh (1001 1111) 0 0 1 to 3 2+ Erase Operations SE Sector Erase D8h (1101 1000) 3 0 0 4 BE Bulk(Chip) Erase C7h (1100 0111) 0 0 0 1 0 1 to 256 5+ Program Operations PP Page Program 02h (0000 0010) 3 DP Deep Power Down B9h (1011 1001) 0 0 0 1 Release from DP ABh (1010 1011) 0 0 0 1 Release from DP and Read Electronic Signature ABh (1010 1011) 0 3 1 to Infinity 5+ Power Savings Mode Operations RES Note: 1. All instructions, addresses and data are shifted in and out of the device, MSB first. SI is sampled on the 1st rising edge of SCK after CS# is driven low. Then, the 1-byte instruction opcode is shifted into the device via SI, MSB first. 3 Designing a Serial Peripheral Interface March 4, 2008 Ap pl ic atio n No t e 5. Spansion SPI Flash Operations 5.1 Normal Read Operation Normal Read command (0x03h) enables data to be read from the memory array at the SCK (maximum 33 MHz). 1. The host system must first select the device by driving CS# to active low. 2. The READ command (0x03h) is written to SI, followed by a 3-byte address (A23-A0) and can be at any location of the device. 3. The device automatically increments to the next higher address after each byte of data is outputted. 4. The device allows single-byte read sequence and can continue data output, indefinitely. 5. The READ command is terminated by driving CS# high at any time during data output. 6. The device rejects any READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. 5.2 Page Program Operation and How to Check Status Page Program (PP) command (0x02h) enables memory array data to be programmed from 1 to 0. 1. The host system must first select the device by driving CS# to low. 2. A WREN command (0x06h) is required prior to writing the PP command. The Write Enable (WREN) command (shown below) sets the Write Enable Latch (WEL) bit to a 1, which enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command. March 4, 2008 Designing a Serial Peripheral Interface 4 A pplication Note 3. The PP command (0x02h) (shown below) is written to SI, followed by three address bytes, and at least one data byte written to SI. 4. The device programs only the last 256 data bytes sent to the device. 5. The host system must drive CS# high after the device has latched the 8th bit of the data byte. 6. Use Read Status Register command (0x05h) (shown below) to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. 7. The WIP bit is 1 during the PP operation, and is 0 when the operation is completed. Table 5.1 highlights the 8 bits that are part of the SPI Status register. 5 Designing a Serial Peripheral Interface March 4, 2008 Ap pl ic atio n No t e Table 5.1 SPI Status Register Bits Bit Status Register Bit Bit Function Description 1 = Protects when W# is low 0 = No protection, even when W# is low 7 SRWD Status Register Write Disable 6 — — Not used 5 — — Not used 4 BP2 3 BP1 2 BP0 1 WEL Write Enable Latch 0 WIP Write in Progress Block Protect Protected memory size starting from upper most address: 000 = none, 001 = 1/64, 010 = 1/32, 011 = 1/16, 100 = 1/8, 101= 1/4, 110 = 1/2, 111 = all 1 = Device accepts Write Status Register, program, or erase commands 0 = Ignores Write Status Register, program, or erase commands 1 = Device Busy. A Write Status Register, program, or erase operation is in progress 0 = Ready. Device is in standby mode and can accept commands. 6. Power-Up During power-up certain conditions must be observed. 1. CS# must follow the voltage applied on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows 2. No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC(min), and then to a further delay of tPU 3. At power-up, the device is in standby mode and the WEL bit is reset (0). March 4, 2008 Symbol Parameter Min VCC(min) VCC(minimum) 2.7 V tPU VCC(min) to device operations 10 ms Designing a Serial Peripheral Interface Max Unit 6 A pplication Note 7. Revision History Section Description Revision 01 (March 4, 2008) Initial Release 7 Designing a Serial Peripheral Interface March 4, 2008 App l ic atio n No t e Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2008 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, ORNAND2™, HD-SIM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. March 4, 2008 Designing a Serial Peripheral Interface 8