AN98518 Versatile I/O to Interface S25FL-S SPI Multi I/O Flash in 1.8-V and 2.5-V Systems Author: Cypress Associated Part Family: S25FL-S AN98518 discusses the versatile I/O (VIO) supply feature available in S25FL-S MirrorBit® Serial Peripheral Interface (SPI) Multi-I/O Flash Memory family. 1 Introduction The S25FL-S MirrorBit® Serial Peripheral Interface (SPI) Multi-I/O Flash Memory family has added the Versatile I/O (VIO) supply feature as a model ordering option for the SOIC-16 and both 24-ball BGA packages. Many embedded system applications have processors or chipsets operating at lower voltages even though a 3-V supply voltage is present in the system. As the voltage source for all flash device input receivers and output drivers, the Versatile I/O (VIO) supply allows the host system to set the voltage levels that the device tolerates on all inputs and drives on outputs (control and I/O signals). The Versatile I/O (VIO) supply range is from 1.65V to VCC, and VIO cannot be greater than the core SPI flash VCC supply voltage which may range from 2.7V to 3.6V. For example, a VIO of 1.65V - 3.6V allows for I/O at the 1.8V, 2.5V or 3V levels, driving and receiving signals to and from other 1.8V, 2.5V or 3V devices on the same data bus. 2 VIO Package Options Versatile I/O (VIO) is available for the following S25FL-S SPI Flash packages: the 300-mil 16-Lead SOIC, the 24Ball BGA arranged as 5 x 5 balls (FAB024), and the alternative 24-Ball BGA arranged as 4 x 6 balls (FAC024). These S25FL-S SPI flash V IO package models also support the Hardware Reset input signal on another dedicated pin. VIO is not available for products offered in the WSON 8-contact 6 x 8 mm no-lead package since there are only six core Input/Output signals for Multi-I/O without VIO or RESET#. For package models that do not support V IO, the VIO supply is tied internally to VCC inside the package for backward compatibility with the S25FL-P SPI Flash family. For 3V designs requiring a Hardware Reset pin, VIO must be tied to VCC so the interface signals operate at the same voltage as the core of the device. Please refer to the specific S25FL-S SPI Multi-I/O Flash device data sheet for complete details on the VIO model ordering options. www.cypress.com Document No. 001-98518 Rev. *A 1 Versatile I/O to Interface S25FL-S SPI Multi I/O Flash in 1.8-V and 2.5-V Systems 2.1 Package Connection Diagrams The location of the VIO and RESET# pins are shown in the following S25FL-S SPI Flash package connection diagrams. Figure 1. 16-Lead SOIC Package, Top View HOLD#/IO3 1 16 SCK VCC 2 15 SI/IO0 RESET#/RFU 3 14 VIO/RFU DNU 4 13 NC DNU 5 12 DNU RFU 6 11 DNU CS# 7 10 VSS SO/IO1 8 9 WP#/IO2 Figure 2. 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View 1 2 3 4 5 NC NC RESET#/ RFU NC DNU SCK VSS VCC NC DNU CS# RFU WP#/IO2 NC DNU SO/IO1 NC NC A B C D SI/IO0 HOLD#/IO3 NC E NC VIO/RFU NC Figure 3. 24-Ball BGA, 4 x 6 Ball Footprint (FAC024), Top View 1 2 3 4 NC NC NC RESET#/ RFU DNU SCK VSS VCC DNU CS# RFU WP#/IO2 DNU SO/IO1 NC NC NC VIO/RFU NC NC NC NC A B C D SI/IO0 HOLD#/IO3 E F www.cypress.com Document No. 001-98518 Rev. *A 2 Versatile I/O to Interface S25FL-S SPI Multi I/O Flash in 1.8-V and 2.5-V Systems 3 VIO Interfacing Examples In Figure 4, the S25FL-S SPI Flash interface to a processor or chipset controller requiring 2.5V Input/Output signals is illustrated in a Quad Mode implementation. The SPI 2.5V VIO signal is typically tied to the core VCC of the controller. In this example, the controller also drives the SPI Hardware Reset signal with the timings compatible with the specific S25FL-S SPI Multi-I/O Flash device data sheet. Figure 4. 2.5V VIO Interface with RESET# Example Master Slave 3.3V IO0 IO0 IO1 IO1 IO2 IO2 IO3 IO3 VCC SCLK SCK /SCS1 CS# VIO 2.5V GND /RESET Controller RESET# FL-S SPI Flash Quad Mode In Figure 5, the S25FL-S SPI Flash interface to a processor or chipset controller requiring 1.8V Input/Output signals is illustrated in a Quad Mode implementation. Again, the SPI 1.8V VIO signal is typically tied to the core VCC of the controller. In this example, the controller does not drive the SPI Hardware Reset signal. The SPI RESET# input has an internal pull-up and may be left unconnected if the Hardware Reset feature is not used. Figure 5. 1.8V VIO Interface without RESET# Example Master Slave 3.3V IO0 IO0 IO1 IO1 IO2 IO2 IO3 IO3 SCLK SCK /SCS1 CS# VCC VIO 1.8V GND RESET# Controller www.cypress.com FL-S SPI Flash Quad Mode Document No. 001-98518 Rev. *A 3 Versatile I/O to Interface S25FL-S SPI Multi I/O Flash in 1.8-V and 2.5-V Systems 3.1 Power-Up Specifications During the rise of power supplies at power-up, the VIO supply voltage must remain less than or equal to the VCC supply voltage. However, the VIO supply voltage must also be above VCC -200 mV until the VIO supply voltage is > 1.65V, i.e. the VIO supply voltage must not lag behind the VCC supply voltage by more than 200 mV during power up, until the VIO supply voltage reaches its minimum operating level. 4 Summary The Versatile I/O (VIO) supply feature of the S25FL-S MirrorBit SPI Flash Memory family enables interfacing to system processor or chipset controllers requiring Input/Output levels between 1.65V and 3.6V, depending on the SPI core VCC voltage, when a 3V supply voltage is present in the system. The dedicated Hardware Reset input feature paired with the VIO package options may be left unconnected if not used since the RESET# input has an internal pull-up. However, 3V designs requiring a Hardware Reset pin must tie VIO to VCC so the interface signals operate at the same voltage as the core VCC of the SPI device. 5 References S25FL128S and S25FL256S Data Sheet (S25FL128S_256S_00) Migration from FL-P to FL-S Family SPI Interface Flash Memories Application Note www.cypress.com Document No. 001-98518 Rev. *A 4 Versatile I/O to Interface S25FL-S SPI Multi I/O Flash in 1.8-V and 2.5-V Systems Document History Page Document Title: AN98518 - Versatile I/O to Interface S25FL-S SPI Multi I/O Flash in 1.8-V and 2.5-V Systems Document Number: 001-98518 Rev. ECN No. Orig. of Change 4928221 MSWI ** *A www.cypress.com Submission Date Description of Change 03/27/2012 Initial version 09/21/2015 Updated in Cypress template Document No. 001-98518 Rev. *A 5 Versatile I/O to Interface S25FL-S SPI Multi I/O Flash in 1.8-V and 2.5-V Systems Worldwide Sales and Design Support Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. # 999 Products PSoC® Solutions Automotive..................................cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers ................................ cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface......................................... cypress.com/go/interface Cypress Developer Community Lighting & Power Control ............cypress.com/go/powerpsoc Memory........................................... cypress.com/go/memory PSoC ....................................................cypress.com/go/psoc Touch Sensing .................................... cypress.com/go/touch Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support USB Controllers ....................................cypress.com/go/USB Wireless/RF .................................... cypress.com/go/wireless MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: Fax: Website: 408-943-2600 408-943-4730 www.cypress.com © Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-98518 Rev. *A 6