S29VS064R/S29XS064R (64Mb) PCB Routing Recommendation Application Note 1. Introduction This document provides general routing guidelines for PCBs (printed circuit boards) designed with Spansion® S29VS064R or S29XS064R products. This document does not eliminate the need for customer signal integrity/power delivery simulations and should be used as an initial reference towards PCB design with Spansion part. Spansion provided IBIS models should be used for signal timing/crosstalk simulations. 2. Signal Descriptions The following table describes various pins and their function used in the S29VS064R and S29XS064R. Signal Description A21-A16 Address Inputs (A21 is for 64 Mb only). A/DQ15–A/DQ0 Multiplexed Address/Data input/output. CE# Chip Enable Input. Asynchronous relative to CLK for the Burst mode. OE# Output Enable Input. Asynchronous relative to CLK for the Burst mode. WE# Write Enable Input. VCC Device Power Supply (1.70V–1.95V). VCCQ Input/Output Power Supply (1.70V–1.95V). VSS Ground. VSSQ Input/Output Ground. NC No Connect; not connected internally. RDY Ready output; indicates the status of the Burst read. VOL= data invalid. VOH = data valid. CLK The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. AVD# Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15–A0 are multiplexed, address bits Amax–A16 are address only). VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs RESET# Hardware reset input. VIL= device resets and returns to reading array data. VPP At 9V, accelerates programming. At VIL, disables program and erase functions. Should be at VIH for all other conditions. Publication Number S29VS_XS064R_PCB_Routing_AN Revision 01 Issue Date October 8, 2012 A pplication Note 3. Package Breakout Routing Recommendations Figure 3.1 S29VS/XS-64R — 44-Ball Very Thin FBGA Top View, Balls Facing Down NC NC A1 A2 A3 A4 A5 A6 A7 A8 A9 RDY A21 VSS CLK VCC WE# A19 A17 NC B1 B2 B3 B4 B5 B6 VPP B7 B8 B9 B10 VCCQ A16 NC RESET# NC A18 C1 C2 A20 AVD# C3 C4 C5 C6 C7 C8 A10 CE# VSSQ C9 C10 VSS A/DQ7 A/DQ6A/DQ13A/DQ12A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 A/DQ15A/DQ14 VSSQ A/DQ5 A/DQ4A/DQ11A/DQ10 VCCQ A/DQ1 A/DQ0 NC NC Figure 3.2 PCB Top Layer Escape Routing 2 S29VS_XS064R_PCB_Routing_AN_01 October 8, 2012 App l ic atio n No t e Figure 3.3 PCB Bottom Layer Escape Routing For an example 2-layer escape routing shown in Figure 3.2 and Figure 3.3, you should use; Ball Pad Size: 0.25 mm (9.84 mils) Solder Mask Opening: 0.35 mm (13.78 mils) Ball Pitch: 0.5mm (19.685 mils) Minimum trace width and trace spacing: 0.1 mm (4 mils) Once the ball field is cleared, you can redirect the traces in the direction of the SPI controller package while maintaining minimum (4 mils) or better spacing being traces. 4. Supply Routing Guidelines It is recommended that you meet or beat the supply routing recommendations below. VSS and VSSQ balls can be connected to a single ground plane. VCC and VCCQ balls can be connected to a single supply plane. Maintain low impedance routing (traces > 20 mils) from voltage regulator to flash supply pins. Except the package breakout area, maintain a minimum trace width of 20 mils for all supply traces. Both supply and ground traces (or planes) must be closely coupled to each other (i.e. route them close to each other to avoid large inductive loops). In case of a 2-layer PCB where both layers can be treated as mixed (signals and supply/ GND routed), ensure GND routing underneath all signal traces for a continuous return path. You should place PCB decoupling capacitors as close to the package as possible. Minimum 1 µF 0402 ceramic capacitor near each side of the package should be placed, as shown below. The selected capacitor should have low ESL and ESR. VCC and GND trace routing from the capacitor should be as wide as possible to avoid inductive/resistive effects. October 8, 2012 S29VS_XS064R_PCB_Routing_AN_01 3 A pplication Note PCB decap Placement NC NC A1 A2 A3 A4 A5 A6 A7 A8 A9 RDY A21 VSS CLK VCC WE# A19 A17 NC B1 B2 B3 B4 B5 B6 VPP B7 B8 B9 B10 VCCQ A16 NC RESET# NC A18 C1 C2 A20 AVD# C3 C4 C5 C6 C7 C8 A10 CE# VSSQ C9 C10 VSS A/DQ7 A/DQ6A/DQ13A/DQ12A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 A/DQ15A/DQ14 VSSQ A/DQ5 A/DQ4A/DQ11A/DQ10 VCCQ A/DQ1 A/DQ0 NC NC PCB decap Placement Since VPP is a high voltage signal, route it as close to GND as possible and as far away from VCC and other signals (> 12 mils). Also maintain a wide trace on VPP to provide low inductance path on PCB. 5. Signal Routing Guidelines It is recommended that you meet or beat the signal routing recommendations below. Notes – All length/mismatch guidelines are provided in picoseconds (ps). This is because based on customer topology, the transmission line delay will change (normally 1 inch ~ 166 ps). You should use signal integrity tools to estimate the actual trace velocity and subsequent path delays. – You should perform signal integrity simulations using Spansion provided IBIS models to determine actual guidelines suitable for their application. The guidelines below and simulation methodology should be used as a starting reference. – Normally delay is measured between TVM (timing reference voltage which is usually VCC/2) of source to TVM of destination. However, please pay attention to signal polarity in the data sheet to ensure that the destination timing is to the rising edge of the destination signal, or falling edge, or both. – The recommendations below assume (for simplicity) synchronous (burst read) operation and point-topoint routing between controller and Spansion flash. If that is not the case, then you need to first select which topology type to follow (star/T or daisy chain). Star or T topology is recommended (with appropriate termination resistors determined based on IBIS simulations). 4 S29VS_XS064R_PCB_Routing_AN_01 October 8, 2012 App l ic atio n No t e Guidelines 1. Maintain a continuous GND return path for all signals. If A/DQ bus switches layers through a set of vias, it is recommended to add stitching capacitors (connected between VCC and GND) near the transition point. Capacitor value can be equal to or greater than 1 µF. 2. PCB should target impedance of 50 ohms ±15%. However, the actual impedance tolerance needs to be simulated to verify that your topology can accommodate a 15% tolerance around nominal impedance. 3. A/DQ0-15 and clock topology min/max lengths should be determined as below: a. First obtain the memory controller and flash port IBIS model. b. Generate Clock and A/DQ0-15 topologies based on target PCB stackup and topology min/max restrictions. If multiple devices are present on the flash bus, a termination resistor on clock is recommended. Determine value based on simulations. c. Transmission line coupling (between A/DQ and other nets as well as CLK and other nets) should be included. It is also beneficial to include via models (in case of signal layer changes) as well as transmission line loss for long lines (e.g. > 10 inches). d. CLK trace should be spaced from any other signal > 3 times Clock trace width (to avoid crosstalk). e. Simulate both clock delay (TCLK_PCB) and A/DQ delay (TDQ_PCB). Simulations need to be performed across minimum/typical/maximum corners of the IBIS model as well as PCB impedance tolerance. Also odd/even data patterns need to be included in A/DQ switching to incorporate cross-talk effects. f. Meet the following equation: TCLK - (TCLK_PCB + TCLK_JITmax + TBACCmax + TDQ_PCBmax + TMSCUmin) 0 Where; TCLK = Clock period (since burst reads are single cycle transfer). TCLK_PCB = Delay on clock line from controller to flash. TDQ_PCBmax = Worst case delay on A/DQ0-15 line from flash to controller. TCLK_JITmax = Maximum cycle to cycle jitter on clock at flash pin. TBACCmax = Maximum Burst access time valid clock to output delay (refer to the S29V/XS-R MirrorBit Flash Family data sheet). TMCSUmin = Minimum memory controller data set-up time. This equation ensures that clock travel from the memory controller to (memory clock jitter + memory burst data output + data travel) back to the (memory controller + data set-up at the controller) all fits within a single clock cycle. 4. The Address net length should be calculated (including crosstalk) as follows. Take the clock length (and topology) determined in Step 3. Meet the following equation for all address signals: TCLK - TCLK_JITmax - TCNTR_ADD_TCOmax – (TADD_PCBmax - TCLK_PCB) – TACS 0 Where; TCNTR_ADD_TCOmax = Max. CLK to address launch delay at the controller. TCLK_PCB = Flight delay for CLK net. TADD_PCBmax = Max flight delay for A16-A21 or A/DQ0-15. TACS = Minimum Address to CLK setup time required at flash. TCLK_JITmax = Maximum cycle to cycle jitter on clock at flash pin. This equation assumes that controller switches address on the clock edge previous to the one used by flash to sample the incoming address signals. October 8, 2012 S29VS_XS064R_PCB_Routing_AN_01 5 A pplication Note 5. AVD# length should be calculated as below. Taking the clock length from Step 3., meet the following equation: T CLK - TCLK_JITmax - TCNTR_AVD_TCOmax – (TAVD_PCB - TCLK_PCB) – TAVDS 0 Where; TCNTR_AVD_TCOmax = Max. CLK to AVD# launch delay at the controller. TCLK_PCB = Flight delay for CLK net. TAVD_PCB = Flight delay for AVD#. TAVDS = Minimum AVD# to CLK setup time required at flash. TCLK_JITmax = Maximum cycle to cycle jitter on clock at flash pin. This equation assumes that controller switches AVD# on clock edge previous to the one used by flash to sample the incoming AVD# signal. 6. CE# topology should be determined as below. Taking the clock length from Step 3., meet the following equation: TCLK - TCLK_JITmax - TCNTR_CE_TCOmax – (TCE_PCB - TCLK_PCB) – TCES 0 Where; TCNTR_CE_TCOmax = Max. CLK to CE# launch delay at the controller. TCLK_PCB = Flight delay for CLK net. TCE_PCB = Flight delay for CE#. TCES = Minimum CE# to CLK setup time required at flash. TCLK_JITmax = Maximum cycle to cycle jitter on clock at flash pin. This equation assumes that controller switches CE# on clock edge previous to the one used by flash to sample the incoming CE# signal. 7. OE# topology should be determined as below. Taking the clock length from Step 3., meet the following equation: TCNTR_ADD_TCOmax + TACCmax - TCNTR_OE_TCOmax - TOE_PCB –TOEmax 0 Where; TCNTR_ADD_TCOmax = Maximum Address launch delay at the controller. TCNTR_OE_TCOmax = Maximum OE# launch delay at the controller. TOE_PCB = Flight delay for CE#. TOEmax = Maximum OE# set-up time requirement at flash. 8. RDY length should be targeted to be A/DQ0-15 lengths. 9. Since RESET# is asynchronous, no specific length requirement is placed on this signal. 10. Since writes are asynchronous, no specific length requirement is placed on the WE# signal. 6 S29VS_XS064R_PCB_Routing_AN_01 October 8, 2012 App l ic atio n No t e 6. Revision History Section Description Revision 01 (October 8, 2012) Initial release October 8, 2012 S29VS_XS064R_PCB_Routing_AN_01 7 A pplication Note Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2012 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 8 S29VS_XS064R_PCB_Routing_AN_01 October 8, 2012