Migration from S29NS064N to S29VS064R Application Note 1. Introduction The S29VS064R MirrorBit® flash offers a 1.8-volt, burst mode, simultaneous read and write, Address and Data Multiplexed (ADM) product. This document discusses the new features of the S29VS064R and the considerations the designer should make when migrating from the S29NS064N. 2. Feature Comparison Summary The following lists the items to consider when migrating from NS064N to VS064R: VS064R simplifies the software sector protection method, supports DYB (Dynamic Protection Bit) only, compared with the ASP (Advanced Sector Protection) feature in NS064N – NS064N sectors default DYB locked – VS064R sectors default DYB unlocked Command Set Changes – Unlock Bypass command removed VS064R is a 4-bank device, compared with the 8 banks of NS064N VS064R has different Device ID value than NS064N VS064R has changes in synchronous burst read – VS064R offers 108 MHz burst frequency, compared with the 66 MHz of NS064N – VS064R only supports modes 8 or 16 words with wrap-around, or continuous VS064R has differences in Electrical Specifications Hardware Migration Considerations VS064R has no WP# pin Table 2.1 Feature Comparisons (Sheet 1 of 2) Key Features Technology Process Node Data Bus Width NS064N VS064R MirrorBit MirrorBit 110 nm 65 nm 16-bit (Word) 16-bit (Word) Bus Interface VCC Temperature Range ADM ADM 1.70V to 1.95V 1.70V to 1.95V Wireless (-25°C to +85°C) Wireless (-25°C to +85°C) Common Flash Interface (CFI) Yes Yes Burst Frequency Order Options 66 MHz 108 MHz 8 / 16 / 32 with or without wrap-around / continuous 8 / 16 with wrap-around / continuous Burst Length (linear, words) Burst Mode can be automatically activated Yes No Sector Erase Architecture 16 kB small sectors, 64 kB large sectors 16 kB small sectors, 64 kB large sectors Boot Sector Architecture Top Top / Bottom 8 4 Unlock Cycles Unlock Cycles Banks Command Set Publication Number Migrate_S29NS064N_to_S29VS064R_AN Revision 01 Issue Date July 7, 2011 A pplication Note Table 2.1 Feature Comparisons (Sheet 2 of 2) Key Features NS064N VS064R DQ Polling Yes Yes Status Register No No Write Buffer Programming 64-byte Write Buffer 64-byte Write Buffer Single Word Programming Yes Yes Program Suspend / Resume Yes Yes Erase Suspend / Resume Yes Yes Low VCC Write Inhibit Yes Yes Hardware Sector Protection WP# and VPP pins VPP pin Software Sector Protection ASP (PPB, DYB, password) DYB 256 bytes factory locked 256 bytes factory locked Secure Silicon Region Program-Erase Endurance Data Retention 256 bytes customer lockable 256 bytes customer lockable 100,000 cycles per sector (typical) 100,000 cycles per sector (typical) 20-year (typical) 10-year (typical) 3. Software Sector Protection The VS064R simplifies the software sector protection. Instead of ASP supported in NS064N, VS064R supports Dynamic Protection Bits (DYBs) only. Refer to the NS064N and VS064R data sheet for a full explanation of ASP and DYB. VS064R sectors are default DYB unlocked. NS064N sectors are default DYB locked. After power up, NS064N needs to unlock the sectors before erasing and programming, while VS064R does not need to do this. 4. Command Set Changes VS064R has almost the same Command Set as NS064N. Except that the Unlock Bypass Mode is not supported in VS064R any more. The Spansion Low Level Driver (LLD) provides software examples for the command sets. The LLD can be downloaded from the Spansion web site (www.spansion.com). Select the “Drivers & Software” page from the “Support” menu. 2 Migrate_S29NS064N_to_S29VS064R_AN_01 July 7, 2011 App l ic atio n 5. No t e Flash Memory Array The VS064R is a 4-bank device, compared with the 8-banks of the NS064N. The sector sizes are the same for both. This difference in bank architecture may (or may not) requires software changes. In the example from Table 5.1, the Operating System image requires 1 MB of flash space, and it fits into bank 0 on NS064N, but on VS064R, it requires a separate bank to enable Simultaneous Read/Write, thus 2 MB of space is required for the OS. Table 5.1 NS064N to VS064R Bank/Sector Example NS064N VS064R Format of Flash Image Bank Sector Size Number of Sectors 0 64 kB 16 1 64 kB 16 2 64 kB 16 3 64 kB 16 4 64 kB 16 5 64 kB 16 6 64 kB 16 7 64 kB 15 16 kB 4 OS Image File System Volume Bootloader Bank Sector Size Number of Sectors 0 64 kB 32 1 64 kB 32 2 64 kB 32 64 kB 31 16 kB 4 3 6. Device ID Table 6.1 illustrates the differences in the Device ID between VS964R and NS064N. Table 6.1 NS064N vs. VS064R Device ID NS064N VS064R Description Word Offset Data Word Offset Data (BA) + 00h 0001h (SA) + 00h 0001h Device ID, Word 1 (BA) + 01h 2B7Eh (SA) + 01h 007Eh Device ID, Word 2 (BA) + 0Eh 2B33h (SA) + 0Eh Manufacture ID Device ID, Word 3 (BA) + 0Fh 2B00h (SA) + 0Fh DQ15 - DQ8 = Reserved DQ7 - Factory Lock Bit: 1 = Locked (BA) + 07h 0 = Not Locked DQ5 - Handshake Bit: 1 = Reserved 0 = Std Handshake DQ4 and DQ3 - WP# Protection Boot Code 01 = WP# protects the top boot sectors 0002h (bottom) DQ15 - DQ8 = Reserved DQ7 - Factory Lock Bit: 1 = Locked 0 = Not Locked DQ6 - Customer Lock Bit: 1 = Locked Indicator Bits 0061h 0001h (top) (SA) + 07h 0 = Not Locked DQ6 - Customer Lock Bit: 1 = Locked 0 = Not Locked DQ5 - DQ0 = Reserved DQ2 - DQ0 = Reserved July 7, 2011 Migrate_S29NS064N_to_S29VS064R_AN_01 3 A pplication 7. Note Synchronous Burst Read The VS064R supports synchronous burst read, but it does not support as many burst read modes as the NS064N. Table 7.1 highlights the modes supported. Refer to the VS064R data sheet for a full explanation of the synchronous burst read mode. Table 7.1 Synchronous Burst Read Mode Burst Read Mode Supported in NS064N Supported in VS064R Continuous Yes Yes 8-word with wrap-around Yes Yes 16-word with wrap-around Yes Yes 32-word with wrap-around Yes No 8-word without wrap-around Yes No 16-word without wrap-around Yes No 32-word without wrap-around Yes No Burst mode can be automatically activated Yes No The Configuration Register bits definition are a little different between NS064N and VS064R. Table 7.2 shows the Configuration Register comparison between these two devices. Table 7.2 Configuration Register Differences Between NS064N and VS064R CR Bit Function NS064N VS064R CR15 Reserved 0 = Default 0 = Default CR14 Reserved 0 = Default 0 = Default Programmable Wait State 000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) 110 = Reserved 111 = Reserved 000 = Reserved 001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) 110 = Data is valid on the 8τ ηactive CLK edge after AVD# transition to VIH 111 = Data is valid on the 9th active CLK edge after AVD# transition to VIH CR13 CR12 CR11 0 = RDY signal is active low 0 = RDY signal is active low 1 = RDY signal is active high (default) 1 = RDY signal is active high (default) CR10 RDY Polarity CR9 Reserved 1 = Default 1 = Default CR8 RDY 0 = RDY active one clock cycle before data 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 1 = RDY active with data (default) CR7 Reserved 1 = Default 1 = Default CR6 Reserved 1 = Default 1 = Default CR5 Reserved 0 = Default 0 = Default CR4 Reserved 0 = Default 0 = Default 0 = No Wrap Around Burst 0 = Reserved 1 = Wrap Around Burst (default) 1 = Wrap Around Burst (default) CR3 Burst Wrap Around 000 = Continuous (default) CR2 CR1 CR0 010 = 8-word Linear Burst Burst Length 011 = 16-word Linear Burst 100 = 32-word Linear Burst (All other bit settings are reserved) 4 Migrate_S29NS064N_to_S29VS064R_AN_01 000 = Continuous (default) 010 = 8-word Linear Burst 011 = 16-word Linear Burst (All other bit settings are reserved) July 7, 2011 App l ic atio n 8. No t e Hardware Sector Protection The VS064R does not have a WP# pin, which can be used to lock specific sectors for NS064N. The VS064R can lock all sectors with the VPP pin, similar to NS064N. Refer to the device data sheet for a full explanation of the hardware data protection methods. 9. Electrical Specification Differences Electrical considerations for porting from NS064N to VS064R are described in this section. Since there are several differences between burst read on the NS064N and the VS064R, burst read current and timings are not discussed here. Please refer to the device data sheets for a detailed description of electrical specifications. 9.1 DC Characteristics Table 9.1 DC Characteristics Parameter Source Min/Typ/Max NS064N VS064R ICC1 VCC Active Asynchronous Read Current (tested at 5 MHz) VCC Max 18 mA 40 mA ICC2 VCC Active Write Current VCC Typ 19 mA 30 mA 40 µA ICC3 Description VCC VCC Standby Current ICC6 VCC Sleep Current VCC IPP Accelerated Program Current VCC VLKO Low VCC Lock-out Voltage Typ 20 µA Max 70 µA 70 µA Typ 20 µA 40 µA Typ 20 mA 20 mA Max 30 mA 30 mA Min 1.0V 1.0V Max 1.4V 1.1V - VS064R has a higher current draw from VCC in some situations. This change in current should be noted, but the overall system impact is expected to minimal. 9.2 VCC Power-up Table 9.2 VCC Power-up Parameter Description Min or Max NS064N VS064R 300 µs tVCS VCC Setup Time Min 1 ms tVIOS VIO Setup Time Min - 300 µs Time Between RESET# (high) and CE# (low) Min - 200 ns tRH VS064R requires a minimum 300 µs VIO Setup time (tVIOS), and also a minimum 200 ns between RESET# (high) and CE# (low) (tRH). NS064N does not specify these requirements. When moving from NS064N to VS064R, the timing of Power-up should be checked to ensure these requirements are satisfied. Circuit changes may be needed to accommodate the new specification. July 7, 2011 Migrate_S29NS064N_to_S29VS064R_AN_01 5 A pplication 9.3 Note AC Characteristics Table 9.3 AC Characteristics Parameter Min or Max NS064N VS064R Output Enable to Output Valid Max 11 ns 18 ns tAVDO AVD# High to OE# Low Min 0 ns 0 ns tWEA WE# Disable to AVD# Enable Min - 9.6 ns tOE tOEH (data reads) tVLWH WE# Disable to OE# Enable Min 0 ns 0 ns AVD# Disable to WE# Disable Min - 23.5 ns CE# Low to RDY Valid Max - 10 ns tWEH OE# Disable to WE# Enable Min - 4 ns tESL Erase Suspend Latency Max 35 µs 30 µs tPSL Program Suspend Latency Max 35 µs 30 µs tCR 9.3.1 Description Output Enable to Output Valid (tOE) VS064R provides a read cycle output within 18 ns of OE# going low. NS064N provides a valid output within 11 ns. When changing from NS064N to VS064R, devices and components reading from flash must now wait at least 18 ns before latching data. 9.3.2 WE# Disable to AVD# Enable (tWEA) VS064R requires AVD# be driven low at least 9.6 ns after a write cycle. NS064N does not specify this requirement. When moving from NS064N to VS064R, the timing of back to back cycles should be checked to ensure this requirement is satisfied. The memory controller may need adjustment. 9.3.3 AVD# Disable to WE# Disable (tVLWH) For flash write cycles, VS064R requires WE# be driven high at least 23.5 ns after AVD# goes high. NS064N does not specify this requirement. When moving from NS064N to VS064R, the timing of write cycles should be checked to ensure this requirement is satisfied. The memory controller may need adjustment. 9.3.4 CE# Low to RDY Valid (tCR) When the flash device is not chip selected, the RDY pin is tri-stated to High-Z. Once the device is selected for read or write, VS064R provides a valid output on RDY within 10 ns of CE# going low. NS064N does not specify this parameter. When using VS064R, devices and components reading from the flash RDY pin must wait at least 10 ns before latching the value. 9.3.5 OE# Disable to WE# Enable (tWEH) For flash write cycles, VS064R requires WE# be driven low at least 4 ns after OE# goes high. NS064N does not specify this requirement. When moving from NS064N to VS064R, the timing of back to back cycles should be checked to ensure this requirement is satisfied. The memory controller may need adjustment. 6 Migrate_S29NS064N_to_S29VS064R_AN_01 July 7, 2011 App l ic atio n 9.4 No t e Erase and Program Performance Table 9.4 Erase and Program Performance Parameter Voltage NS064N (Max) VS064R (Max) 64 kB VCC 3s 3.5s 16 kB VCC 2s 2s VCC 400 µs 800 µs VCC 3000 µs 3000 µs VPP 1920 µs 1920 µs Sector Erase Time Single Word Programming Time Total 32-Word Buffer Programming Time VS064R could take longer to program and erase in certain cases, as shown in Table 9.4. Software timeouts should be checked to ensure they allow the applicable maximum time. 10. Packaging VS064R and NS064N are available in 44-ball, 0.50 mm pitch FBGA packages. The difference is that VS064R package has NC instead of WP#. 11. Conclusion VS064R provides a more cost-effective product, and offers several improvements over NS064N. Simplified sector protection Higher read performance (108 MHz) 12. References S29NS-N Data Sheet S29VS-XS064R Data Sheet July 7, 2011 Migrate_S29NS064N_to_S29VS064R_AN_01 7 A pplication Note 13. Revision History Section Description Revision 01 (July 7, 2011) Initial release 8 Migrate_S29NS064N_to_S29VS064R_AN_01 July 7, 2011 App l ic atio n No t e Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. July 7, 2011 Migrate_S29NS064N_to_S29VS064R_AN_01 9