DESIGN INFORMATION Component and Measurement Advances Ensure 16-Bit DAC by Jim Williams Settling Time (Part One) Introduction Instrumentation, waveform generation, data acquisition, feedback control systems and other application areas are beginning to utilize 16-bit data converters. More specifically, 16bit digital-to-analog converters (DACs) have seen increasing use. New components (see the sidebar “Components for 16-Bit Digital-to-Analog Conversion” on page 31) have made 16-bit DACs a practical design alternative. These ICs provide 16-bit performance at reasonable cost compared to previous modular and hybrid technologies. The DC and AC specifications of the monolithic DACs approach or equal previous converters at significantly lower cost. DAC Settling Time DAC DC specifications are relatively easy to verify. Measurement techniques are well understood, albeit often tedious. AC specifications require more sophisticated approaches to produce reliable information. In particular, the settling time of the DAC and its output amplifier is extraordinarily difficult to determine to 16-bit resolution. DAC settling time is the elapsed time from input code application until the output arrives at and DAC INPUT (ALL BITS) Considerations for Measuring DAC Settling Time Historically, DAC settling time has been measured with circuits similar to that in Figure 2. The circuit uses the “false sum node” technique. The resistors and DAC-amplifier form a bridge-type network. Assuming ideal resistors, the amplifier output will step to VIN when the DAC inputs move to all ones. During slew, the settle node is bounded by the diodes, limiting voltage excursion. When settling occurs, the oscilloscope probe voltage should be zero. Note that the resistor divider’s attenuation means the probe’s output will be one-half of the actual settled voltage. In theory, this circuit allows settling to be observed to small amplitudes. In practice, it cannot be relied upon to produce useful measurements. The oscilloscope connection presents problems. As probe capacitance rises, AC loading of the resistor junction influences observed settling waveforms. A 10pF probe alleviates this problem but its 10× attenuation sacrifices oscilloscope gain. 1× probes are not suitable because of their excessive input capacitance. An active INPUT STEP TO OSCILLOSCOPE DIGITAL INPUTS SETTLING TIME FB RING TIME DAC OUTPUT remains within a specified error band around the final value. It is usually specified for a full-scale 10V transition. Figure 1 shows that DAC settling time has three distinct components. The delay time is very small and is almost entirely due to propagation delay through the DAC and output amplifier. During this interval there is no output movement. During slew time the output amplifier moves at its highest possible speed towards the final value. Ring time defines the region where the amplifier recovers from slewing and ceases movement within some defined error band. There is normally a trade-off between slew and ring time. Fast-slewing amplifiers generally have extended ring times, complicating amplifier choice and frequency compensation. Additionally, the architecture of very fast amplifiers usually dictates trade-offs that degrade DC error terms. Measuring anything at any speed to 16 bits (≈0.0015%) is hard. Dynamic measurement to 16-bit resolution is particularly challenging. Reliable 16-bit settling-time measurement constitutes a high order difficulty problem requiring exceptional care in approach and experimental technique. SLEW TIME DELAY TIME INPUT FROM PULSE GENERATOR ALLOWABLE OUTPUT ERROR BAND – DAC REF OUTPUT AMPLIFIER + 0V TO 10V TRANSITION R DIGITAL INPUTS AN74 F01 SETTLE NODE OUTPUT TO OSCILLOSCOPE R – VREF Figure 1. DAC-settling-time components include delay, slew and ring times. Fast amplifiers reduce slew time, although longer ring time usually results. Delay time is normally a small term. 30 AN74 F02 Figure 2. Popular summing scheme for DAC-settling-time measurement provides misleading results. 16-bit measurement causes >200× oscilloscope overdrive. Displayed information is meaningless. Linear Technology Magazine • August 1998 DESIGN INFORMATION Components for 16-Bit D/A Conversion Components suitable for 16-bit D/A conversion are members of an elite class. 16 binary bits is one part in 65,536—just 0.0015% or 15 partsper -million. This mandates a vanishingly small error budget and the demands on components are high. The digital-to-analog converters listed in Table A all use Si-Chrome thin- film resistors for high stability and linearity over temperature. Gain drift is typically 1ppm/°C or about 2LSBs over 0°C to 70°C. The amplifiers shown contribute less than 1LSB error over 0°C to 70°C with 16-bit DAC driven settling times of 1.7µ s available. The references offer drifts as low as 1LSB over 0°C to 70°C with initial trimmed accuracy to 0.05% Table A. Short-form descriptions of components suitable for 16-bit digital-to-analog conversion Error Contribution Over 0°C to 70°C ≈2LSB Gain Drift ≈1LSB Linearity Component Type LTC1597 DAC LTC1595 DAC ≈2LSB Gain Drift ≈1LSB Linearity LTC1650 DAC ≈ 3.5LSB Gain Drift ≈6LSB Offset ≈4LSB Linearity LT1001 Amplifier <1LSB LT1012 Amplifier <1LSB LT1468 Amplifier <2LSB LM199A Reference: 6.95V ≈1LSB LT1021 Reference: 10V ≈ 4LSB LT1027 Reference: 5V ≈ 4LSB LT1236 Reference: 10V ≈10LSB LT1461 Reference: 4.096V ≈10LSB Comments Full Parallel Inputs Current Outputs Serial Input 8-Pin Package Current Output Complete Voltage Output DAC Good Low Speed Choice 10mA Output Capability Good Low Speed Choice Low Power Consumption 1.7µs Settling to 16 Bits Fastest Available Lowest Drift Reference in this Group Good General Purpose Choice Good General Purpose Choice Trimmed to 0.05% Absolute Accuracy Recommended for LTC1650 DACs (see Above) 1× FET probe will work, but another issue remains. The clamp diodes at the settle node are intended to reduce swing during a m p l i fi e r s l e w i n g , p r e v e n t i n g excessive oscilloscope overdrive. Unfortunately, oscilloscope overdrive recovery characteristics vary widely among different types and are not usually specified. The Schottky diodes’ 400mV drop means the oscilloscope may see an unacceptable overload, bringing displayed results into question. At 10-bit resolution (10mV at the DAC output—5mV at the oscilloscope), the oscilloscope typically undergoes a 2× overdrive at 50mV/ DIV and the desired 5mV baseline is just discernible. At 12-bit or higher resolution, the measurement becomes hopeless with this arrangement. Increasing oscilloscope gain brings commensurate increased vulnerability to overdrive induced errors. At 16 bits, there is clearly no chance of measurement integrity. The preceding discussion indicates that measuring 16-bit settling time requires a high gain oscilloscope that is somehow immune to overdrive. The gain issue is addressable with an external wideband preamplifier that accurately amplifies the diodeclamped settle node. Getting around the overdrive problem is more difficult. The only oscilloscope technology that offers inherent overdrive immunity is the classical sampling ’scope. INPUT STEP TO OSCILLOSCOPE DIGITAL INPUTS FB INPUT FROM PULSE GENERATOR – DAC REF OUTPUT AMPLIFIER PREAMPLIFIER + R DIGITAL INPUTS SETTLE NODE SWITCH OUTPUT TO OSCILLOSCOPE R – VREF DELAYED PULSE GENERATOR AN74 F03 Figure 3. Conceptual arrangement eliminates oscilloscope overdrive. A delayed pulse generator controls the switch, preventing the oscilloscope from monitoring settle node until settling is nearly complete. Linear Technology Magazine • August 1998 31 DESIGN INFORMATION TIME CORRECTED INPUT STEP TO OSCILLOSCOPE BRIDGE DRIVER/RESIDUE AMPLIFIER DELAY COMPENSATION DIGITAL INPUTS FB INPUT FROM PULSE GENERATOR – DAC REF 0V TO 10V TRANSITION + OUTPUT AMPLIFIER DIGITAL INPUTS SAMPLING BRIDGE SWITCH SAMPLING BRIDGE DRIVER RESIDUE AMPLIFIER R SETTLE NODE ×1 × 40 R OUTPUT TO OSCILLOSCOPE 0.01V/DIV = 500µV/DIV AT DAC AMPLIFIER OUTPUT – VREF BRIDGE SWITCHING CONTROL DELAYED PULSE GENERATOR VARIABLE DELAY SAMPLING BRIDGE TEMPERATURE CONTROL VARIABLE WIDTH PULSE GENERATOR AN74 F04 Figure 4. Block diagram of DAC-settling-time measurement scheme: diode bridge switch minimizes switching feedthrough, preventing residue-amplifier oscilloscope overdrive. Temperature control maintains 10µV switch offset baseline. Input step-time reference is compensated for ×1 and ×40 amplifier delays. Unfortunately, these instruments are no longer manufactured (although still available on the secondary market). It is possible, however, to construct a circuit that borrows the overload advantages of classical sampling ’scope technology. Additionally, the circuit can be endowed with features particularly suited for measuring 16bit DAC settling time. Practical DACSettling-Time Measurement Figure 3 is a conceptual diagram of a 16-bit DAC-settling-time measurement circuit. This figure shares attributes with Figure 2, although some new features appear. In this case, the preamplified oscilloscope is connected to the settle point by a switch. The switch state is determined by a delayed pulse generator, which is triggered from the same pulse that controls the DAC. The delayed pulse generator’s timing is arranged so that the switch does not close until settling is very nearly complete. In this way the incoming waveform is sampled in time, as well as amplitude. The oscilloscope is never subjected to overdrive—no off-screen activity ever occurs. Figure 4 is a more complete representation of the DAC settling time scheme. Figure 3’s blocks appear in 32 greater detail and some new refinements show up. The DAC-amplifier summing area is unchanged. Figure 3’s delayed pulse generator has been split into two blocks; a delay and a pulse generator, both independently variable. The input step to the oscilloscope runs through a section that compensates for the propagation delay of the settling-time-measurement path. The most striking new aspect of the diagram is the diode bridge switch. Borrowed from classical sampling oscilloscope circuitry, it is the key to the measurement. The diode bridge’s inherent balance eliminates charge- injection-based errors in the output. It is far superior to other electronic switches in this characteristic. Any other high speed switch technology contributes excessive output spikes due to charge-based feedthrough. FET switches are not suitable because their gate-channel capacitance permits such feedthrough. This capacitance allows gate-drive artifacts to corrupt the oscilloscope display, inducing overload and defeating the switch’s purpose. The diode bridge’s balance, combined with matched, low capacitance, monolithic diodes and complementary high speed switching, yields a cleanly ON OFF V+ V– AC BALANCE SKEW COMPENSATION ALL DIODES = CA3039 MONOLITHIC ARRAY OUTPUT INPUT SENSE HEAT DC BALANCE + V– V+ ON OFF V+ – BRIDGE TEMPERATURE CONTROL AN74 F05 Figure 5. Diode bridge switch trims include AC and DC balance and switch drive timing skew. Remaining diodes in monolithic array are used for temperature control. Linear Technology Magazine • August 1998 DESIGN INFORMATION switched output. The monolithic diode bridge is also temperature controlled, providing a bridge offset error below 10µ V, stabilizing the measurement baseline. The temperature control is implemented using uncommitted diodes in the monolithic array as heater and sensor. Figure 5 details considerations for the diode bridge switch. The bridge diodes tend to cancel each other’s temperature coefficient—unstabilized bridge drift is about 100µV/°C and the temperature control reduces residual drift to a few microvolts/°C. Bridge temperature control is achieved by using one diode as a sensor. Another diode, running in reverse breakdown (V Z ≈ 7V), serves as the heater. The control amplifier, comparing the sensor diode to a voltage at its negative terminal, drives the heater diode to temperature stabilize the array. DC balance is achieved by trimming the bridge on-current for zero input– output offset voltage. Two AC trims are required. The “AC balance” corrects for diode and layout capacitive imbalances and the “skew compensation” corrects for any timing asymmetry in the nomi- nally complementary bridge drive. These AC trims compensate small dynamic imbalances that could result in parasitic bridge outputs. Conclusion This concludes part one of this article. Part two, which will appear in the November issue of Linear Technology magazine, details the settling time cir cuitry and presents results. Both parts represent a distillation of a full-length LTC application note, AN74, Component and Measurement Advances Ensure 16-Bit DAC Settling Time. New 16-Bit Bipolar Output DAC in Narrow SO-16 Package by Hassan Malik Linear Technology introduces its first bipolar, voltage output 16-bit digital to analog converter, the LTC1650. The LTC1650 is available in a narrow 16-pin SO package, making it the smallest bipolar, 16-bit voltage output DAC on the market today. The LTC1650 operates from ± 5V supplies and draws 5mA. It is equipped with a rail-to-rail, low noise, deglitched output amplifier that can be configured to operate in a unipolar or bipolar mode. The mid-scale glitch is under 2nV-s and the full-scale settling time in unipolar mode is 4µ s. The LTC1650 is 16-bit monotonic over the industrial temperature range, 5V 3 8 CLK 7 DOUT 5V MICROWIRE is a trademark of National Semiconductor Corp. 4.096V DVDD 11 RSTOUT REFHI 15 10 AVDD 1.0 0.8 POWER-ON RESET SUPPLY SENSE 16-BIT DAC REGISTER 5 16-BIT SHIFT REGISTER DIN cleared. There are supply brown-out detectors on all three supplies, AVDD, DVDD and AV SS. When any of these supplies drops below 2.5V, the part is cleared, connecting the output to VRST, and the RSTOUT pin changes to a logic low. The 3-wire serial interface of the LTC1650 is SPI/QSPI and MICROWIRE™ compatible. All the logic inputs are TTL/CMOS compatible and the CLK input is equipped with a Schmitt trigger that allows direct optocoupler interfacing. There is also a DOUT pin for daisy-chaining several DACs. The digital feedthrough is 0.05nV-s. 9 CLR 2 VRST 16-BIT DAC + 1 VOUT – 0.6 DNL ERROR (LSB) CS/LD with a typical differential nonlinearity of less than ±0.3LSB. Figures 1 and 2 show a typical application for the part and its DNL curve. The LTC1650 is equipped with an outputspan-setting resistor tied to the UNI/ BIP pin. When this pin is tied to the VOUT pin, the output will swing from REFLO to REFHI; when the pin is tied to REFHI, the output swings from –REFHI to REFHI. The LTC1650 has a user-defined voltage to which its output resets on power-up or when the part is cleared. The voltage on the VRST pin is applied to the output through a transmission gate when the part powers up or is 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 6 0 16 4 DGND 12,13 REFLO 14 – 5V Figure 1. LTC1650 block diagram Linear Technology Magazine • August 1998 AVSS UNI/BIP 16384 32768 CODE 49152 65535 1650 TA02 1650 TA01 Figure 2. The LTC1650 bipolar output DAC has ±0.3LSB typical DNL. 33