DESIGN FEATURES 48 Volt Hot Swap Controller for Negative Voltages by Henry Yun and Robert Reay Introduction As supply voltages for PC boards continue to drop, designers face the difficult task of minimizing the voltage drops through distributed power systems. At operating voltages of 3.3V or lower, the voltage drops across power busses, connector pins and inrush control circuitry can cause a supply voltage to drop out of tolerance. A solution to this problem is to distribute power at a high voltage, commonly 48V, and then step the voltage down to the final desired value on each board in the system, using power modules. Most 48V power modules require an input bypass capacitor with a typical value of hundreds of microfarads. When the board is hot-plugged into a live 48V power rail, the input capacitor can draw huge inrush currents as it charges. The inrush current can cause permanent damage to the board’s components and create glitches on the system power supply that can make the system function improperly. The LTC1640H and LTC1640L provide a simple, flexible solution to –48V hot-swapping problems. The chips allow a board to be safely inserted into or removed from a live backplane with a supply voltage from –10V to –80V. They feature programmable inrush current control, programmable undervoltage and overvoltage protec- tion, a programmable electronic circuit breaker and direct power-module-enable control. DRAIN voltage has finished increasing, the voltage on the GATE pin then rises to its final value. Power Supply Control Electronic Circuit Breaker A typical LT1640 application is shown in Figure 1. The input voltage of the power module on a circuit board is controlled by gradually increasing the gate voltage of the external N-channel pass MOSFET (Q1) in the power path. R1 provides current fault detection and R2 prevents high frequency oscillation. Resistors R4, R5 and R6 provide undervoltage and overvoltage sensing. Resistor R3 and capacitor C2 act as a feedback network to accurately control the inrush current. The waveforms are shown in Figure 2. The inrush current can be calculated with the following equation: The LT1640 features an electronic circuit-breaker function that protects against short circuits or excessive supply currents. By placing a sense IINRUSH = (45µA × CL)/ C2 Figure 2. Inrush-current control waveforms where CL is the total load capacitance. Resistor R3 helps keep Q1 off when the power pins first make contact. When the power pins make contact, they bounce several times. While the contacts are bouncing, the LT1640 senses an undervoltage condition and the GATE is immediately pulled low. Once the power pins stop bouncing, the GATE pin starts increasing until when Q1 turns on and the GATE voltage is held constant by the feedback network of R3 and C2. When the Figure 3. Short-circuit protection waveforms GND R4 562k 1% UV = 37V OV = 71V R5 9.09k 1% R6 10k 1% LUCENT JW050A1-E 8 C3 0.1µF 100V VDD 3 UV LT1640L 2 PWRGD + C4 100µF 100V 1 OV VEE GATE SENSE 4 5 R1 0.02Ω 5% – 48V DRAIN 6 C1 33nF 25V R2 10Ω 5% 1 VIN+ VOUT+ 9 8 SENSE + 7 2 ON/OFF TRIM 6 SENSE – 5 4 – – VOUT VIN 5V + C5 100µF 16V 7 R3 C2 10k 5% 3.3nF 100V 1640 TA01 Q1 IRF530 Figure 1. Typical LT1604 application with a power module Linear Technology Magazine • August 1998 19 DESIGN FEATURES GND R7 1M 5% 2 C4 1µF 100V Q2 2N2222 8 R4 562k 1% VDD 3 R5 9.09k 1% LT1640L 2 R6 10k 1% 3 Q3 ZVN3310 UV + C3 100µF 100V OV VEE GATE SENSE 5 4 R8 510k 5% D1 1N4148 1 PWRGD R1 0.02Ω 5% – 48V DRAIN 6 7 R2 R3 10Ω 10k C2 5% 5% 3.3nF 100V C1 33nF 25V Q1 IRF530 1640 F10a Figure 4b. Waveforms of Figure 4a’s circuit Figure 4a. This circuit resets the circuit breaker after a current fault. resistor between the V EE and SENSE pins, the circuit breaker will be tripped whenever the voltage across the sense resistor is greater than 50mV for more than 3µ s, as shown in Figure 3. When the circuit breaker trips, the GATE pin is immediately pulled to VEE and the external N-channel MOSFET is turned off. The GATE pin will remain low until the circuit breaker is reset by pulling UV low then high or cycling power to the part. A circuit that automatically resets the circuit breaker after a current fault is shown in figure 4. Transistors Q2 and Q3, along with R7, R8, C4 and D1, form a programmable one-shot circuit. Before a short occurs, the GATE pin is pulled high and Q3 is turned on, pulling node 2 to VEE. Resistor R8 turns off Q2. When a short occurs, the GATE pin is pulled low and Q3 turns off. Node 2 starts to charge C4, and Q2 turns on, pulling the UV pin low and resetting the circuit breaker. As soon as C4 is fully With R4 = 562k, R5 = 9.09k and R6 = 10k, the undervoltage threshold is set to 37V and the overvoltage threshold is set to 71V. charged, R8 turns off Q2, UV goes high and the voltage on the GATE starts to increase. Q3 turns back on and quickly pulls node 2 back to VEE. Diode D1 clamps node 3 one diode drop below VEE. The duty cycle is set t o 1 0 % t o p r e v e n t Q 1 f ro m overheating. PWRGD/PWRGD Output The PWRGD/PWRGD output can be used to directly enable a power module when the input voltage to the module is within tolerance. The LT1640H has a PWRGD output for modules with an active-high enable input, and the LT1640L has a PWRGD output for modules with an activelow enable input. When the DRAIN pin of the LT1640H is more than VPG (1.4V) above VEE (see Figure 6), internal transistor Q3 is turned off and R7 and Q2 clamp the PWRGD pin one diode drop (~0.7V) above the DRAIN pin. Transistor Q2 sinks the module’s pull-up current and the module turns off. Undervoltage and Overvoltage Detection The UV (3) and OV (2) pins can be used to detect undervoltage and overvoltage conditions at the power supply input. The UV and OV pins are internally connected to analog comparators with 20mV of hysteresis. When the UV pin falls below its threshold or the OV pin rises above its threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until UV is high and OV is low. The undervoltage and overvoltage trip voltages can be programmed using a 3-resistor-divider, as shown in Figure 5. ACTIVE HIGH ENABLE MODULE VIN+ GND 8 3 GND R5 8 VUV = 1.223 VOV = 1.223 ( ( R4 + R5+ R6 R5 + R6 R4 + R5+ R6 R6 ) ) R4 VDD 3 2 R6 UV + 2 PWRGD R7 5k + 1 + ON/OFF C3 Q2 VIN– Q3 OV 1.4V VOUT– – – UV VEE DRAIN 7 R6 VEE LT1640H LT1640L R5 VDD LT1640H R4 VOUT+ SENSE 4 OV GATE 5 VEE 6 C1 R2 R3 C2 4 – 48V R1 1640 F11 – 48V Figure 5. Undervoltage and overvoltage sensing 20 1640 F12 Q1 Figure 6. Active-high enable module Linear Technology Magazine • August 1998 DESIGN FEATURES ACTIVE LOW ENABLE MODULE VIN+ GND 8 R4 3 R5 VDD LT1640L 2 PWRGD 1 + Q2 UV + + 1.8V – OV ON/OFF C3 VIN– VEE DRAIN – VOUT+ the GATE voltage will be about 2V below the supply voltage. At the minimum 10V supply voltage, the gate voltage is guaranteed to be greater than 6V and no greater than 18V for supply voltages up to 80V. VOUT– Conclusion 7 LT1640 provides a simple and flexible solution for hot swap applications. It 4 5 6 is the first part that allows system R3 designers to connect an 80V supply C2 C1 R2 directly to the chip without any voltR1 age step-down circuitry. It can be – 48V Q1 programmed to control the output voltage slew up rate and the inrush Figure 7. Active-low enable module current. It has programmable undervoltage and overvoltage protection, and When the DRAIN pin drops below Gate Pin Voltage Regulation the PWRGD/PWRGD output can be VPG, Q3 will turn on, shorting the When the supply voltage to the chip is tied directly to a power-module enable bottom of R7 to VEE and turning Q2 more than 15.5V, the GATE pin volt- pin. The LT1640 simplifies the design off. The pull-up current in the module age is regulated at 13.5V above VEE. If of high voltage hot-swap control systhen flows through the R7, pulling the the supply voltage is less than 15.5V, tems and combines all of these features PWRGD pin high and enabling the in an 8-pin SO/PDIP package. module. GND When the DRAIN pin of the LT1640L R7 is more than VPG (1.4V) above VEE, the 51k PWRGD 5% 8 R4 internal pull-down transistor, Q2, is 562k + C3 VDD off and the PWRGD pin is in high 1% 100µF 3 100V UV 4N25 impedance state (see Figure 7). The R5 1 LT1640L PWRGD 9.09k PWRGD pin will be pulled high by the 2 1% OV module’s internal pull-up current R6 VEE SENSE GATE DRAIN source, turning the module off. When 10k 1% 4 5 6 7 the DRAIN pin drops below VPG , Q2 R2 C1 will turn on, and the PWRGD pin will R3 10Ω 10k C2 33nF R1 be pulled low, enabling the module. 5% 5% 3.3nF 25V 0.02Ω 100V The PWRGD signal can also be 5% – 48V used to turn on an LED or optoisolaQ1 IRF530 tor to indicate that the power is good, Figure 8. Using PWRGD to drive an optoisolator as shown in Figure 8. R6 VEE SENSE GATE 1640 F13 1640 F14 Authors can be contacted at (408) 432-1900 Linear Technology Magazine • August 1998 for the latest information on LTC products, visit www.linear-tech.com 21