LT1640L/LT1640H Negative Voltage Hot Swap Controller U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ The LT®1640L/LT1640H is an 8-pin, negative voltage Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Inrush current is limited to a programmable value by controlling the gate voltage of an external N-channel pass transistor. The pass transistor is turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. A programmable electronic circuit breaker protects the system against shorts. The PWRGD (LTC1640L) or PWRGD (LTC1640H) signal can be used to directly enable a power module. The LT1640L is designed for modules with a low enable input and the LT1640H for modules with a high enable input. Allows Safe Board Insertion and Removal from a Live – 48V Backplane Operates from –10V to – 80V Programmable Inrush Current Programmable Electronic Circuit Breaker Programmable Overvoltage Protection Programmable Undervoltage Lockout Power Good Control Output U APPLICATIONS ■ ■ ■ Central Office Switching – 48V Distributed Power Systems Negative Power Supply Control The LT1640L/LT1640H is available in 8-pin PDIP and SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATION Input Inrush Current GND R4 562k 1% UV = 37V OV = 71V R5 9.09k 1% R6 10k 1% 8 VDD 3 CONTACT BOUNCE UV LT1640L 2 1 PWRGD OV VEE SENSE 4 R1 0.02Ω 5% GATE 5 DRAIN 6 – 48V 7 R2 10Ω 5% C1 33nF 24V R3 10k 5% C2 3.3nF 100V Q1 IRF530 2 1 C3 0.1µF 100V + C4 100µF 100V 4 ON/OFF 9 VOUT+ VIN 8 SENSE + 7 TRIM 6 SENSE – 5 VOUT– VIN– + 5V + C5 100µF 16V 1640 F07b LUCENT JW050A1-E 1640 TA01 1 LT1640L/LT1640H U W W W ABSOLUTE MAXIMUM RATINGS (Note 1), All Voltages Referred to VEE Supply Voltage (VDD – VEE) .................... – 0.3V to 100V DRAIN, PWRGD, PWRGD Pins ............... – 0.3V to 100V SENSE, GATE Pins .................................... – 0.3V to 20V UV, OV Pins .............................................. – 0.3V to 60V Maximum Junction Temperature ......................... 125°C Operating Temperature Range LT1640LC/LT1640HC ............................. 0°C to 70°C LT1640LI/LT1640HI .......................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C W U U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW PWRGD 1 8 VDD OV 2 7 DRAIN UV 3 6 GATE VEE 4 5 SENSE N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 120°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) LT1640LCN8 LT1640LCS8 LT1640LIN8 LT1640LIS8 S8 PART MARKING ORDER PART NUMBER TOP VIEW PWRGD 1 8 VDD OV 2 7 DRAIN UV 3 6 GATE VEE 4 5 SENSE N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO LT1640HCN8 LT1640HCS8 LT1640HIN8 LT1640HIS8 S8 PART MARKING TJMAX = 125°C, θJA = 120°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) 1640L 1640LI 1640H 1640HI Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Note 2), VDD = 48V, VEE = 0V, TA = 25°C unless otherwise noted. CONDITIONS MIN TYP MAX UNITS DC VDD Supply Voltage IDD Supply Current VCB IPU ● 10 V 5 mA UV = 3V, OV = VEE, SENSE = VEE ● Circuit Breaker Trip Voltage VCB = (VSENSE – VEE) ● 40 50 60 mV GATE Pin Pull-Up Current Gate Drive On, VGATE = VEE ● – 30 – 45 – 60 µA IPD GATE Pin Pull-Down Current Any Fault Condition 24 50 70 mA ISENSE SENSE Pin Current VSENSE = 50mV ∆VGATE External Gate Drive (VGATE – VEE), 15V ≤ VDD ≤ 80V (VGATE – VEE), 10V ≤ VDD < 15V ● ● 10 6 13.5 8 18 15 V V VUVH UV Pin High Threshold Voltage UV Low to High Transition ● 1.213 1.243 1.272 V VUVL UV Pin Low Threshold Voltage UV High to Low Transition ● 1.198 1.223 1.247 VUVHY UV Pin Hysteresis IINUV UV Pin Input Current VUV = VEE ● VOVH OV Pin High Threshold Voltage OV Low to High Transition ● VOVL OV Pin Low Threshold Voltage OV High to Low Transition ● VOVHY OV Pin Hysteresis IINOV OV Pin Input Current VOV = VEE ● 2 1.3 80 µA – 20 20 V mV – 0.02 – 0.5 µA 1.198 1.223 1.247 V 1.165 1.203 1.232 V 20 – 0 .03 mV – 0.5 µA LT1640L/LT1640H ELECTRICAL CHARACTERISTICS VDD = 48V, VEE = 0V, TA = 25°C unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX VPG Power Good Threshold VDRAIN – VEE, High to Low Transition 1.1 1.4 2.0 UNITS VPGHY Power Good Threshold Hysteresis VOL Output Low Voltage PWRGD (LT1640L), IOUT = 1mA, (VDRAIN – VEE) < VPG ● ROUT Power Good Output Impedance PWRGD (LT1460H), (VDRAIN – VEE) < VPG ● tPHLOV OV High to GATE Low tPHLUV UV Low to GATE Low tPLHOV OV Low to GATE High tPLHUV UV High to GATE High tPHLSENSE SENSE High to Gate Low Figures 1, 4 tPHLPG DRAIN Low to PWRGD Low DRAIN Low to (PWRGD – DRAIN) High (LT1640L) Figures 1, 5 (LT1640H) Figures 1, 5 0.5 0.5 µs µs tPLHPG DRAIN High to PWRGD High DRAIN High to (PWRGD – DRAIN) Low (LT1640L) Figures 1, 5 (LT1640H) Figures 1, 5 0.5 0.5 µs µs V 0.4 0.48 2 V 0.8 V 6.5 kΩ Figures 1, 2 1.7 µs Figures 1, 3 1.5 µs Figures 1, 2 5.5 µs Figures 1, 3 6.5 µs AC 2 The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 3 µs 4 Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage Supply Current vs Temperature 1.8 15 14 1.5 1.5 1.4 1.3 1.2 13 GATE VOLTAGE (V) 1.6 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 1.7 1.4 1.3 1.2 12 11 10 9 8 1.1 1.1 0 Gate Voltage vs Supply Voltage 1.6 7 0 20 40 80 60 SUPPLY VOLTAGE (V) 100 1640 G01 1.0 – 50 – 25 0 25 50 TEMPERATURE (°C) 75 100 1640 G02 6 0 20 80 60 40 SUPPLY VOLTAGE (V) 100 1640 G03 3 LT1640L/LT1640H U W TYPICAL PERFOR A CE CHARACTERISTICS 55 48 14.5 54 47 14.0 13.5 13.0 12.5 GATE PULL-UP CURRENT (µA) 15.0 TRIP VOLTAGE (mV) GATE VOLTAGE (V) Gate Pull-Up Current vs Temperature Circuit Breaker Trip Voltage vs Temperature Gate Voltage vs Temperature 53 52 51 50 49 12.0 – 50 – 25 25 50 0 TEMPERATURE (°C) 75 – 25 50 0 25 TEMPERATURE (°C) 75 1640 G04 52 49 46 43 75 100 – 25 0 25 50 TEMPERATURE (°C) 75 PWRGD Output Impedance vs Temperature (LT1640H) 8 7 0.4 0.3 0.2 0.1 0 – 50 100 1640 G06 OUTPUT IMPEDANCE (Ω) PWRGD OUTPUT LOW VOLTAGE (V) GATE PULL-DOWN CURRENT (mA) 42 40 – 50 100 0.5 0 50 25 TEMPERATURE (°C) 43 PWRGD Output Low Voltage vs Temperature (LT1640L) 55 – 25 44 1640 G05 Gate Pull-Down Current vs Temperature 40 – 50 45 41 48 – 50 100 46 6 5 4 3 – 25 25 50 0 TEMPERATURE (°C) 1640 G07 75 100 1640 G08 2 – 50 – 25 0 25 50 TEMPERATURE (°C) 75 100 1640 G09 U U U PIN FUNCTIONS PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin will toggle when VDRAIN is within VPG of VEE. This pin can be connected directly to the enable pin of a power module. When the DRAIN pin of the LT1640L is above VEE by more than VPG, the PWRGD pin will be high impedance, allowing the pull-up current of the module’s enable pin to pull the pin high and turn the module off. When VDRAIN drops below VPG, the PWRGD pin sinks current to VEE, pulling the enable pin low and turning on the module. When the DRAIN pin of the LT1640H is above VEE by more than VPG, the PWRGD pin will sink current to the DRAIN 4 pin which pulls the module’s enable pin low, forcing it off. When VDRAIN drops below VPG, the PWRGD sink current is turned off and a 5k resistor is connected between PWRGD and DRAIN, allowing the module’s pull-up current to pull the enable pin high and turn on the module. OV (Pin 2): Analog Overvoltage Input. When OV is pulled above the 1.223V low to high threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.203V high to low threshold. LT1640L/LT1640H U U U PIN FUNCTIONS UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.223V high to low threshold, an undervoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV rises above the 1.243 low to high threshold. The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. VEE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply. SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between VEE and SENSE, the circuit breaker will trip when the voltage across the resistor exceeds 50mV. Noise spikes of less than 2µs are filtered out and will not trip the circuit breaker. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, VEE and SENSE can be shorted together. GATE (Pin 6): Gate Drive Output for the External N-Channel. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low and (VSENSE – VEE) < 50mV. The GATE pin is pulled high by a 45µA current source and pulled low with a 50mA current source. DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel and the V – pin of the power module. When the DRAIN pin is below VPG, the PWRGD or PWRGD pin will toggle. VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V + pin of the power module. The input supply voltage ranges from 10V to 80V. W BLOCK DIAGRA VDD – UV VCC AND REFERENCE GENERATOR + VCC REF OUTPUT DRIVE PWRGD/PWRGD REF – OV + 50mV –+ LOGIC AND GATE DRIVE – + + + – – VPG VEE 1640 BD VEE SENSE GATE DRAIN 5 LT1640L/LT1640H TEST CIRCUIT R 5k V+ 5V PWRGD/PWRGD VDD VOV + – DRAIN OV VDRAIN LT1640L/LT1460H UV GATE VEE SENSE 48V C 0.033µF VUV VSENSE 1640 F01 Figure 1. Test Circuit W UW TIMING DIAGRAMS 2V OV 1.223V 1.203V 50mV SENSE 0V tPHLOV tPHLSENSE tPLHOV GATE GATE 1V 1V 1V 1640 F02 1640 F04 Figure 2. OV to GATE Timing 2V UV Figure 4. SENSE to GATE Timing 1.8V 1.223V 1.243V VEE 0V tPHLUV GATE 1.4V DRAIN tPLHPG tPLHUV PWRGD 1V 1V VEE 1640 F03 1V 1.8V Figure 3. UV to GATE Timing tPHLPG 1V 1.4V DRAIN 0V PWRGD VPWRGD – VDRAIN = 0V tPLHPG tPHLPG 1V 1V Figure 5. DRAIN to PWRGD/PWRGD Timing 6 1640 F05 LT1640L/LT1640H U U W U APPLICATIONS INFORMATION Hot Circuit Insertion IINRUSH = (45µA • CL)/C2 When circuit boards are inserted into a live –48V backplane, the bypass capacitors at the input of the board’s power module or switching power supply can draw huge transient currents as they charge up. The transient currents can cause permanent damage to the board’s components and cause glitches on the system power supply. where CL is the total load capacitance. Capacitor C1 and resistor R3 prevent Q1 from momentarily turning on when the power pins first make contact. Without C1 and R3, capacitor C2 would pull the gate of Q1 up to a voltage roughly equal to VEE • C2/CG(Q1) before the LT1640 could power up and actively pull the gate low. By placing capacitor C1 parallel with the gate capacitance of Q1 and isolating them from C2 using resistor R3 the problem is solved. The value of C1 should be 10 times the value of C and R3 • C1 ≈ 300µs. The LT1640 is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides undervoltage, overvoltage and overcurrent protection while keeping the power module off until its input voltage is stable and within tolerance. Power Supply Ramping CONTACT BOUNCE The input to the power module on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path (Figure 6a, all waveforms are with respect to the VEE pin of the LT1640). R1 provides current fault detection and R2 prevents high frequency oscillations. Resistors R4, R5 and R6 provide undervoltage and overvoltage sensing. By ramping the gate of Q1 up at a slow rate, the surge current charging load capacitors C3 and C4 can be limited to a safe value when the board makes connection. Resistor R3 and capacitor C2 act as a feedback network to accurately control the inrush current. The inrush current can be calculated with the following equation: 1640 F07b Figure 6b. Inrush Control Waveforms GND R4 562k 1% UV = 37V OV = 71V R5 9.09k 1% R6 10k 1% C3 0.1µF 100V VDD 3 UV LT1640H 2 PWRGD + C4 100µF 100V 1 VIN+ VOUT+ VEE SENSE 4 GATE 5 6 C1 0.033µF 24V VIN– DRAIN 5V + GATE IN OV R1 0.02Ω 5% – 48V VICOR VI-J3D-CY 8 C5 100µF 16V VOUT– 7 R2 R3 10Ω 10k C2 5% 5% 3.3nF 100V 1640 F06a Q1 IRF530 Figure 6a. Inrush Control Circuitry 7 LT1640L/LT1640H U W U U APPLICATIONS INFORMATION The waveforms are shown in Figure 6b. When the power pins make contact, they bounce several times. While the contacts are bouncing, the LT1640 senses an undervoltage condition and the GATE is immediately pulled low when the power pins are disconnected. Once the power pins stop bouncing, the GATE pin starts to ramp up. When Q1 turns on, the GATE voltage is held constant by the feedback network of R3 and C2. When the DRAIN voltage has finished ramping, the GATE pin then ramps to its final value. Electronic Circuit Breaker The LT1640 features an electronic circuit breaker function that protects against short circuits or excessive supply currents. By placing a sense resistor between the VEE and SENSE pin, the circuit breaker will be tripped whenever the voltage across the sense resistor is greater than 50mV for more than 3µs as shown in Figure 7. GATE pin will remain low until the circuit breaker is reset by pulling UV low, then high or cycling power to the part. If more than 3µs deglitching time is needed to reject current noise, an external resistor and capacitor can be added to the sense circuit as shown in Figure 8. R7 and C3 act as a lowpass filter that will slow down the SENSE pin voltage from rising too fast. Since the SENSE pin will source current, typically 20µA, there will be a voltage drop on R7. This voltage will be counted into the circuit breaker trip voltage just as the voltage across the sense resistor. A small resistor is recommended for R7. A 100Ω for R7 will cause a 2mV error. The following equation can be used to estimate the delay time at the SENSE pin: V( t) – V( tO ) t = –R • C • In 1 – Vi – V( tO ) Where V(t) is the circuit breaker trip voltage, typically 50mV. V(tO) is the voltage drop across the sense resistor before the short or over current condition occurs. Vi is the voltage across the sense resistor when the short current or over current is applied on it. Example: A system has a 1A current load and a 0.02Ω sense resistor is used. An extended delay circuit needs to be designed for a 50µs delay time after the load jumps to 5A. In this case: V(t) = 50mV V(tO) = 20mV Vi = 5A • 0.02Ω = 100mV If we choose R = 100Ω, we will get C = 1µF. GND R4 562k 1% 1640 F07 Figure 7. Short-Circuit Protection Waveforms Note that the circuit breaker threshold should be set sufficiently high to account for the sum of the load current and the inrush current. If the load current can be controlled by the PWRGD/PWRGD pin (as in Figure 6a), the threshold can be set lower, since it will never need to accommodate inrush current and load current simultaneously. When the circuit breaker trips, the GATE pin is immediately pulled to VEE and the external N-channel turns off. The 8 UV = 37V OV = 71V R5 9.09k 1% R6 10k 1% 8 VDD 3 UV LT1640L /LT1640H 2 OV VEE SENSE 4 C3 R1 0.02Ω 5% – 48V PWRGD/ PWRGD GATE 5 R7 + CL 100µF 100V DRAIN 6 C1 0.033µF 24V 1 7 R2 R3 10Ω 10k C2 5% 5% 3.3nF 100V Q1 IRF530 1640 F08 Figure 8. Extending the Short-Circuit Protection Delay LT1640L/LT1640H U U W U APPLICATIONS INFORMATION Under some conditions, a short circuit at the output can cause the input supply to dip below the UV threshold, resetting the circuit breaker immediately. the GATE pin is pulled high and Q3 is turned on, pulling node 2 to VEE. Resistor R8 turns off Q2. When a short occurs, the GATE pin is pulled low and Q3 turns off. Node 2 starts to charge C4 and Q2 turns on, pulling the UV pin low and resetting the circuit breaker. As soon as C4 is fully charged, R8 turns off Q2, UV goes high and the GATE starts to ramp up. Q3 turns back on and quickly pulls node 2 back to VEE. Diode D1 clamps node 3 one diode drop below VEE. The duty cycle is set to 10% to prevent Q1 from overheating. The LT1640 then cycles on and off repeatedly until the short is removed. This can be minimized by adding a deglitching delay to the UV pin with a capacitor from UV to VEE. This capacitor forms an RC time constant with the resistors at UV, allowing the input supply to recover before the UV pin resets the circuit breaker. A circuit that automatically resets the circuit breaker after a current fault is shown in Figure 9. Undervoltage and Overvoltage Detection Transistors Q2 and Q3 along with R7, R8, C4 and D1 form a programmable one-shot circuit. Before a short occurs, The UV (Pin 3) and OV (Pin 2) pins can be used to detect undervoltage and overvoltage conditions at the power GND R7 1M 5% R4 562k 1% 2 C4 1µF 100V Q2 2N2222 D1 1N4148 – 48V R5 9.09k 1% 3 Q3 ZVN3310 R8 510k 5% R6 10k 1% 8 VDD 3 UV LT1640L 2 PWRGD OV VEE SENSE 4 R1 0.02Ω 5% GATE 5 DRAIN 6 C1 0.033µF 24V 1 + C3 100µF 100V 7 R2 R3 10Ω 10k C2 5% 5% 3.3nF 100V Q1 IRF530 1640 F09a 1640 F09b Figure 9. Automatic Restart After Current Fault 9 LT1640L/LT1640H U W U U APPLICATIONS INFORMATION supply input. The UV and OV pins are internally connected to analog comparators with 20mV of hysteresis. When the UV pin falls below its threshold or the OV pin rises above its threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until UV is high and OV is low. With R4 = 506k, R5 = 8.87k and VOVH = 1.223V, the overvoltage threshold will be 71V. GND 8 The undervoltage and overvoltage trip voltages can be programmed using a three resistor divider as shown in Figure 10a. With R4 = 562k, R5 = 9.09k and R6 = 10K, the undervoltage threshold is set to 37V and the overvoltage threshold is set to 71V. The resistor divider will also gain up the 20mV hysteresis at the UV pin and OV pin to 0.6V and 1.2V at the input respectively. VUV = 1.223 R4 + R5+ R6 R5 + R6 R4 + R5+ R6 VOV = 1.223 R6 ) ) where VUVL is typically 1.223V. The new hysteresis value will be: R2 • R3 + R1 • R3 + R1 • R2 R1 VHYS = VUVHY + VGATE • R3 R2 • R3 With R1 = 562k, R2 = 16.9k and R3 = 1.62M, VGATE = 135mV and VUVHY = 20mV, the undervoltage threshold will be 43V (from low to high) and 37.6V (from high to low). The hysteresis is 5.4V. A separate resistor divider should be used to set the overvoltage threshold given by: R4 + R5 VOV = VOVH R5 10 UV LT1640L LT1640H R5 2 OV VEE 4 1640 F10a Figure 10a. Undervoltage and Overvoltage Sensing GND 8 R4 506k 1% UV = 37.6V UV = 43V OV = 71V VDD 2 R1 562k 1% R5 8.87k 1% R2 16.9k 1% OV LT1640L /LT1640H 3 R3 1.62M 1% UV VEE SENSE 4 R1 0.02Ω 5% where VUVH is typically 1.243V. R2 • R3 + R1 • R3 + R1 • R2 R1 VUV,HL = VUVL – VGATE • R3 R2 • R3 3 – 48V R2 • R3 + R1 • R3 + R1 • R2 VUV,LH = VUVH R2 • R3 The new threshold voltage when the input moves from high to low is: VDD R6 More hysteresis can be added to the UV threshold by connecting resistor R3 between the UV pin and the GATE pin as shown in Figure 10b. The new threshold voltage when the input moves from low to high is: ( ( R4 GATE 5 6 C1 0.033µF 24V – 48V R6 10Ω 5% Q1 1640 F10b IRF530 Figure 10b. Programmable Hysteresis for Undervoltage Detection PWRGD/PWRGD Output The PWRGD/PWRGD output can be used to directly enable a power module when the input voltage to the module is within tolerance. The LT1640L has a PWRGD output for modules with an active low enable input, and the LT1640H has a PWRGD output for modules with an active high enable input. When the DRAIN voltage of the LT1640H is high with respect to VEE (Figure 11), the internal transistor Q3 is turned off and R7 and Q2 clamp the PWRGD pin one diode drop (≈ 0.7V) above the DRAIN pin. Transistor Q2 sinks the module’s pull-up current and the module turns off. When the DRAIN voltage drops below VPG, Q3 will turn on, shorting the bottom of R7 to VEE and turning Q2 off. The LT1640L/LT1640H U U W U APPLICATIONS INFORMATION ACTIVE LOW ENABLE MODULE VIN+ GND 8 VDD LT1640H R4 3 UV + – R5 2 PWRGD 1 R7 5k + VOUT+ + 8 ON/OFF 3 R5 VEE DRAIN 7 VIN– R6 VEE SENSE 4 VOUT– GATE 5 + – VPG OV R3 ON/OFF C3 VEE – VEE SENSE R2 + Q2 DRAIN 4 7 VIN– VOUT– GATE 5 C2 6 C1 R1 VOUT+ 1 R6 6 C1 PWRGD + UV 2 – OV VDD LT1640L C3 Q2 VIN+ GND R4 Q3 VPG ACTIVE LOW ENABLE MODULE R2 R3 C2 R1 – 48V 1640 F11 – 48V Q1 1640 F12 Q1 Figure 11. Active High Enable Module Figure 12. Active Low Enable Module pull-up current in the module then flows through R7, pulling the PWRGD pin high and enabling the module. When the DRAIN voltage of the LT1640L is high with respect to VEE, the internal pull-down transistor Q2 is off and the PWRGD pin is in a high impedance state (Figure 12). The PWRGD pin will be pulled high by the module’s internal pull-up current source, turning the module off. When the DRAIN voltage drops below VPG, Q2 will turn on and the PWRGD pin will pull low, enabling the module. Gate Pin Voltage Regulation When the supply voltage to the chip is more than 15.5V, the GATE pin voltage is regulated at 13.5V above VEE. If the supply voltage is less than 15.5V, the GATE voltage will be about 2V below the supply voltage. At the minimum 10V supply voltage, the gate voltage is guaranteed to be greater than 6V. The gate voltage will be no greater than 18V for supply voltages up to 80V. The PWRGD signal can also be used to turn on an LED or optoisolator to indicate that the power is good as shown in Figure 13. GND R4 562k 1% R5 9.09k 1% R6 10k 1% 8 UV LT1640L 2 PWRGD + VDD 3 PWRGD 1 4N25 C3 100µF 100V OV VEE SENSE 4 GATE 5 R1 0.02Ω 5% – 48V R7 51k 5% DRAIN 6 C1 0.033µF 24V 7 R2 R3 10Ω 10k C2 5% 5% 3.3nF 100V Q1 IRF530 1640 F13 Figure 13. Using PWRGD to Drive an Optoisolator Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LT1640L/LT1640H U TYPICAL APPLICATION Using an EMI Filter Module using the Lucent FLTR100V10 filter module is shown in Figure 14. When using a filter, a capacitor (C6) is required across the enable pin and VIN– pin of the module to prevent noise from momentarily disabling the module. Many applications place an EMI filter module in the power path to prevent switching noise of the module from being injected back onto the power supply. A typical application LUCENT JW050A1-E GND 8 R4 562k 1% VDD 3 R5 9.09k 1% 1 1 7 DRAIN UV R6 10k 1% OV 6 GATE VIN+ C2 3.3nF 100V LT1640L 2 4 – 48V VIN– 2 VOUT+ LUCENT FLTR100V10 C4 0.1µF 100V + C6 0.1µF 100V C5 100µF 100V VOUT– 9 VOUT+ 7 TRIM ON/OFF 5V 8 SENSE + + 6 4 SENSE – C7 100µF 16V 5 VOUT– VIN– CASE R2 10Ω 5% C1 0.033µF 24V 5 R1 0.02Ω 5% C3 0.1µF 100V R3 10k 5% SENSE VEE VIN+ PWRGD CASE 3 1640 F14 Q1 IRF530 Figure 14. Typical Application Using a Filter Module U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1510) (LTC DWG # 05-08-1610) 0.400* (10.160) MAX 0.189 – 0.197* (4.801 – 5.004) 8 8 7 6 0.255 ± 0.015* (6.477 ± 0.381) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 +0.889 8.255 –0.381 ) 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.300 – 0.325 (7.620 – 8.255) 7 5 2 3 4 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.008 – 0.010 (0.203 – 0.254) 0.065 (1.651) TYP 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 N8 1197 (0.457 ± 0.076) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 2 3 0.053 – 0.069 (1.346 – 1.752) 4 0.004 – 0.010 (0.101 – 0.254) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.050 (1.270) TYP SO8 0996 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC 1421 Dual Channel, Hot Swap Controller Operates from 3V to 12V LTC1422 High Side Drive, Hot Swap Controller in SO-8 System Reset Output with Programmable Delay LTC1643 PCI Hot Swap Controller 3.3V, 5V, 12V, – 12V Supplies for PCI Bus ® 12 Linear Technology Corporation 1640lhf LT/TP 1198 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998